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LM26484SQE/NOPB [TI]

两个直流/直流转换器和一个 LDO 可配置 PMIC | NHZ | 24 | -40 to 125;
LM26484SQE/NOPB
型号： LM26484SQE/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

两个直流/直流转换器和一个 LDO 可配置 PMIC | NHZ | 24 | -40 to 125

集成电源管理电路 转换器
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LM26484  
www.ti.com  
SNVS573F –SEPTEMBER 2008–REVISED MARCH 2013  
LM26484 Power Management Unit  
Check for Samples: LM26484  
1
FEATURES  
APPLICATIONS  
2
•
Step-Down DC/DC Converter (Buck)  
•
•
•
•
•
•
Digital Cores and I/Os (FPGAs, ASICs, DSPs)  
Automotive Infotainment  
Set-Top-Box  
–
–
–
–
–
–
–
–
–
3.0–5.5V Input Range  
Externally Adjustable VOUT  
:
Bucks 1 & 2: 0.8V–3.5V @ 2A  
180° Phase Shift Between Bucks Clocks  
2 MHz PWM Switching Frequency  
±1% feedback Voltage Accuracy  
Automatic Soft Start  
Cordless Phone Base Station  
Networking Router  
Printers  
DESCRIPTION  
The LM26484 is a multi-function, configurable Power  
Management Unit. This device integrates two highly  
efficient 2.0A Step-Down DC/DC converters, one  
LDO Controller, a POR (Power On Reset) circuit, and  
thermal overload protection circuitry. All regulator  
output voltages are externally adjustable. The LDO  
controller is a low-voltage NMOS voltage regulator.  
The LM26484 is offered in a 5 x 4 x 0.8 mm WQFN-  
24 pin package.  
Current Overload Protection  
PWM/PFM efficiency Modes Available  
•
Linear Regulator (LDO) Controller  
–
–
–
–
3.0V–5.5V Input Range  
Externally Adjustable VOUT  
±1.5% Feedback Voltage Accuracy  
Regulated to Low VIN - Low VOUT LI-LO (Low  
Input Low Output) NFET Operation  
–
–
Input to the LI-LO Configuration, Can Be  
Post Regulated When Supply is Regulated  
by Buck2  
Up to 1000 mA Output Current by Selection  
of External FET  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2013, Texas Instruments Incorporated  
LM26484  
SNVS573F –SEPTEMBER 2008–REVISED MARCH 2013  
www.ti.com  
Typical Application Circuit  
Comm DC  
Input voltage  
Comm DC  
Input voltage  
19  
4
1
VIN1  
AVDD  
AVIN  
24  
C1  
C9  
L1  
R7  
VOUT1  
22  
23  
SW1  
FB1  
2
6
ENSW1  
ENSW2  
C3  
C4  
C2  
Power  
On-Off  
Logic  
R1  
R2  
BUCK1  
3
13  
18  
ENLDO  
nPOR  
RESET  
20  
21  
PGND_SW1  
Logic  
Control  
and  
BG_vref  
Central Bias  
Thermal SD  
and  
C4 and C8 usually not needed  
depending on the  
application layout and  
amount of parasitic on board.  
PVIN  
Registers  
Supervisory  
14  
LDOGATE  
Comm DC  
LDO_OUT  
C10  
Input voltage  
LDO  
CONTROLLER  
7
8
VIN2  
C5  
R5  
C11  
15  
LDOFB  
L2  
VOUT2  
9
SW2  
FB2  
10  
R6  
C6  
C8  
R3 C7  
BUCK2  
5
R4  
11  
12  
PGND_SW2  
17  
16  
Connection Diagram  
19  
14  
18  
17  
16  
15  
13  
20  
12  
11  
21  
22  
10  
9
23  
24  
8
6
7
2
3
4
5
1
Figure 1. 24-Lead WQFN Package (top view)  
Package NHZ0024B  
2
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LM26484  
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SNVS573F –SEPTEMBER 2008–REVISED MARCH 2013  
PIN DESCRIPTIONS  
Pins  
1
Name  
VIN1  
I/O  
I
Type(1)  
Description  
PWR  
D
Power in DC source Buck1 PMOS  
Enable for Buck1 switcher, a logic HIGH enables Buck1  
Buck1 input feedback terminal  
2
ENSW1  
FB1  
I
3
I
A
4
AVIN  
I
PWR  
A
Analog power for internal circuits  
Buck2 input feedback terminal  
5
FB2  
I
6
ENSW2  
VIN2  
I
D
Enable for Buck2 switcher, a logic HIGH enables Buck2  
Power in DC source Buck2 PMOS  
Power in DC source Buck2 PMOS  
Buck2 switcher output  
7
I
PWR  
PWR  
A
8
VIN2  
I
9
SW2  
O
O
G
G
I
10  
11  
12  
13  
14  
15  
16  
17  
18  
SW2  
A
Buck2 switcher output  
PGND_SW2  
PGND_SW2  
ENLDO  
LDOGATE  
LDOFB  
AGND  
GND  
G
Buck2 NMOS Power Ground  
G
Buck2 NMOS Power Ground  
D
Enable for LDO, a logic HIGH enables LDO  
LDO Controller output to NMOS power transistor Gate  
LDO Controller input to feedback terminal  
Analog GND  
O
I
A
A
G
G
O
G
G
Ground  
nPOR  
D
nPOR Active low Reset output. nPOR remains LOW while the input  
supply is below threshold, and goes HIGH after the threshold is  
reached and timed delay  
19  
20  
AVDD  
PGND_SW1  
PGND_SW1  
SW1  
I
G
PWR  
G
Analog Power Pin  
Buck1 NMOS Power Ground  
Buck1 NMOS Power Ground  
Buck1 switcher output  
21  
G
G
22  
O
A
23  
SW1  
O
A
Buck1 switcher output  
24  
VIN1  
I
PWR  
GND  
Power in DC source Buck1 PMOS  
DAP  
DAP  
GND  
Connection isn't necessary for electrical performance, but it is  
recommended for better thermal dissipation.  
(1) A: Analog Pin  
D: Digital Pin  
G: Ground Pin  
PWR: Power Pin  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Table 1. Default Options  
Orderable  
Number  
Package  
Marking  
Ordering  
Specification  
Buck1  
Buck2  
Supplied As  
LM26484SQE  
LM26484SQ  
LM26484SQX  
26484SQ  
26484SQ  
26484SQ  
NOPB  
NOPB  
NOPB  
PWM  
PWM  
PWM  
PWM  
PWM  
PWM  
250 units, tape-and-reel  
1000 units, tape-and-reel  
4500 units, tape-and-reel  
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SNVS573F –SEPTEMBER 2008–REVISED MARCH 2013  
www.ti.com  
Absolute Maximum Ratings(1)(2)(3)  
VIN1, VIN2, AVDD, AVIN  
−0.3V to +6V  
−0.3 to VIN + 0.3V  
±0.3V  
nPOR, ENSW1, FB1, ENSW2, FB2, ENLDO, LDO_FB  
GND to GND SLUG  
Junction Temperature (TJ-MAX  
Storage Temperature Range  
)
150°C  
−65°C to +150°C  
260°C  
Maximum Lead Temperature (Soldering)  
ESD Ratings  
(4)  
Human Body Model  
2 kV  
Machine Model:  
VIN1,2; SW1,2 PGND1,2  
All other pins  
150V  
200V  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under  
which operation of the device is specified. Operating Ratings do not imply ensured performance limits. For specified performance limits  
and associated test conditions, see the Electrical Characteristics tables.  
(2) All voltages are with respect to the potential at the GND pin.  
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.  
(4) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF  
capacitor discharged directly into each pin. (MILSTD - 883 3015.7)  
Operating Ratings  
VIN1, VIN2, AVDD, AVIN  
3.0V to 5.5V  
0V to VIN + 0.3V  
nPOR, ENSW1, ENSW2, ENLDO, LDO_GATE, SW1, SW2  
FB1, FB2  
LDOFB  
0v to VBuck1 and VBuck2 respectively  
0v to VLDO  
Power Dissipation (PD-MAX  
)
1.2W  
TA = 85°C, TMAX = 125°C  
(1)  
Junction Temperature (TJ) Range  
−40°C to +125°C  
(1) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and  
disengages at TJ = 130°C (typ.)  
Thermal Properties(1) (2)  
Junction-to-Ambient  
Thermal Resistance  
33.1°C/W based on a  
4-layer 1 oz. PCB  
(θJA  
)
Junction-to-Case  
4.3°C/W  
Thermal Resistance (θJC  
)
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may  
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature, the  
maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the package in  
the application (θJA), as given by the following equation: TA-MAX = TJ-MAX − (θJA × PD-MAX).Refer to dissipation rating table for PD-MAX  
values at different ambient temperatures.  
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power  
dissipation exists, special care must be paid to thermal dissipation issues in board design. More information is available in Application  
Note AN-1187 (SNOA401).  
4
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SNVS573F –SEPTEMBER 2008–REVISED MARCH 2013  
General Electrical Characteristics(1)  
Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the  
(2) (3)  
entire junction temperature range for operation, −40°C to +125°C.  
Symbol  
VIN  
Parameter  
Operational Voltage Range  
Thermal Shutdown  
Conditions  
Min  
3.0  
Typ  
3.3  
160  
10  
Max  
5.5  
Units  
V
AVDD, AVIN  
(4)  
TSD  
CIN  
Iq  
°C  
Input Capacitor  
C9 (Typ App Circuit)  
µF  
Quiescent Current “Off”  
VIN = 3.3V,  
0.03  
1
µA  
ENSW1, ENSW2, ENLDO = 0  
(1) Specified by design.Not productoin tested.  
(2) All voltages are with respect to the potential at the GND pin.  
(3) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.  
(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and  
disengages at TJ = 130°C (typ.)  
LDO Controller  
Unless otherwise noted, AVDD = AVIN 3.3V, PVIN = 1.8V. Typical values and limits appearing in normal type apply for TA =  
(1)  
25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.  
(2)  
Symbol  
Parameter  
Operational Voltage Range  
NMOS configuration  
Conditions  
AVIN LDO internal circuits  
Externally configured  
Min  
3.0  
0.8  
Typ  
Max  
5.5  
Units  
VIN  
3.3  
V
V
V
VOUT  
VFB  
1.5  
Feedback Voltage Accuracy  
0.5  
−1.5  
−2  
1.5  
%
2
PSRR  
TON  
Power Supply Ripple Rejection  
Turn On Time  
F = 10 kHz, Load Current = IMAX  
Start up from shut-down  
C11 (Typ. App. Circuit)  
−30  
500  
12  
dB  
µsec  
pF  
CFB  
Feedback Capacitor  
Output Capacitor  
Capacitance for stability:  
−40°C ≤ TJ ≤ 125°C  
µF  
10  
22  
(3)  
C10,  
COUT  
ESR (Equivalent Series  
Resistance)  
0.5  
Ω
(1) All voltages are with respect to the potential at the GND pin.  
(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.  
(3) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under  
which operation of the device is specified. Operating Ratings do not imply ensured performance limits. For specified performance limits  
and associated test conditions, see the Electrical Characteristics tables.  
Buck Converters SW1, SW2  
Unless otherwise noted, AVDD=AVIN=VIN1=VIN2 = 3.3V, CIN = 10 µF, COUT = 22 µF, LOUT = 0.5 µH. Buck1 is configured to  
1.8V. Buck2 is configured to 1.0V. Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in  
(1) (2)  
boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.  
Symbol  
Parameter  
Conditions  
AVDD=VIN1=VIN2  
Min  
3.0  
Typ  
3.3  
0.5  
Max  
5.5  
Units  
VIN  
VIN Range  
V
VFB  
Feedback Voltage Accuracy  
DC Line Regulation  
−1.0  
−1.5  
+1.0  
%
+1.5  
3.0 < VIN < 3.6  
IO =1000 mA  
0.174  
%/V  
ΔVOUT  
DC Load Regulation  
100 mA < IO < IMAX  
0.75  
2.0  
%/A  
MHz  
A
fOSC  
Oscillator Frequency  
1.8  
IPEAK  
Peak Switching Current Limit  
3.2  
(1) All voltages are with respect to the potential at the GND pin.  
(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.  
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Buck Converters SW1, SW2 (continued)  
Unless otherwise noted, AVDD=AVIN=VIN1=VIN2 = 3.3V, CIN = 10 µF, COUT = 22 µF, LOUT = 0.5 µH. Buck1 is configured to  
1.8V. Buck2 is configured to 1.0V. Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in  
(1) (2)  
boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.  
Symbol  
RDSON (P)  
RDSON (N)  
TON  
Parameter  
Pin-Pin Resistance PFET  
Pin-Pin Resistance NFET  
Turn On Time  
Conditions  
Min  
Typ  
70  
Max  
100  
100  
Units  
mΩ  
mΩ  
µsec  
µF  
80  
Start up from shut-down  
Capacitance for stability  
Capacitance for stability  
500  
CIN  
Input Capacitor  
10  
10  
CO  
Output Capacitor  
22  
µF  
I/O Electrical Characteristics  
Unless otherwise noted: AVDD=AVIN=VIN1=VIN2 = 3.3V. Typical values and limits appearing in normal type apply for TJ =  
(1)  
25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40 to +125°C  
(2)  
Symbol  
VIL  
Parameter  
Min  
Typ  
Max  
0.4  
Units  
V
Input Low Level, ENSW1, ENSW2, ENLDO  
VIH  
Input High Level, ENSW1, ENSW2, ENLDO  
0.8*VIN  
V
IOH  
nPOR  
nPOR  
0.01  
0.125  
200  
2
µA  
V
VOL  
0.25  
475  
TnPOR  
nPOR Delay  
60  
msec  
(1) All voltages are with respect to the potential at the GND pin.  
(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.  
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SNVS573F –SEPTEMBER 2008–REVISED MARCH 2013  
Typical Performance Characteristics — LDO  
TA = 25°C unless otherwise noted.  
Load Transient VOUT — 1.0V, IOUT = 200 mA-1A  
Load Transient VOUT — 1.0V, IOUT = 50 mA- 500 mA  
100 mV/  
DIV  
VOUT  
500 mA/  
DIV  
IL  
200 µs/DIV  
Figure 2.  
Figure 3.  
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Typical Performance Characteristics — Buck  
TA = 25°C unless otherwise noted.  
Startup of Buck1: VOUT = 1.8V; IOUT = 100 mA  
Startup of Buck1: VOUT = 1.8V; IOUT = 2A  
Figure 4.  
Figure 5.  
Startup of Buck2: VOUT = 1.0V; IOUT = 100 mA  
Startup of Buck2: VOUT = 1.0V; IOUT = 2A  
Figure 6.  
Figure 7.  
Line Transient: VIN = 3.0V - 3.6V;  
IOUT = 250 mA; VOUT = 1.8V  
Line Transient: VIN = 3.3V - 4.2V  
IOUT = 250 mA; VOUT = 1.0V  
Figure 8.  
Figure 9.  
8
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Typical Performance Characteristics — Buck (continued)  
TA = 25°C unless otherwise noted.  
Buck1 Load Transient: VIN = 3.3V;  
VOUT = 1.8V; IOUT = 250 mA - 1.5A  
Buck1 Load Transient: VIN = 3.3V;  
VOUT = 1.8V; IOUT = 500 mA - 2A  
Figure 10.  
Figure 11.  
Buck2 Load Transient: VIN = 3.3V;  
VOUT = 1.0V; IOUT = 250 mA - 1.5A  
Buck2 Load Transient: VIN = 3.3V;  
VOUT = 1.0V; IOUT = 500 mA - 2A  
Figure 12.  
Figure 13.  
Efficiency of Buck1, VOUT = 1.8V, at Room Temp  
Efficiency of Buck2, VOUT = 1.0V, at Room Temp  
Figure 14.  
Figure 15.  
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Typical Performance Characteristics — Buck (continued)  
TA = 25°C unless otherwise noted.  
Efficiency of Buck1, VOUT = 3.5V at Room Temp  
Figure 16.  
10  
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FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER SUPPLIES  
The two bucks and the LDO in the LM26484 can be individually controlled with ENSW1, ENSW2, and ENLDO,  
respectively. All the enable inputs need to be either grounded or tied to VIH.  
Power-On Reset  
The LM26484 provides an active low reset output nPOR. Typical waveform is as shown in Figure 17 below:  
AVIN  
nPOR  
170 ms  
Figure 17. Power-On Reset Waveform  
LDO Functional Description  
The LDO is a linear regulator which targets analog loads characterized by low noise requirements. The LDO is  
enabled through the ENLDO pin. The output voltage is determined by the configuration of the external feedback  
resistors, as seen in Typical Application Circuit, R5 and R6.  
NO-LOAD STABILITY  
The LDO will remain stable and in regulation with no external load. This is an important consideration in some  
circuits, for example CMOS RAM keep-alive applications.  
Table 2. LDO Configuration and Component Selection Guide  
Feedback  
Capacitor  
Target  
Ideal Resistor Values  
Common R Values  
Actual VOUT with  
Com R (V)  
VOUT(V)  
0.8  
R5 (KΩ)  
R6 (KΩ)  
200  
R5 (KΩ)  
R6 (KΩ)  
200  
C11 (pF)  
15  
120  
160  
200  
240  
280  
320  
360  
400  
120  
162  
200  
240  
280  
324  
357  
402  
0.8  
0.905  
1
0.9  
200  
200  
15  
1
200  
200  
15  
1.1  
200  
200  
1.1  
15  
1.2  
200  
200  
1.2  
12  
1.3  
200  
200  
1.31  
1.393  
1.505  
12  
1.4  
200  
200  
10  
1.5  
200  
200  
10  
RESISTOR SELECTION FOR LDO  
The output voltage of the LDO on the LM26484 is established by the feed back resistor divider R5 and R6 shown  
on the typical application circuit (page 1). The equation for determining VOUT is: VOUT = VFB*(R5+R6)/R6, where  
VFB is the voltage on the LDO_FB pin.  
The LDO control loop will force the voltage on VFB to be 0.50V.  
Table 2 shows ideal resistor values to establish LDO voltages from 0.8V to 1.5V along with common resistor  
values to establish these voltages. Common resistors do not always produce the target value. The resulting  
output voltage using common resistors is also found in Table 2. To keep the power consumed by the feedback  
network low it is recommended that R6 be established as about 200 kΩ. Lesser values of R6 are OK and can be  
used at the user’s discretion.  
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NFET SELECTION  
There are a few major concerns when selecting an NFET for the LM26484 controller. The most important factor  
to consider is the maximum power rating. It is important for the NFET to have a maximum power rating larger  
than the application will need. The LM26484 has the ability to drive the gate voltage very close to VIN and down  
to approximately 1.5V. Selecting an NFET where the ensured operation of the VGS is ≥1.5V is important.  
Table 3. Recommended NFET  
Part  
Vendor  
VGS  
PDISSIPATION  
Number  
Si1450DH  
Vishay  
1.5V  
2.78W  
EXTERNAL CAPACITORS  
The LDO on the LM26484 requires external capacitors for regulator stability. These are specifically designed for  
portable applications requiring minimum board space and smallest components. These capacitors must be  
correctly selected for good performance. The tolerance and temperature coefficient must be considered when  
selecting the capacitor to ensure that the capacitance will remain close to ideal over the entire operating  
temperature range.  
FEEDBACK CAPACITOR  
A Feedback capacitor is required for stability; recommended values can be seen in Table 2. This capacitor must  
be located a distance of not more than 1 cm from the LDO_FB pin and LDO_OUT. Any good quality ceramic or  
film capacitor should be used.  
OUTPUT CAPACITOR  
The LDO on the LM26484 is designed specifically to work with very small ceramic output capacitors. A 10.0 µF  
ceramic capacitor, marked as C10 in the Typical Application Circuit on page 1, temperature types Z5U, Y5V or  
X7R with ESR between 5 mΩ to 500 mΩ, is suitable for proper operation.  
It is also possible to use tantalum or film capacitors, but these are not as attractive for reasons of size and cost.  
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR  
value that is within the range 50 mΩ to 500 mΩ for stability.  
CAPACITOR CHARACTERISTICS  
The LDO is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer.  
For capacitance values in the range of 0.47 μF to 44 μF, ceramic capacitors are the smallest, least expensive  
and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a  
typical 10 μF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for  
stability for the LDO.  
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure  
correct device operation. The capacitor value can change greatly, depending on the operating conditions and  
capacitor type.  
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the  
specification is met within the application. The capacitance can vary with DC bias conditions as well as  
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.  
The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer  
performance figures in general.  
Buck Regulator Functional Description  
The LM26484 incorporates two high efficiency synchronous switching buck regulators which are 180° out of  
phase, SW1 and SW2 that deliver voltages from a single DC input voltage. Using a voltage mode architecture  
with synchronous rectification, both bucks have the ability to deliver up to 2A depending on the input voltage and  
output voltage (voltage head room), and the inductor chosen (maximum current capability).  
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There are three modes of operation depending on the current required - PWM, PFM, and shutdown. PWM mode  
handles current loads of approximately 70 mA or higher, delivering voltage precision with high efficiency. Lighter  
output current loads cause the device to automatically switch into PFM for reduced current consumption (Iq = 15  
µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering the lowest current  
consumption. Forced PWM is factory programmed. For Auto PFM-PWM please contact TI Sales.  
Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of  
the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.  
Additional features include soft-start, under-voltage lockout, current overload protection, and thermal overload  
protection.  
PWM OPERATION  
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This  
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional  
to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input  
voltage is introduced.  
INTERNAL SYNCHRONOUS RECTIFICATION  
While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward  
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in  
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier  
diode.  
CURRENT LIMITING  
A current limit feature allows the converter to protect the LM26484 and any external components during overload  
conditions. An internal comparator senses the voltage across an internal sense resistor and will turn on the NFET  
when the output current is sensed at 2.5A (min.) with 0.5 µH inductors. If the output is shorted to ground the  
device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor  
current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing  
runaway.  
PFM OPERATION  
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply  
current to maintain high efficiency. For the PFM mode to be enabled, please contact TI Sales.  
The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or  
more clock cycles:  
A. The inductor current becomes discontinuous  
or  
B. The peak PMOS switch current drops below the IMODE level  
VIN  
(Typically IMODE < 66 mA +  
)
100W  
(1)  
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage  
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy  
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output  
FETs such that the output voltage ramps between 0.8% and 1.6% (typ.) above the nominal PWM output voltage.  
If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It  
remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level  
set for PFM mode. The typical peak current in PFM mode is:  
VIN  
IPFM = 66 mA +  
80W  
(2)  
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Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps  
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output  
voltage is below the ‘high’ PFM comparator threshold (see Figure 18), the PMOS switch is again turned on and  
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM  
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output  
switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this  
‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load  
conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage  
to ~1.6% above the nominal PWM output voltage.  
If the load current should increase during PFM mode (see Figure 18) causing the output voltage to fall below the  
‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.  
During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The  
NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is  
activated. It is recommended to disable the converter during the system power up and under voltage conditions  
when the supply is less than 3.0V.  
High PFM Threshold  
~1.016*Vout  
PFM Mode at Light Load  
Load current  
increases  
Low1 PFM Threshold  
~1.008*Vout  
High PFM  
Voltage  
Threshold  
reached,  
go into  
sleep mode  
Current load  
increases,  
draws V  
towards  
Low2 PFM  
Threshold  
Low PFM  
Threshold,  
turn on  
OUT  
NFET on  
PFET on  
until  
drains  
conductor  
current  
until  
I inductor = 0  
PFET  
I limit  
PFM  
reached  
Low2 PFM Threshold  
Vout  
Low2 PFM Threshold,  
switch back to PWM mode  
PWM Mode at Moderate to  
Heavy Loads  
-18  
Figure 18. PFM vs PWM  
SOFT START  
The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus  
reducing start-up stresses and surges. The two LM26484 buck converters have a soft-start circuit that limits in-  
rush current during start-up or the one which ramps up output voltage linearly over about 500 µs. During start-up  
the switch current limit is ramped up (100 µs, typ.), depending on the kind of soft-start. Soft start is activated only  
if EN goes from logic low to logic high after VIN reaches 2.8V.  
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LOW DROPOUT OPERATION  
The LM26484 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout  
support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input  
voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The  
minimum input voltage needed to support the output voltage is  
VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT  
(3)  
ILOAD  
RDSON, PFET  
Load current  
Drain to source resistance of  
PFET switch in the triode region  
RINDUCTOR  
Inductor resistance  
Component Selection  
SW1, SW2 OPERATION  
Table 4. Buck1/2 Configuration and Component Selection Guide  
Actual VOUT  
Delta from  
Target (V)  
Actual VOUT  
with Com/R (V)  
Target  
Ideal Resistor Values  
Common R Values  
Feedback Capacitors  
VOUT (V)  
0.8  
0.9  
1
R1/3 (KΩ)  
120  
160  
200  
240  
280  
320  
360  
400  
440  
427  
463  
498  
450  
480  
422  
446  
471  
400  
420  
440  
460  
480  
500  
520  
540  
560  
580  
600  
R2/4 (KΩ)  
200  
200  
200  
200  
200  
200  
200  
200  
200  
178  
178  
178  
150  
150  
124  
124  
124  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
R1/3 (KΩ)  
121  
162  
200  
240  
280  
324  
357  
402  
442  
432  
464  
499  
453  
475  
422  
442  
475  
402  
422  
442  
464  
475  
499  
523  
536  
562  
576  
604  
R2/4 (KΩ)  
200  
200  
200  
200  
200  
200  
200  
200  
200  
178  
178  
178  
150  
150  
124  
124  
124  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
(V)  
(V)  
0.002  
0.005  
0
C3/6 (pF)  
15  
C4/8 (pF)  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
none  
33  
0.803  
0.905  
1
15  
15  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
1.7  
1.8  
1.9  
2
1.1  
0
15  
1.2  
0
12  
1.31  
0.01  
12  
1.393  
1.505  
1.605  
1.713  
1.803  
1.902  
2.01  
-0.008  
0.005  
0.005  
0.013  
0.003  
0.002  
0.01  
10  
10  
8.2  
8.2  
8.2  
8.2  
8.2  
8.2  
8.2  
8.2  
8.2  
8.2  
8.2  
8.2  
8.2  
8.2  
6.8  
6.8  
6.8  
6.8  
6.8  
6.8  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
2.9  
3
2.083  
2.202  
2.282  
2.415  
2.51  
-0.017  
0.002  
-0.018  
0.015  
0.01  
2.61  
0.01  
2.71  
0.01  
2.82  
0.02  
33  
2.875  
2.995  
3.115  
3.18  
-0.025  
-0.005  
0.015  
-0.02  
0.01  
33  
33  
3.1  
3.2  
3.3  
3.4  
3.5  
33  
33  
3.31  
33  
3.38  
-0.02  
0.02  
33  
3.52  
33  
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The Buck control loop will force the voltage on VFB to be 0.50V.  
Table 4 shows ideal resistor values to establish buck voltages from 0.8V to 3.5V along with common resistor  
values to establish these voltages. Common resistors do not always produce the target value, error is given in  
the delta column.  
In addition to the resistor feedback, feedback capacitors are also required. (Table 4 — C3/4/6/8) When choosing  
the output voltage for the two bucks, please take into account the fact that, the factory has optimized the  
accuracy of Buck1 at the top end of the VOUT range and Buck2 for the bottom end of the VOUT range.  
0603, 10V, X5R  
100%  
80%  
60%  
0402, 6.3V, X5R  
40%  
20%  
0
1.0  
2.0  
3.0  
4.0  
5.0  
DC BIAS (V)  
Figure 19. Typical Variation in Capacitance vs. DC Bias  
As shown in Table 4, increasing the DC Bias condition can result in a capacitance value that falls below the  
minimum value given in the recommended capacitor specifications table. Note that the graph shows the  
capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended  
that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions,  
as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.  
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a  
temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R  
has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic  
capacitors, larger than 1 μF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance  
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over  
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.  
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more  
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 44 µF range. Another  
important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This  
means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it  
would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the  
same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the  
temperature goes from 25°C down to −40°C, so some guard band must be allowed.  
OUTPUT INDUCTORS & CAPACITORS FOR SW1 AND SW2  
There are several design considerations related to the selection of output inductors and capacitors:  
•
•
•
•
•
Load transient response;  
Stability;  
Efficiency;  
Output ripple voltage; and  
Over-current ruggedness.  
The LM26484 has been optimized for use with nominal values 0.5 µH and 22 µF. If other values are needed for  
the design, please contact TI sales with any concerns.  
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INDUCTOR SELECTION FOR SW1 AND SW2  
A nominal inductor value of 0.5 µH is recommended. It is important to ensure the inductor core does not saturate  
during any foreseeable operational situation.  
Care should be taken when reviewing the different saturation current ratings that are specified by different  
manufacturers. Saturation current ratings are typically specified at 25ºC, so ratings at maximum ambient  
temperature of the application should be requested from the manufacturer.  
There are two methods to choose the inductor saturation current rating:  
Recommended method:  
The best way to ensure the inductor does not saturate is to choose an inductor that has saturation current rating  
greater than the maximum LM26484 current limit of 3.0A. In this case the device will prevent inductor saturation.  
Alternate method:  
If the recommended approach cannot be used, care must be taken to ensure that the saturation current is  
greater than the peak inductor current:  
ISAT > ILPEAK  
IRIPPLE  
2
ILPEAK = IOUTMAX  
+
(VIN œ VOUT  
)
D x  
IRIPPLE  
=
L x F  
VOUT  
D =  
VIN x EFF  
where  
•
•
•
•
•
•
•
•
•
•
•
ISAT: Inductor saturation current at operating temperature  
ILPEAK: Peak inductor current during worst case conditions  
IOUTMAX: Maximum average inductor current  
IRIPPLE: Peak-to-Peak inductor current  
VOUT: Output voltage  
VIN: Input voltage  
L: Inductor value in Henries at IOUTMAX  
F: Switching frequency, Hertz  
D: Estimated duty factor  
EFF: Estimated power supply efficiency  
(4)  
ISAT may not be exceeded during any operation, including transients, startup, high temperature, worst case  
conditions, etc.  
Inductor  
Value  
Unit  
Description  
Notes  
L1 and L2  
0.5  
µH  
SW1 and SW2 inductor  
D.C.R. 50 mΩ  
SUGGESTED INDUCTORS AND THEIR SUPPLIERS  
Output Voltage Range  
OUT ≥ 2.0V  
VOUT < 2.0V  
Vendor  
Coilcraft  
Coilcraft  
Part Number  
LPS4012–222ML  
LPS4414–501ML  
Value  
2.2 µH  
0.5 µH  
DCR (max)  
V
100 mΩ  
50 mΩ  
OUTPUT CAPACITOR SELECTION FOR SW1 AND SW2  
A ceramic output capacitor of 10 µF, 6.3V is recommended with an ESR of less than 500 mΩ.  
Output ripple can be estimated from the vector sum of the reactive (Capacitor) voltage component and the real  
(ESR) voltage component of the output capacitor.  
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IRIPPLE  
VCOUT  
=
8 x F x COUT  
VROUT = IRIPPLE x ESRCOUT  
2
VPPOUT  
=
VCOUT2 + VROUT  
where  
•
•
•
VCOUT: Estimated reactive output ripple  
VROUT: Estimated real output ripple  
VPPOUT: Estimated peak-to-peak output ripple  
(5)  
The output capacitor needs to be mounted as close as possible to the output pin of the device.  
The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output  
voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with  
sufficient capacitance and sufficiently low ESR to perform these functions.  
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series  
resistance of the output capacitor (ESRCOUT). ESRCOUT is frequency dependent as well as temperature  
dependent. The RESR should be calculated with the applicable switching frequency and ambient temperature.  
INPUT CAPACITOR SELECTION FOR SW1 AND SW2  
It is required to use a ceramic input capacitor of at least 10 μF and 6.3V with an ESR of less than 500 mΩ.  
The input power source supplies average current continuously. During the PFET switch on-time, however, the  
demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by the  
input capacitor.  
A simplified “worst case” assumption is that all of the PFET current is supplied by the input capacitor. This will  
result in conservative estimates of input ripple voltage and capacitor RMS current. Input ripple voltage is  
estimated as follows:  
IOUT x D  
CIN x F  
+ IOUT x ESRCIN  
VPPIN  
=
where  
•
•
•
•
VPPIN: Estimated peak-to-peak input ripple voltage  
IOUT: Output current, Amps  
CIN: Input capacitor value, Farads  
ESRIN: Input capacitor ESR, Ohms  
(6)  
This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate  
RMS current rating. Capacitor RMS current estimated as follows:  
«
2
≈
IRIPPLE  
12  
2
≈
IRMSCIN  
=
D x IOUT  
+
«
where  
•
IRSCIN: Estimated input capacitor RMS current  
(7)  
Model  
Type  
Vendor  
Voltage Rating  
Case Size Inch  
(mm)  
10 µF for CIN or COUT; C9, C2, C1, C5, C7, C10  
GRM21BR60J106K  
JMK212BJ106K  
Ceramic, X7R  
Murata  
Taiyo-Yuden  
Taiyo-Yuden  
TDK  
6.3V  
6.3V  
10V  
0805, (2012)  
0805, (2012)  
0805, (2012)  
0603, (1608)  
Ceramic, X5R  
Ceramic, X7R  
Ceramic, X5R  
LMK212C106KG-T  
C1608X5R0J106K  
6.3V  
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SNVS573F –SEPTEMBER 2008–REVISED MARCH 2013  
Model  
Type  
Vendor  
Voltage Rating  
Case Size Inch  
(mm)  
22 µF for COUT; C10, C2, C7  
GRM31CR70J226KE23L  
JMK316B7226ML-T  
Ceramic, X7R  
Ceramic, X7R  
Murata  
6.3V  
6.3V  
1206, (3216)  
1206, (3216)  
Taiyo-Yuden  
Capacitor  
C10, Table 4  
C2, Table 4  
C7, Table 4  
Min Value  
Unit  
µF  
Description  
Recommended Type  
10.0  
10.0  
10.0  
LDO1 output capacitor  
SW1 output capacitor  
SW2 output capacitor  
Ceramic, 6.3V, X5R  
Ceramic, 6.3V, X5R  
Ceramic, 6.3V, X5R  
µF  
µF  
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REVISION HISTORY  
Changes from Revision E (March 2013) to Revision F  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 19  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
LM26484SQ/NOPB  
LM26484SQE/NOPB  
LM26484SQX/NOPB  
ACTIVE  
ACTIVE  
ACTIVE  
WQFN  
WQFN  
WQFN  
NHZ  
NHZ  
NHZ  
24  
24  
24  
1000 RoHS & Green  
250 RoHS & Green  
4500 RoHS & Green  
SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
-40 to 125  
26484SQ  
SN  
SN  
26484SQ  
26484SQ  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
21-Mar-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LM26484SQ/NOPB  
LM26484SQE/NOPB  
LM26484SQX/NOPB  
WQFN  
WQFN  
WQFN  
NHZ  
NHZ  
NHZ  
24  
24  
24  
1000  
250  
178.0  
178.0  
330.0  
12.4  
12.4  
12.4  
4.3  
4.3  
4.3  
5.3  
5.3  
5.3  
1.3  
1.3  
1.3  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
4500  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
21-Mar-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LM26484SQ/NOPB  
LM26484SQE/NOPB  
LM26484SQX/NOPB  
WQFN  
WQFN  
WQFN  
NHZ  
NHZ  
NHZ  
24  
24  
24  
1000  
250  
210.0  
210.0  
367.0  
185.0  
185.0  
367.0  
35.0  
35.0  
35.0  
4500  
Pack Materials-Page 2  
MECHANICAL DATA  
NHZ0024B  
SQA24B (Rev A)  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you  
permission to use these resources only for development of an application that uses the TI products described in the resource. Other  
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third  
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,  
damages, costs, losses, and liabilities arising out of your use of these resources.  
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on  
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable  
warranties or warranty disclaimers for TI products.  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2020, Texas Instruments Incorporated  

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