LM2743MTCX/NOPB_技术文档

LM2743

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SNVS276G –APRIL 2004–REVISED MARCH 2013

LM2743 Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller

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1

FEATURES

DESCRIPTION

The LM2743 is a high-speed synchronous buck

regulator controller with an accurate feedback voltage

accuracy of ±2%. It can provide simple down

conversion to output voltages as low as 0.6V. Though

the control sections of the IC are rated for 3 to 6V,

the driver sections are designed to accept input

supply rails as high as 16V. The use of adaptive non-

overlapping MOSFET gate drivers helps avoid

potential shoot-through problems while maintaining

high efficiency. The IC is designed for the more cost-

effective option of driving only N-channel MOSFETs

in both the high-side and low-side positions. It senses

the low-side switch voltage drop for providing a

simple, adjustable current limit.

2

•

Power Stage Input Voltage from 1V to 16V

Control Stage Input Voltage from 3V to 6V

Output Voltage Adjustable down to 0.6V

Power Good Flag and Shutdown

•

Output Over-Voltage and Under-Voltage

Detection

•

±2% Feedback Voltage Accuracy Over

Temperature

•

Low-Side Adjustable Current Sensing

Adjustable Soft-Start

Tracking and Sequencing with Shutdown and

Soft-Start Pins

The fixed-frequency voltage-mode PWM control

architecture is adjustable from 50 kHz to 1 MHz with

one external resistor. This wide range of switching

frequency gives the power supply designer the

flexibility to make better tradeoffs between

component size, cost and efficiency.

•

Switching Frequency from 50 kHz to 1 MHz

TSSOP-14 Package

APPLICATIONS

•

3.3V Buck Regulation

Features include soft-start, input under-voltage

lockout (UVLO) and Power Good (based on both

under-voltage and over-voltage detection). In

addition, the shutdown pin of the IC can be used for

providing startup delay, and the soft-start pin can be

used for implementing precise tracking, for the

purpose of sequencing with respect to an external

rail.

Cable Modem, DSL and ADSL

Laser Jet and Ink Jet Printers

Low Voltage Power Modules

DSP, ASIC, Core and I/O

Typical Application

V

= 3.3V

V

= 3.3V

IN

CC

D

1

C

BOOT

R

PULL-UP

Q1

+

C

IN

1,2

R

CC

V

HG

CC

SD

BOOT

R

CS

C

L1

CC

V

OUT

= 1.2V@4A

I

PWGD

FREQ

SS/TRACK

SGND

EAO

SEN

LM2743

LG

PGND

FB

R

FADJ

+

R

FB2

C 1,2

O

C

SS

R

C2

C

C3

R

FB1

C

C1

C

C2

R

C1

Figure 1. Typical Application Circuit

1

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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

2

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM2743

SNVS276G –APRIL 2004–REVISED MARCH 2013

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Connection Diagram

1

2

3

4

5

6

7

14

13

12

11

BOOT

LG

HG

PGND

SGND

V_CC

SD

FREQ

10

9

FB

SS/TRACK

EAO

PWGD

I_SEN

8

Figure 2. 14-Lead Plastic TSSOP

θ_JA= 155°C/W

Pin Descriptions

BOOT (Pin 1) - Bootstrap pin. This is the supply rail for the gate drivers. When the high-side MOSFET turns on, the voltage on this pin

should be at least one gate threshold above the regulator input voltage V_INto properly turn on the MOSFET. See MOSFET GATE

DRIVERS in the Application Information section for more details on how to select MOSFETs.

LG (Pin 2) - Low-gate drive pin. This is the gate drive for the low-side N-channel MOSFET. This signal is interlocked with the high-side gate

drive HG (Pin 14), so as to avoid shoot-through.

PGND (Pins 3, 13) - Power ground. This is also the ground for the low-side MOSFET driver. Both the pins must be connected together on

the PCB and form a ground plane, which is usually also the system ground.

SGND (Pin 4) - Signal ground. It should be connected appropriately to the ground plane with due regard to good layout practices in

switching power regulator circuits.

V_CC(Pin 5) Supply rail for the control sections of the IC.

PWGD (Pin 6) - Power Good pin. This is an open drain output, which is typically meant to be connected to V_CCor any other low voltage

source through a pull-up resistor. Choose the pull-up resistor so that the current going into this pin is kept below 1 mA. For most

applications a recommended value for the pull-up resistor is 100 kΩ. The voltage on this pin is thus pulled low under output under-voltage

or over-voltage fault conditions and also under input UVLO.

I_SEN(Pin 7) - Current limit threshold setting pin. This sources a fixed 40 µA current. A resistor of appropriate value should be connected

between this pin and the drain of the low-side MOSFET (switch node).

EAO (Pin 8) - Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to determine

the duty cycle. This pin is necessary for compensating the control loop.

SS/TRACK (Pin 9) - Soft-start and tracking pin. This pin is internally connected to the non-inverting input of the error amplifier during soft-

start, and in fact any time the SS/TRACK pin voltage happens to be below the internal reference voltage. For the basic soft-start function, a

capacitor of minimum value 1 nF is connected from this pin to ground. To track the rising ramp of another power supply’s output, connect a

resistor divider from the output of that supply to this pin as described in Application Information.

FB (Pin 10) - Feedback pin. This is the inverting input of the error amplifier, which is used for sensing the output voltage and compensating

the control loop.

FREQ (Pin 11) - Frequency adjust pin. The switching frequency is set by connecting a resistor of suitable value between this pin and

ground. The equation for calculating the exact value is provided in Application Information, but some typical values (rounded up to the

nearest standard values) are 324 kΩ for 100 kHz, 97.6 kΩ for 300 kHz, 56.2 kΩ for 500 kHz, 24.9 kΩ for 1 MHz.

SD (Pin 12) - IC shutdown pin. Pull this pin to V_CCto ensure the IC is enabled. Connect to ground to disable the IC. Under shutdown, both

high-side and low-side drives are off. This pin also features a precision threshold for power supply sequencing purposes, as well as a low

threshold to ensure minimal quiescent current.

HG (Pin 14) - High-gate drive pin. This is the gate drive for the high-side N-channel MOSFET. This signal is interlocked with LG (Pin 2) to

avoid shoot-through.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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Absolute Maximum Ratings⁽¹⁾⁽²⁾

V_CC

-0.3 to 7V

-0.3 to 21V

-0.3 to 9.5V

-0.3 to V_CC+ 0.3V

150°C

BOOT Voltage

I_SEN

All other pins

Junction Temperature

Storage Temperature

−65°C to 150°C

260°C

Lead Temperature (soldering, 10sec)

Infrared or Convection (20sec)

Soldering Information

ESD Rating⁽³⁾

235°C

2 kV

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for

which the device operates correctly. Operating Ratings do not imply specified performance limits.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Operating Ratings

Supply Voltage Range (V_CC

Junction Temperature Range (T_J)

Thermal Resistance (θ_JA

)

3V to 6V

−40°C to +125°C

155°C/W

)

Electrical Characteristics⁽¹⁾

V_CC= 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for T_A= T_J= 25°C. Limits appearing in

boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are specified by design,

test, or statistical analysis.

Symbol

V_FB

Parameter

FB Pin Voltage

Conditions

V_CC= 3V to 6V

Min

Typ

Max

Units

0.588

0.6

0.612

V

V_ON

UVLO Thresholds

Rising

Falling

2.76

2.42

V

V_CC= 3.3V, V_SD= 3.3V

Fsw = 600kHz

1.0

1.5

1.7

2.1

Operating V_CCCurrent

mA

I_{Q_VCC}

V_CC= 5V, V_SD= 3.3V

Fsw = 600kHz

2.1

Shutdown V_CCCurrent

V_CC= 3.3V, V_SD= 0V

V_FBRising

110

6

185

µA

µs

µA

t_PWGD1

t_PWGD2

I_SS-ON

I_SS-OC

PWGD Pin Response Time

SS Pin Source Current

V_FBFalling

6

V_SS= 0V

7

10

14

55

SS Pin Sink Current During Over

Current

V_SS= 2.5V

90

40

µA

I_SEN-TH

I_SENPin Source Current Trip Point

25

ERROR AMPLIFIER

GBW

Error Amplifier Unity Gain

Bandwidth

9

MHz

G

Error Amplifier DC Gain

Error Amplifier Slew Rate

106

3.2

dB

SR

I_EAO

V/µs

EAO Pin Current Sourcing and

Sinking Capability

V_EAO= 1.5, FB = 0.55V

V_EAO= 1.5, FB = 0.65V

2.6

9.2

mA

V_EA

Error Amplifier Output Voltage

Minimum

Maximum

1

2

V

(1) The power MOSFETs can run on a separate 1V to 16V rail (Input voltage, V_IN). Practical lower limit of V_INdepends on selection of the

external MOSFET.

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Electrical Characteristics⁽¹⁾(continued)

V_CC= 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for T_A= T_J= 25°C. Limits appearing in

boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are specified by design,

test, or statistical analysis.

Symbol

GATE DRIVE

I_Q-BOOT

Parameter

Conditions

Min

Typ

Max

Units

BOOT Pin Quiescent Current

V_BOOT= 12V, V_SD= 0

18

3

90

µA

R_{HG_UP}

High-Side MOSFET Driver Pull-Up

ON resistance

V_BOOT= 5V @ 350mA Sourcing

Ω

R_{HG_DN}

R_{LG_UP}

High-Side MOSFET Driver Pull-

Down ON resistance

HG = 5V @ 350mA Sourcing

V_BOOT= 5V @ 350mA Sourcing

LG = 5V @ 350mA Sourcing

2

3

2

Ω

Low-Side MOSFET Driver Pull-Up

ON resistance

R_{LG_DN}

Low-Side MOSFET Driver Pull-

Down ON resistance

OSCILLATOR

R_FADJ= 702.1 kΩ

R_FADJ= 98.74 kΩ

R_FADJ= 45.74 kΩ

R_FADJ= 24.91 kΩ

50

300

600

1000

f_SW

PWM Frequency

kHz

%

475

725

D

Max High-Side Duty Cycle

f_SW= 300kHz

f_SW= 600kHz

f_SW= 1MHz

80

76

73

LOGIC INPUTS AND OUTPUTS

V _STBY-IHStandby High Trip Point

V_FB= 0.575V, V_BOOT= 3.3V, V_SD

Rising

1.1

1.3

V

V _STBY-IL

Standby Low Trip Point

V_FB= 0.575V, V_BOOT= 3.3V, V_SD

Falling

0.232

V _SD-IH

V _SD-IL

SD Pin Logic High Trip Point

SD Pin Logic Low Trip Point

PWGD Pin Trip Points

PWGD Hysteresis

V_SDRising

V_SDFalling

FB Falling

FB Rising

V

0.8

V_PWGD-TH-LO

V_PWGD-TH-HI

V_PWGD-HYS

0.408

0.677

0.434

0.710

0.457

0.742

FB Falling

FB Rising

60

90

mV

4

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Typical Performance Characteristics

Efficiency (V_OUT= 1.2V)

V_CC= 3.3V, f_SW= 300 kHz

Efficiency (V_OUT= 2.5V)

V_CC= 3.3V, f_SW= 300 kHz

100

90

80

70

60

50

100

90

80

70

60

50

V

IN

= 3.3V

V

= 12V

IN

V_IN= 3.3V

V_IN= 5V

V

= 5V

IN

V_IN= 12V

40

30

20

40

30

20

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

OUTPUT CURRENT (A)

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

OUTPUT CURRENT (A)

Figure 3.

Figure 4.

V_CCOperating Current plus BOOT Current

vs

Efficiency (V_OUT= 3.3V)

V_CC= 5V, f_SW= 300 kHz

Frequency

FDS6898A FET (T_A= 25°C)

100

90

80

70

60

50

25

19

V

IN

= 5V

13

V

= 12V

IN

40

30

20

6

0

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

0.05

0.25

0.45

0.65

0.85

1.05

OUTPUT CURRENT (A)

FREQUENCY (MHz)

Figure 5.

Figure 6.

BOOT Pin Current

vs

BOOT Pin Current

vs

Temperature for BOOT Voltage = 3.3V

f_SW= 300 kHz, FDS6898A FET, No-Load

6.7

Temperature for BOOT Voltage = 5V

f_SW= 300 kHz, FDS6898A FET, No-Load

10

6.6

9.9

9.8

9.7

6.5

6.4

6.3

6.2

9.6

9.5

6.1

6

9.4

9.3

5.9

-40 -25 -10

50

65 80 95 110125

5

20 35

50

65 80 95 110125

-40 -25 -10

5

20 35

TEMPERATURE (^oC)

Figure 7.

Figure 8.

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Typical Performance Characteristics (continued)

BOOT Pin Current

vs

Temperature for BOOT Voltage = 12V

f_SW= 300 kHz, FDS6898A FET, No-Load

Internal Reference Voltage

vs

Temperature

24.9

0.2

0.1

24.8

24.7

24.6

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

24.5

24.4

24.3

24.2

24.1

24

23.9

50

65 80 95 110125

-40 -25 -10

5

20 35

50

65 80 95 110125

-40 -25 -10

5

20 35

TEMPERATURE (^oC)

Figure 9.

Figure 10.

Frequency

vs

Temperature

Output Voltage

vs

Output Current

1.210

1.209

1.208

1.207

1.206

1.205

1.204

1.203

1.202

1.201

1.200

640

620

600

580

560

540

520

45

-55 -35 -15

5

25

65 85 105 125

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

TEMPERATURE (^oC)

OUTPUT CURRENT (A)

Figure 11.

Figure 12.

Switch Waveforms (HG Rising)

V_CC= 3.3V, V_IN= 5V, V_OUT= 1.2V

I_OUT= 4A, C_SS= 12nF, f_SW= 300 kHz

Switch Waveforms (HG Falling)

V_CC= 3.3V, V_IN= 5V, V_OUT= 1.2V

I_OUT= 4A, C_SS= 12nF, f_SW= 300 kHz

1V/div

HG

LG

2V/div

1V/div

2V/div

5V/div

HG

SW

LG

SW

5V/div

100 ns/DIV

Figure 13.

Figure 14.

6

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Typical Performance Characteristics (continued)

Start-Up (No-Load)

V_CC= 3.3V, V_IN= 5V, V_OUT= 1.2V

C_SS= 12nF, f_SW= 300 kHz

Start-Up (Full-Load)

V_CC= 3.3V, V_IN= 5V, V_OUT= 1.2V

I_OUT= 4A, C_SS= 12nF, f_SW= 300 kHz

Figure 15.

Figure 16.

Shutdown (Full-Load)

V_CC= 3.3V, V_IN= 5V, V_OUT= 1.2V

I_OUT= 4A, C_SS= 12nF, f_SW= 300 kHz

Load Transient Response (I_OUT= 0A to 4A)

V_CC= 3.3V, V_IN= 5V, V_OUT= 1.2V

C_SS= 12nF, f_SW= 300 kHz

V

OUT

50 mV/div

2A/div

I

OUT

40 ms/DIV

Figure 17.

Figure 18.

Load Transient Response (I_OUT= 4A to 0A)

V_CC= 3.3V, V_IN= 5V, V_OUT= 1.2V

C_SS= 12nF, f_SW= 300 kHz

Load Transient Response

V_CC= 3.3V, V_IN= 5V, V_OUT= 1.2V

C_SS= 12nF, f_SW= 300 kHz

V_OUT

V

OUT

20 mV/div

20mV/div

2A/div

I

OUT

2A/div

I_OUT

40 ms/DIV

100 ms/DIV

Figure 19.

Figure 20.

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Typical Performance Characteristics (continued)

Line Transient Response (V_IN= 3V to 9V)

Line Transient Response (V_IN= 9V to 3V)

V_CC= 3.3V, V_OUT= 1.2V

I_OUT= 2A, f_SW= 300 kHz

V_CC= 3.3V, V_OUT= 1.2V

I_OUT= 2A, f_SW= 300 kHz

100mV/div

100 mV/div

V_OUT

5V/div

V_IN

5V/div

V_IN

100 ms/DIV

Figure 21.

Figure 22.

8

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Block Diagram

V

CC

SD

PGND

FREQ

SGND

CLOCK &

RAMP

UVLO

SHUT DOWN

LOGIC

BOOT

10 ms

DELAY

HG

SSDONE

PWGD

SYNCHRONOUS

DRIVER LOGIC

OV

UV

LG

0.71V

0.434V

10 mA

SS/TRACK

1V

PP

PWM LOGIC

PWM

40 mA

Soft-Start

Comparator

+ Logic

REF

-

I

+

SEN

90 mA

EA

ILIM

-

+

V

REF

= 0.6V

FB

EAO

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APPLICATION INFORMATION

THEORY OF OPERATION

The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is

designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high

efficiency buck converters. It has output shutdown (SD), input under-voltage lock-out (UVLO) mode and power

good (PWGD) flag (based on over-voltage and under-voltage detection). The over-voltage and under-voltage

signals are logically OR'ed to drive the power good signal and provide a logic signal to the system if the output

voltage goes out of regulation. Current limit is achieved by sensing the voltage V_DSacross the low side MOSFET.

START UP/SOFT-START

When V_CCexceeds 2.76V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an

internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start

capacitor C_SSis connected internally to the non-inverting input of the error amplifier. The soft-start period lasts

until the voltage on the soft-start capacitor exceeds the LM2743 reference voltage of 0.6V. At this point the

reference voltage takes over at the non-inverting error amplifier input. The capacitance of C_SSdetermines the

length of the soft-start period, and can be approximated by:

t_SS

C_SS

=

60

Where C_SSis in µF and t_SSis in ms.

During soft start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of

0.6V. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage

monitoring starts.

NORMAL OPERATION

While in normal operation mode, the LM2743 regulates the output voltage by controlling the duty cycle of the

high side and low side MOSFETs (see Figure 1). The equation governing output voltage is:

R_FB1+ R_FB2

V_OUT

=

V_FB

R_FB1

(V_FB= 0.6V)

The PWM frequency is adjustable between 50 kHz and 1 MHz and is set by an external resistor, R_FADJ, between

the FREQ pin and ground. The resistance needed for a desired frequency is approximately:

10¹²

10⁷

f_SW

+ 0.24

R_FADJ= -5.93 + 3.06

2

(f_SW

)

Where f_SWis in Hz and R_FADJis in kΩ.

TRACKING A VOLTAGE LEVEL

The LM2743 can track the output of a master power supply during soft-start by connecting a resistor divider to

the SS/TRACK pin. In this way, the output voltage slew rate of the LM2743 will be controlled by the master

supply for loads that require precise sequencing. When the tracking function is used no soft-start capacitor

should be connected to the SS/TRACK pin. Otherwise, a C_SSvalue of at least 1 nF between the soft-start pin

and ground should be used.

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Master Power

Supply

V

= 5V

OUT1

R

T2

1 kW

V

OUT2

= 1.8V

SS/TRACK

LM2743

V

= 0.65V

SS

R

T1

FB2

FB

150W

10 kW

V

FB

R

FB1

5 kW

Figure 23. Tracking Circuit

One way to use the tracking feature is to design the tracking resistor divider so that the master supply’s output

voltage (V_OUT1) and the LM2743’s output voltage (represented symbolically in Figure 23 as V_OUT2, i.e. without

explicitly showing the power components) both rise together and reach their target values at the same time. For

this case, the equation governing the values of the tracking divider resistors R_T1and R_T2is:

R_T1

0.65 = V_OUT1

R_T1+ R_T2

The current through R_T1should be about 3 mA to 4 mA for precise tracking. The final voltage of the SS/TRACK

pin should be set higher than the feedback voltage of 0.6V (say about 0.65V as in the above equation). If the

master supply voltage was 5V and the LM2743 output voltage was 1.8V, for example, then the value of R_T1

needed to give the two supplies identical soft-start times would be 150Ω. A timing diagram for the equal soft-start

time case is shown in Figure 24.

5V

V_OUT1

1.8V

V_OUT2

Figure 24. Tracking with Equal Soft-Start Time

TRACKING A VOLTAGE SLEW RATE

The tracking feature can alternatively be used not to make both rails reach regulation at the same time but rather

to have similar rise rates (in terms of output dV/dt). This method ensures that the output voltage of the LM2743

always reaches regulation before the output voltage of the master supply. Because the output of the master

supply is divided down, in order to track properly the output voltage of the LM2743 must be lower than the

voltage of the master supply. In this case, the tracking resistors can be determined based on the following

equation:

R_T1

V_OUT2

=

V_OUT1

R_T1+ R_T2

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For the example case of V_OUT1= 5V and V_OUT2= 1.8V, with R_T1set to 150Ω as before, R_T2is calculated from the

above equation to be 265Ω. A timing diagram for the case of equal slew rates is shown in Figure 25.

5V

1.8V

V_OUT1

1.8V

V_OUT2

Figure 25. Tracking with Equal Slew Rates

SEQUENCING

The start up/soft-start of the LM2743 can be delayed for the purpose of sequencing by connecting a resistor

divider from the output of a master power supply to the SD pin, as shown in Figure 26.

Master Power

Supply

V_OUT1

R_S2

V_OUT2

SD

LM2743

R_FB2

V_FB

R_S1

FB

R_FB1

Figure 26. Sequencing Circuit

A desired delay time t_DELAYbetween the startup of the master supply output voltage and the LM2743 output

voltage can be set based on the SD pin low-to-high threshold V_SD-IHand the slew rate of the voltage at the SD

pin, SR_SD

:

t_DELAY= V_SD-IH/ SR_SD

Note again, that in Figure 26, the LM2743’s output voltage has been represented symbolically as V_OUT2, i.e.

without explicitly showing the power components.

V_SD-IHis typically 1.08V and SR_SDis the slew rate of the SD pin voltage. The values of the sequencing divider

resistors R_S1and R_S2set the SR_SDbased on the master supply output voltage slew rate, SR_OUT1, using the

following equation:

R_S1

SR_SD= SR_OUT1

R_S1+ R_S2

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For example, if the master supply output voltage slew rate was 1V/ms and the desired delay time between the

startup of the master supply and LM2743 output voltage was 5ms, then the desired SD pin slew rate would be

(1.08V/5 ms) = 0.216V/ms. Due to the internal impedance of the SD pin, the maximum recommended value for

R_S2is 1kΩ. To achieve the desired slew rate, R_S1would then be 274Ω. A timing diagram for this example is

shown in Figure 27.

5V

V

SD-IH

1.08V

V

OUT1

1.8V

V

OUT2

t = 5 ms

Figure 27. Delay for Sequencing

SD PIN IMPEDANCE

When connecting a resistor divider to the SD pin of the LM2743 some care has to be taken. Once the SD voltage

goes above V_SD-IH, a 17 µA pull-up current is activated as shown in Figure 28. This current is used to create the

internal hysteresis (≊170 mV); however, high external impedances will affect the SD pin logic thresholds as well.

The external impedance used for the sequencing divider network should preferably be a small fraction of the

impedance of the SD pin for good performance (around 1kΩ).

17 mA

8 mA

Bias Enable

SD

10k

Soft-Start Enable

+

-

1.25V

Figure 28. SD Pin Logic

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MOSFET GATE DRIVERS

The LM2743 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Note that

unlike most other synchronous controllers, the bootstrap capacitor of the LM2743 provides power not only to the

driver of the upper MOSFET, but the lower MOSFET driver too (both drivers are ground referenced, i.e. no

floating driver). To fully turn the top MOSFET on, the BOOT voltage must be at least one gate threshold greater

than V_INwhen the high-side drive goes high. This bootstrap voltage is usually supplied from a local charge pump

structure. But looking at the Typical Application schematic, this also means that the difference voltage V_CC- V_D1

,

which is the voltage the bootstrap capacitor charges up to, must be always greater than the maximum tolerance

limit of the threshold voltage of the upper MOSFET. Here V_D1is the forward voltage drop across the bootstrap

diode D1. This therefore may place restrictions on the minimum input voltage and/or type of MOSFET used.

The most basic charge bootstrap pump circuit can be built using one Schottky diode and a small capacitor, as

shown in Figure 29. The capacitor C_BOOTserves to maintain enough voltage between the top MOSFET gate and

source to control the device even when the top MOSFET is on and its source has risen up to the input voltage

level. The charge pump circuitry is fed from V_CC, which can operate over a range from 3.0V to 6.0V. Using this

basic method the voltage applied to the gates of both high-side and low-side MOSFETs is V_CC- V_D. This method

works well when V_CCis 5V±10%, because the gate drives will get at least 4.0V of drive voltage during the worst

case of V_CC-MIN= 4.5V and V_D-MAX= 0.5V. Logic level MOSFETs generally specify their on-resistance at V_GS

=

4.5V. When V_CC= 3.3V±10%, the gate drive at worst case could go as low as 2.5V. Logic level MOSFETs are

not specified to turn on, or may have much higher on-resistance at 2.5V. Sub-logic level MOSFETs, usually

specified at V_GS= 2.5V, will work, but are more expensive, and tend to have higher on-resistance. The circuit in

Figure 29 works well for input voltages ranging from 1V up to 16V and V_CC= 5V ±10%, because the drive

voltage depends only on V_CC

.

LM2743

BOOT

D1

V

CC

C

BOOT

V

IN

O

HG

+

V

LG

Figure 29. Basic Charge Pump (Bootstrap)

Note that the LM2743 can be paired with a low cost linear regulator like the LM78L05 to run from a single input

rail between 6.0 and 14V. The 5V output of the linear regulator powers both the V_CCand the bootstrap circuit,

providing efficient drive for logic level MOSFETs. An example of this circuit is shown in Figure 30.

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LM2743

V

CC

5V

LM78L05

D1

BOOT

C

BOOT

V

IN

+

HG

LG

V

O

+

Figure 30. LM78L05 Feeding Basic Charge Pump

Figure 31 shows a second possibility for bootstrapping the MOSFET drives using a doubler. This circuit provides

an equal voltage drive of V_CC- 3V_D+ V_INto both the high-side and low-side MOSFET drives. This method should

only be used in circuits that use 3.3V for both V_CCand V_IN. Even with V_IN= V_CC= 3.0V (10% lower tolerance on

3.3V) and V_D= 0.5V both high-side and low-side gates will have at least 4.5V of drive. The power dissipation of

the gate drive circuitry is directly proportional to gate drive voltage, hence the thermal limits of the LM2743 IC will

quickly be reached if this circuit is used with V_CCor V_INvoltages over 5V.

LM2743

BOOT

D1

D3

D2

V

CC

V

IN

HG

+

V

O

LG

Figure 31. Charge Pump with Added Gate Drive

All the gate drive circuits shown in the above figures typically use 100 nF ceramic capacitors in the bootstrap

locations.

POWER GOOD SIGNAL

The open drain output on the Power Good pin needs a pull-up resistor to a low voltage source. The pull-up

resistor should be chosen so that the current going into the Power Good pin is less than 1 mA. A 100 kΩ resistor

is recommended for most applications.

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The Power Good signal is an OR-gated flag which takes into account both output over-voltage and under-voltage

conditions. If the feedback pin (FB) voltage is 18% above its nominal value (118% x V_FB= 0.708V) or falls 28%

below that value (72 %x V_FB= 0.42V) the Power Good flag goes low. The Power Good flag can be used to signal

other circuits that the output voltage has fallen out of regulation, however the switching of the LM2743 continues

regardless of the state of the Power Good signal. The Power Good flag will return to logic high whenever the

feedback pin voltage is between 72% and 118% of 0.6V.

UVLO

The 2.76V turn-on threshold on V_CChas a built in hysteresis of about 300 mV. If V_CCdrops below 2.42V, the chip

enters UVLO mode. UVLO consists of turning off the top and bottom MOSFETS and remaining in that condition

until V_CCrises above 2.76V. As with shutdown, the soft-start capacitor is discharged through an internal

MOSFET, ensuring that the next start-up will be controlled by the soft-start circuitry.

CURRENT LIMIT

Current limit is realized by sensing the voltage across the low-side MOSFET while it is on. The R_DS(ON)of the

MOSFET is a known value; hence the current through the MOSFET can be determined as:

V_DS= I_OUTx R_DS(ON)

The current through the low-side MOSFET while it is on is also the falling portion of the inductor current. The

current limit threshold is determined by an external resistor, R_CS, connected between the switching node and the

I_SENpin. A constant current of 40 µA is forced through R_CS, causing a fixed voltage drop. This fixed voltage is

compared against V_DSand if the latter is higher, the current limit of the chip has been reached. To obtain a more

accurate value for R_CSyou must consider the operating values of R_DS(ON)and I_SEN-THat their operating

temperatures in your application and the effect of slight parameter differences from part to part. R_CScan be found

by using the following equation using the R_DS(ON)value of the low side MOSFET at it's expected hot temperature

and the absolute minimum value expected over the full temperature range for the for the I_SEN-THwhich is 25 µA:

R_CS= R_DSON-HOTx I_LIM/ 40 µA

For example, a conservative 15A current limit in a 10A design with a minimum R_DS(ON)of 10 mΩ would require a

6 kΩ resistor. To prevent the I_SENpin from sinking too much current when the switch node goes above 9.5V, the

value of the current limit setting resistor R_CSshould not be too low. The criterion is as follows,

í ^{V œ 9.5V}

IN

R_CS

10 mA

where the 10 mA is the maximum current I_SENpin is allowed to sink. For example if V_IN= 13.2V, the minimum

value of R_CSis 370Ω. Because current sensing is done across the low-side MOSFET, no minimum high-side on-

time is necessary. The LM2743 enters current limit mode if the inductor current exceeds the current limit

threshold at the point where the high-side MOSFET turns off and the low-side MOSFET turns on. (The point of

peak inductor current, see Figure 32). Note that in normal operation mode the high-side MOSFET always turns

on at the beginning of a clock cycle. In current limit mode, by contrast, the high-side MOSFET on-pulse is

skipped. This causes inductor current to fall. Unlike a normal operation switching cycle, however, in a current

limit mode switching cycle the high-side MOSFET will turn on as soon as inductor current has fallen to the

current limit threshold. The LM2743 will continue to skip high-side MOSFET pulses until the inductor current peak

is below the current limit threshold, at which point the system resumes normal operation.

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Normal Operation

Current Limit

I_LIM

I_L

D

Figure 32. Current Limit Threshold

Unlike a high-side MOSFET current sensing scheme, which limits the peaks of inductor current, low-side current

sensing is only allowed to limit the current during the converter off-time, when inductor current is falling.

Therefore in a typical current limit plot the valleys are normally well defined, but the peaks are variable, according

to the duty cycle. The PWM error amplifier and comparator control the off-pulse of the high-side MOSFET, even

during current limit mode, meaning that peak inductor current can exceed the current limit threshold. Assuming

that the output inductor does not saturate, the maximum peak inductor current during current limit mode can be

calculated with the following equation:

V_IN- V_O

I_PK-CL= I_LIM+ (T_SW- 200 ns)

L

Where T_SWis the inverse of switching frequency f_SW. The 200 ns term represents the minimum off-time of the

duty cycle, which ensures enough time for correct operation of the current sensing circuitry.

In order to minimize the time period in which peak inductor current exceeds the current limit threshold, the IC

also discharges the soft-start capacitor through a fixed 90 µA sink. The output of the LM2743 internal error

amplifier is limited by the voltage on the soft-start capacitor. Hence, discharging the soft-start capacitor reduces

the maximum duty cycle D of the controller. During severe current limit this reduction in duty cycle will reduce the

output voltage if the current limit conditions last for an extended time. Output inductor current will be reduced in

turn to a flat level equal to the current limit threshold. The third benefit of the soft-start capacitor discharge is a

smooth, controlled ramp of output voltage when the current limit condition is cleared.

FOLDBACK CURRENT LIMIT

In the case where extra protection is used to help an output short condition, a current foldback resistor (R_CLF

)

should be considered, see Figure 33. First select the percentage of current limit foldback (P_LIM):

P_LIM= I_LIMx P

where P is a ratio between 0 and 1.

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V_OUT

40 mA

R_CLF

R_CS

-

SW

ILIM

I_SEN

+

Figure 33. Foldback Current Limit Circuit

Obtain the R_CSwith the following equation:

P_LIMx R_DS(ON)

= R_CS

I_SEN

where I_SEN= 40 μA. If the switch node goes above 9.5V the following criterion must be satisfied:

í ^{V œ 9.5V}

IN

R_CS

10 mA

The equation for calculating the foldback resistance value is:

R_CSx V_OUT

R_CLF

=

(I_LIMx R_DS(ON)) œ (I_SENx R_CS

)

SHUTDOWN

If the shutdown pin is pulled low, (below 0.8V) the LM2743 enters shutdown mode, and discharges the soft-start

capacitor through a MOSFET switch. The high and low-side MOSFETs are turned off. The LM2743 remains in

this state as long as V_SDsees a logic low (see the Electrical Characteristics table). To assure proper IC start-up

the shutdown pin should not be left floating. For normal operation this pin should be connected directly to V_CCor

to another voltage between 1.3V to V_CC(see the Electrical Characteristics table).

DESIGN CONSIDERATIONS

The following is a design procedure for all the components needed to create the Figure 1. This design converts

3.3V (V_IN) to 1.2V (V_OUT) at a maximum load of 4A with an efficiency of 89% and a switching frequency of 300

kHz. The same procedures can be followed to create many other designs with varying input voltages, output

voltages, and load currents.

Duty Cycle Calculation

The complete duty cycle for a buck converter is defined with the following equation:

V_OUT+ V_SWL

D =

V_IN- V_SWH+ V_SWL

where V_SWLand V_SWHare the respective forward voltage drops that develop across the low side and high side

MOSFETs. Assuming the inductor ripple current is 20% to 30% of the output current, therefore:

V_SWL= I_OUTx R_DS(ON)LOW(Low-Side MOSFET)

V_SWH= I_OUTx R_DS(ON)HIGH(High-Side MOSFET)

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To calculate the maximum duty cycle use the estimated 'hot' R_DS(on)value of the MOSFETs, the minimum input

voltage, and maximum load. As shown in Figure 34, the worst case maximum duty cycles of the LM2743 occurs

at 125°C junction temperature vs V_CC(IC control section voltage). Ensure that the operating duty cycle is below

the curve in Figure 34, if this condition is not satisfied, the system will be unable to develop the required duty

cycle to derive the necessary system power and so the output voltage will fall out of regulation.

Figure 34. Maximum Duty Cycle vs V_CC

T_J= 125°C

Input Capacitor

The input capacitors in a Buck converter are subjected to high stress due to the input current trapezoidal

waveform. Input capacitors are selected for their ripple current capability and their ability to withstand the heat

generated since that ripple current passes through their ESR. Input rms ripple current is approximately:

I_{RMS_RIP}= I_OUT

x

D(1 - D)

The power dissipated by each input capacitor is:

(I_{RMS_RIP})²x ESR

P_CAP

=

n²

where n is the number of capacitors, and ESR is the equivalent series resistance of each capacitor. The equation

above indicates that power loss in each capacitor decreases rapidly as the number of input capacitors increases.

The worst-case ripple for a Buck converter occurs during full load and when the duty cycle (D) is 0.5. For this

3.3V to 1.2V design the duty cycle is 0.364. For a 4A maximum load the ripple current is 1.92A.

Output Inductor

The output inductor forms the first half of the power stage in a Buck converter. It is responsible for smoothing the

square wave created by the switching action and for controlling the output current ripple (ΔI_OUT). The inductance

is chosen by selecting between tradeoffs in efficiency and response time. The smaller the output inductor, the

more quickly the converter can respond to transients in the load current. However, as shown in the efficiency

calculations, a smaller inductor requires a higher switching frequency to maintain the same level of output current

ripple. An increase in frequency can mean increasing loss in the MOSFETs due to the charging and discharging

of the gates. Generally the switching frequency is chosen so that conduction loss outweighs switching loss. The

equation for output inductor selection is:

V_IN- V_OUT

x D

L =

DI_OUTx f_SW

3.3V - 1.2V

1.2V

3.3V

x

L =

0.4 x 4A x 300 kHz

L = 1.6µH

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Here we have plugged in the values for output current ripple, input voltage, output voltage, switching frequency,

and assumed a 40% peak-to-peak output current ripple. This yields an inductance of 1.6 µH. The output inductor

must be rated to handle the peak current (also equal to the peak switch current), which is (I_OUT+ (0.5 x ΔI_OUT)) =

4.8A, for a 4A design. The Coilcraft DO3316P-222P is 2.2 µH, is rated to 7.4A peak, and has a direct current

resistance (DCR) of 12 mΩ.

After selecting an output inductor, inductor current ripple should be re-calculated with the new inductance value,

as this information is needed to select the output capacitor. Re-arranging the equation used to select inductance

yields the following:

V_IN(MAX)- V_O

x D

DI_OUT

=

F_SWx L_ACTUAL

V_IN(MAX)is assumed to be 10% above the steady state input voltage, or 3.6V. The actual current ripple will then

be 1.2A. Peak inductor/switch current will be 4.6A.

Output Capacitor

The output capacitor forms the second half of the power stage of a Buck switching converter. It is used to control

the output voltage ripple (ΔV_OUT) and to supply load current during fast load transients.

In this example the output current is 4A and the expected type of capacitor is an aluminum electrolytic, as with

the input capacitors. Other possibilities include ceramic, tantalum, and solid electrolyte capacitors, however the

ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums

tend to be more expensive than aluminum electrolytic. Aluminum capacitors tend to have very high capacitance

and fairly low ESR, meaning that the ESR zero, which affects system stability, will be much lower than the

switching frequency. The large capacitance means that at the switching frequency, the ESR is dominant, hence

the type and number of output capacitors is selected on the basis of ESR. One simple formula to find the

maximum ESR based on the desired output voltage ripple, ΔV_OUTand the designed output current ripple, ΔI_OUT

,

is:

DV_OUT

ESR_MAX

=

DI_OUT

In this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor

current ripple, the required maximum ESR is 20 mΩ. The Sanyo 4SP560M electrolytic capacitor will give an

equivalent ESR of 14 mΩ. The capacitance of 560 µF is enough to supply energy even to meet severe load

transient demands.

MOSFETs

Selection of the power MOSFETs is governed by a tradeoff between cost, size, and efficiency. One method is to

determine the maximum cost that can be endured, and then select the most efficient device that fits that price.

Breaking down the losses in the high-side and low-side MOSFETs and then creating spreadsheets is one way to

determine relative efficiencies between different MOSFETs. Good correlation between the prediction and the

bench result is not specified, however. Single-channel buck regulators that use a controller IC and discrete

MOSFETs tend to be most efficient for output currents of 2A to 10A.

Losses in the high-side MOSFET can be broken down into conduction loss, gate charging loss, and switching

loss. Conduction loss, or I²R loss, is approximately:

P_C= D ((I_O)²x R_DSON-HIx 1.3) (High-Side MOSFET)

P_C= (1 - D) x ((I_O)²x R_DSON-LOx 1.3) (Low-Side MOSFET)

In the above equations the factor 1.3 accounts for the increase in MOSFET R_DSONdue to heating. Alternatively,

the 1.3 can be ignored and the R_DSONof the MOSFET estimated using the R_DSONVs. Temperature curves in the

MOSFET datasheets.

Gate charging loss results from the current driving the gate capacitance of the power MOSFETs, and is

approximated as:

P_GC= n x (V_DD) x Q_Gx f_SW

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where ‘n’ is the number of MOSFETs (if multiple devices have been placed in parallel), V_DDis the driving voltage

(see MOSFET GATE DRIVERS section) and Q_GSis the gate charge of the MOSFET. If different types of

MOSFETs are used, the ‘n’ term can be ignored and their gate charges simply summed to form a cumulative Q_G.

Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the

LM2743, and not in the MOSFET itself.

Switching loss occurs during the brief transition period as the high-side MOSFET turns on and off, during which

both current and voltage are present in the channel of the MOSFET. It can be approximated as:

P_SW= 0.5 x V_INx I_Ox (t_r+ t_f) x f_SW

where t_Rand t_Fare the rise and fall times of the MOSFET. Switching loss occurs in the high-side MOSFET only.

For this example, the maximum drain-to-source voltage applied to either MOSFET is 3.6V. The maximum drive

voltage at the gate of the high-side MOSFET is 3.1V, and the maximum drive voltage for the low-side MOSFET

is 3.3V. Due to the low drive voltages in this example, a MOSFET that turns on fully with 3.1V of gate drive is

needed. For designs of 5A and under, dual MOSFETs in SOIC-8 package provide a good trade-off between size,

cost, and efficiency.

Support Components

C_IN2 - A small value (0.1 µF to 1 µF) ceramic capacitor should be placed as close as possible to the drain of the

high-side MOSFET and source of the low-side MOSFET (dual MOSFETs make this easy). This capacitor should

be X5R type dielectric or better.

R_CC, C_CC- These are standard filter components designed to ensure smooth DC voltage for the chip supply. R_CC

should be 1Ω to 10Ω. C_CCshould 1 µF, X5R type or better.

C_BOOT- Bootstrap capacitor, typically 100 nF.

R_PULL-UP– This is a standard pull-up resistor for the open-drain power good signal (PWGD). The recommended

value is 10 kΩ connected to V_CC. If this feature is not necessary, the resistor can be omitted.

D₁- A small Schottky diode should be used for the bootstrap. It allows for a minimum drop for both high and low-

side drivers. The MBR0520 or BAT54 work well in most designs.

R_CS- Resistor used to set the current limit. Since the design calls for a peak current magnitude (I_OUT+ (0.5 x

ΔI_OUT)) of 4.8A, a safe setting would be 6A. (This is below the saturation current of the output inductor, which is

7A.) Following the equation from the CURRENT LIMIT section, a 1.3 kΩ resistor should be used.

R_FADJ- This resistor is used to set the switching frequency of the chip. The resistor value is calculated from

equation in NORMAL OPERATION section. For 300 kHz operation, a 97.6 kΩ resistor should be used.

C_SS- The soft-start capacitor depends on the user requirements and is calculated based on the equation given in

the section titled START UP/SOFT-START. Therefore, for a 700 μs delay, a 12 nF capacitor is suitable.

Control Loop Compensation

The LM2743 uses voltage-mode (‘VM’) PWM control to correct changes in output voltage due to line and load

transients. One of the attractive advantages of voltage mode control is its relative immunity to noise and layout.

However VM requires careful small signal compensation of the control loop for achieving high bandwidth and

good phase margin.

The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle

modulator, output inductor, output capacitor, and load. The second part is the error amplifier, which for the

LM2743 is a 9 MHz op-amp used in the classic inverting configuration. Figure 35 shows the regulator and control

loop components.

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R

L

+

C

O

V

IN

R

O

+

-

R

C

V

RAMP

-

+

R

C2

C

R

C1

C2

10 kW

C

C3

C

C1

-

+

-

V

REF

Figure 35. Power Stage and Error Amp

One popular method for selecting the compensation components is to create Bode plots of gain and phase for

the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the

regulator easy to see. Software tools such as Excel, MathCAD, and Matlab are useful for showing how changes

in compensation or the power stage affect system gain and phase.

The power stage modulator provides a DC gain A_DCthat is equal to the input voltage divided by the peak-to-peak

value of the PWM ramp. This ramp is 1.0VP-P for the LM2743. The inductor and output capacitor create a

double pole at frequency f_DP, and the capacitor ESR and capacitance create a single zero at frequency f_ESR. For

this example, with V_IN= 3.3V, these quantities are:

V_IN

3.3

=

= 10.4 dB

A_DC

=

1.0

V_RAMP

R_O+ R_L

LC_O(R_O+ ESR)

1

2p

f_DP

=

= 4.5 kHz

1

= 20.3 kHz

f_ESR

=

2pC_OESR

In the equation for f_DP, the variable R_Lis the power stage resistance, and represents the inductor DCR plus the

on resistance of the top power MOSFET. R_Ois the output voltage divided by output current. The power stage

transfer function G_PSis given by the following equation, and Figure 36 shows Bode plots of the phase and gain in

this example.

V_INx R_O

V_RAMP

sC_OR_C+ 1

a x s²+ b x s + c

x

G_PS

=

a = LC_O(R_O+ R_C)

b = L + C_O(R_OR_L+ R_OR_C+ R_CR_L)

c = R_O+ R_L

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20

4

-12

-28

-44

-60

100

1k

10k

100k

1M

FREQUENCY (Hz)

0

-30

-60

-90

-120

-150

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 36. Power Stage Gain and Phase

The double pole at 4.5 kHz causes the phase to drop to approximately -130° at around 10 kHz. The ESR zero, at

20.3 kHz, provides a +90° boost that prevents the phase from dropping to -180º. If this loop were left

uncompensated, the bandwidth would be approximately 10 kHz and the phase margin 53°. In theory, the loop

would be stable, but would suffer from poor DC regulation (due to the low DC gain) and would be slow to

respond to load transients (due to the low bandwidth.) In practice, the loop could easily become unstable due to

tolerances in the output inductor, capacitor, or changes in output current, or input voltage. Therefore, the loop is

compensated using the error amplifier and a few passive components.

For this example, a Type III, or three-pole-two-zero approach gives optimal bandwidth and phase.

In most voltage mode compensation schemes, including Type III, a single pole is placed at the origin to boost DC

gain as high as possible. Two zeroes f_Z1and f_Z2are placed at the double pole frequency to cancel the double

pole phase lag. Then, a pole, f_P1is placed at the frequency of the ESR zero. A final pole f_P2is placed at one-half

of the switching frequency. The gain of the error amplifier transfer function is selected to give the best bandwidth

possible without violating the Nyquist stability criteria. In practice, a good crossover point is one-fifth of the

switching frequency, or 60 kHz for this example. The generic equation for the error amplifier transfer function is:

s

+ 1

2pf_Z1

2pf_Z2

G_EA= A_EA

x

s

+ 1

s

+ 1

2pf_P1

2pf_P2

In this equation the variable A_EAis a ratio of the values of the capacitance and resistance of the compensation

components, arranged as shown in Figure 35. A_EAis selected to provide the desired bandwidth. A starting value

of 80,000 for A_EAshould give a conservative bandwidth. Increasing the value will increase the bandwidth, but will

also decrease phase margin. Designs with 45° to 60° are usually best because they represent a good trade-off

between bandwidth and phase margin. In general, phase margin is lowest and gain highest (worst-case) for

maximum input voltage and minimum output current. One method to select A_EAis to use an iterative process

beginning with these worst-case conditions.

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1. Increase A_EA

2. Check overall bandwidth and phase margin

3. Change V_INto minimum and recheck overall bandwidth and phase margin

4. Change I_Oto maximum and recheck overall bandwidth and phase margin

The process ends when the both bandwidth and the phase margin are sufficiently high. For this example input

voltage can vary from 3.0 to 3.6V and output current can vary from 0 to 4A, and after a few iterations a moderate

gain factor of 101dB is used.

The error amplifier of the LM2743 has a unity-gain bandwidth of 9 MHz. In order to model the effect of this

limitation, the open-loop gain can be calculated as:

2p x 9 MHz

OPG =

s

The new error amplifier transfer function that takes into account unity-gain bandwidth is:

G_EAx OPG

H_EA

=

1 + G_EA+ OPG

The gain and phase of the error amplifier are shown in Figure 37.

60

48

36

24

12

0

100

1k

10k

100k

1M

FREQUENCY (Hz)

50

20

-10

-40

-70

-100

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 37. Error Amp. Gain and Phase

In VM regulators, the top feedback resistor R_FB2forms a part of the compensation. Setting R_FB2to 10 kΩ, ±1%

usually gives values for the other compensation resistors and capacitors that fall within a reasonable range.

(Capacitances > 1pF, resistances < 1MΩ) C_C1, C_C2, C_C3, R_C1, and R_C2are selected to provide the poles and

zeroes at the desired frequencies, using the following equations:

f_Z1

= 27 pF

C_C1

=

A_EAx 10,000 x f_P2

24

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1

- C_C1= 882 pF

C_C2

=

A_EAx 10,000

1

x

-

C_C3

= 2.73 nF

f_Z2f_P1

2p x 10,000

1

= 39.8 kW

= 2.55 kW

R_C1

2p x C_C2x f_Z1

1

R_C2

=

2p x C_C3x f_P1

In practice, a good trade off between phase margin and bandwidth can be obtained by selecting the closest

±10% capacitor values above what are suggested for C_C1and C_C2, the closest ±10% capacitor value below the

suggestion for C_C3, and the closest ±1% resistor values below the suggestions for R_C1, R_C2. Note that if the

suggested value for R_C2is less than 100Ω, it should be replaced by a short circuit. Following this guideline, the

compensation components will be:

C_C1= 27pF ±10%

C_C2= 820pF ±10%

C_C3= 2.7nF ±10%

R_C1= 39.2kΩ ±1%

R_C2= 2.55kΩ ±1%

The transfer function of the compensation block can be derived by considering the compensation components as

impedance blocks Z_Fand Z_Iaround an inverting op-amp:

Z_F

G_EA-ACTUAL

=

Z_I

1

x

10,000 +

sC_C2

sC_C1

Z_F=

1

10,000 +

+

sC_C1sC_C2

1

R_C2

+

R_C1

sC_C3

Z₁=

1

+

R_C1+ R_C2

sC_C3

As with the generic equation, G_EA-ACTUALmust be modified to take into account the limited bandwidth of the error

amplifier. The result is:

G_EA-ACTUALx OPG

H_EA

=

1 + G_EA-ACTUAL+ OPG

The total control loop transfer function H is equal to the power stage transfer function multiplied by the error

amplifier transfer function.

H = G_PSx H_EA

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The bandwidth and phase margin can be read graphically from Bode plots of H_EAare shown in Figure 38.

60

40

20

0

-20

-40

100

1k

10k

100k

1M

FREQUENCY (Hz)

-60

-84

-108

-132

-156

-180

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 38. Overall Loop Gain and Phase

The bandwidth of this example circuit is 59 kHz, with a phase margin of 60°.

EFFICIENCY CALCULATIONS

The following is a sample calculation.

A reasonable estimation of the efficiency of a switching buck controller can be obtained by adding together the

Output Power (P_OUT) loss and the Total Power (P_TOTAL) loss:

P_OUT

x 100%

h =

P_OUT+ P_TOTAL

The Output Power (P_OUT) for the Figure 1 design is (1.2V x 4A) = 4.8W. The Total Power (P_TOTAL), with an

efficiency calculation to complement the design, is shown below.

The majority of the power losses are due to low and high side of MOSFET’s losses. The losses in any MOSFET

are group of switching (P_SW) and conduction losses(P_CND).

P_FET= P_SW+ P_CND= 61.38 mW + 270.42 mW

P_FET= 331.8 mW

FET Switching Loss (P_SW

)

P_SW= P_SW(ON)+ P_SW(OFF)

P_SW= 0.5 x V_INx I_OUTx (t_r+ t_f) x f_SW

P_SW= 0.5 x 3.3V x 4A x 300 kHz x 31 ns

P_SW= 61.38 mW

26

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SNVS276G –APRIL 2004–REVISED MARCH 2013

The FDS6898A has a typical turn-on rise time t_rand turn-off fall time t_fof 15 ns and 16 ns, respectively. The

switching losses for this type of dual N-Channel MOSFETs are 0.061W.

FET Conduction Loss (P_CND

)

P_CND= P_CND1+ P_CND2

P_CND1= (I_OUT)²x R_DS(ON)x k x D

P_CND2= (I_OUT)²x R_DS(ON)x k x (1-D)

R_DS(ON)= 13 mΩ and the factor is a constant value (k = 1.3) to account for the increasing R_DS(ON)of a FET due to

heating.

P_CND1= (4A)²x 13 mΩ x 1.3 x 0.364

P_CND2= (4A)²x 13 mΩ x 1.3 x (1 - 0.364)

P_CND= 98.42 mW + 172 mW = 270.42 mW

There are few additional losses that are taken into account:

IC Operating Loss (P_IC)

P_IC= I_{Q_VCC}x V_CC

,

where I_Q-VCCis the typical operating V_CCcurrent

P_IC= 1.5 mA x 3.3V = 4.95 mW

FET Gate Charging Loss (P_GATE

)

P_GATE= n x V_CCx Q_GSx f_SW

P_GATE= 2 x 3.3V x 3 nC x 300 kHz

P_GATE= 5.94 mW

The value n is the total number of FETs used and Q_GSis the typical gate-source charge value, which is 3 nC. For

the FDS6898A the gate charging loss is 5.94 mW.

Input Capacitor Loss (P_CAP

)

(I_{RMS_RIP})²x ESR

P_CAP

=

n²

where,

I_{RMS_RIP}= I_OUT

x

D(1 - D)

Here n is the number of paralleled capacitors, ESR is the equivalent series resistance of each, and P_CAPis the

dissipation in each. So for example if we use only one input capacitor of 24 mΩ.

(1.924A)²x 24 mW

P_CAP

=

1²

P_CAP= 88.8 mW

Output Inductor Loss (P_IND

)

P_IND= I²_OUTx DCR

where DCR is the DC resistance. Therefore, for example

P_IND= (4A)²x 11 mΩ

P_IND= 176 mW

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Total System Efficiency

P_TOTAL= P_FET+ P_IC+ P_GATE+ P_CAP+ P_IND

P_OUT

x 100%

h =

P_OUT+ P_TOTAL

4.8W

= 89%

4.8W + 0.6W

Example Circuits

V

= V = 3.3V

IN

CC

D

C

BOOT

1

R

PULL-UP

+

C

IN

1,2

Q1

R

CC

V

HG

CC

SD

BOOT

R

CS

C

CC

L1

V

OUT

= 1.8V@2A

I

PWGD

FREQ

SS/TRACK

SGND

EAO

SEN

LM2743

LG

PGND

FB

R

FADJ

+

R

FB2

C

O

1,2

C

SS

R

C2

C_C3

R

FB1

C

C1

C

C2

R

C1

Figure 39. 3.3V to 1.8V @ 2A, f_SW= 300kHz

Table 1. Bill of Materials

PART

PART NUMBER

TYPE

PACKAGE

DESCRIPTION

VENDOR

U1

LM2743

Synchronous

Controller

TSSOP-14

TI

Q1

FDS6898A

Dual N-MOSFET

SOIC-8

20V, 10mΩ@ 4.5V,

Fairchild

16nC

D1

L1

MBR0520LTI

DO3316P-472

16SP100M

Schottky Diode

Inductor

SOD-123

4.7µH, 4.8Arms 18mΩ Coilcraft

C_IN

1

Aluminum Electrolytic 10mm x 6mm

100µF, 16V, 2.89Arms Sanyo

C_O1

6SP220M

220µF, 6.3V 3.1Arms

0.1µF, 10%

Sanyo

Vishay

C_CC, C_BOOT,

C_IN2, C_O2

VJ1206Y104KXXA

Capacitor

1206

C_C3

VJ0805Y332KXXA

VJ0805A123KXAA

VJ0805A821KXAA

VJ0805A220KXAA

CRCW08051002F

CRCW08054991F

CRCW08051103F

CRCW08052101F

Capacitor

Resistor

805

3300pF, 10%

12nF, 10%

820pF 10%

22pF, 10%

10.0kΩ 1%

4.99kΩ1%

110kΩ 1%

2.1kΩ 1%

Vishay

C_SS

C_C2

C_C1

R_FB2

R_FB1

R_FADJ

R_C2

R_CS

2.1 kΩ 1%

28

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SNVS276G –APRIL 2004–REVISED MARCH 2013

Table 1. Bill of Materials (continued)

PART

R_CC

PART NUMBER

CRCW080510R0F

CRCW08055492F

CRCW08051003J

TYPE

PACKAGE

805

DESCRIPTION

10.0Ω 1%

VENDOR

Vishay

Resistor

R_C1

805

54.9kΩ 1%

100kΩ 5%

Vishay

R_PULL-UP

805

Vishay

V

= 5V

CC

D

C

1

BOOT

V

IN

= 5V

R

PULL-UP

+

C

1,2

IN

Q1

R

CC

V

CC

HG

SD

BOOT

R

C

CC

CS

L1

V

OUT

= 2.5V@2A

I

PWGD

FREQ

SS/TRACK

SGND

EAO

SEN

LM2743

LG

PGND

FB

R

FADJ

+

R

FB2

C 1,2

O

C

SS

R

C

C2

C3

R

FB1

C

C1

C

C2

R

C1

Figure 40. 5V to 2.5V @ 2A, f_SW= 300kHz

Table 2. Bill of Materials

PART

PART NUMBER

TYPE

PACKAGE

DESCRIPTION

VENDOR

U1

LM2743

Synchronous

Controller

TSSOP-14

TI

Q1

D1

L1

FDS6898A

Dual N-MOSFET

Schottky Diode

Inductor

SOIC-8

20V, 10mΩ@ 4.5V, 16nC

Fairchild

MBR0520LTI

DO3316P-682

16SP100M

SOD-123

6.8µH, 4.4Arms, 27mΩ

Coilcraft

Sanyo

C_IN

1

Aluminum

Electrolytic

10mm x 6mm

6.3mm x 6mm

1206

100µF, 16V, 2.89Arms

C_O1

10SP56M

Aluminum

Electrolytic

56µF, 10V 1.7Arms

0.1µF, 10%

Sanyo

Vishay

C_CC, C_BOOT,

C_IN2, C_O2

VJ1206Y104KXXA

Capacitor

C_C3

VJ0805Y182KXXA

VJ0805A123KXAA

VJ0805A821KXAA

VJ0805A330KXAA

CRCW08051002F

CRCW08053161F

CRCW08051103F

CRCW08051301F

CRCW08052101F

CRCW080510R0F

CRCW08053322F

CRCW08051003J

Capacitor

Resistor

805

1800pF, 10%

12nF, 10%

820pF 10%

33pF, 10%

10.0kΩ 1%

3.16kΩ 1%

110kΩ 1%

1.3kΩ 1%

Vishay

C_SS

C_C2

C_C1

R_FB2

R_FB1

R_FADJ

R_C2

R_CS

2.1 kΩ 1%

10.0Ω 1%

33.2kΩ 1%

100kΩ 5%

R_CC

R_C1

R_PULL-UP

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V

= 5V

CC

D

C

1

BOOT

V

IN

= 12V

R

PULL-UP

+

C

1,2

IN

Q1

R

CC

V

CC

HG

SD

BOOT

R

C

CC

CS

L1

V

OUT

= 3.3V@4A

I

PWGD

FREQ

SS/TRACK

SGND

EAO

SEN

LM2743

LG

PGND

FB

R

FADJ

+

R

FB2

C 1,2

O

C

SS

R

C

C2

C3

R

FB1

C

C1

C

C2

R

C1

Figure 41. 12V to 3.3V @ 4A, f_SW= 300kHz

Table 3. Bill of Materials

PART

PART NUMBER

TYPE

PACKAGE

DESCRIPTION

VENDOR

U1

LM2743

Synchronous

Controller

TSSOP-14

TI

Q1

D1

L1

FDS6898A

Dual N-MOSFET

Schottky Diode

Inductor

SOIC-8

20V, 10mΩ@ 4.5V, 16nC Fairchild

MBR0520LTI

DO3316P-332

16SP100M

SOD-123

3.3µH, 5.4Arms 15mΩ

100µF, 16V, 2.89Arms

220µF, 6.3V 3.1Arms

0.1µF, 10%

Coilcraft

Sanyo

Vishay

C_IN

1

Aluminum Electrolytic 10mm x 6mm

C_O1

6SP220M

C_CC, C_BOOT,

C_IN2, C_O2

VJ1206Y104KXXA

Capacitor

1206

C_C3

VJ0805Y222KXXA

VJ0805A123KXAA

VJ0805Y332KXXA

VJ0805A820KXAA

CRCW08051002F

CRCW08052211F

CRCW08051103F

CRCW08052611F

CRCW08054121F

CRCW080510R0F

CRCW08051272F

CRCW08051003J

Capacitor

Resistor

805

2200pF, 10%

12nF, 10%

3300pF 10%

82pF, 10%

10.0kΩ 1%

2.21kΩ 1%

110kΩ 1%

2.61kΩ 1%

4.12 kΩ 1%

10.0Ω 1%

Vishay

C_SS

C_C2

C_C1

R_FB2

R_FB1

R_FADJ

R_C2

R_CS

R_CC

R_C1

12.7kΩ 1%

100kΩ 5%

R_PULL-UP

30

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SNVS276G –APRIL 2004–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision F (March 2013) to Revision G

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 30

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PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM2743MTCX

TSSOP

PW

14

2500

330.0

12.4

6.95

8.3

1.6

8.0

12.0

Q1

LM2743MTCX/NOPB

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM2743MTCX

TSSOP

PW

14

2500

367.0

35.0

LM2743MTCX/NOPB

Pack Materials-Page 2

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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型号：	LM2743MTCX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	LM2743 Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller 信息通信管理开关光电二极管
文件：	总37页 (文件大小：1390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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