LM2833XSD/NOPB [TI]

1.5MHz/3MHz 3.0A 降压直流/直流开关稳压器 | DSC | 10 | -40 to 125;


型号：	LM2833XSD/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	1.5MHz/3MHz 3.0A 降压直流/直流开关稳压器 \| DSC \| 10 \| -40 to 125 开关信息通信管理光电二极管稳压器
文件：	总32页 (文件大小：1399K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

LM2833 1.5MHz/3MHz 3.0A Step-Down DC-DC Switching Regulator

Check for Samples: LM2833

FEATURES

DESCRIPTION

The LM2833 regulator is a monolithic, high frequency,

PWM step-down DC/DC converter available in a 10-

pin WSON or MSOP-PowerPAD package. It contains

all the active functions to provide local DC/DC

conversion with fast transient response and accurate

regulation in the smallest possible PCB area. With a

minimum of external components, the LM2833 is

easy to use. The ability to drive 3.0A loads with an

internal 56 mΩ PMOS switch using state-of-the-art

0.5µm BiCMOS technology results in the best power

density available. The world-class control circuitry

allows on-times as low as 30ns, thus supporting

exceptionally high frequency conversion over the

entire 3V to 5.5V input operating range down to the

minimum output voltage of 0.6V. Switching frequency

is internally set to 1.5MHz or 3.0MHz, allowing the

use of extremely small surface mount inductors and

capacitors. Even though the operating frequency is

high, efficiencies up to 93% are easy to achieve.

External shutdown is included, featuring an ultra-low

stand-by current of 300nA. The LM2833 utilizes peak

current-mode control and internal compensation to

provide high-performance regulation over a wide

range of operating conditions. Additional features

include internal soft-start circuitry to reduce inrush

current, cycle-by-cycle current limit, frequency

foldback, thermal shutdown, and output over-voltage

protection.

•

Input Voltage Range of 3.0V to 5.5V

Output Voltage Range of 0.6V to 4.5V

Tiny MSOP-PowerPAD 10 or WSON-10

Package

•

3.0A Steady-State Output Current

High Switching Frequencies

–

1.5MHz (LM2833X)

3.0MHz (LM2833Z)

•

Enable Pin

56mΩ PMOS Switch

0.6V, 2% Internal Voltage Reference Over Line

and Temperature

•

Internal Soft-Start

Internally Compensated Peak Current-Mode

Control

•

Cycle-by-Cycle Current Limit and Thermal

Shutdown

•

Frequency Foldback Protection

Input Voltage UVLO (Under-Voltage Lockout)

Output Over-Voltage Protection

APPLICATIONS

•

Multimedia Set Top Box

Broadband Communications

Core Power in HDDs

Data Acquisition/Telemetry

USB Powered Devices

DSL Modems

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

Typical Application Circuit

OUT

7,8

9,10

VIND

LM2833

VINC

PGND

SGND

Connection Diagrams

10 VIND

VINC

VIND

VINC

VIND

SGND

DAP

SGND

DAP

PGND

Figure 1. 10-Pin WSON

See Package DSC

Figure 2. 10-pin MSOP-PowerPAD

See Package DGQ

PIN DESCRIPTIONS

Pin(s)

Name

Description

VINC

Input supply for internal bias and control circuitry. Need to locally bypass this pin to GND.

Enable control input. Logic high enables operation. Do not allow this pin to float or subject to

voltages greater than V_IN+ 0.3V.

Signal (analog) ground. Place the bottom resistor of the feedback network as close as possible to

this pin for good load regulation.

SGND

No user function, connect this pin to GND.

Feedback pin. Connect this pin to the external resistor divider to set output voltage.

Power ground pin. Provides ground return path for the internal driver.

Switch pins. Connect these pins to the inductor and catch diode.

Input supply voltage. Connect a bypass capacitor locally from these pins to PGND.

PGND

7, 8

9, 10

VIND

Connect to system ground for low thermal impedance, but it cannot be used as a primary GND

connection.

DAP

Die Attach Pad

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings⁽¹⁾⁽²⁾

VINC, VIND

-0.5V to 7V

-0.5V to 3V

-0.5V to 7V

2kV

FB Voltage

EN Voltage

SW Voltage

ESD Susceptibility⁽³⁾

Junction Temperature⁽⁴⁾

Storage Temperature

Soldering Information

150°C

−65°C to +150°C

220°C

Infrared/Convection Reflow (15sec)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings

indicate conditions at which the device is functional and should not be operated beyond such conditions.

(2) If Military/Aerospace specified devices are required, please contact Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Human body model, 1.5kΩ in series with 100pF.

(4) Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.

Operating Ratings

VINC, VIND

3V to 5.5V

−40°C to +125°C

Junction Temperature

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

Electrical Characteristics

Unless otherwise specified under the Conditions column, V_IN= 5V. Limits in standard type are for T_J= 25°C only; limits in

boldface type apply over the junction temperature (T_J) range of -40°C to +125°C. Minimum and Maximum limits are specified

through test, design, or statistical correlation. Typical values represent the most likely parametric norm, and are provided for

reference purposes only.

Symbol

Parameter

Conditions

Min

Typ

Max

0.612

0.616

Units

WSON-10 Package

0.588

0.584

0.600

V_FB

Feedback Voltage

MSOP-PowerPAD-10

Package

ΔV_FB/(ΔV_INxV_FB

)

Feedback Voltage Line Regulation

Feedback Input Bias Current

V_IN= 3V to 5.5V

0.08

0.1

2.70

2.35

0.35

1.5

3.0

%/V

I_B

100

V_INRising

V_INFalling

2.90

Undervoltage Lockout

UVLO Hysteresis

UVLO

1.85

LM2833X

1.1

2.25

1.95

3.75

f_SW

Switching Frequency

MHz

LM2833Z

LM2833X

D_MAX

Maximum Duty Cycle

Minimum Duty Cycle

LM2833Z

LM2833X

D_MIN

LM2833Z

WSON-10 Package

R_DS(ON)

Switch On Resistance

mΩ

MSOP-PowerPAD 10

Package

I_CL

Switch Current Limit

Enable Threshold Voltage

Shutdown Threshold Voltage

Switch Leakage

3.4

1.8

4.4

V_{EN_TH}

0.4

I_SW

I_EN

100

3.2

Enable Pin Current

Sink/Source

LM2833X, V_FB= 0.55

LM2833Z, V_FB= 0.55

All Options V_EN= 0V

All Options

Quiescent Current (switching)

I_Q

4.3

6.5

Quiescent Current (shutdown)

300

0.32

400

800

V_{FB_F}

f_FB

FB Frequency Foldback Threshold

LM2833X, V_FB= 0V

LM2833Z, V_FB= 0V

WSON-10 Package

Foldback Frequency

kHz

Junction to Ambient

0 LFPM Air Flow⁽¹⁾

θ_JA

°C/W

MSOP-PowerPAD-10

Package

WSON-10 Package

θ_JC

Junction to Case⁽¹⁾

°C/W

MSOP-PowerPAD-10

Package

Junction Temperature

Rising

T_SD

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

165

°C

Junction Temperature

Falling

T_{SD_HYS}

(1) Applies for packages soldered directly onto a 4” x 3” 4-layer standard JEDEC board in still air.

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

Typical Performance Characteristics

Unless otherwise specified, V_IN= 5V and T_A= 25°C.

Efficiency vs Load Current - "LM2833X" and "LM2833Z"

Efficiency vs Load Current - "LM2833X"

Figure 3.

Figure 4.

Efficiency vs Load Current - "LM2833Z"

Oscillator Frequency vs Temperature - "LM2833X"

Figure 5.

Figure 6.

Oscillator Frequency vs Temperature - "LM2833Z"

Current Limit vs Temperature

Figure 7.

Figure 8.

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

Typical Performance Characteristics (continued)

Unless otherwise specified, V_IN= 5V and T_A= 25°C.

R_DS(ON)vs Temperature (WSON-10 Package)

R_DS(ON)vs Temperature (MSOP-PowerPAD-10 Package)

Figure 9.

Figure 10.

LM2833X I_Q(Quiescent Current)

LM2833Z I_Q(Quiescent Current)

Figure 11.

Figure 12.

V_FBvs Temperature

Frequency Foldback

Figure 13.

Figure 14.

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

Typical Performance Characteristics (continued)

Unless otherwise specified, V_IN= 5V and T_A= 25°C.

Loop Gain and Phase - "LM2833X"

Loop Gain and Phase - "LM2833Z"

Figure 15.

Figure 16.

Load Step Response - "LM2833X"

Line Transient Response - "LM2833X"

Figure 17.

Figure 18.

Startup by EN - "LM2833X"

Shutdown by EN - "LM2833X"

Figure 19.

Figure 20.

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

Typical Performance Characteristics (continued)

Unless otherwise specified, V_IN= 5V and T_A= 25°C.

Startup with EN tied to V_IN- "LM2833X"

Short-circuit Triggering - "LM2833X"

Figure 21.

Figure 22.

Recovery from Thermal Shutdown - "LM2833X"

Short-circuit Release - "LM2833X"

Figure 23.

Figure 24.

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

Block Diagram

Figure 25. Simplified Block Diagram

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

APPLICATION INFORMATION

THEORY OF OPERATION

The LM2833 is a constant frequency PWM buck regulator IC that delivers a 3.0A load current. The regulator is

available in preset switching frequencies of 1.5MHz or 3.0MHz. This high frequency allows the LM2833 to

operate with small surface mount capacitors and inductors, resulting in a DC/DC converter that requires a

minimum amount of board space. The LM2833 is internally compensated, therefore it is simple to use and

requires few external components. The LM2833 uses peak current-mode control to regulate the output voltage.

The following description of operation of the LM2833 will refer to the Typical Application Circuit, to the waveforms

in Figure 26 and simplified block diagram in Figure 25. The LM2833 supplies a regulated output voltage by

switching the internal PMOS power switch at a constant frequency and variable duty cycle. A switching cycle

begins at the falling edge of the reset pulse generated by the internal oscillator. When this pulse goes low, the

output control logic turns on the internal PMOS power switch. During this on-time, the SW pin voltage (V_SW

)

swings up to approximately V_IN, and the inductor current (I_L) increases with a linear slope. I_Lis measured by the

current sense amplifier, which generates an output proportional to the switch current. The sense signal is

summed with the regulator’s corrective ramp and compared to the error amplifier’s output, which is proportional

to the difference between the feedback voltage and V_REF. When the PWM comparator output goes high, the

internal power switch turns off until the next switching cycle begins. During the switch off-time, the inductor

current discharges through the catch diode D1, which forces the SW pin to swing below ground by the forward

voltage (V_D) of the catch diode. The regulator loop adjusts the duty cycle (D) to maintain a constant output

voltage.

D = T /T

ON SW

Voltage

OFF

-V

LPK

OUT

Inductor

Current

Figure 26. SW Pin Voltage and Inductor Current Waveforms

SOFT-START/SHUTDOWN

The LM2833 has both enable and shutdown modes that are controlled by the EN pin. Connecting a voltage

source greater than 1.8V to the EN pin enables the operation of the LM2833, while reducing this voltage below

0.4V places the part in a low quiescent current (300nA typical) shutdown mode. There is no internal pull-up on

EN pin, therefore an external signal is required to initiate switching. Do not allow this pin to float or rise to 0.3V

above V_IN. It should be noted that when the EN pin voltage rises above 1.8V while the input voltage is greater

than UVLO, there is 15µs delay before switching starts. During this delay the LM2833 will go through a power on

reset state after which the internal soft-start process commences. During soft-start, the error amplifier’s reference

voltage ramps from 0V to its nominal value of 0.6V in approximately 600µs. This forces the regulator output to

ramp up in a controlled fashion, which helps reduce inrush current seen at the input and minimizes output

voltage overshoot.

The simplest way to enable the operation of the LM2833 is to connect the EN pin to V_INwhich allows self start-up

of the LM2833 whenever the input voltage is applied. However, when an input voltage of slow rise time is used to

power the application and if both the input voltage and the output voltage are not fully established before the soft-

start time elapses, the control circuit will command maximum duty cycle operation of the internal power switch to

bring up the output voltage rapidly. When the feedback pin voltage exceeds 0.6V, the duty cycle will have to

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

reduce from the maximum value accordingly, to maintain regulation. It takes a finite amount of time for this

reduction of duty cycle and this can result in a transient in output voltage for a short duration, as shown in

Figure 27. In applications where this output voltage overshoot is undesirable, one simple solution is to add a

feed-forward capacitor (C_FF) across the top feedback resistor R1 to speed Gm Amplifier recovery. In practice, a

27nF to 100nF ceramic capacitor is usually a good choice to remove the overshoot completely or limit the

overshoot to an insignificant level during startup, as shown in Figure 28. Another more effective solution is to

control EN pin voltage by a separate logic signal, and pull the signal high only after V_INis fully established. In this

way, the chip can execute a normal, complete soft start process, minimizing any output voltage overshoot. Under

some circumstances at cold temperature, this approach may also be required to minimize any unwanted output

voltage transients that may occur when the input voltage rises slowly. For a fast rising input voltage (100µs for

example), there is no need to control EN separately or add a feed-forward capacitor since the soft-start can bring

up output voltage smoothly as shown in Figure 29.

During startup, the LM2833 gradually increases the switching frequency from 400kHz (LM2833X) or 800kHz

(LM2833Z) to the nominal fixed value, as the feedback voltage increases (see FREQUENCY FOLDBACK section

for more information). Since the internal corrective ramp signal adjusts its slope dynamically, and is proportional

to the switching frequency during startup, a larger output capacitance may be required to insure a smooth output

voltage rise, at low programmed output voltage and high output load current.

Figure 27. Startup Response to V_IN

Figure 28. Startup Response to V_INwith C_FF

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

Figure 29. Startup Response to V_INwith 100µs rise time

FREQUENCY FOLDBACK

The LM2833 uses frequency foldback to help limit switch current and power dissipation during start-up, short-

circuit and over load conditions by sensing if the feedback voltage is below 0.32V (typical). The LM2833 will

reduce the switching frequency from the nominal fixed value (1.5MHz or 3.0MHz) down to 400kHz (LM2833X) or

800kHz (LM2833Z) when the feedback voltage drops to 0V. See Figure 14 in the Typical Performance

Characteristics section.

LOAD STEP RESPONSE

The LM2833 has a fixed internal loop compensation, which results in a small-signal loop bandwidth highly related

to the output voltage level. In general, the loop bandwidth at low voltage is larger than at high voltage due to the

increased overall loop gain. The limited bandwidth at high output voltage may pose a challenge when loop step

response is concerned. In this case, one effective approach to improving loop step response is to add a feed-

forward capacitor (C_FF) in the range of 27nF to 100nF in parallel with the upper feedback resistor (assuming the

lower feedback resistor is 2kΩ), as shown in Figure 30. The feed-forward capacitor introduces a zero-pole pair

which helps compensate the loop. The position of the zero-pole pair is a function of the feedback resistors and

capacitor:

(1)

(2)

Note the factor in parenthesis is the ratio of the output voltage to the feedback voltage. As the output voltage

gets close to 0.6V, the pole moves towards the zero, tending to cancel it out. Consequently, adding C_FFwill have

less effect on the step response at lower output voltages.

As an example, Figure 32 shows that at the output voltage of 3.3V, a 47nF of C_FFcan boost the loop bandwidth

to 117kHz, from the original 23kHz as shown in Figure 31. Correspondingly, the responses to a load step

between 0.3A and 3A without and with C_FFare shown in Figure 33 and Figure 34 respectively. The higher loop

bandwidth as a result of C_FFreduces the total output excursion by more than half.

Aside from the above approach, increasing the output capacitance is generally also effective to reduce the

excursion in output voltage caused by a load step. This approach remains valid for applications where the

desired output voltages are close to the feedback voltage.

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

Figure 30. Adding a C_FFCapacitor

Figure 31. Loop Gain and Phase without C_FF

Figure 32. Loop Gain and Phase with C_FF

Figure 33. Load Step Response without C_FF

Figure 34. Load Step Response with C_FF

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

OUTPUT OVER-VOLTAGE PROTECTION

The LM2833 has a built in output over-voltage comparator that compares the FB pin voltage to a threshold

voltage that is 15% higher than the internal reference V_REF. Once the FB pin voltage exceeds this threshold level

(typically 0.69V), the internal PMOS power switch is turned off, which allows the output voltage to decrease

towards regulation.

UNDER-VOLTAGE LOCKOUT

Under-voltage lockout (UVLO) prevents the LM2833 from operating until the input voltage exceeds 2.70V

(typical). The UVLO threshold has approximately 350mV of hysteresis, so the part will operate until V_INdrops

below 2.35V (typical). Hysteresis prevents the part from turning off during power up if V_INis non-monotonic.

CURRENT LIMIT

The LM2833 uses cycle-by-cycle current limiting to protect the internal power switch. During each switching

cycle, a current limit comparator detects if the power switch current exceeds 4.4A (typical), and turns off the

switch until the next switching cycle begins.

THERMAL SHUTDOWN

Thermal shutdown limits total power dissipation by turning off the internal power switch when the IC junction

temperature typically exceeds 165°C. After thermal shutdown occurs, the power switch does not turn on again

until the junction temperature drops below approximately 150°C.

Design Guide

INDUCTOR SELECTION

The Duty Cycle (D) can be approximated quickly using the ratio of output voltage (V_OUT) to input voltage (V_IN):

V_OUT

D =

V_IN

(3)

The catch diode (D1) forward voltage drop and the voltage drop across the internal PMOS must be included to

calculate a more accurate duty cycle. Calculate D by using the following formula:

V_OUT+ V_D

D =

V_IN+ V_D- V_SW

(4)

V_SWcan be approximated by:

V_SW= I_OUTx R_DS(ON)

where

•

I_OUTis output load current.

(5)

The diode forward drop (V_D) can range from 0.3V to 0.7V depending on the quality of the diode. The lower the

V_D, the higher the operating efficiency of the converter.

The inductor value determines the output ripple current (Δi_L, as defined in Figure 26). Lower inductor values

decrease the size of the inductor, but increase the output ripple current. An increase in the inductor value will

decrease the output ripple current. In general, the ratio of ripple current to the output current is optimized when it

is set between 0.2 and 0.4 for output currents above 2A. This ratio r is defined as:

Di_L

r =

l_OUT

(6)

One must ensure that the minimum current limit (3.4A) is not exceeded, so the peak current in the inductor must

be calculated. The peak current (I_LPK) in the inductor is calculated by:

I_LPK= I_OUT+ Δi_L/2

(7)

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

When the designed maximum output current is reduced, the ratio r can be increased. At a current of 0.1A, r can

be made as high as 0.9. The ripple ratio can be increased at lighter loads because the net ripple is actually quite

low, and if r remains constant the inductor value can be made quite large. An equation empirically developed for

the maximum ripple ratio at any current below 2A is:

-0.3667

r = 0.387 x I_OUT

(8)

Note that this is just a guideline, and it needs to be combined with two important factors for proper selection of

inductance values at any operating condition. The first consideration is at output voltage above 2.5V, one needs

to ensure that the inductance given by the above guideline should not be less than 1µH for the LM2833X or

0.5µH for the LM2833Z. Since the LM2833 has a fixed internal corrective ramp signal, a very low inductance

value at high output voltage will generate a very steep down slope of inductor current, which will result in an

insufficient slope compensation, and cause instability known as sub-harmonic oscillation. Another consideration

is at low load current, one needs to ensure that the inductance value given by the guideline should not exceed

10µH for the LM2833X and 4.7µH for the LM2833Z, since too much inductance effectively flattens the down

slope of the inductor current, and may significantly limit the system bandwidth and phase margin resulting in

instability.

The LM2833 operates at frequencies allowing the use of ceramic output capacitors without compromising

transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple.

See the OUTPUT CAPACITOR section for more details on calculating output voltage ripple.

Now that the ripple current is determined, the inductance is calculated by:

V_OUT+ V_D

x (1-D)

L =

I_OUTx r x f_SW

where

•

f_SWis the switching frequency.

(9)

When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating.

Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating

properly. Because of the operating frequency of the LM2833, ferrite based inductors are preferred to minimize

core losses. This presents little restriction since the variety and availability of ferrite-based inductors is large.

Lastly, inductors with lower series resistance (DCR) will provide better operating efficiency. For recommended

inductor selection, refer to Design Examples.

INPUT CAPACITOR

An input capacitor is necessary to ensure that V_INdoes not drop excessively during switching transients. The

primary specifications of the input capacitor are capacitance, voltage rating, RMS current rating, and ESL

(Equivalent Series Inductance). The input voltage rating is specifically stated by the capacitor manufacturer.

Make sure to check any recommended deratings and also verify if there is any significant change in capacitance

at the operating input voltage and the operating temperature. The input capacitor maximum RMS input current

rating (I_RMS-IN) must be greater than:

r²

I_RMS-IN= I_OUT

D x

1 - D +

Neglecting inductor ripple simplifies the above equation to:

I_RMS-IN= I_OUT

(10)

D x

1 - D

(11)

It can be shown from the above equation that maximum RMS capacitor current occurs when D = 0.5. Always

calculate the RMS at the point where the duty cycle D is closest to 0.5. The ESL of an input capacitor is usually

determined by the effective cross sectional area of the current path. As a rule of thumb, a large leaded capacitor

will have high ESL and a 1206 ceramic chip capacitor will have very low ESL. At the operating frequencies of the

LM2833, leaded capacitors may have an ESL so large that the resulting impedance (2πfL) will be higher than

that required to provide stable operation. It is strongly recommended to use ceramic capacitors due to their low

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

ESR and low ESL. A 22µF multilayer ceramic capacitor (MLCC) is a good choice for most applications. In cases

where large capacitance is required, use surface mount capacitors such as Tantalum capacitors and place at

least a 4.7µF ceramic capacitor close to the V_INpin. For MLCCs it is recommended to use X7R or X5R

dielectrics. Consult capacitor manufacturer datasheet to see how rated capacitance varies over operating

conditions.

OUTPUT CAPACITOR

The output capacitor is selected based upon the desired output ripple and transient response. The initial current

of a load transient is provided mainly by the output capacitor. The output ripple of the converter is:

R_ESR

DV_OUT= DI_L

8 x f_SWx C_OUT

(12)

When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the

output ripple will be approximately sinusoidal and 90° phase shifted from the switching action. Given the

availability and quality of MLCCs and the expected output voltage of designs using the LM2833, there is really no

need to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to bypass

high frequency noise. A certain amount of switching edge noise will couple through parasitic capacitances in the

inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not. Since the output

capacitor is one of the two external components that control the stability of the regulator control loop, most

applications will require a minimum of 22µF output capacitance. In the case of low output voltage, a larger output

capacitance is required to ensure sufficient phase margin. Capacitance can often, but not always, be increased

significantly with little detriment to the regulator stability. Like the input capacitor, recommended multilayer

ceramic capacitors are X7R or X5R types. Again, verify actual capacitance at the desired operating voltage and

temperature. Check the RMS current rating of the capacitor. The maximum RMS current rating of the capacitor

is:

(13)

One may select a 1206 size MLCC for output capacitor, since its current rating is typically above 1A, more than

enough for the requirement.

CATCH DIODE

The catch diode conducts during the switch off-time. A Schottky diode is recommended for its fast switching time

and low forward voltage drop. The catch diode should be chosen such that its current rating is greater than:

I_D= I_OUTx (1-D)

(14)

The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin.

To improve efficiency, choose a Schottky diode with a low forward voltage drop.

OUTPUT VOLTAGE

The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and

R1 is connected between V_OUTand the FB pin. A good value for R2 is 2kΩ.

V_OUT

x R2

- 1

R1 =

V_REF

V_REF= 0.60V

(15)

(16)

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

EFFICIENCY ESTIMATION

The complete LM2833 DC/DC converter efficiency can be calculated in the following manner:

P_OUT

h =

P_IN

(17)

(18)

P_OUT

h =

P_OUT+ P_LOSS

Calculations for determining the most significant power losses are shown below. Other losses totaling less than

2% are not discussed.

The main power loss (P_LOSS) in the converter includes two basic types of losses: switching loss and conduction

loss. In addition, there is loss associated with the power required for the internal circuitry of IC. Conduction

losses usually dominate at higher output loads, whereas switching losses dominate at lower output loads. The

first step in determining the losses is to calculate the duty cycle (D):

V_OUT+ V_D

D =

V_IN+ V_D- V_SW

(19)

V_SWis the voltage drop across the internal power switch when it is on, and is equal to:

V_SW= I_OUTx R_DS(ON)

(20)

V_Dis the forward voltage drop across the catch diode. It can be obtained from the diode manufactures Electrical

Characteristics section. If the DC voltage drop across the inductor (V_DCR) is accounted for, the equation

becomes:

V_OUT+ V_D+ V_DCR

D =

V_IN+ V_D- V_SW

(21)

The conduction losses in the catch diode are calculated as follows:

P_DIODE= V_Dx I_OUTx (1-D)

(22)

Often this is the single most significant power loss in the circuit. Care should be taken to choose a Schottky

diode with a low forward voltage drop.

Another significant external power loss is the conduction loss in the output inductor. The equation can be

simplified to:

P_IND= I_OUT²x R_DCR

(23)

The LM2833 conduction loss is mainly associated with the internal power switch:

Di_L

P_COND= (I_OUT²x D) x

x R_{DS (ON)}

1 +

I_OUT

(24)

(25)

If the inductor ripple current is fairly small, the conduction losses can be simplified to:

P_COND= I_OUT²x R_DS(ON)x D

Switching losses are also associated with the internal power switch. They occur during the switch on and off

transition periods, where voltages and currents overlap resulting in power loss. The simplest means to determine

this loss is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node.

Switching Power Loss is calculated as follows:

P_SWR= 0.5 x (V_INx I_OUTx f_SWx T_RISE

)

(26)

(27)

(28)

P_SWF= 0.5 x (V_INx I_OUTx f_SWx T_FALL

)

P_SW= P_SWR+ P_SWF

The power loss required for operation of the internal circuitry is given by:

P_Q= I_Qx V_IN

(29)

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

I_Qis the quiescent operating current, and is typically around 3.2mA for the LM2833X, and 4.3mA for the

LM2833Z.

An example of efficiency calculation for a typical application is shown in Table 1:

Table 1. Power Loss Tabulation

Conditions

Power loss

V_IN

3.3V

V_OUT

I_OUT

3.0A

P_OUT

P_DIODE

P_COND

9.9W

V_D

0.33V

56mΩ

1.5MHz

10ns

277mW

363mW

R_DS(ON)

f_SW

T_RISE

P_SW

225mW

T_FALL

10ns

IND_DCR

28mΩ

3.2mA

89.7%

P_IND

P_Q

252mW

16mW

I_Q

D is calculated to be 0.72

P_LOSS= Σ ( P_COND+ P_SW+ P_Q+ P_IND+ P_DIODE

)

(30)

(31)

P_LOSS= 1.133W

PCB LAYOUT CONSIDERATIONS

When planning layout there are a few things to consider to achieve a clean, regulated output. The most important

consideration is the close coupling of the GND connections of the input capacitor C1 and the catch diode D1.

These ground ends should be close to one another and be connected to the GND plane with at least two

through-holes. Place these components as close to the IC as possible. The next consideration is the location of

the GND connection of the output capacitor C2, which should be near the GND connections of C1 and D1. There

should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node

island. The signal ground SGND (pin 3) and power ground PGND (pin 6) should be tied together and connected

to ground plane through vias.

The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup

that causes inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with

the GND of R2 placed as close as possible to the SGND of the IC. The V_OUTtrace to R1 should be routed away

from the inductor and any other traces that are switching.

High AC currents flow through the V_IN, SW and V_OUTtraces, so they should be as short and wide as possible.

Radiated noise can be decreased by choosing a shielded inductor.

The remaining components should also be placed as close as possible to the IC. Please see Application Note

AN-1229 SNVA054 for further considerations and the LM2833 demo board as an example of a four-layer layout.

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

LM2833X Design Example 1

OUT

7,8

9,10

VIND

LM2833X

VINC

PGND

SGND

Figure 35. LM2833X (1.5MHz): V_IN= 3.3V, Output = 1.2V/3.0A

Table 2. Bill of Materials

Part ID

Part Value

3.0A Buck Regulator

22µF, 6.3V, X5R

47µF, 6.3V, X5R

0.22µF, 10V, X7R

Schottky, 0.33V at 3A, V_R=30V

1.8µH, 3.6A

Manufacturer

Part Number

LM2833X

C1, Input Cap

TDK

C3216X5R0J226M

C3216X5R0J476M

GRM216R71A224KC01D

CMS01

C2, Output Cap

TDK

C3, Bypass Cap

Murata

Toshiba

TDK

D1, Catch Diode

LTF5022T-1R8N3R6

CRCW08052K00FKEA

CRCW080510R0FKEA

2.0kΩ, 1%

Vishay

2.0kΩ, 1%

10Ω, 1%

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

LM2833X Design Example 2

Figure 36. LM2833X (1.5MHz): V_IN= 5V, Output = 3.3V/3.0A

Table 3. Bill of Materials

Part ID

Part Value

Manufacturer

Part Number

3.0A Buck Regulator

22µF, 6.3V, X5R

47µF, 6.3V, X5R

0.22µF, 10V, X7R

47nF, 10V, X7R

Schottky, 0.43V at 3A, V_R=30V

1.2µH, 4.2A

LM2833X

C1, Input Cap

TDK

C3216X5R0J226M

C3216X5R0J476M

GRM216R71A224KC01D

0805ZC473JAZ2A

C2, Output Cap

TDK

C3, Bypass Cap

Murata

AVX

C_FF, Feed-forward Cap

D1, Catch Diode

Vishay

TDK

SSA33L-E3/61T

LTF5022T-1R2N4R2

CRCW080510K2FKEA

CRCW08052K26FKEA

CRCW080510R0FKEA

10.2kΩ, 1%

Vishay

2.26kΩ, 1%

10Ω, 1%

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

LM2833Z Design Example 3

OUT

7,8

9,10

VIND

LM2833Z

VINC

PGND

SGND

Figure 37. LM2833Z (3MHz): V_IN= 3.3V, Output = 1.2V/3.0A

Table 4. Bill of Materials

Part ID

Part Value

3.0A Buck Regulator

22µF, 6.3V, X5R

47µF, 6.3V, X5R

0.22µF, 10V, X7R

Schottky, 0.33V at 3A, V_R=30V

1.0µH, 4.0A

Manufacturer

Part Number

LM2833Z

C1, Input Cap

TDK

C3216X5R0J226M

C3216X5R0J476M

GRM216R71A224KC01D

CMS01

C2, Output Cap

TDK

C3, Bypass Cap

Murata

Toshiba

Taiyo Yuden

Vishay

D1, Catch Diode

NP04SZB1R0N

2.0kΩ, 1%

CRCW08052K00FKEA

CRCW080510R0FKEA

2.0kΩ, 1%

10Ω, 1%

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

SNVS505E –MAY 2008–REVISED APRIL 2013

www.ti.com

LM2833Z Design Example 4

Figure 38. LM2833Z (3MHz): V_IN= 5V, Output = 3.3V/3.0A

Table 5. Bill of Materials

Part ID

Part Value

Manufacturer

Part Number

3.0A Buck Regulator

22µF, 6.3V, X5R

47µF, 6.3V, X5R

0.22µF, 10V, X7R

47nF, 10V, X7R

Schottky, 0.43V at 3A, V_R=30V

1.0µH, 4.0A

LM2833Z

C1, Input Cap

TDK

C3216X5R0J226M

C3216X5R0J476M

GRM216R71A224KC01D

0805ZC473JAZ2A

SSA33L-E3/61T

C2, Output Cap

TDK

C3, Bypass Cap

Murata

AVX

C_FF, Feed-forward Cap

D1, Catch Diode

Vishay

Taiyo Yuden

Vishay

NP04SZB1R0N

10.2kΩ, 1%

CRCW080510K2FKEA

CRCW08052K26FKEA

CRCW080510R0FKEA

2.26kΩ, 1%

10Ω, 1%

Submit Documentation Feedback

Product Folder Links: LM2833

LM2833

www.ti.com

SNVS505E –MAY 2008–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision D (April 2013) to Revision E

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 22

Submit Documentation Feedback

Product Folder Links: LM2833

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM2833XMY/NOPB

LM2833XSD/NOPB

LM2833ZMY/NOPB

LM2833ZMYX/NOPB

LM2833ZSD/NOPB

ACTIVE

HVSSOP

WSON

DGQ

DSC

DGQ

DSC

1000 RoHS & Green

3500 RoHS & Green

1000 RoHS & Green

Level-3-260C-168 HR

Level-1-260C-UNLIM

Level-3-260C-168 HR

Level-1-260C-UNLIM

-40 to 125

SPYB

2833X

SPZB

2833Z

HVSSOP

WSON

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM2833XMY/NOPB

LM2833XSD/NOPB

LM2833ZMY/NOPB

HVSSOP DGQ

WSON DSC

HVSSOP DGQ

1000

3500

1000

178.0

330.0

178.0

12.4

5.3

3.3

5.3

3.3

3.4

3.3

3.4

3.3

1.4

1.0

1.4

1.0

8.0

12.0

LM2833ZMYX/NOPB HVSSOP DGQ

LM2833ZSD/NOPB WSON DSC

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM2833XMY/NOPB

LM2833XSD/NOPB

LM2833ZMY/NOPB

LM2833ZMYX/NOPB

LM2833ZSD/NOPB

HVSSOP

WSON

DGQ

DSC

DGQ

DSC

1000

3500

1000

208.0

210.0

208.0

356.0

210.0

191.0

185.0

191.0

356.0

185.0

35.0

HVSSOP

WSON

Pack Materials-Page 2

PACKAGE OUTLINE

DGQ0010A

PowerPAD^TM- 1.1 mm max height

PLASTIC SMALL OUTLINE

5.05

4.75

TYP

SEATING PLANE

PIN 1 ID

AREA

0.1 C

8X 0.5

3.1

2.9

NOTE 3

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.08

C A B

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

EXPOSED

THERMAL PAD

0.25

GAGE PLANE

2.05

1.75

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

1.88

1.58

4214864/A 05/2020

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA-T.

www.ti.com

EXAMPLE BOARD LAYOUT

DGQ0010A

PowerPAD^TM- 1.1 mm max height

PLASTIC SMALL OUTLINE

(2.2)

NOTE 9

(1.88)

SOLDER MASK

OPENING

SOLDER MASK

DEFINED PAD

SEE DETAILS

10X (1.45)

10X (0.3)

(1.3)

TYP

(2.05)

SOLDER MASK

OPENING

SYMM

(3.1)

NOTE 9

8X (0.5)

(R0.05) TYP

SYMM

METAL COVERED

BY SOLDER MASK

(

0.2) TYP

VIA

(1.3) TYP

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214864/A 05/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

DGQ0010A

PowerPAD^TM- 1.1 mm max height

PLASTIC SMALL OUTLINE

(1.88)

BASED ON

0.125 THICK

STENCIL

10X (1.45)

10X (0.3)

(2.05)

SYMM

BASED ON

0.125 THICK

STENCIL

8X (0.5)

(R0.05) TYP

SEE TABLE FOR

SYMM

(4.4)

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

METAL COVERED

BY SOLDER MASK

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:15X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.10 X 2.29

1.88 X 2.05 (SHOWN)

1.72 X 1.87

0.125

0.150

0.175

1.59 X 1.73

4214864/A 05/2020

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

MECHANICAL DATA

DSC0010A

SDA10A (Rev A)

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LM2833XSD/NOPB [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E