LM3207TLX-2.53/NOPB [TI]
650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers 9-DSBGA;
| 型号： | LM3207TLX-2.53/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers 9-DSBGA 开关 |
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LM3207
www.ti.com
SNVS400A –AUGUST 2006–REVISED APRIL 2007
LM3207 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power
Amplifiers with Integrated Vref LDO
Check for Samples: LM3207
1
FEATURES
•
•
•
•
Fast 3uS Vref LDO On/Off Time
9-pin micro SMD Package
2
•
2MHz (typ.) PWM Switching Frequency
Current Overload Protection
Thermal Overload Protection
•
Operates from a single Li-Ion cell (2.7V to
5.5V)
•
•
•
Variable Output Voltage (0.8V to 3.6V)
650mA Maximum load capability
APPLICATIONS
•
•
•
•
Cellular Phones
High Efficiency (95% Typ at 3.9VIN, 3.4VOUT at
400mA) from internal synchronous
rectification
Hand-Held Radios
RF PC Cards
•
•
Integrated Vref LDO
Battery Powered RF Devices
Regulated LDO Output up to 10mA max
DESCRIPTION
The LM3207 is a DC-DC converter optimized for powering WCDMA / CDMA RF power amplifiers (PAs) from a
single Lithium-Ion cell; however they may be used in many other applications. It steps down an input voltage
from 2.7V to 5.5V to a variable output voltage from 0.8V(typ.) to 3.6V(typ.). Output voltage is set using a VCON
analog input for controlling power levels and efficiency of the RF PA.
The LM3207 also provides a regulated reference voltage(Vref) required by linear RF power amplifiers through an
integrated LDO that has a maximum Iref up to 10 mA. See Ordering Information table on page 2 for Voltage
Options.
The LM3207 is available in a 9-pin lead free micro SMD package. High switching frequency (2MHz) allows use of
surface-mount components. Only four small external surface-mount components are required, an inductor and
three ceramic capacitors.
Typical Application
Vin
2.7V to 5.5V
VOUT
0.8V to 3.6V
3.3 mH
PVIN
EN
SW
FB
4.7 mF
10 mF
VCON
LM3207
LDO OUT
EN
LDO
SGND
LDO
PGND
100 nF
Figure 1. LM3207 Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
LM3207
SNVS400A –AUGUST 2006–REVISED APRIL 2007
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Connection Diagrams
SW
A
1
A1
A2
A3
PV
PGND
SGND
LDO
IN
EN
B2
EN
B1
C1
B3
C3
LDO
XVS/Device #
FB
C2
Vcon
Top View
Package Mark - Top View
9–Bump Thin Micro SMD Package, Large Bump NS Package Number TLA09TTA
(1)
Table 1. Pin Descriptions
Pin #
A1
Name
PVIN
Description
Power Supply Voltage Input.
B1
ENLDO
LDO Enable Input. Set this digital input high to turn on LDO (ENpin must also be set high). For shutdown, set
low.
C1
C2
C3
B3
A3
A2
FB
Feedback Analog Input. Connect to the output at the output filter capacitor.
Voltage Control Analog input. VCON controls VOUT in PWM mode.
LDO Output Voltage.
VCON
LDO
SGND
PGND
SW
Analog and Control Ground.
Power Ground.
Switch node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor
with a saturation current rating that exceeds the maximum Switch Peak Current Limit specification of the
LM3207.
B2
EN
PWM enable Input. Set this digital input high for normal operation. For shutdown, set low.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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(1) (2)
Absolute Maximum Ratings
PVIN to SGND
−0.2V to +6.0V
−0.2V to +0.2V
PGND to SGND
EN, FB, VCON, ENLDO, LDO
(SGND −0.2V)
to (VDD +0.2V)
w/6.0V max
SW
(PGND −0.2V)
to (PVIN +0.2V)
w/6.0V max
PVIN
−0.2V to +0.2V
Continuous Power Dissipation
(3)
Internally Limited
+150°C
Junction Temperature (TJ-MAX
Storage Temperature Range
)
−65°C to +150°C
Maximum Lead Temperature
(Soldering, 10 sec)
+260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed
performance limits and associated test conditions, see the Electrical Characteristics tables.
(2) All voltages are with respect to the potential at the GND pins. The LM3207 is designed for mobile phone applications where turn-on after
power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal
Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds
2.7V.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and
disengages at TJ = 130°C (typ.).
(1) (2)
Operating Ratings
Input Voltage Range
2.7V to 5.5V
0mA to 650mA
−30°C to +125°C
−30°C to +85°C
Recommended Load Current
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
(3)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed
performance limits and associated test conditions, see the Electrical Characteristics tables.
(2) All voltages are with respect to the potential at the GND pins. The LM3207 is designed for mobile phone applications where turn-on after
power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal
Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds
2.7V.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
=
Thermal Properties
Junction-to-Ambient Thermal
100°C/W
Resistance (θJA), TLA09 Package
(1)
(1) Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7.
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(1) (2) (3)
Electrical Characteristics
Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature
range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, all specifications apply to all LM3207 LDO options with: PVIN = VIN
= ENLDO = EN = 3.6V.
Symbol
LDO
Parameter
Conditions
Min
Typ
Max
Units
VLDO
VLDO,MIN
ISC
LDO Output Voltage
Iout = 0 mA
+2.6
%
%
Minimum LDO Output Voltage
Short circuit current(DC)
Pull-up current (transient)
Iout = 10mA, PVIN = 3V
VLDO = 0
-2.6
50
mA
IPUT
VLDO = VLDO(nom)/2, PVIN = 3V
150
mA
mA
mA
(4)
IPD
DC Pull-down current (DC)
Pull-down current (transient)
VLDO = PVIN, ENLDO = 0
-50
IPDT
VLDO = 1.44V, PVIN = 3V
-200
(4)
IQ_LDO + PWM
DC Bias current into PVIN
LDO Pin pull down current
VCON = 2V, FB = 0V, No Switching,
ENLDO = EN = 3.6V
1.2
5
1.6
10
mA
uA
(5)
IPIN,EN
LDO
Switcher
VFB, MIN
Feedback Voltage at minimum
setting
VCON = 0.32V
0.75
0.8
3.6
0.85
3.683
2
V
V
VFB, MAX
ISHDN
IQ_PWM
RDSON(P)
Feedback Voltage at maximum VCON = 1.44V, PVIN = 4.2V
setting
3.537
Shutdown supply current
DC bias current into PVIN
Pin-pin resistance for PFET
EN = ENLDO= SW = VCON = 0V,
0.01
1.1
µA
mA
(6)
VCON = 2V, FB = 0V, ENLD(5O) = 0V ,
EN = 3.6V, No Switching
1.6
ISW = 200mA
200
230
415
485
1200
2.3
140
300
mΩ
mΩ
RDSON(N)
Pin-pin resistance for NFET
ISW = - 200mA
(7)
ILIM,PFET
FOSC
Switch peak current limit
935
1.7
1100
2
mA
Internal oscillator frequency
MHz
VIH,EN
Logic high input threshold
(PWM, LDO)
1.2
V
V
VIL,EN
Logic low input threshold
(PWM, LDO)
0.5
10
IPIN,EN
Gain
ICON
PWM Pin pull down current
VCON to VOUT Gain
5
µA
V/V
µA
0.32V ≤ VCON ≤ 1.44V
2.5
VCON pin leakage current
VCON = 1.0V
±1
(1) All voltages are with respect to the potential at the GND pins. The LM3207 is designed for mobile phone applications where turn-on after
power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal
Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds
2.7V.
(2) Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the
most likely norm. Due to the pulsed nature of the testing TA = TJ for the electrical characteristics table.
(3) The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = 3.6V. For performance over the
input voltage range and closed loop results refer to the datasheet curves.
(4) Transient Pull-up current (IPUT) and Transient Pull-down Current (IPDT) will be tested which are inversely proportional to charge and
discharge times tLDO, ON and tLDO, OFF respectively.
(5) IQ specified here is when the part is operating at 100% duty cycle.
(6) Shutdown current includes leakage current of PFET.
(7) Current limit is built-in, fixed, and not adjustable. Refer to datasheet curves for closed loop data and its variation with regards to supply
voltage and temperature. Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until
cycle by cycle limit is activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing
output current until output voltage drops by 10%.
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System Characteristics
The following spec table entries are guaranteed by design providing the component values in the typical application circuit are
used (L = 3.0µH, (DCR = 0.12Ω, FDK MIPW3226D3R0M);
CIN = 10µF, (6.3V, 0805, TDK C2012X5R0J106K); COUT = 4.7µF, (6.3V, 0603, TDK C1608X5R0J475M); CLDO = 100nF, (10V,
0402, TDK C1005X5R1A104KT) (or 220nF, (6.3V, 0402, TDK C1005X5R0J224KT))) . These parameters are not
guaranteed by production testing. Min and Max values are specified over the VIN range = 2.7V to 5.5V and over the
ambient temp range TA = −30°C to 85°C unless otherwise specified. Typical values are specified at PVIN = EN = 3.6V and TA
= 25°C unless otherwise specified.
Symbol
LDO
Parameter
Conditions
Min
Typ
Max
Units
PSRR
Power Supply Rejection
Ratio
Offset Freq = 1Khz, Cout = 100nF,
Iout = 1mA, PVin = Vout(nom) + 0.5V
50
dB
VLDO(NOISE)
tLDO, ON
Output Noise Voltage
BW = 10Hz to 100Khz, Iout = 1mA
30
uVrms
Time to reach 90% of
VLDO(nom) after ENLDO
signal goes high.
CLDO = 100nF, PWM mode assumed to be
fully functional before ENLDO goes high.
3
uS
uS
(1)
PVin = 3V, RLOAD = 562 Ω
CLDO = 220nF, PWM mode assumed to be
fully functional before ENLDO goes high.
5
(1)
PVin = 3V, RLOAD = 562 Ω
tLDO, OFF
Time to reach 10% of
VLDO(nom) after ENLDO
signal goes low.
CLDO = 100nF, PVin = 3V, Iout = 0mA
3
5
(1)
uS
CLDO = 220nF, PVin = 3V, Iout = 0mA
(1)
Switcher
TRESPONSE (Rise Time for VOUT to rise from PVIN = 4.2V, COUT = 4.7uF, L = 3.0uH,
20
20
30
30
20
+3
µs
µs
pF
%
time)
0.8V to 3.6V
RLOAD = 5.5Ω
TRESPONSE (Fall
time)
Time for VOUT to fall from PVIN = 4.2V, COUT = 4.7uF, L = 3.0uH,
3.6V to 0.8V
RLOAD = 10Ω
CCON
VCON input capacitance
VCON = 1V,
Test frequency = 100 kHz
VCON Linearity
T_ON
Linearity in control
range 0.32V to 1.44V
PVIN = 3.9V, Monotonic in nature
-3
Turn on time
EN = Low to High, PVIN = 4.2V,
VO = 3.6V, COUT = 4.7µF,
(time for output to reach
3.6V from Enable low to
high transition)
70
100
µs
IOUT ≤ 1mA
η
Efficiency
(L = 3.0µH, DCR ≤
100mΩ)
PVIN = 3.6V, VOUT = 0.8V, IOUT = 90mA
PVIN = 3.9V, VOUT = 3.4V, IOUT = 400mA
81
95
%
%
VO_ripple
Line_tr
Ripple voltage, PWM
mode
PVIN = 3V to 4.5V, VOUT = 0.8V,
IOUT = 10mA to 400mA,
10
50
mVp-p
mV
(2)
Line transient response
PVIN = 600mV perturbance,
TRISE = TFALL = 10µs, VOUT = 0.8V,
IOUT = 100mA
Load_tr
Load transient response
PVIN = 3.1/3.6/4.5V, VOUT = 0.8V,
transients up to 100mA,
TRISE = TFALL = 10µs
50
mV
(1) Transient Pull-up current (IPUT) and Transient Pull-down Current (IPDT) will be tested which are inversely proportional to charge and
discharge times tLDO, ON and tLDO, OFF respectively.
(2) Ripple voltage should measured at COUT electrode on good layout PC board and under condition using suggested inductors and
capacitors.
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Typical Performance Characteristics
(Circuit in Figure 3, See Operation Description Section),
PVIN = EN = 3.6V, L = 3.0µH, (DCR = 0.12Ω, FDK MIPW3226D3R0M); CIN = 10µF, (6.3V, 0805, TDK C2012X5R0J106K);
COUT = 4.7µF, (6.3V, 0603, TDK C1608X5R0J475M), CLDO = 100nF, 10V, (0402, TDK C1005X5R1A104KT) (or 220nF, (6.3V,
0402, TDK C1005X5R0J224KT)) can be used. TA = 25°C unless otherwise specified.
LDO Typical Performance Curves (2.875 Option)
LDO Voltage
vs
LDO Dropout Voltage
vs
Load Current
(CLDO = 100nF)
Load Current
(CLDO = 100nF),
(1)
LDO Short Circuit Current
vs
Voltage
LDO Output Noise Density
(VIN = 3.0V, CLDO = 100nF)
(ILOAD = 1mA, CLDO = 100nF and 220nF)
LDO Turn On Time
vs
VIN
LDO Power Supply Rejection Ratio
(VIN = Vout(nom) + 0.5V, CLDO = 100nF)
(CLDO = 100nF)
50
40
I
= 1mA
LOAD
30
20
10
0
-10
-20
-30
-40
-50
100
1k
10k
100k
1M
FREQUENCY (Hz)
(1) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
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LDO Typical Performance Curves (2.875 Option) (continued)
LDO Turn Off Time
vs
VIN
LDO Line Transient Response
(CLDO = 100nF)
(VIN = 3.0V to 3.6V, ILOAD = 10mA, CLDO = 100nF)
I
= 0 mA
L
1.4
1.2
1.0
0.8
0.6
T
= 25°C
A
T
= -30°C
A
T
= 85°C
A
3.0
3.5
4.0
4.5
5.0
5.5
PVIN (V)
LDO VLDO Out
vs
LDO Load Transient Repsonse
(VIN= 3.2V, VOUT = 0.8V, CLDO = 100nF)
Temperature
(VIN = 3.6V,CLDO = 100nF)
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LDO Typical Performance Curves (2.53 Option)
LDO Voltage
vs
LDO Dropout Voltage
vs
Load Current
(CLDO = 100nF)
Load Current
(CLDO = 100nF),
(1)
2.53
2.52
2.51
0
-10
T
= -30°C
A
-20
V
= 3.6V
IN
-30
-40
V
= 5.5V
IN
V
= 4.2V
-50
IN
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
T
= 85°C
V
IN
= 3.0V
A
V
= 3.2V
IN
T
A
= 25°C
0
5
10
15
20
0
2
4
6
8
10
LOAD CURRENT (mA)
LDO LOAD CURRENT (mA)
LDO Short Circuit Current
vs
Voltage
(VIN = 3.0V, CLDO = 100nF)
LDO Power Supply Rejection Ratio
(VIN = Vout(nom) + 0.5V, CLDO = 100nF)
10
0
60
50
40
30
20
10
0
T
= 25°C
A
I
= 1 mA
LOAD
-10
-20
-30
-40
-50
-60
-70
T
= 85°C
A
T
= -30°C
A
1
10
100
1000
0.0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (kHz)
V
(V)
LDO
(1) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
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LDO Typical Performance Curves (2.53 Option) (continued)
LDO Turn On Time
LDO Turn Off Time
vs
VIN
vs
VIN
(CLDO = 100nF)
(CLDO = 100nF)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
I
= 5 mA
I
= 0 mA
LOAD
LOAD
T
= 85°C
A
T
= 25°C
A
T
= -30°C
A
T
= -30°C
A
T
A
= 85°C
4.0
T
A
= 25°C
4.0
3.0
3.5
4.5
5.0
5.5
3.0
3.5
4.5
5.0
5.5
PVIN (V)
PVIN (V)
LDO VLDO Out
vs
Temperature
(VIN = 3.6V,CLDO = 100nF)
I
= 0 mA
LOAD
2.536
I
= 5 mA
LOAD
I
= 1 mA
LOAD
I
=
LOAD
2.534
2.532
2.530
2.528
2.526
10 mA
V
= 3.6V
IN
-40
-20
0
20
40
60
80 100
TEMPERATURE (°C)
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SWITCHER Typical Performance Curves
Quiescent Current
Quiescent Current
vs
vs
Supply Voltage
Supply Voltage
(VCON = 2V, FB = 0V, No Switching, LDO Disabled)
(VCON = 2V, FB = 0V, No Switching, LDO Enabled)
Shutdown Current
vs
Switching Frequency
vs
Temperature
(VCON = 0V, EN = 0V)
Temperature
(VOUT = 1.3V, IOUT = 200mA)
4.0
3.0
V
= 5.5V
IN
2.0
1.0
V
= 4.2V
IN
0.0
-1.0
-2.0
-3.0
-4.0
V
= 3.6V
IN
V
= 2.7V
IN
-40 -20
0
20
40
60
80
100
AMBIENT TEMPERATURE (oC)
Output Voltage Regulation(%)
Output Voltage
vs
vs
Output Load
Temperature
(VOUT = 1.5V)
(VIN = 3.6V, VOUT = 0.8V)
-0.30
-0.25
-0.20
V
IN
= 3.6V
-0.15
-0.10
-0.05
-0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
V
= 2.7V
IN
V
IN
= 5.5V
V
= 4.5V
IN
0
100 200 300 400 500 600 700
OUTPUT LOAD (mA)
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SWITCHER Typical Performance Curves (continued)
Output Voltage
vs
Open/Closed Loop Current Limit
vs
Temperature
(VIN = 3.6V, VOUT = 3.4V)
Temperature
(PWM Mode)
VCON Voltage
vs
Efficiency
vs
Output Voltage
(VIN = 4.2V, RLOAD = 8Ω)
Output Voltage
(VIN = 3.9V)
Efficiency
vs
Efficiency
vs
Output Current
(VOUT = 0.8V)
Output Current
(VOUT = 3.4V)
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SWITCHER Typical Performance Curves (continued)
Load Transient Response
(VOUT = 0.8V)
Load Transient Response
(VIN = 4.2V, VOUT = 3.4V)
Startup
Startup
(VIN = 3.6V, VOUT = 1.3V, RLOAD = 1kΩ)
(VIN = 4.2V, VOUT = 3.4V, RLOAD = 5kΩ)
Shutdown Response
Line Transient Reponse
(VIN = 4.2V, VOUT = 3.4V, RLOAD = 10Ω)
(VIN = 3.0V to 3.6V, IOUT = 100mA)
V
SW
5V/DIV
V
V
= 4.2V
IN
V
OUT
= 3.4V
= 10W
OUT
2V/DIV
R
L
I
L
500 mA/DIV
2V/DIV
EN
40 ms/DIV
VCON Voltage Response
(VIN = 4.2V, VCON = 0.32V/1.44V, RLOAD = 10Ω)
VCON and Load Transient
(VIN = 4.2V, VCON = 0.32V/1.44V, RLOAD = 15Ω/8Ω)
V
SW
2V/DIV
2V/DIV
V
SW
3.6V
3.6V
VIN = 4.2V
VIN = 4.2V
V
OUT
VCON = 0.32/1.44V
RL = 10W
VCON = 0.32/1.44V
RL = 15W/8W
V
OUT
0.8V
0.8V
1.44V
1.44V
V
CON
V
CON
0.32V
0.32V
40 ms/DIV
40 ms/DIV
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SWITCHER Typical Performance Curves (continued)
Timed Current Limit Response
(VIN = 3.6V)
Output Voltage Ripple
(VOUT = 1.3V)
Output Voltage Ripple
(VOUT = 3.4V)
Output Voltage Ripple in Pulse Skip
(VIN = 3.64V, VOUT = 3.4V, RLOAD = 5Ω)
V
SW
2V/DIV
V
2V/DIV
SW
V
V
= 3.64V
IN
= 3.4V
OUT
VIN = 4.2V
R
L
= 5W
VOUT = 3.4V
IOUT = 200 mA
10 mV/DIV
AC Coupled
10 mV/DIV
AC Coupled
V
V
OUT
OUT
I
L
I
L
500 mA/DIV
500 mA/DIV
400 ns/DIV
400 ns/DIV
RDSON
vs
RDSON
vs
Temperature (microSMD)
(P-ch, ISW = 200mA)
Temperature (microSMD)
(N-ch, ISW = -200mA)
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SWITCHER Typical Performance Curves (continued)
EN High Threshold
vs
VIN
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Block Diagram
PV
IN
CURRENT
SENSE
OSCILLATOR
ERROR AMPLIFIER
FB
~
PWM
COMP
MOSFET
CONTROL
LOGIC
SW
V
CON
MAIN CONTROL
EN
SHUTDOWN
CONTROL
PGND
PVIN
Active Charge Control
Vref
LDO
LDO Control
(Over Current and Thermal
Protection)
EN
LDO
Active Discharge Control
PGND
Figure 2. Functional Block Diagram
Operation Description
The LM3207 is a simple, step-down DC-DC converter with a VREF LDO optimized for powering RF power
amplifiers (PAs) in mobile phones, portable communicators, and similar battery powered RF devices. The DC-DC
converter is designed to allow the RF PA to operate at maximum efficiency over a wide range of power levels
from a single Lithium-Ion battery cell. The DC-DC is based on current-mode buck architecture, with synchronous
rectification for high efficiency. It is designed for a maximum load capability of 650mA in PWM mode.
Maximum load range may vary from this depending on input voltage, output voltage and the inductor chosen.
The device has two pin-selectable operating modes required for powering RF PAs in mobile phones and other
sophisticated portable devices. Fixed-frequency PWM operation offers regulated output at high efficiency while
minimizing interference with sensitive IF and data acquisition circuits. Shutdown mode turns the device off and
reduces battery consumption to 0.01uA (typ).
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Efficiency is typically around 95% for a 400mA load with 3.9VIN, 3.4VOUT. The output voltage is dynamically
programmable from 0.8V (typ) to 3.6V (typ) by adjusting the voltage on the control pin without the need for
external feedback resistors. This ensures longer battery life by being able to change the PA supply voltage
dynamically depending on its transmitting power.
Additional features include current overload protection, and thermal overload shutdown.
The LM3207 is constructed using a chip-scale 9-pin micro SMD package. This package offers the smallest
possible size, for space-critical applications such as cell phones, where board area is an important design
consideration. Use of a high switching frequency (2MHz) reduces the size of external components. As shown in
Figure 1, only four external power components are required for implementation. Use of a micro SMD package
requires special design considerations for implementation. (See Micro SMD Package Assembly and use in the
Applications Information section.) The fine bump-pitch requires careful board design and precision assembly
equipment. Use of this package is best suited for opaque-case applications, where its edges are not subject to
high-intensity ambient red or infrared light. Also, the system controller should set EN low during power-up and
other low supply voltage conditions. (See Shutdown Mode in the Device Information section.)
V
IN
10 mF
3.3 mH
PV
IN
EN
SW
FB
TX_ON/OFF
V
CC
4.7 mF
R
F
I
RFin
VCON LM3207
DAC
PA
C
V
REF
EN
RF_ON/OFF
LDO
LDO
100 nF
Figure 3. Typical Application Circuit
Circuit Operation (DC-DC Converter)
Referring to Figure 1 and Figure 2, the LM3207 operates as follows. During the first part of each switching cycle,
the control block in the LM3207 turns on the internal PFET (P-channel MOSFET) switch. This allows current to
flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a
ramp with a slope of around (PVIN - VOUT) / L, by storing energy in a magnetic field. During the second part of
each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the
NFET (N-channel MOSFET) synchronous rectifier on. In response, the inductor’s magnetic field collapses,
generating a voltage that forces current from ground through the synchronous rectifier to the output filter
capacitor and load. As the stored energy is transferred back into the circuit and depleted, the inductor current
ramps down with a slope around VOUT / L. The output filter capacitor stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output
voltage is equal to the average voltage at the SW pin.
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PWM Operation
While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant
frequency and then modulating the energy per cycle to control power to the load. Energy per cycle is set by
modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by comparing
the signal from the current-sense amplifier with a slope compensated error signal from the voltage-feedback error
amplifier. At the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to
ramp up. When the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the
PFET switch and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load
pulls the output down, the error amplifier output increases, which allows the inductor current to ramp higher
before the comparator turns off the PFET. This increases the average current sent to the output and adjusts for
the increase in the load. Before appearing at the PWM comparator, a slope compensation ramp from the
oscillator is subtracted from the error signal for stability of the current feedback loop. The minimum on time of
PFET in PWM mode is 50ns (typ.)
Shutdown Mode
Setting the EN digital pin low (<0.5V) places the LM3207 in a 0.01µA (typ.) Shutdown mode. During shutdown,
the PFET switch, NFET synchronous rectifier, reference voltage source, control and bias circuitry of theLM3207
are turned off. Setting EN high (>1.2V) enables normal operation.
EN should be set low to turn off the LM3207 during power-up and under voltage conditions when the power
supply is less than the 2.7V minimum operating voltage. The LM3207 is designed for compact portable
applications, such as mobile phones. In such applications, the system controller determines power supply
sequencing and requirements for small package size outweigh the additional size required for inclusion of UVLO
(Under Voltage Lock-Out) circuitry.
Internal Synchronous Rectification
While in PWM mode, the LM3207 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across and ordinary rectifier
diode.
The internal NFET synchronous rectifier is turned on during the inductor current down slope in the second part of
each cycle. The synchronous rectifier is turned off prior to the next cycle. The NFET is designed to conduct
through its intrinsic body diode during transient intervals before it turns on, eliminating the need for an external
diode.
Current Limiting
A current limit feature allows the LM3207 to protect itself and external components during overload conditions. In
PWM mode, a 1200mA (max.) cycle-by-cycle current limit is normally used. If an excessive load pulls the output
voltage down to approximately 0.375V, then the device switches to a timed current limit mode. In timed current
limit mode the internal PFET switch is turned off after the current comparator trips and the beginning of the next
cycle is inhibited for 3.5us to force the instantaneous inductor current to ramp down to a safe value. The
synchronous rectifier is off in timed current limit mode. Timed current limit prevents the loss of current control
evident in some products when the output voltage is pulled low in serious overload conditions.
Dynamically Adjustable Output Voltage
The LM3207 features dynamically adjustable output voltage to eliminate the need for external feedback resistors.
The output can be set from 0.8V(typ.) to 3.6V(typ.) by changing the voltage on the analog VCON pin. This feature
is useful in PA applications where peak power is needed only when the handset is far away from the base station
or when data is being transmitted. In other instances the transmitting power can be reduced. Hence the supply
voltage to the PA can be reduced, promoting longer battery life. See Setting the Output Voltage in the Application
Information section for further details.
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Thermal Overload Protection
The LM3207 has a thermal overload protection function that operates to protect itself from short-term misuse and
overload conditions. When the junction temperature exceeds 150°C, the device inhibits operation. The PFET and
NFET are turned off in PWM mode. The LDO is turned off as well. When the temperature drops below 130°C,
normal operation resumes. Prolonged operation in thermal overload conditions may damage the device and is
considered bad practice.
LDO Operation
An LDO is used to provide a regulated Vref supply to a RF PA with a fixed voltage. The LDO can be enabled
only after the PWM is running. The LDO will automatically be disabled whenever the EN or ENLDO is disabled.
Included in the LDO are active charge and discharge circuits to quickly move a 100nF capacitor to meet the 3us
timing requirements, or an 220nF capacitor to meet the 5us timing requirements. The charging and discharging
currents are controlled to minimize supply disturbances. The LM3207 was designed specifically to work with a
100nF or a 220nF ceramic capacitor and no bypass capacitor. See Ordering Information table on page 2 for
Voltage Options.
Application Information
SETTING THE DC-DC CONVERTER OUTPUT VOLTAGE
The LM3207 features a pin-controlled variable output voltage to eliminate the need for external feedback
resistors. It can be programmed for an output voltage from 0.8V (typ.) to 3.6V (typ.) by setting the voltage on the
VCON pin, as in the following formula:
VOUT = 2.5 x VCON
(2)
When VCON is between 0.32V and 1.44V, the output voltage will follow proportionally by 2.5 times of VCON
.
If VCON is over 1.44V (VOUT = 3.6V), sub-harmonic oscillation may occur because of insufficient slope
compensation. If VCON voltage is less than 0.32V (VOUT = 0.8V), the output voltage may not be regulated due to
the required on-time being less than the minimum on-time (50ns). The output voltage can go lower than 0.8V
providing a limited VIN range is used. Refer to datasheet curve (VCON Voltage vs Output Voltage) for details. This
curve is for a typical part and there could have part-to-part variation for output voltages less than 0.8V over the
limited VIN range.
LDO CAPACITOR SELECTION
The output capacitor should be connected between the LDO output and a good ground connection. This
capacitor must be selected within specified capacitance range and have sufficiently low ESR. The ESR of the
capacitor is generally a major factor in LDO stability. Refer to manufacturer ESR curves for more detail. Table 2
suggests acceptable capacitors and their suppliers.
Table 2. Suggested capacitors and their suppliers
Model
Vendor
TDK
C1005X5R1A104KT, 100nF, 10V
C1005X5R0J224KT, 220nF, 6.3V
TDK
INDUCTOR SELECTION
A 3.3µH inductor with saturation current rating over 1200mA and low inductance drop at the full DC bias
condition is recommended for almost all applications. The inductor’s DC resistance should be less than 0.2Ω for
good efficiency. For low dropout voltage, lower DCR inductors are advantageous. The lower limit of acceptable
inductance is 1.7µH at 1200mA over the operating temperature range. Full attention should be paid to this limit,
because some small inductors show large inductance drops at high DC bias. These can not be used with the
LM3207. Table 3 suggests some inductors and suppliers.
Table 3. Suggested inductors and their suppliers
Model
Size (WxLxH) [mm]
Vendor
NR3015T3R3M
3.0 x 3.0 x 1.5
Taiyo-Yuden
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Table 3. Suggested inductors and their suppliers (continued)
Model
Size (WxLxH) [mm]
3.3 x 3.3 x 1.4
Vendor
DO3314-332MXC
MIPW3226D3R0M
Coilcraft
FDK
3.2 x 2.6 x 1.0
If a smaller inductance inductor is used in the application, the LM3207 may become unstable during line and load
transients and VCON transient response times may be affected. For low-cost applications, an unshielded bobbin
inductor is suggested. For noise critical applications, a toroidal or shielded-bobbin inductor is recommended. A
good practice is to layout the board with footprints accommodating both types for design flexibility. This allows
substitution of a low-noise toroidal inductor, in the event that noise from low-cost bobbin models is unacceptable.
Saturation occurs when the magnetic flux density from current through the windings of the inductor exceeds what
the inductor’s core material can support with a corresponding magnetic field. This can result in poor efficiency,
regulation errors or stress to DC-DC converter like the LM3207.
DC-DC CONVERTER CAPACITOR SELECTION
The LM3207 is designed with a ceramic capacitor for its input and output filters. Use a 10µF ceramic capacitor
for input and a 4.7µF ceramic capacitor for output. They should maintain at least 50% capacitance at DC bias
and temperature conditions. Ceramic capacitors types such as X5R, X7R are recommended for both filters.
These provide an optimal balance between small size, cost, reliability and performance for cell phones and
similar applications. Table 4 lists suggests acceptable part numbers and their suppliers. DC bias characteristics
of the capacitors must be considered when selecting the voltage rating and case size of the capacitor. If it is
necessary to choose a 0603-size capacitor for VIN, the operation of the LM3207should be carefully evaluated on
the system board. Output capacitors with smaller case sizes mitigate piezo electric vibrations when the output
voltage is stepped up and down at fast rates. However, they have a larger percentage drop in value with dc bias.
Use of multiple 2.2µF or 1µF capacitors in parallel may also be considered.
Table 4. Suggested capacitors and their suppliers
Model
Vendor
Taiyo-Yuden
TDK
0805ZD475KA, 4.7µF, 10V
C1608X5R0J475M, 4.7uF, 6.3V
C1608X5R0J106M, 10µF, 6.3V
C2012X5R0J106M, 10uF, 6.3V
C2012X5R1A475M, 4.7uF, 6.3V
TDK
TDK
TDK
The input filter capacitor supplies AC current drawn by the PFET switch of the LM3207 in the first part of each
cycle and reduces the voltage ripple imposed on the input power source. The output filter capacitor absorbs the
AC inductor current, helps maintain a steady output voltage during transient load changes and reduces output
voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR
(Equivalent Series Resistance) to perform these functions. The ESR of the filter capacitors is generally a factor in
voltage ripple.
EN PIN CONTROL
Drive the EN and ENLDO pins using the system controller to turn the LM3207 ON and OFF. Use a comparator,
Schmidt trigger or logic gate to drive the EN and ENLDO pins. Set EN high (>1.2V) for normal operation and low
(<0.5V) for a 0.01µA (typ.) shutdown mode.
Set EN low to turn off the LM3207 during power-up and under voltage conditions when the power supply is less
than the 2.7V minimum operating voltage. The part is out of regulation when the input voltage is less than 2.7V.
The LM3207 is designed for mobile phones where the system controller controls operation mode for maximizing
battery life and requirements for small package size outweigh the additional size required for inclusion of UVLO
(Under Voltage Lock-Out) circuitry.
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Micro SMD PACKAGE ASSEMBLY AND USE
Use of the Micro SMD package requires specialized board layout, precision mounting and careful re-flow
techniques, as detailed in National Semiconductor Application Note 1112. Refer to the section Surface Mount
Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board
should be used to facilitate placement of the device. The pad style used with Micro SMD package must be the
NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size.
This prevents a lip that otherwise forms if the solder-mask and pad overlap, from holding the device off the
surface of the board and interfering with mounting. See Application Note 1112 for specific instructions.
The 9-Bump package used for LM3207 has 300 micron solder balls and requires 10.82mil pads for mounting the
circuit board. The trace to each pad should enter with a 90° entry angle to prevent debris from being caught in
deep corners. Initially, the trace to each pad should be 6-7mil wide, for a section approximately 6mil long or
longer, to provide thermal relief. Each trace should then neck up or down to its optimal width. The important
criterion is symmetry. This ensures the solder bumps re-flow evenly and that the device solders level to the
board. In particular, special attention must be paid to the pads for bumps A1, A3 and B3. Because PGND and
PVIN are typically connected to large copper planes, inadequate thermal relief’s may result in late or inadequate
re-flow of these bumps. The Micro SMD package is optimized for the smallest possible size in applications with
red or infrared opaque cases. Because the Micro SMD package lacks the plastic encapsulation characteristic of
larger devices, it is vulnerable to light. Backside metalization and/or epoxy coating, along with front-side shading
by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. Micro SMD
devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges.
BOARD LAYOUT CONSIDERATIONS
V
IN
Fosc = 2 MHz
i
i
2.7V to 5.5V
L1
3.3 mH
V
PV
OUT
IN
SW
E
+
C1
10 mF
EN
EN
-
FB
LDO
C2
4.7 mF
+
ENLDO
LDO
LDO
+
OUT
V
CON
SGND
-
PGND
-
100 nF
C7
C
Figure 4. Current Loop
Referring to Figure 4, the LM3207 has two major current loops where pulse and ripple current flow. The loop
shown in the left hand side is most important, because pulse current shown in Figure 4 flows in this path. The
right hand side is next. The current waveform in this path is triangular, as shown in Figure 4. Pulse current has
many high-frequency components due to fast di/dt. Triangular ripple current also has wide high-frequency
components. Board layout and circuit pattern design of these two loops are the key factors for reducing noise
radiation and stable operation. Other lines, such as from battery to C1(+) and C2(+) to load, are almost DC
current, so it is not necessary to take so much care. Only pattern width (current capability) and DCR drop
considerations are needed.
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3.3 mH
4.7 mF
10 mF
100 nF
Figure 5. Evaluation Board Layout
BOARD LAYOUT FLOW
1. Minimize C1, PVIN, and PGND loop. These traces should be as wide and short as possible. This is most
important.
2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second
priority.
3. Above layout patterns should be placed on the component side of the PCB to minimize parasitic inductance
and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between C2(+) and
C2(-) land patterns. If vias are used in these large current paths, multiple via-holes should be used if
possible.
4. Connect C1(-), C2(-) and PGND with wide GND pattern. This pattern should be short, so C1(-), C2(-), and
PGND should be as close as possible. Then connect to a PCB common GND pattern with as many via-holes
as possible.
5. SGND should not connect directly to PGND. Connecting these pins under the device should be avoided. (If
possible, connect SGND to the common port of C1(-), C2(-) and PGND.)
6. FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a shield.
7. The LDO Cap C7 (CLDO) should be placed as close to the PA as possible and as far away from the switcher
to suppress high frequency switch noises.
NOTE
The evaluation board shown in Figure 5 for the LM3207 was designed with these
considerations, and it shows good performance. However some aspects have not been
optimized because of limitations due to evaluation-specific requirements. Please refer
questions to a National representative.
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PACKAGE OPTION ADDENDUM
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17-Nov-2012
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Samples
Drawing
(1)
(2)
(3)
(Requires Login)
LM3207TL-2.53/NOPB
LM3207TL/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
YZR
YZR
YZR
YZR
9
9
9
9
250
250
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
LM3207TLX-2.53/NOPB
LM3207TLX/NOPB
3000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3207TL-2.53/NOPB DSBGA
LM3207TL/NOPB DSBGA
LM3207TLX-2.53/NOPB DSBGA
LM3207TLX/NOPB DSBGA
YZR
YZR
YZR
YZR
9
9
9
9
250
250
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
2.08
2.08
2.08
2.08
2.08
2.08
2.08
2.08
0.76
0.76
0.76
0.76
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
3000
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3207TL-2.53/NOPB
LM3207TL/NOPB
DSBGA
DSBGA
DSBGA
DSBGA
YZR
YZR
YZR
YZR
9
9
9
9
250
250
203.0
203.0
206.0
206.0
190.0
190.0
191.0
191.0
41.0
41.0
90.0
90.0
LM3207TLX-2.53/NOPB
LM3207TLX/NOPB
3000
3000
Pack Materials-Page 2
MECHANICAL DATA
YZR0009xxx
TLA09XXX (Rev C)
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