LM3370SD-3013/NOPB [TI]
具有动态电压调节功能的双路同步降压直流/直流转换器 | NHR | 16 | -30 to 85;
| 型号： | LM3370SD-3013/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有动态电压调节功能的双路同步降压直流/直流转换器 | NHR | 16 | -30 to 85 开关 光电二极管 转换器 |
| 文件： | 总35页 (文件大小：5058K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM3370
www.ti.com
SNVS406N –NOVEMBER 2005–REVISED MAY 2013
LM3370 Dual Synchronous Step-Down DC-DC Converter
with Dynamic Voltage Scaling Function
Check for Samples: LM3370
1
FEATURES
APPLICATIONS
•
I2C-compatible interface
•
•
•
•
Baseband Processors
Application Processors (Video, Audio)
I/O Power
2
–
–
–
VOUT1 = 1V to 2V in 50 mV Steps
VOUT2 = 1.8V to 3.3V in 100 mV Steps
Automatic PFM/PWM Mode Switching and
Forced PWM Mode for Low Noise Operation
Spread Spectrum Capability Using I2C
FPGA Power and CPLD
DESCRIPTION
–
The LM3370 is a dual step-down DC-DC converter
optimized for powering ultra-low voltage circuits from
a single Li-Ion battery and input rail ranging from 2.7V
to 5.5V. It provides two outputs with 600mA load per
channel. The output voltage range varies from 1V to
3.3V and can be dynamically controlled using the I2C-
compatible interface. This dynamic voltage scaling
function allows processors to achieve maximum
performance at the lowest power level. The I2C-
compatible interface can also be used to control auto
PFM-PWM/PWM mode selection and other
performance enhancing features.
•
•
•
600mA Load Per Channel
2MHz PWM Fixed Switching Frequency (Typ.)
The Bucks Operate 180° Out-of-Phase Timing
Offset for Noise and Input Surge Current
Abatement
•
Internal Synchronous Rectification for High
Efficiency
•
•
•
•
Internal Soft Start
Power-on-Reset Function for Both Outputs
2.7V ≤ VIN ≤ 5.5V
The LM3370 offers superior features and
performance for portable systems with complex
Operates from a Single Li-Ion Cell or 3 Cell
NiMH/NiCd Batteries and 3.3V/5.5V Fixed Rails
power
management
requirements.
Automatic
•
•
•
2.2µH Inductor, 4.7µF Input and 10µF Output
Capacitor Per Channel
intelligent switching between PWM low-noise and
PFM low-current mode offers improved system
16-lead WSON Package (4 mm x 5 mm x 0.8
mm)
efficiency.
Internal
synchronous
rectification
enhances the converter efficiency without the use of
further external devices.
20-Bump DSBGA Package (3.0 mm x 2.0 mm x
0.6 mm)
Typical Application Circuit
C
IN1
4.7 mF
V
IN1
2.7V to 5.5V
FB1
SDA
V
OUT1
SW1
L1:2.2 mH
SCL
PGND1
SGND
C
OUT1
10 mF
nPOR1
nPOR2
EN1
V
V
IN1
IN2
LM3370
V
DD
V
IN1
4.7 mF
*
PGND2
SW2
V
OUT2
EN2
L2:2.2 mH
V
IN2
FB2
C
OUT2
10 mF
2.7V to 5.5V
C
IN2
4.7 mF
* Optional Capacitor
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM3370
SNVS406N –NOVEMBER 2005–REVISED MAY 2013
www.ti.com
DESCRIPTION (CONTINUED)
There is a power-on-reset function that monitors the level of the output voltage to avoid unexpected power
losses. The independent enable pin for each output allows for simple and effective power sequencing.
LM3370 is available in a 4mm by 5mm 16-lead non-pullback WSON and a 20-bump DSBGA, 3.0mm x 2.0mm x
0.6mm, package. A high switching frequency—2 MHz (typ)—allows use of tiny surface-mount components
including a 2.2µH inductor.
Default fixed voltages for the 2 output voltages combination can be customized to fit system requirements by
contacting Texas Instruments.
Functional Block Diagram
FB1
FB1
EN1
V
V
IN1
IN1
SDA
SDA
SCL
buck1 control
buck2 control
SW
SW1
Buck1
I2C
SCL
Registers
EPROM
POR1
PGND
PGND1
EN_bk1
EN_bk2
OR2
EN_I2C
SGND
nPOR1
nPOR2
U1
V
DD
U2
AND
AND
EN1
POR2
PGND
SW2
PGND2
SW2
Buck2
EN2
FB2
EN2
FB2
V
IN2
V
IN2
Typical Performance Curve
2
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SNVS406N –NOVEMBER 2005–REVISED MAY 2013
V
16
15
FB2
EN2
IN2
1
2
SW2
PGND2
3
14
13
12
EN1
V
DD
nPOR2
4
nPOR1
SCL
SGND
PGND1
SW1
5
6
11
10
SDA
7
8
FB1
9
V
IN1
Figure 1. WSON Connection Diagram
(See Package Number NHR0016B)
PIN DESCRIPTIONS (WSON)
Pin #
Name
VIN2
Description
1
2
Power supply voltage input to PFET and NFET switches for Buck 2
Buck 2 Switch Pin
SW2
PGND2
VDD
3
Buck 2 Power Ground
4
Signal supply voltage input, VDD must be equal or greater of the two inputs (VIN1 and VIN2
Signal GND
)
5
SGND
PGND1
SW1
VIN1
6
Buck 1 Power Ground
7
Buck 1 Switch Pin
8
Power supply voltage input to PFET and NFET switches for Buck 1
Analog Feedback Input for Buck 1
9
FB1
10
11
SDA
I2C-Compatible Data, a 2 kΩ pull up resistor is required
I2C-Compatible Clock, a 2 kΩ pull up resistor is required
SCL
Power ON Reset for Buck 1, Open drain output Low when Buck 1 output is 92% of target
output. A 100 kΩ pull up resistor is required
12
13
nPOR1
nPOR2
Power ON Reset for Buck 2, Open drain output Low when Buck 2 output is 92% of target
output. A 100 kΩ pull up resistor is required
14
15
16
EN1
EN2
FB2
Buck 1 Enable
Buck 2 Enable
Analog feedback for Buck 2
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4
3
SGND
A3
2
1
2
3
SGND
A3
4
1
FB1
VIN1
A2
FB1
SW1
A1
VIN1
A2
SW1
A1
A
B
A4
A
B
A4
SDA
B3
SCL
B4
PGND1_S PGND1
SDA
B3
PGND1 PGND1_S
SCL
B4
B1
B2
B1
B2
NPOR1
C3
SGND
C2
NPOR2
C4
VDD
C1
SGND
C2
NPOR1
C3
VDD
C1
NPOR2
C4
C
D
E
C
D
E
EN1
D4
EN2
D3
PGND2_S PGND2
PGND2 PGND2_S
EN2
D3
EN1
D4
D1
D2
D1
D2
SGND
E3
VIN2
E2
SW2
E1
FB2
E4
SW2
E1
VIN2
E2
SGND
E3
FB2
E4
Bottom View
Top View
Figure 2. DSBGA Connection Diagram
(See Package Number YZR0020DWA)
PIN DESCRIPTIONS (DSBGA)
Pin #
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
Name
SW1
Description
Buck 1 Switch Pin
VIN1
Power supply voltage input to PFET and NFET switches for Buck 1
Signal GND
SGND
FB1
Analog Feedback Input for Buck 1
PGND1
PGND1_S
SDA
Buck 1 Power Ground
Buck 1 Power Ground Sense
I2C-Compatible Data, a 2 kΩ pullup resistor is required
I2C-Compatible Clock, a 2 kΩ pullup resistor is required
SCL
VDD
Signal supply voltage input, VDD must be equal or greater of the two inputs ( VIN1 and VIN2
Signal GND
)
SGND
Power ON Reset for Buck 1, Open drain output Low when Buck 1 output is 92% of target output.
A 100 kΩ pullup resistor is required
C3
C4
nPOR1
nPOR2
Power ON Reset for Buck 2, Open drain output Low when Buck 2 output is 92% of target output.
A 100 kΩ pullup resistor is required
D1
D2
D3
D4
E1
E2
E3
E4
PGND2
PGND2_S
EN2
Buck 2 Power Ground
Buck 2 Power Ground Sense
Buck 2 Enable
EN1
Buck 1 Enable
SW2
Buck 2 Switch Pin
VIN2
Power supply voltage input to PFET and NFET switches for Buck 2
SGND
FB2
Signal GND
Analog feedback for Buck 2
4
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I2C Controlled Features
Features
Parameter
Comments
Output Voltage
VOUT1 and VOUT2
Output voltage is controlled via I2C-
compatible
Modes
Buck 1 and Buck 2
Buck 1 and Buck 2
Mode can be controlled via I2C
compatible by either forcing device
in Auto mode or forced PWM mode
Spread Spectrum capability via I2C-
compatible for noise reduction
Spread Spectrum
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)(2)
Ordering Information
Voltage Option (V)
LM3370 (WSON)
LM3370SD-3013
LM3370SDX-3013
LM3370SD-3021
LM3370SDX-3021
LM3370SD-3416
LM3370SDX-3416
LM3370SD-3621
LM3370SDX-3621
LM3370SD-3806
LM3370SDX-3806
LM3370SD-4221
LM3370SDX-4221
1.2 and 2.5
1.2 and 3.3
1.4 and 2.8
1.5 and 3.3
1.6 and 1.8
1.8 and 3.3
LM3370 (DSBGA)
LM3370TL-2613/NOPB
LM3370TLX-2613/NOPB
LM3370TL-3607/NOPB
LM3370TLX-3607/NOPB
LM3370TL-3008/NOPB
LM3370TLX-3008/NOPB
LM3370TL-3006/NOPB
LM3370TLX-3006/NOPB
LM3370TL-3806/NOPB
LM3370TLX-3806/NOPB
LM3370TL-3206/NOPB
LM3370TLX-3206/NOPB
LM3370TL-3022/NOPB
LM3370TLX-3022/NOPB
1.0 and 2.5
1.5 and 1.9
1.2 and 2.0
1.2 and 1.8
1.6 and 1.8
1.3 and 1.8
1.2 and 1.85
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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Absolute Maximum Ratings(1)(2)(3)
VIN1 , VIN2 VDD to PGND and SGND
−0.2V to 6V
−0.2V to +0.2V
PGND to SGND
SDA, SCL, EN, EN2, nPOR1, nPOR2, SW1, SW2, FB1 and FB2
(GND - 0.2) to (VIN + 0.2V)
Maximum Continuous Power
(4)
Dissipation (PD_MAX
)
Internally Limited
125°C
Junction Temperature (TJ-MAX
Storage Temperature Range
)
−65°C to +150°C
Maximum Lead Temperature
(Soldering)
(5)
(6)
ESD Ratings
All Pins
2 kV HBM
200V MM
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and
associated test conditions, see Electrical Characteristics.
(2) All voltages are with respect to the potential at the GND pin.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) Internal thermal shutdown circuitry protects the device from permanent damage. The thermal shutdown engages at TJ = 150°C (typ.)
and disengages at TJ = 140°C(typ.).
(5) For detailed soldering specifications and information, please refer to Texas Instruments Application Note 1187: Leadless Leadframe
Package (LLP) (SNOA401).
(6) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200 pF capacitor discharged directly into each pin. (EAIJ)
Operating Ratings(1)(2)
Input Voltage Range ((3)
)
2.7V to 5.5V
0 mA to 600 mA
−30°C to +125°C
−30°C to +85°C
Recommended Load Current Per Channel
Junction Temperature (TJ) Range
(4)
Ambient Temperature (TA) Range
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and
associated test conditions, see Electrical Characteristics.
(2) All voltages are with respect to the potential at the GND pin.
(3) Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages: VIN = 2.7V
to 5.5V for 1V ≤ VOUT ≤ 1.7V and for VOUT = 1.8V or greater, VIN = VOUT + 1VorVIN,MIN = ILOAD * (RDSON_PFET + RDCR_INDUCTOR) + VOUT
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
125ºC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
=
6
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Thermal Properties(1)
Junction-to-Ambient Thermal Resistance
θJA (WSON-16)
26°C/W
50°C/W
θJA (20-Bump DSBGA)
(1) Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2 x 1 array
of thermal vias. Thickness of copper layers are 2/1/1/2oz. Junction-to-ambient thermal resistance is highly application and board-layout
dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in
board design.The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In
applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues.
For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) (SNOA401).
Electrical Characteristics(1)(2)(3)
Typical limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range (TA = TJ = −30°C to +85°C). Unless otherwise noted, VIN1 = VIN2 = 3.6V.
Symbol
VFB
Parameter
Feedback Voltage
Conditions
Min
Typ
Max
+3.5
Units
%
(4)
−3.5
VOUT
Line Regulation
2.7V ≤ VIN ≤ 5.5V
0.031
%/V
IO = 10 mA, VOUT = 1.8V
Load Regulation
100 mA ≤ IO ≤ 600 mA
0.0013
%/mA
VIN = 3.6V, VOUT = 1.8V
IQ PFM
IQ SD
ILIM
Quiescent Current “On”
Quiescent Current “Off”
Peak Switching Current Limit
PFET
PFM Mode, Both Bucks ON
EN1 = EN2 = 0V
34
0.2
µA
µA
3
1400
500
350
400
210
2.4
1
VIN = 3.6V
850
1200
390
240
350
170
2.0
mA
RDS_ON
(WSON)
VIN = 3.6V, ISW = 200 mA
VIN = 3.6V, ISW = 200 mA
VIN = 3.6V, ISW = 200 mA
VIN = 3.6V, ISW = 200 mA
mΩ
mΩ
NFET
RDS_ON
(DSBGA)
PFET
NFET
FOSC
IEN
Internal Oscillator Frequency
Enable (EN) Input Current
Enable Logic Low
Enable Logic High
1.5
1.0
MHz
µA
V
0.01
VIL
0.4
VIH
V
POWER ON RESET THRESHOLD/FUNCTION (POR)
nPOR1 and
nPOR2
Delay Time
nPOR1 = Power ON Reset
for Buck 1
50 mS (default)
50
mS
%
nPOR2 = Power ON Reset
for Buck 2
Can be pre-trimmd to 50 uS, 100
mS and 200 mS
POR
Threshold
Percentage of Target VOUT
VOUT Rising
94
85
VOUT Falling, 85% (default), Can be
pre-trimmed to 70% or 94%
(1) All voltages are with respect to the potential at the GND pin.
(2) Min. and Max are specified by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are
tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
(3) Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages: VIN = 2.7V
to 5.5V for 1V ≤ VOUT ≤ 1.7V and for VOUT = 1.8V or greater, VIN = VOUT + 1VorVIN,MIN = ILOAD * (RDSON_PFET + RDCR_INDUCTOR) + VOUT
(4) Test condition: for VOUT less than 2.5V, VIN = 3.6V; for VOUT greater than or equal to 2.5V, VIN = VOUT + 1V.
Dissipation Rating Table
θJA
TA = 60°C
TA = 85°C
Power Rating
Power Rating
26°C/W (4-Layer Board) WSON-16
1538 mW
800 mW
50°C/W (4-Layer Board) 20-bump DSBGA
1300 mW
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Typical Performance Characteristics
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
=
IQ_PFM (Non Switching)
Both Channels
IQ_PWM (Non Switching)
Both Channels
1
0.06
0.05
85oC
0.8
85oC
0.04
0.03
0.02
25oC
0.6
0.4
0.2
0
25oC
-30oC
-30oC
0.01
0
2.7
3.4
4.1
(V)
4.8
5.5
2.7
3.4
4.1
(V)
4.8
5.5
V
IN
V
IN
Figure 3.
Figure 4.
IQ_PWM (Switching)
Both Channels
IQ_SD (EN1 = EN2 = 0V)
14
0.5
0.45
0.4
-30oC
12
10
25oC
0.35
0.3
85oC
8
6
4
2
0
0.25
0.2
0.15
0.1
0.05
0
2.7
2.7
3.4
4.1
(V)
4.8
5.5
3.4
4.1
(V)
4.8
5.5
V
V
IN
IN
Figure 5.
Figure 6.
RDS_ON (PFET)
vs.
Temperature
VIN = 3.6V
RDS_ON (NFET)
vs.
Temperature
VIN = 3.6V
350
300
250
200
500
450
400
350
300
250
200
LLP
LLP
micro SMD
micro SMD
150
100
-40
-20
0
20
40
60
80
-40 -20_
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7.
Figure 8.
8
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN
=
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
RDS_ON (WSON)
Current Limit
vs.
VIN
vs.
VIN
1200
1150
1100
1050
1000
500
450
400
PFET
85°C
25°C
-40°C
350
300
950
900
250
200
150
100
50
NFET
850
800
750
700
0
2.7
2.7 3.2 3.7
4.2 4.7 5.2 5.5
(V)
3.4
4.1
(V)
4.8
5.5
V
IN
V
IN
Figure 9.
Figure 10.
Output Voltage
vs.
Switching Frequency
vs.
VIN
Output Current
VIN = 3.6V (Forced PWM)
1.4
1.35
1.3
1.9
1.8
1.7
1.6
1.5
2.25
2.16
Buck1 = Buck2
1.8V
1.2V
1.25
1.2
2.07
1.98
1.89
1.8
1.15
1.1
1.05
1
2.7
3.4
4.1
(V)
4.8
5.5
0
100
200
300
400
500
600
V
LOAD (mA)
IN
Figure 11.
Figure 12.
Efficiency
vs.
Efficiency
vs.
Output Current
Output Current
Forced PWM Mode, VOUT1 = 1.2V
Forced PWM Mode, VOUT1 = 1.8V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
2.7V
2.7V
3.6V
4.5V
4.5V
3.6V
5.5V
5.5V
0.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
LOAD (mA)
LOAD (mA)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
=
Efficiency
Efficiency
vs.
vs.
Output Current
Auto Mode, VOUT1 = 1.5V
Output Current
Auto Mode, VOUT2 = 1.9V
Figure 15.
Figure 16.
Efficiency
vs.
Output Current
Auto Mode, VOUT2 = 3.3V
Efficiency
vs.
Output Current
Forced PWM Mode, VOUT2 = 3.3V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
4.5V
4.5V
5.5V
5.5V
0.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
LOAD (mA)
LOAD (mA)
Figure 17.
Figure 18.
Typical Operation Waveform
VIN = 3.6V, VOUT1 = 1.8V and VOUT2 = 1.8V
Load = 400 mA
Typical Operation Waveform
VIN = 4.8V, VOUT1 = 1V and VOUT2 = 3.3V
Load = 400 mA
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN
=
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
Typical Operation Waveform
VIN = 3.6V, VOUT1 = 1.5V, VOUT2 = 2.5V,
Load = 600 mA Each
Startup at PWM for BUCK1
(VIN = 3.6V, VOUT = 1.5V, Load = 200 mA)
Figure 21.
Figure 22.
Startup at PWM for BUCK2
(VIN = 3.6V, VOUT = 2.5V, Load = 200 mA)
Line Transient
(VOUT1 = 1.2V)
Figure 23.
Figure 24.
Line Transient
(VOUT2 = 1.8V)
Load Transient in PFM MODE
(VOUT1 = 1.5V)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
=
Load Transient in PFM MODE
Load Transient in PFM MODE
(VOUT1 = 1.5V)
(VOUT1 = 1.8V)
Figure 27.
Figure 28.
Load Transient in PWM MODE
(VIN = 3.6V, VOUT1 = 1.2V)
Load Transient in PFM MODE (VOUT1 = 1.8V)
Figure 29.
Figure 30.
Load Transient in PWM MODE
(VIN = 3.6V, VOUT1 = 1.5V)
Load Transient in PWM MODE
(VIN = 3.6V, VOUT2 = 2.5V)
Figure 31.
Figure 32.
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN
=
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
Spread Spectrum Enabling
(VOUT Signal at 2 MHz)
VOUT Stepping
(From 1.8V to 3.3V)
BUCK2 at 100 mV/STEP
No Spread Spectrum
3.3V
11 dB
With Spread
Spectrum
5 dB/DIV
1.8V
RBW = 1 kHz
1.92 1.94 1.96 1.98 2.0 2.02 2.04 2.06 2.08 2.1 2.12
100 ms/DIV
20 kHz/DIV
Figure 33.
Figure 34.
VOUT Stepping
(From 3.3V to 1.8V)
BUCK2 at 100 mV/STEP
3.3V
1.8V
100 ms/DIV
Figure 35.
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OPERATION DESCRIPTION
Device Information
The LM3370, a dual high efficiency step-down DC-DC converter, delivers regulated voltages from input rails
between 2.7V to 5.5V. Using voltage mode architecture with synchronous rectification, the LM3370 has the ability
to deliver up to 600 mA per channel. The performance is optimized for systems where efficiency and space are
critical.
There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode
handles loads of approximately 70 mA or higher with 90% efficiency or better. Lighter loads cause the device to
automatically switch into PFM mode to maintain high efficiency with low supply current (IQ = 20µA typ.) per
channel.
The LM3370 can operate up to a 100% duty cycle (PFET switch always on) for low drop out control of the output
voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.
Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload
protection.
Circuit Operation
During the first portion of each switching cycle, the control block in the LM3370 turns on the internal PFET
switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The
inductor limits the current to a ramp with a slope of
VIN -VOUT
L
(1)
by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the PFET
switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor
draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor
current down with a slope of
-VOUT
L
(2)
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage
across the load.
PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is
introduced.
Internal Synchronous Rectification
While in PWM mode, the LM3370 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
Current Limiting
A current limit feature allows the LM3370 to protect itself and external components during overload conditions.
PWM mode implements cycle-by-cycle current limiting using an internal comparator that trips at 1200 mA (typ.).
If the outputs are shorted to ground the device enters a timed current limit mode where the NFET is turned on for
a longer duration until the inductor current falls below a low threshold, ensuring inductor has more time to decay,
thereby preventing runaway.
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PFM Operation
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The part will automatically transition into PFM mode when either of two conditions are true, for a duration of 32 or
more clock cycles:
1. The NFET current reaches zero.
2. The peak PFET switch current drops below the IMODE level .
VIN
)
(Typically IMODE < 66 mA +
160W
(3)
Supply current during this PFM mode is less than 20 µA per channel, which allows the part to achieve high
efficiency under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle
repeats to restore the output voltage to ∼1.2% above the nominal PWM output voltage.
If the load current should increase during PFM mode (see Figure 36) causing the output voltage to fall below the
‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output
voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PFET power switch is turned on.
It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level
set for PFM mode. The typical peak current in PFM mode is:
IPFM = 115 mA + VIN/57Ω
(4)
Once the PFET power switch is turned off, the NFET power switch is turned on until the inductor current ramps
to zero. When the NFET zero-current condition is detected, the NFET power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold (see Figure 36), the PFET switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NFET switch is turned on briefly to ramp the inductor current to zero and then both output switches
are turned off and the part enters an extremely low power mode.
Forced PWM Mode
The LM3370 auto mode can be bypassed by forcing the device to operate in PWM mode, this can be
implemented through the I2C-compatible interface, see Table 3.
Soft-Start
The LM3370 has a soft start circuit that limits in-rush current during start up. Soft start is activated only if EN
goes from logic low to logic high after VIN reaches 2.7V.
LDO - Low Drop Out Operation
The LM3370 can operate at 100% duty cycle (no switching, PFET switch completely on) for low drop out support
of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.
The minimum input voltage needed to support the output voltage is
VIN,MIN = ILOAD*(RDSON,PFET + RINDUCTOR) + VOUT
where
•
•
•
ILOAD load current
• RDSON/PFET drain to source resistance of PFET switch in the triode region
• RINDUCTOR inductor resistance
(5)
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High PFM Threshold
~1.016*Vout
PFM Mode at Light Load
Load current
increases
Low1 PFM Threshold
~1.008*Vout
Current load
increases,
draws Vout
towards
Low2 PFM
Threshold
High PFM
Nfet on
Low PFM
Threshold,
turn on
Pfet on
until
Ipfm limit
reached
Voltage
Threshold
reached,
go into
drains
conductor
current
until
I inductor=0
PFET
Low2 PFM Threshold
Vout
sleep mode
PWM Mode at
Moderate to Heavy
Loads
Low2 PFM Threshold,
switch back to PWM mode
Figure 36. Operation in PFM Mode and Transfer to PWM Mode
Table 1. I2C-Compatible Interface Electrical Specifications(1)
Symbol
FCLK
Parameter
Conditions
Min
Typ
Max
Units
kHz
µS
Clock Frequency
400
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
tBF
Bus-Free Time between Start and Stop
Hold Time Repeated Start Condition
CLK Low Period
1.3
0.6
1.3
0.6
0.6
200
200
0.6
tHOLD
tCLKLP
tCLKHP
tSU
µS
µS
CLK High Period
µS
Set Up Time Repeated Start Condition
Data Hold Time
µS
tDATAHLD
tCLKSU
TSU
nS
Data Set Up Time
nS
Set Up Time for Start Condition
µS
TTRANS
Maximum Pulse Width of Spikes that Must be Suppressed
by the Input Filter of Both DATA and CLK signals.
50
nS
VDD_I2C
I2C Logic High Level
1
VIN
V
(1) Unless otherwise noted, VBATT = 2.7V to 5.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −30°C to +125°C.
(2) Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages: VIN = 2.7V
to 5.5V for 1V ≤ VOUT ≤ 1.7V and for VOUT = 1.8V or greater, VIN = VOUT + 1VorVIN,MIN = ILOAD * (RDSON_PFET + RDCR_INDUCTOR) + VOUT
I2C-Compatible Interface
In I2C-compatible mode, the SCL pin is used for the I2C clock and the SDA pin is used for the I2C data. Both
these signals need a pull-up resistor according to I2C specification. The values of the pull-up resistor are
determined by the capacitance of the bus (typ. ∼1.8k). Signal timing specifications are according to the I2C bus
specification. Maximum frequency is 400 kHz.
I2C-Compatible Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
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SCL
SDA
data
data
data
data valid
data valid
change
allowed
change
allowed
change
allowed
Figure 37.
I2C-Compatible START and STOP Conditions
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
START condition
STOP condition
Figure 38.
Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by
an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the
9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an
acknowledge after each byte has been received.
After the START condition, I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the data will be written. The third byte contains data to write
to the selected register.
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I2C-Compatible Write Cycle
ack from slave
ack from slave
ack from slave
start msb Chip Address lsb
w
ack msb Register Add lsb ack msb
DATA
lsb ack stop
SCL
SDA
start
id = h‘xx
w
ack
addr = h‘02
ack
address h‘02 data
ack stop
W = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated startxx=36h
Figure 39.
However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as
shown in I2C-Compatible Read Cycle
I2C-Compatible Read Cycle
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb
w
ack msb Register Add lsb ack rs
msb Chip Address lsb
r
ack msb
DATA
lsb ack stop
SCL
SDA
start
id = h‘xx
w
ack
addr = h‘00
ack rs
id = h‘xx
r
ack
address h‘00 data
ack stop
Figure 40.
Device Register Information
Table 2. Register Information
Register Name
Control
Location
Type
Function
00
01
02
R/W
R/W
R/W
Control signal for Buck 1 and Buck 2
Buck 1
Buck 2
Output setting and Mode selection for Buck 1
Output setting and Mode selection for Buck 2 and POR disable
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I2C Chip Address Information
MSB
LSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
1
0
0
0
0
1
2
I C SLAVE address (chip address)
Figure 41.
Register 00
MSB
7
LSB
6
5
4
3
2
1
0
EN1 for Buck 1 (default = 1)
Bit0 = 1 to enable
EN2 for Buck 2 (default = 1)
Bit1 = 1 to enable
Spread Spectrum (SS) Enable
Bit2 = 1 to enable
SS_fmod (SS Frequency Modulator)
ss_fmod = 1 1 kHz (default)
ss_fmod = 0 2 kHz
mstep Enable for Buck1
mstep = 0 (default) not enable
mstep = 1
50 mV/step at 32 ms/step
mstep Enable for Buck2
mstep = 0 (default) not enable
mstep = 1
100 mV/step at 32 ms/step
Bit 6 & 7 are not used
Register 01
MSB
LSB
0
7
6
5
4
3
2
1
Vout for Buck 1
00101 = 1V (Min.)
11111 = 2V (Max.)
Forced PWM Mode (FPWM1)
Auto = 0 (default)
FPWM1 = 1 (PWM mode only)
Bit 6 and 7 are not used
Figure 42.
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Register 02
MSB
LSB
0
7
6
5
4
3
2
1
Vout for Buck 2
00001 = 1.8V (Min.)
11111 = 3.3V (Max.)
Forced PWM Mode (FPWM2)
Auto = 0 (default)
FPWM2 = 1 (PWM mode only)
Disable Por function (DISPOR)
DISPOR = 0
DISPOR = 1
enable Por (default)
disable Por
Bit 7 is not used
Figure 43.
Table 3. Output Selection Table via I2C Programing
Buck Output Voltage Selection Codes
Data Code
Buck_1 (V)
NA
Buck_2 (V)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
NA
1.8
NA
NA
1.85 or 1.9(1)
NA
2.0
NA
2.1
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
NA
NA
NA
NA
NA
NA
NA
NA
NA
(1) Can be trimmed at the factory at 1.85V or 1.9V using the same trim code.
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Application Information
Setting Output Voltage via I2C-Compatible
The outputs of the LM3370 can be programmed through Buck 1 and Buck 2 registers via I2C. Buck 1 output
voltage can be dynamically adjusted between 1V to 2V in 50 mV steps and Buck 2 output voltage can be
adjusted between 1.8V to 3.3V in 100 mV steps. Finer adjustments to the output of Buck 2 can be achieved with
the placement of a resistor between VOUT2 and the FB2 pin. Typically by placing a 20 KΩ resistor, R, between
these nodes will result in the programmed Output Voltage increasing by approximately 45 mV,ΔVTYP
.
ΔVTYP= R × 500mV / 234KΩ
(6)
Please refer to for programming the desire output voltage. If the I2C-compatible feature is not used, the default
output voltage will be the pre-trimmed voltage. For example, LM3370SD-3021 refers to 1.2V for Buck 1 and 3.3V
for Buck 2.
VDD Pin
VDD is the power supply to the internal control circuit, if VDD pin is not tied to VIN during normal operating
condition, VDD must be set equal or greater of the two inputs ( VIN1 or VIN2 ). An optional capacitor can be used
for better noise immunity at VDD pin or when VDD is not tied to either VIN pins. Additionally, for reasons of noise
suppression, it is advisable to tie the EN1/EN2 pins to VDD rather than VIN
.
SDA, SCL Pins
When not using I2C the SDA and SCL pins should be tied directly to the VDD pin.
Micro-Stepping:
The Micro-Stepping feature minimizes output voltage overshoot/undershoot during large output transients. If
Micro-stepping is enabled through I2C, the output voltage automatically ramps at 50 mV per step for Buck 1 and
100 mV per step for Buck 2. The steps are summarized as follow:
•
•
Buck 1: 50 mV/step and 32 µs/step
Buck 2: 100 mV/step and 32 µs/step
For example if changing Buck 1 voltage from 1V to 1.8V yields 20 steps [(1.8 - 1)/ 0.05 = 20]. This translates to
640 μs [(20 x 32 µs) = 640 µs] needed to reach the final target voltage.
Inductor Selection
There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor
current ripple is small enough to achieve the desired output voltage ripple.
There are two methods to choose the inductor current rating.
method 1:
The total current is the sum of the load and the inductor ripple current. This can be written as
IRIPPLE
)
IMAX = ILOAD + (
2
VIN - VOUT
2 * L
VOUT
VIN
1
f
) * (
) * (
)
= ILOAD + (
where
•
•
•
•
ILOAD load current
VIN input voltage
L inductor
f switching frequency
(7)
21
method 2:
A more conservative approach is to choose an inductor that can handle the maximum current limit of 1400 mA.
Given a peak-to-peak current ripple (IPP) the inductor needs to be at least
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VIN - VOUT
VOUT
VIN
1
f
L >= (
) * (
) * (
)
IPP
(8)
A 2.2 µH inductor with a saturation current rating of at least 1400 mA is recommended for most applications. The
inductor’s resistance should be less than around 0.2Ω for good efficiency. Table 4 lists suggested inductors and
suppliers.
For low-cost applications, an unshielded bobbin inductor is suggested. For noise critical applications, a toroidal or
shielded-bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of
both types for design flexibility. This allows substitution of a low-noise toroidal inductor, in the event that noise
from low-cost bobbin models is unacceptable.
Below are some suggested inductor manufacturers that include but are not limited to:
Table 4. Suggested Inductors and Suppliers
Model
DO3314-222
Vendor
Dimensions (mm)
3.3 x 3.3 x 1.4
3.3 x 3.3 x 1.0
3.1 x 3.1 x 1.4
3.0 x 3.0 x 1.0
3.0 x 3.0 x 1.5
2.6 x 2.8 x 1.0
ISAT
1.6A
1.1A
1.48A
1.1A
1.48A
1.0A
Coilcraft
LPO3310-222
SD3114-2R2
Cooper
NR3010T2R2M
NR3015T2R2M
VLF3010AT- 2R2M1R0
Taiyo Yuden
TDK
Input Capacitor Selection
A ceramic input capacitor of 4.7 μF, 6.3V is sufficient for most applications. A larger value may be used for
improved input voltage filtering. The input filter capacitor supplies current to the PFET switch of the LM3370 in
the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor's
low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select
an input filter capacitor with a surge current rating sufficient for the power-up surge from the input power source.
The power-up surge current is approximately the capacitor’s value (µF) times the voltage rise rate (V/µs).
The input current ripple can be calculated as:
VOUT
VIN
VOUT
VIN
≈
∆
«
’
÷
◊
1 -
IRMS = IOUTMAX
*
*
The worst case IRMS is:
IOUTMAX
(duty cycle = 50%)
IRMS
=
2
(9)
Output Capacitor Selection
DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603.
DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested from
them as part of the capacitor selection process.
The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output
voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with
sufficient capacitance and sufficiently low ESR to perform these functions. The output ripple voltage can be
calculated as:
Voltage peak-to-peak ripple due to capacitance =
IPP
=
VPP-C
f*8*C
(10)
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Voltage peak-to-peak ripple due to ESR = VPP-ESR = IPP*RESR
Voltage peak-to-peak ripple, root mean squared =
2
VPP-RMS
=
VPP-C2 + VPP-ESR
(11)
Note that the output ripple is dependent on the current ripple and the equivalent series resistance of the output
capacitor (RESR). The RESR is frequency dependent (as well as temperature dependent); make sure that the
frequency of the RESR given is the same order of magnitude as the switching frequency.
Table 5. Suggested Capacitors and Their Suppliers
Model
Description
Case Size
Vendor
4.7 µF for CIN
C1608X5R0J475
C2012X5R0J475
JMK212BJ475
Ceramic, X5R, 6.3V Rating
Ceramic, X5R, 6.3V Rating
Ceramic, X5R, 6.3V Rating
Ceramic, X5R, 6.3V Rating
Ceramic, X5R, 6.3V Rating
0603
0805
0805
0805
TDK
Taiyo Yuden
muRata
GRM21BR60J475
GRM219R60J-
475KE19D
0805(Thin)
<1mm Height
10µF COUT
C2012X5R0J106
JMK212BJ106
Ceramic, X5R, 6.3V Rating
Ceramic, X5R, 6.3V Rating
Ceramic, X5R, 6.3V Rating
Ceramic, X5R, 6.3V Rating
0805
0805
0805
TDK
Taiyo Yuden
GRM21BR60J106
muRata
GRM219R60J-
106KE19D
0805(Thin)
< 1mm Height
POR (Power on Reset)
The LM3370 has an independent POR functions (nPOR) for each buck converter. The nPOR1 and nPOR2 are
open drain circuits which pull low when the outputs are below 94% (rising VOUT) or 85% (falling VOUT) of the
desire output. The inherent delay between the output (at 94% of VOUT) to the time at which the nPOR is enabled
is about 50 ms. A pullup resistor of 100 kΩ at nPOR pin is required. Please refer to the electrical specification
table for other timing options. The diagram below illustrates the timing response of the POR function.
EN
T
POR
T
POR
94%
VOUT
85%
nPOR
Figure 44.
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SNVS406N –NOVEMBER 2005–REVISED MAY 2013
www.ti.com
Spread Spectrum (SS)
The LM3370 features Spread Spectrum capability, via I2C, to reduce the noise amplitude of the switching
frequency during data transmission. The feature can be enabled by activating the appropriate control register bit
(see Table 2 for details). The main clock of the LM3370 features spread spectrum at FOSC = 2 MHz ± 22 kHz (
peak frequency deviation) with the modulation frequency of either 1 kHz (default) or 2 kHz via I2C. This help
reduce noise caused by the harmonics present in the waveforms at the switch pins of the buck regulators. It is
controlled by I2C in the following manner:
I2C bit
Modulation Frequency
SS_fmod = 1 (default)
SS_fmod = 0
1 kHz
2 kHz
Board Layout Considerations
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or
instability.
Good layout for the LM3370 can be implemented by following a few simple design rules:
1. Place the LM3370, inductor and filter capacitors close together and make the traces short. The traces
between these components carry relatively high switching currents and act as antennas. Following this rule
reduces radiated noise. Place the capacitors and inductor within 0.2 in. (5mm) of the LM3370.
2. Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor, through the LM3370 and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground, through the LM3370 by the inductor, to the output filter capacitor and then back through
ground, forming a second current loop. Routing these loops so the current curls in the same direction
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
3. Connect the ground pins of the LM3370, and filter capacitors together using generous component-side
copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several
vias. This reduces ground-plane noise by preventing the switching currents from circulating through the
ground plane. It also reduces ground bounce at the LM3370 by giving it a low-impedance ground connection.
4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces.
5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power
components. The voltage feedback trace must remain close to the LM3370 circuit and should be direct but
should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace.
6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through
distance.
In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board,
arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive
preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a
metal pan and power to it is post-regulated to reduce conducted noise, using low-dropout linear regulators.
DSBGA Package Assembly and Use
Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow
techniques, as detailed in Texas Instruments Application Note 1112 (SNVA009). Refer to the section Surface
Mount Technology Assembly Considerations. For best results in assembly, alignment ordinals on the PC board
should be used to facilitate placement of the device. The pad style used with DSBGA package must be the
NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size.
This prevents a lip that otherwise forms if the solder-mask and pad overlap, from holding the device off the
surface of the board and interfering with mounting. See Application Note 1112 (SNVA009) for specific
instructions how to do this. The 20-bump DSBGA package used for the LM3370 has 300 micron solder balls and
requires 10.82 mils pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90°
24
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Product Folder Links: LM3370
LM3370
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SNVS406N –NOVEMBER 2005–REVISED MAY 2013
entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 7 mil
wide, for a section approximately 7 mil long or longer, as a thermal relief. Then each trace should neck up or
down to its optimal width. The important criteria is symmetry. This ensures the solder bumps on the LM3370
DSBGA package re-flow evenly and that the device solders level to the board. In particular, special attention
must be paid to the pads for bumps A2/B1 of VOUT1, and E2/D1 of VOUT2, because VIN and PGND are typically
connected to large copper planes, inadequate thermal relief can result in late or inadequate re-flow of these
bumps.
The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque
cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is
vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed
circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA
devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges.
Copyright © 2005–2013, Texas Instruments Incorporated
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SNVS406N –NOVEMBER 2005–REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision M (May 2013) to Revision N
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
26
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Product Folder Links: LM3370
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-30 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
LM3370SD-3013/NOPB
LM3370SD-3021/NOPB
LM3370SD-3416/NOPB
LM3370SD-3621/NOPB
LM3370SD-3806/NOPB
LM3370SD-4221/NOPB
LM3370SDX-3013/NOPB
LM3370SDX-3021/NOPB
LM3370SDX-3416/NOPB
LM3370SDX-3621/NOPB
LM3370SDX-3806/NOPB
LM3370SDX-4221/NOPB
LM3370TL-3006/NOPB
LM3370TL-3008/NOPB
LM3370TL-3022/NOPB
LM3370TL-3206/NOPB
LM3370TL-3607/NOPB
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
NHR
16
16
16
16
16
16
16
16
16
16
16
16
20
20
20
20
20
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
S0003UB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
YZR
YZR
YZR
YZR
YZR
1000
1000
1000
1000
1000
4500
4500
4500
4500
4500
4500
250
Green (RoHS
& no Sb/Br)
-30 to 85
S0003TB
S0003VB
S0004AB
S0003XB
S0003YB
S0003UB
S0003TB
S0003VB
S0004AB
S0003XB
S0003YB
SPUB
Green (RoHS
& no Sb/Br)
CU SN
-30 to 85
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
-30 to 85
-30 to 85
-30 to 85
-30 to 85
-30 to 85
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
-30 to 85
-30 to 85
-30 to 85
-30 to 85
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
250
Green (RoHS
& no Sb/Br)
SPTB
250
Green (RoHS
& no Sb/Br)
STHB
250
Green (RoHS
& no Sb/Br)
-30 to 85
-30 to 85
SPXB
250
Green (RoHS
& no Sb/Br)
SPSB
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-30 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
LM3370TL-3806/NOPB
LM3370TLX-3006/NOPB
LM3370TLX-3008/NOPB
LM3370TLX-3022/NOPB
LM3370TLX-3206/NOPB
LM3370TLX-3607/NOPB
LM3370TLX-3806/NOPB
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YZR
20
20
20
20
20
20
20
250
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SPVB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
YZR
YZR
YZR
YZR
YZR
YZR
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
-30 to 85
SPUB
SPTB
STHB
SPXB
SPSB
SPVB
Green (RoHS
& no Sb/Br)
-30 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-30 to 85
-30 to 85
-30 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3370SD-3013/NOPB WSON
LM3370SD-3021/NOPB WSON
LM3370SD-3416/NOPB WSON
LM3370SD-3621/NOPB WSON
LM3370SD-3806/NOPB WSON
LM3370SD-4221/NOPB WSON
LM3370SDX-3013/NOPB WSON
LM3370SDX-3021/NOPB WSON
LM3370SDX-3416/NOPB WSON
LM3370SDX-3621/NOPB WSON
LM3370SDX-3806/NOPB WSON
LM3370SDX-4221/NOPB WSON
LM3370TL-3006/NOPB DSBGA
LM3370TL-3008/NOPB DSBGA
LM3370TL-3022/NOPB DSBGA
LM3370TL-3206/NOPB DSBGA
LM3370TL-3607/NOPB DSBGA
LM3370TL-3806/NOPB DSBGA
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
YZR
YZR
YZR
YZR
YZR
YZR
16
16
16
16
16
16
16
16
16
16
16
16
20
20
20
20
20
20
1000
1000
1000
1000
1000
1000
4500
4500
4500
4500
4500
4500
250
178.0
178.0
178.0
178.0
178.0
178.0
330.0
330.0
330.0
330.0
330.0
330.0
178.0
178.0
178.0
178.0
178.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
8.4
4.3
4.3
5.3
5.3
1.3
1.3
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
4.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
4.3
5.3
1.3
4.3
5.3
1.3
4.3
5.3
1.3
4.3
5.3
1.3
4.3
5.3
1.3
4.3
5.3
1.3
4.3
5.3
1.3
4.3
5.3
1.3
4.3
5.3
1.3
4.3
5.3
1.3
2.18
2.18
2.18
2.18
2.18
2.18
3.12
3.12
3.12
3.12
3.12
3.12
0.76
0.76
0.76
0.76
0.76
0.76
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
250
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3370TLX-3006/NOPB DSBGA
LM3370TLX-3008/NOPB DSBGA
LM3370TLX-3022/NOPB DSBGA
LM3370TLX-3206/NOPB DSBGA
LM3370TLX-3607/NOPB DSBGA
LM3370TLX-3806/NOPB DSBGA
YZR
YZR
YZR
YZR
YZR
YZR
20
20
20
20
20
20
3000
3000
3000
3000
3000
3000
178.0
178.0
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
2.18
2.18
2.18
2.18
2.18
2.18
3.12
3.12
3.12
3.12
3.12
3.12
0.76
0.76
0.76
0.76
0.76
0.76
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3370SD-3013/NOPB
LM3370SD-3021/NOPB
LM3370SD-3416/NOPB
LM3370SD-3621/NOPB
LM3370SD-3806/NOPB
LM3370SD-4221/NOPB
LM3370SDX-3013/NOPB
LM3370SDX-3021/NOPB
LM3370SDX-3416/NOPB
LM3370SDX-3621/NOPB
LM3370SDX-3806/NOPB
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
NHR
16
16
16
16
16
16
16
16
16
16
16
1000
1000
1000
1000
1000
1000
4500
4500
4500
4500
4500
210.0
210.0
210.0
210.0
210.0
210.0
367.0
367.0
367.0
367.0
367.0
185.0
185.0
185.0
185.0
185.0
185.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3370SDX-4221/NOPB
LM3370TL-3006/NOPB
LM3370TL-3008/NOPB
LM3370TL-3022/NOPB
LM3370TL-3206/NOPB
LM3370TL-3607/NOPB
LM3370TL-3806/NOPB
LM3370TLX-3006/NOPB
LM3370TLX-3008/NOPB
LM3370TLX-3022/NOPB
LM3370TLX-3206/NOPB
LM3370TLX-3607/NOPB
LM3370TLX-3806/NOPB
WSON
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
NHR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
YZR
16
20
20
20
20
20
20
20
20
20
20
20
20
4500
250
367.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
367.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
250
250
250
250
250
3000
3000
3000
3000
3000
3000
Pack Materials-Page 3
MECHANICAL DATA
NHR0016B
SDA16B (Rev A)
www.ti.com
MECHANICAL DATA
YZR0020xxx
D
0.600±0.075
E
TLA20XXX (Rev D)
D: Max = 3.025 mm, Min =2.965 mm
E: Max = 2.086 mm, Min =2.026 mm
4215053/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
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