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LM3424-Q1

SNVSB96 –JULY 2019

LM3424-Q1 Constant Current N-channel Controller

with Thermal Foldback For Driving LEDs

1 Features

3 Description

The LM3424-Q1 is a versatile high voltage N-channel

MOSFET controller for LED drivers. It can be easily

configured in buck, boost, buck-boost and SEPIC

topologies. In addition, the LM3424-Q1 includes a

1

•

AEC Qualified for automotive applications

–

Device temperature grade 1: −40°C ≤ T_A≤

125°C

•

V_INrange from 4.5 V to 75 V

thermal

foldback

feature

for

temperature

management of the LEDs. This flexibility, along with

an input voltage rating of 75 V, makes the LM3424-

Q1 ideal for illuminating LEDs in a large family of

applications.

High-side adjustable current sense

2-Ω, 1-A peak MOSFET gate driver

Input undervoltage and output overvoltage

protection

Adjustable high-side current sense allows for tight

regulation of the LED current with the highest

efficiency possible. The LM3424-Q1 uses standard

peak current-mode control providing inherent input

voltage feed-forward compensation for better noise

immunity. It is designed to provide accurate thermal

foldback with a programmable foldback breakpoint

and slope. In addition, a 2.45V reference is provided.

•

PWM and analog dimming

Cycle-by-cycle current limit

Programmable soft-start and slope compensation

Programmable, synchronizable switching

frequency

•

Programmable thermal foldback

Precision voltage reference

The LM3424-Q1 includes a high-voltage startup

regulator that operates over a wide input range of 4.5

V to 75 V. The internal PWM controller is designed

for adjustable switching frequencies of up to 2.0 MHz

and external synchronization is possible. The

controller is capable of high speed PWM dimming

and analog dimming.

Low-power shutdown and thermal shutdown

2 Applications

•

LED Drivers (buck, boost, buck-boost, and

SEPIC)

•

Indoor and outdoor area SSL

Automotive

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

General illumination

LM3424-Q1

HTSSOP (20)

6.50 mm × 4.40 mm

Constant-current regulators

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Boost Application Circuit

V_IN

1

2

20

19

18

17

16

15

14

13

12

11

VIN

HSP

HSN

SLOPE

IS

LM3424-Q1

EN

3

COMP

CSH

4

I_LED

5

RT/SYNC

nDIM

VCC

GATE

GND

DDRV

OVP

VS

6

PWM

7

SS

8

TGAIN

TSENSE

TREF

9

TEMP

DAP

10

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM3424-Q1

SNVSB96 –JULY 2019

www.ti.com

Table of Contents

7.4 Device Functional Modes........................................ 25

Application and Implementation ........................ 26

8.1 Application Information............................................ 26

8.2 Typical Applications ................................................ 29

Power Supply Recommendations...................... 61

9.1 Input Supply Current Limit ...................................... 61

1

2

3

4

5

6

Features.................................................................. 1

8

9

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics ............................................. 8

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 12

10 Layout................................................................... 61

10.1 Layout Guidelines ................................................. 61

10.2 Layout Example .................................................... 62

11 Device and Documentation Support ................. 63

11.1 Device Support...................................................... 63

11.2 Community Resources.......................................... 63

11.3 Trademarks........................................................... 63

11.4 Electrostatic Discharge Caution............................ 63

11.5 Glossary................................................................ 63

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 63

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

VERSION

NOTES

Initial release of separate data sheet for the automotive grade

device. For revision history before February 2019, see the LM3424

data sheet.

July 2019

*

Changed EN Pulldown Resistance maximum value from: 1.3 MΩ to:

2.85 MΩ in the Electrical Characteristics table.

Changed EN Pulldown Resistance minimum value from: 0.45 MΩ to:

0.245 MΩ in the Electrical Characteristics table.

2

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5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP With PowerPAD™

Top View

1

2

3

4

5

6

7

8

9

20 HSP

19 HSN

18 SLOPE

17 IS

V

IN

EN

COMP

CSH

21

V

16

RT

CC

DAP

nDIM

15 GATE

14 GND

13 DDRV

12 OVP

SS

TGAIN

TSENSE

V

11

TREF 10

S

Pin Functions

NAME

I/O

DESCRIPTION

NO.

Bypass with 100 nF capacitor to GND as close to the device as

possible.

1

V_IN

I

Input Voltage

Connect to > 2.4V to enable the device or to < 0.8V for low power

shutdown.

2

3

EN

I

Enable

COMP

Compensation

Connect a capacitor to GND to compensate control loop.

Connect a resistor to GND to set the signal current. Can also be used to

analog dim as explained in the Thermal Foldback and Analog Dimming

section.

4

5

6

CSH

RT

I

Current Sense High

Resistor Timing

Connect a resistor to GND to set the switching frequency. Can also be

used to synchronize to an external clock as explained in the Switching

Frequency section.

Connect a PWM signal for dimming as detailed in the PWM Dimming

section and/or a resistor divider from V_INto program input under-voltage

lockout.

Dimming Input /

Under-Voltage Protection

nDIM

7

8

SS

I

Soft-start

Connect a capacitor to GND to extend start-up time.

Connect a resistor to GND to set the foldback slope.

TGAIN

Temp Foldback Gain

Connect a resistor/ thermistor divider from V_Sto sense the temperature

as explained in the Thermal Foldback and Analog Dimming section.

9

TSENSE

TREF

V_S

I

Temp Sense Input

10

11

Temp Foldback Reference

Voltage Reference

Connect a resistor divider from V_Sto set the foldback reference voltage.

2.45V reference for temperature foldback circuit and other external

circuitry.

O

Connect a resistor divider from V_Oto program output over-voltage

lockout.

12

OVP

I

Over-Voltage Protection

13

14

15

16

DDRV

GND

GATE

V_CC

O

Dimming Gate Drive Output

Connect to gate of dimming MOSFET.

GND Ground

Connect to DAP to provide proper system GND

Connect to gate of main switching MOSFET.

Bypass with a 2.2 µF – 3.3 µF ceramic capacitor to GND.

O

Main Gate Drive Output

Internal Regulator Output

Main Switch Current Sense

Slope Compensation

Connect to the drain of the main N-channel MOSFET switch for R_DS-ON

sensing or to a sense resistor installed in the source of the same device.

17

18

19

IS

I

SLOPE

HSN

Connect a resistor to GND to set slope of additional ramp.

Connect through a series resistor to LED current sense resistor

(negative).

LED Current Sense Negative

Connect through a series resistor to LED current sense resistor

(positive).

20

HSP

DAP

I

LED Current Sense Positive

DAP

GND Thermal pad on bottom of IC

Connect to GND.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

MAX

76

UNIT

V_IN, EN, nDIM

OVP, HSP, HSN

76

IS

–2 for 100 ns

V_CC

–0.3

8

6

Voltage

V

V_S, TREF, TSENSE, TGAIN, COMP, CSH,

RT, SLOPE, SS

–0.3

V_CC

GATE, DDRV

GND

–2.5 for 100 ns

–0.3

V_CC+ 2.5 for 100 ns

0.3

–2.5 for 100 ns

2.5 for 100 ns

V_IN, EN, nDIM

OVP, HSP, HSN

IS

–1

–100

–1

mA

µA

Continuous current

mA

µA

SS

–30

–1

30

GATE, DDRV

1

mA

Continuous power dissipation

Internally Limited

Maximum Junction Temperature

°C

Maximum lead temperature (Reflow and Solder)⁽³⁾

Storage temperature

260

150

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Refer toTI’s packaging website for more detailed information and mounting techniques. http://www.ti.com/analogpackaging

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM Classification Level 2

±2500

Electrostatic

discharge

V_(ESD)

V

Charged-device model (CDM), per AEC Q100-011

CDM Classification Level C6

±1000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN

MAX UNIT

Operating Ambient Temperature Range

Input Voltage V_IN

–40

4.5

125

75

°C

V

4

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6.4 Thermal Information

LM3424-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

20 PINS

36.7

21.5

18

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

17.8

1.9

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

6.5 Electrical Characteristics

V_IN= 14 V, T_A= T_J= −40°C to 125°C unless otherwise specified. Minimum and Maximum limits are ensured through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for

reference purposes only.

PARAMETER

TEST CONDITIONS

MIN

6.3

20

TYP

MAX

UNIT

START-UP REGULATOR (V_CC

)

I_CC= 0 mA

7.35

V_CC-REG

V_CCRegulation

V

I_CC= 0 mA, T_J= 25°C

V_CC= 0 V

6.9

25

I_CC-LIM

V_CCCurrent Limit

mA

V_CC= 0 V, T_J= 25°C

EN = 3 V, Static

3

I_Q

Quiescent Current

Shutdown Current

mA

µA

V

EN = 3 V, Static, T_J= 25°C

EN = 0 V, T_J= 25°C

V_CCIncreasing

2

I_SD

0.1

1

4.5

V_CCIncreasing, T_J= 25°C

V_CCDecreasing

4.17

V_CC-UVLO

V_CCUVLO Threshold

V_CCUVLO Hysteresis

3.7

V

V_CCDecreasing, T_J= 25°C

T_J= 25°C

4.08

0.1

V_CC-HYS

ENABLE (EN)

EN Increasing

2.4

V

EN Increasing, T_J= 25°C

EN Decreasing

1.75

V_EN-ST

EN start-up Threshold

0.8

V

EN Decreasing, T_J= 25°C

T_J= 25°C

1.63

0.1

V_EN-HYS

R_EN

EN start-up Hysteresis

EN pulldown resistance

0.245

2.85

MΩ

T_J= 25°C

0.82

OVERVOLTAGE PROTECTION (OVP)

OVP Increasing

1.185

13

1.285

27

V_TH-OVP

OVP OVLO Threshold

V

OVP Increasing, T_J= 25°C

OVP Active (high)

1.24

20

I_HYS-OVP

OVP Hysteresis Source Current

µA

OVP Active (high), T_J= 25°C

ERROR AMPLIFIER

V_CSH

With Respect to GND

With Respect to GND, T_J= 25°C

T_J= 25°C

1.21

1.26

CSH Reference Voltage

V

1.235

0

Error Amplifier Input Bias Current

COMP Sink / Source Current

–0.6

17

0.6

35

µA

T_J= 25°C

26

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Electrical Characteristics (continued)

V_IN= 14 V, T_A= T_J= −40°C to 125°C unless otherwise specified. Minimum and Maximum limits are ensured through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for

reference purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

100

MAX

UNIT

µA/V

mV

Transconductance

Linear Input Range

T_J= 25°C

See⁽¹⁾, T_J= 25°C

±125

–6-dB Unloaded Response⁽¹⁾

T_J= 25°C

,

Transconductance Bandwidth

1

MHz

OSCILLATOR (RT)

f_SW

R_T= 36 kΩ

164

525

250

669

kHz

R_T= 36 kΩ, T_J= 25°C

R_T= 12 kΩ

207

Switching Frequency

Sync Threshold

kHz

V

R_T= 12 kΩ, T_J= 25°C

T_J= 25°C

597

3.5

V_RT-SYNC

PWM COMPARATOR

750

1050

COMP to PWM Offset - No Slope

V_CP-BASE

mV

Compensation

SLOPE COMPENSATION (SLOPE)

T_J= 25°C

900

85

Additional COMP to PWM Offset

- SLOPE sinking 100 µA,

T_J= 25°C

ΔV_CP

Slope Compensation Amplitude

CURRENT LIMIT (IS)

215

140

275

75

V_LIM

Current Limit Threshold

V_LIMDelay to Output

mV

ns

T_J= 25°C

245

35

340

t_ON-MIN

Leading Edge Blanking Time

ns

240

10

HIGH-SIDE TRANSCONDUCTANCE AMPLIFIER

Input Bias Current

µA

Transconductance

20

mA/V

–1.5

1.5

5

Input Offset Current

Input Offset Voltage

µA

T_J= 25°C

0

–5

mV

T_J= 25°C

0

Transconductance Bandwidth

I_CSH= 100 µA⁽¹⁾, T_J= 25°C

500

kHz

GATE DRIVER (GATE)

GATE = High

6

R_SRC-GATE

GATE Sourcing Resistance

GATE Sinking Resistance

Ω

GATE = High, T_J= 25°C

GATE = Low

2

4.5

R_SNK-GATE

GATE = Low, T_J= 25°C

1.3

UNDERVOLTAGE LOCKOUT AND DIM INPUT (nDIM)

V_TH-nDIM

nDIM / UVLO Threshold

nDIM Hysteresis Current

1.185

13

1.240

20

1.285

27

V

I_HYS-nDIM

µA

DIM DRIVER (DDRV)

DDRV = High

30

R_SRC-DDRV

DDRV Sourcing Resistance

Ω

DDRV = High, T_J= 25°C

13.5

(1) These electrical parameters are ensured by design, and are not verified by test.

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Electrical Characteristics (continued)

V_IN= 14 V, T_A= T_J= −40°C to 125°C unless otherwise specified. Minimum and Maximum limits are ensured through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for

reference purposes only.

PARAMETER

TEST CONDITIONS

DDRV = Low

MIN

TYP

MAX

UNIT

10

R_SNK-DDRV

DDRV Sinking Resistance

Ω

DDRV = Low, T_J= 25°C

3.5

700

360

nDIM rising to DDRV rising

nDIM falling to DDRV falling

ns

SOFT-START (SS)

I_SS

Soft-start current

10

µA

THERMAL CONTROL

I_VS= 0 A,

I_VS= 1 mA

2.4

2.5

V_S

V_SVoltage

V

I_VS= 0 A,

I_VS= 1 mA,

T_J= 25°C

2.45

V_TREF= 1.5 V

V_TSENSE= 1.5 V, T_J= 25°C

TREF input bias current

0.1

µA

V_TREF= 1.5 V

V_TSENSE= 1.5 V, T_J= 25°C

TSENSE Input Bias Current

V_TGAIN= 2 V

200

I_TGAIN-MAX

TGAIN Maximum Sourcing Current

µA

V_TGAIN= 2 V, T_J= 25°C

600

100

V_TREF= 1.5 V

V_TSENSE= 0.5 V

µA

R_TGAIN= 10

V_TREF= 1.5 V

kΩ, T_J=

CSH Current with High-side

Amplifier Disabled

I_TF

10

2

V_TSENSE= 1.4 V

25°C

V_TREF= 1.5 V

V_TSENSE= 1.5 V

THERMAL SHUTDOWN

T_SD

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

See⁽¹⁾, T_J= 25°C

165

25

°C

T_HYS

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6.6 Typical Characteristics

T_A= 25°C and V_IN= 14 V unless otherwise specified. The measurements for Figure 1, Figure 3, andFigure 6 were made

using the standard boost evaluation board from AN-1967 LM3424 Buck-Boost Evaluation Board (SNVA397). The

measurements for Figure 2, Figure 4, and Figure 5 were made using the standard buck-boost evaluation board from AN-1969

LM3424 Boost Evaluation Board (SNVA398).

100

95

90

85

80

100

95

90

85

80

75

70

10

15

20

(V)

25

30

0

16

32

48

(V)

64

80

V

IN

V_O= 21 V (6 LEDs)

V_O= 32 V (9 LEDs)

Figure 2. Buck-Boost Efficiency vs. Input Voltage

Figure 1. Boost Efficiency vs Input Voltage

1.010

1.02

1.005

1.000

0.995

0.990

1.01

1.00

0.99

0.98

5

10

15

20

25

30

0

16

32

48

64

80

V

IN

(V)

V

(V)

IN

V_O= 32 V (9 LEDs)

V_O= 21 V (6 LEDs)

Figure 3. Boost LED Current vs. Input Voltage

Figure 4. Buck-Boost LED Current vs. Input Voltage

1.0

0.8

0.6

0.4

0.2

0.0

0.8

0.6

1 kHz

0.4

25 kHz

0.2

0.8

0

20

40

60

80

100

0

20

40

I

60

80

100

(éA)

DUTY CYCLE (%)

CSH

V_O= 21 V (6 LEDs)

Figure 5. Analog Dimming

V_IN= 24 V

V_O= 32V (9 LEDs)

Figure 6. PWM Dimming

V_IN= 24 V

8

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Typical Characteristics (continued)

T_A= 25°C and V_IN= 14 V unless otherwise specified. The measurements for Figure 1, Figure 3, andFigure 6 were made

using the standard boost evaluation board from AN-1967 LM3424 Buck-Boost Evaluation Board (SNVA397). The

measurements for Figure 2, Figure 4, and Figure 5 were made using the standard buck-boost evaluation board from AN-1969

LM3424 Boost Evaluation Board (SNVA398).

7.20

7.10

7.00

6.90

6.80

6.70

1.250

1.245

1.240

1.235

1.230

1.225

1.220

-50

-14

22

58

94

130

-50

-14

22

58

94

130

TEMPERATURE (°C)

Figure 8. V_CCvs. Junction Temperature

Figure 7. V_CSHvs. Junction Temperature

248

2.500

246

244

242

240

2.450

2.400

-50

-14

22

58

94

130

-50

-14

22

58

94

130

TEMPERATURE (°C)

Figure 9. V_Svs. Junction Temperature

Figure 10. V_LIMvs. Junction Temperature

1000

255

R

= 12 kÖ

T

250

245

240

235

230

225

R

T

= 36 kÖ

100

-50

-14

22

58

94

130

-50

-14

22

58

94

130

TEMPERATURE (°C)

Figure 12. Switching Frequency vs. Junction Temperature

Figure 11. Minimum On-Time vs. Junction Temperature

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Typical Characteristics (continued)

T_A= 25°C and V_IN= 14 V unless otherwise specified. The measurements for Figure 1, Figure 3, andFigure 6 were made

using the standard boost evaluation board from AN-1967 LM3424 Buck-Boost Evaluation Board (SNVA397). The

measurements for Figure 2, Figure 4, and Figure 5 were made using the standard buck-boost evaluation board from AN-1969

LM3424 Boost Evaluation Board (SNVA398).

100.3

100.1

99.9

1M

100k

10k

1k

99.7

99.5

-50

-14

22

58

94

130

10k

100k

1M

10M

TEMPERATURE (°C)

f

(Hz)

SW

R_GAIN= 10 kΩ

V_TSENSE= 0.5 V

V_TREF= 1.5 V

Figure 13. I_TFvs. Junction Temperature

Figure 14. Switching Frequency vs. Timing Resistance

1.25

R_BIAS= 24.3 kW

1.00

0.75

0.50

0.25

0.00

0.75

R_GAIN= 15 kW

0.50

R_GAIN= 5 kW

R_BIAS= 84.5 kW

R_BIAS= 43.2 kW

0.25

R_GAIN= 10 kW

0.00

0

25

50

75

100

125

0

25

50

75

100

125

TEMPERATURE (°C)

R_REF1= R_REF2= 49.9 kΩ

R_NTC-BK= R_BIAS= 43.2 kΩ

R_REF1= R_REF2= 49.9 kΩ

R_GAIN= 10 kΩ

Figure 15. Ideal Thermal Foldback with Varied Slope

Figure 16. Ideal Thermal Foldback with Varied Breakpoint

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7 Detailed Description

7.1 Overview

The LM3424-Q1 is an N-channel MOSFET (NFET) controller for buck, boost and buck-boost current regulators

which are ideal for driving LED loads. The controller has wide input voltage range allowing for regulation of a

variety of LED loads. The high-side differential current sense, with low adjustable threshold voltage, provides an

excellent method for regulating output current while maintaining high system efficiency. The LM3424-Q1 uses

peak current mode control providing good noise immunity and an inherent cycle-by-cycle current limit. The

adjustable current sense threshold provides the capability to amplitude (analog) dim the LED current and the

thermal foldback circuitry allows for precise temperature management of the LEDs. The output enable/disable

function coupled with an internal dimming drive circuit provides high speed PWM dimming through the use of an

external MOSFET placed at the LED load. When designing, the maximum attainable LED current is not internally

limited because the LM3424-Q1 is a controller. Instead it is a function of the system operating point, component

choices, and switching frequency allowing the LM3424-Q1 to easily provide constant currents up to 5 A. This

simple controller contains all the features necessary to implement a high efficiency versatile LED driver.

7.2 Functional Block Diagram

V_IN

6.9V LDO

Regulator

EN

V_CC

V

UVLO

820k

CC

UVLO

(4.1V)

1.24V

REFERENCE

Standby

UVLO

HYSTERESIS

20 mA

TLIM

Thermal

V

CC

nDIM

Limit

Dimming

1.24V

DDRV

OVLO

Reset

Dominant

Clock

V

CC

Q

S

RT

Artificial Ramp

GATE

GND

Oscillator

SLOPE

R

LEB

t = 240 ns

COMP

CSH

20 mA

OVP

HYSTERESIS

1.24V

PWM

OVLO

OVP

1.24V

HSP

HSN

90k

10 mA

1.7k

1.24V

CURRENT

LIMIT

IS

0.245V

100k

V_S

LEB

100k

TREF

COMP

10 mA

SS

TSENSE

TGAIN

100k

STANDBY

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7.3 Feature Description

7.3.1 Current Regulators

i_L(t)

I

L-MAX

Âi

L-PP

I

L

I

L-MIN

t

= DT

t = (1-D)T

OFF S

ON

S

0

t

T

S

Figure 17. Ideal CCM Regulator Inductor Current i_L(t)

Current regulators can be designed to accomplish three basic functions: buck, boost, and buck-boost. All three

topologies in their most basic form contain a main switching MOSFET, a recirculating diode, an inductor and

capacitors. The LM3424-Q1 is designed to drive a ground referenced NFET which is perfect for a standard boost

regulator. Buck and buck-boost regulators, on the other hand, usually have a high-side switch. When driving an

LED load, a ground referenced load is often not necessary, therefore a ground referenced switch can be used to

drive a floating load instead. The LM3424-Q1 can then be used to drive all three basic topologies as shown in

the Basic Topology Schematics section. Other topologies such as the SEPIC and flyback converter (both

derivatives of the buck-boost) can be implemented as well.

Looking at the buck-boost design, the basic operation of a current regulator can be analyzed. During the time

that the NFET (Q1) is turned on (t_ON), the input voltage source stores energy in the inductor (L1) while the output

capacitor (C_O) provides energy to the LED load. When Q1 is turned off (t_OFF), the re-circulating diode (D1)

becomes forward biased and L1 provides energy to both C_Oand the LED load. Figure 17 shows the inductor

current (i_L(t)) waveform for a regulator operating in CCM.

The average output LED current (I_LED) is proportional to the average inductor current (I_L) , therefore if I_Lis tightly

controlled, I_LEDwill be well regulated. As the system changes input voltage or output voltage, the ideal duty cycle

(D) is varied to regulate I_Land ultimately I_LED. For any current regulator, D is a function of the conversion ratio:

Buck

V_O

D =

V

IN

(1)

(2)

(3)

Boost

V_O- V

IN

D =

V_O

Buck-Boost

V_O

D =

V_O+ V

IN

7.3.2 Peak Current Mode Control

Peak current mode control is used by the LM3424-Q1 to regulate the average LED current through an array of

HBLEDs. This method of control uses a series resistor in the LED path to sense LED current and can use either

a series resistor in the MOSFET path or the MOSFET R_DS-ONfor both cycle-by-cycle current limit and input

voltage feed forward. The controller has a fixed switching frequency set by an internal programmable oscillator

which means current mode instability can occur at duty cycles higher than 50%. To mitigate this standard

problem, an artificial ramp is added to the control signal internally. The slope of this ramp is programmable to

allow for a wider range of component choices for a given design. A detailed explanation of this control method is

presented in the following sections.

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Feature Description (continued)

7.3.3 Average LED Current

To first understand how the LM3424-Q1 regulates LED current, the thermal foldback functionality will be ignored.

Figure 18 shows the physical implementation of the LED current sense circuitry assuming the thermal foldback

circuitry is a simple current source which, for now, will be set to zero (I_TF= 0A). The LM3424-Q1 uses an

external current sense resistor (R_SNS) placed in series with the LED load to convert the LED current (I_LED) into a

voltage (V_SNS). The HSP and HSN pins are the inputs to the high-side sense amplifier which are forced to be

equal potential (V_HSP=V_HSN) through negative feedback. Because of this, the V_SNSvoltage is forced across R_HSP

which generates a current that is summed with the thermal foldback current (I_TF) to generate the signal current

(I_CSH) which flows out of the CSH pin and through the R_CSHresistor. The error amplifier will regulate the CSH pin

to 1.24V and assuming I_TF= 0A, I_CSHcan be calculated:

V_SNS

R_HSP

I_CSH

=

(4)

(5)

(6)

This means V_SNSwill be regulated as follows:

R_HSP

V_SNS= 1.24V x

R_CSH

I_LEDcan then be calculated:

V_SNS

R_SNS

1.24V R_HSP

x

I_LED

=

R_SNS

R_CSH

The selection of the three resistors (R_SNS, R_CSH, and R_HSP) is not arbitrary. For matching and noise performance,

the suggested signal current I_CSHis approximately 100 µA. This current does not flow in the LEDs and will not

affect either the off-state LED current or the regulated LED current. I_CSHcan be above or below this value, but

the high-side amplifier offset characteristics may be affected slightly. In addition, to minimize the effect of the

high-side amplifier voltage offset on LED current accuracy, the minimum V_SNSis suggested to be 50 mV. Finally,

a resistor (R_HSN= R_HSP) should be placed in series with the HSN pin to cancel out the effects of the input bias

current (~10 µA) of both inputs of the high-side sense amplifier.

Note that he CSH pin can also be used as a low-side current sense input regulated to 1.24V. The high-side

sense amplifier is disabled if HSP and HSN are tied to GND.

LM3424-Q1

I

LED

High-Side

Sense Amplifier

R

HSP

HSN

V

SNS

R

SNS

R

Thermal Foldback Current

HSN

I

TF

I

CSH

R

C

CSH

Error Amplifier

CSH

To PWM

Comparator

1.24 V

CMP

COMP

Figure 18. LED Current Sense Circuitry

7.3.4 Thermal Foldback and Analog Dimming

Thermal foldback is necessary in many applications due to the extreme temperatures created in LED

environments. In general, two functions are necessary: a temperature breakpoint (T_BK) after which the nominal

operating current needs to be reduced, and a slope corresponding to the amount of LED current decrease per

temperature increase as shown in Figure 19. The LM3424-Q1 allows the user to program both the breakpoint

and slope of the thermal foldback profile.

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Feature Description (continued)

I

LED

1

î

R_GAIN

0

T

BK

T

END

Figure 19. Ideal Thermal Foldback Profile

LM3424-Q1

V_S

2.45 V

I

LED

High-Side

Sense Amplifier

R

REF2

HSP

HSN

100 k

NTC

TREF

V

SNS

R

SNS

R

HSN

R

BIAS

REF1

V

DIF

TSENSE

I

TF

100 k

TGAIN

R

NTC

I

CSH

R

C

CSH

Error Amplifier

To PWM

Comparator

R

GAIN

1.24 V

CMP

COMP

LM94022

Precision Temp Sensor

Figure 20. Thermal Foldback Circuitry

Foldback is accomplished by adding current (I_TF) to the CSH summing node. As more current is added, less

current is needed from the high side amplifier and correspondingly, the LED current is regulated to a lower value.

The final temperature (T_END) is reached when I_TF= I_CSHcausing no current to be needed from the high-side

amplifier, yielding I_LED= 0A.

Figure 20 shows how the thermal foldback circuitry is physically implemented in the system. I_TFis set by placing

a differential voltage (V_DIF= V_TREF– V_TSENSE) across TSENSE and TREF. V_TREFcan be set with a simple resistor

divider (R_REF1and R_REF2) supplied from the V_Svoltage reference (typical 2.45V). V_TSENSEis set with a

temperature dependant voltage (as temperature increases, voltage should decrease).

An NTC thermistor is the most cost effective device used to sense temperature. As the temperature of the

thermistor increases, its resistance decreases (albeit non-linearly). Usually, the NTC manufacturer's datasheet

will detail the resistance-temperature characteristic of the thermistor. The thermistor will have a different

resistance (R_NTC) at each temperature. The nominal resistance of an NTC is the resistance when the

temperature is 25°C (R₂₅) and in many datasheets this will be given a multiplier of 1. Then the resistance at a

higher temperature will have a multiplier less than 1 (that is, R₈₅multiplier is 0.161 therefore R₈₅= 0.161 x R₂₅).

Given a desired T_BKand T_END, the corresponding resistances at those temperatures (R_NTC-BKand R_NTC-END) can

be found.

Using the NTC method, a resistor divider from V_Scan be implemented with a resistor connected between V_Sand

TSENSE and the NTC thermistor placed at the desired location and connected from TSENSE to GND. This will

ensure that the desired temperature-voltage characteristic occurs at TSENSE.

If a linear decrease over the foldback range is necessary, a precision temperature sensor such as the LM94022

can be used instead as shown in . Either method can be used to set V_TSENSEaccording to the temperature.

However, for the rest of this datasheet, the NTC method will be used for thermal foldback calculations.

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Feature Description (continued)

During operation, if V_DIF< 0V, then the sensed temperature is less than T_BKand the differential sense amplifier

will regulate its output to zero forcing I_TF= 0. This maintains the nominal LED current and no foldback is

observed.

At T_BK, V_DIF= 0V exactly and I_TFis still zero. Looking at the manufacturer's datasheet for the NTC thermistor,

R_NTC-BKcan be obtained for the desired T_BKand the voltage relationship at the breakpoint (V_TSENSE-BK= V_TREF

)

can be defined:

R_REF1

R_NTC-BK

=

R_REF1+ R_REF2

R_NTC-BK+ R_BIAS

(7)

A general rule of thumb is to set R_REF1= R_REF2simplifying the breakpoint relationship to R_BIAS= R_NTC-BK

.

If V_DIF> 0V (temperature is above T_BK), then the amplifier will regulate its output equal to the input forcing V_DIF

across the resistor (R_GAIN) connected from TGAIN to GND. R_GAINultimately sets the slope of the LED current

decrease with respect to increasing temperature by changing I_TF:

V_TREF- V_TSENSE

I_TF

=

R_GAIN

(8)

If an analog temperature sensor such as the LM94022 is used, then R_BIASand the NTC are not necessary and

V_TSENSEwill be the direct voltage output of the sensor.

Since the NTC is not usually local to the controller, a bypass capacitor (C_NTC) is suggested from TSENSE to

GND. If a capacitor is used at TSENSE, then a capacitor (C_REF) of equal or greater value should be placed from

TREF to GND in order to ensure the controller does not start-up in foldback. Alternatively, a smaller C_REFcan be

used to create a fade-up function at start-up (see Application Information).

Thermal foldback is simply analog dimming according to a specific profile, therefore any method of controlling the

differential voltage between TREF and TSENSE can be use to analog dim the LED current. The corresponding

LED current for any V_DIF> 0V is defined:

R

≈

∆

«

’

÷

◊

HSP

I_LED= (I_CSH- I_TF) x

R_SNS

(9)

The CSH pin can also be used to analog dim the LED current by adjusting the current sense voltage (V_SNS),

similar to thermal foldback. There are several different methods to adjust V_SNSusing the CSH pin:

1. External variable resistance: Adjust a potentiometer placed in series with R_CSHto vary V_SNS

.

2. External variable current source: Source current (0 µA to I_CSH) into the CSH pin to adjust V_SNS

.

Variable Current Source

LM3424-Q1

V_S

V_CC

Q8

Q7

R

MAX

Q6

R

CSH

R

CSH

BIAS

ADJ

Variable

Resistance

R

ADJ

Figure 21. Analog Dimming Circuitry

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Feature Description (continued)

In general, analog dimming applications require a lower switching frequency to minimize the effect of the leading

edge blanking circuit. As the LED current is reduced, the output voltage and the duty cycle decreases.

Eventually, the minimum on-time is reached. The lower the switching frequency, the wider the linear dimming

range. Figure 21 shows how both CSH methods are physically implemented.

Method 1 uses an external potentiometer in the CSH path which is a simple addition to the existing circuitry.

However, the LEDs cannot dim completely because there is always some resistance causing signal current to

flow. This method is also susceptible to noise coupling at the CSH pin since the potentiometer increases the size

of the signal current loop.

Method 2 provides a complete dimming range and better noise performance, though it is more complex. Like

thermal foldback, it simply sources current into the CSH pin, decreasing the amount of signal current that is

necessary. This method consists of a PNP current mirror and a bias network consisting of an NPN, 2 resistors

and a potentiometer (R_ADJ), where R_ADJcontrols the amount of current sourced into the CSH pin. A higher

resistance value will source more current into the CSH pin causing less regulated signal current through R_HSP

,

effectively dimming the LEDs. Q7 and Q8 should be a dual pair PNP for best matching and performance. The

additional current (I_ADD) sourced into the CSH pin can be calculated:

≈

∆

«

’

÷

R_ADJx V_REF

R_ADJ+ R_MAX

- V_BE-Q6

◊

I_ADD

=

R_BIAS

(10)

(11)

The corresponding I_LEDfor a specific I_ADDis:

R

HSP

≈

∆

«

’

÷

◊

I_LED= (I_CSH- I_ADD) x

R_SNS

7.3.5 Current Sense and Current Limit

The LM3424-Q1 achieves peak current mode control using a comparator that monitors the main MOSFET (Q1)

transistor current, comparing it with the COMP pin voltage as shown in Figure 22. Further, it incorporates a

cycle-by-cycle over-current protection function. Current limit is accomplished by a redundant internal current

sense comparator. If the voltage at the current sense comparator input (IS) exceeds 245 mV (typical), the on

cycle is immediately terminated. The IS input pin has an internal N-channel MOSFET which pulls it down at the

conclusion of every cycle. The discharge device remains on an additional 240 ns (typical) after the beginning of a

new cycle to blank the leading edge spike on the current sense signal. The leading edge blanking (LEB)

determines the minimum achievable on-time (t_ON-MIN).

R_DS-ON

Sensing

LM3424-Q1

COMP

Q1

GATE

0.9 V

PWM

R_LIM

Sensing

Ramp

IS

0.245 V

I

T

R

LIM

SLOPE

Ramp

LEB

Generator

R

SLP

GND

Figure 22. Current Sense / Current Limit Circuitry

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Feature Description (continued)

There are two possible methods to sense the transistor current. The R_DS-ONof the main power MOSFET can be

used as the current sense resistance because the IS pin was designed to withstand the high voltages present on

the drain when the MOSFET is in the off state. Alternatively, a sense resistor located in the source of the

MOSFET may be used for current sensing, however a low inductance (ESL) type is suggested. The cycle-by-

cycle current limit (I_LIM) can be calculated using either method as the limiting resistance (R_LIM):

245 mV

R_LIM

I_LIM

=

(12)

In general, the external series resistor allows for more design flexibility, however it is important to ensure all of

the noise sensitive low power ground connections are connected together local to the controller and a single

connection is made to GND.

7.3.6 Slope Compensation

The LM3424-Q1 has programmable slope compensation in order to provide stability over a wide range of

operating conditions. Without slope compensation, a well-known condition called current mode instability (or sub-

harmonic oscillation) can result if there is a perturbation of the MOSFET current sense voltage at the IS pin, due

to noise or a some type of transient.

Through a mathematical / geometrical analysis of the inductor current (I_L) and the corresponding control current

(I_C, it can be shown that if D < 0.5, the effect of the perturbation will decrease each switching cycle and the

system will remain stable. However, if D > 0.5 then the perturbation will grow as shown in Figure 23, eventually

causing a "period doubling" effect where the effect of the perturbation remains, yielding current mode instability.

Looking at , the positive PWM comparator input is the IS voltage, a mirror of I_Lduring t_ON, plus a typical 900 mV

offset. The negative input of the PWM comparator is the COMP pin which is proportional to I_C, the threshold at

which the main MOSFET (Q1) is turned off.

The LM3424-Q1 mitigates current mode instability by implementing an aritifical ramp (commonly called slope

compensation) which is summed with the sensed MOSFET current at the IS pin as shown in . This combined

signal is compared to the COMP pin to generate the PWM signal. An increase in the ramp that is added to the

sense voltage will increase the maximum achievable duty cycle. It should be noted that as the artificial ramp is

increased more and more, the control method approaches standard voltage mode control and the benefits of

current mode control are reduced.

To program the slope compensation, an external resistor, R_SLP, is connected from SLOPE to GND. This sets the

slope of the artificial ramp that is added to the MOSFET current sense voltage. A smaller R_SLPvalue will increase

the slope of the added ramp. A simple calculation is suggested to ensure any duty cycle is attainable while

preventing the addition of excessive ramp. This method requires the artifical ramp slope (M_A) to be equal to half

the inductor slope during t_OFF

:

7.5 x 10¹²

V

O

M_A

=

R_Tx R_SLPx R_LIM2x 1

L

(13)

i_L(t)

I

C

Ideal

i (t)

L

Actual

i (t)

L

T

2T

S

0

t

Figure 23. "Period Doubling" due to Current Mode Instability

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Feature Description (continued)

7.3.7 Control Loop Compensation

The LM3424-Q1 control loop is modeled like any current mode controller. Using a first order approximation, the

uncompensated loop can be modeled as a single pole created by the output capacitor and, in the boost and

buck-boost topologies, a right half plane zero created by the inductor, where both have a dependence on the

LED string dynamic resistance. There is also a high frequency pole in the model, however it is near the switching

frequency and plays no part in the compensation design process therefore it will be neglected. Since ceramic

capacitance is recommended for use with LED drivers due to long lifetimes and high ripple current rating, the

ESR of the output capacitor can also be neglected in the loop analysis. Finally, there is a DC gain of the

uncompensated loop which is dependent on internal controller gains and the external sensing network.

A buck-boost regulator will be used as an example case. See the Application Information section for

compensation of all topologies.

The uncompensated loop gain for a buck-boost regulator is given by the following equation:

≈

’

÷

◊

s

w_Z1

∆ -

1

∆

«

T_U= T_U0x

≈

’

÷

◊

s

w_P1

∆

1+

∆

«

(14)

Where the uncompensated DC loop gain of the system is described as:

Å

D x 500Vx R_CSHx R_SNS

Å

D x 620V

T_U0

=

(

)

(

)

1+D x R_HSPx R_LIM

1+D xI_LEDx R_LIM

(15)

(16)

(17)

And the output pole (ω_P1) is approximated:

1+D

w_P1=

r_Dx C_O

And the right half plane zero (ω_Z1) is:

Å²

r_DxD

w_Z1=

DxL1

135

90

100

80

60

40

20

0

ö

P1

ö

Z1

GAIN

45

0

PHASE

-45

-90

-135

-180

-225

0°Phase Margin

-20

-40

-60

1e-1

1e1

1e3

1e5

1e7

FREQUENCY (Hz)

Figure 24. Uncompensated Loop Gain Frequency Response

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Feature Description (continued)

Figure 24 shows the uncompensated loop gain in a worst-case scenario when the RHP zero is below the output

pole. This occurs at high duty cycles when the regulator is trying to boost the output voltage significantly. The

RHP zero adds 20dB/decade of gain while loosing 45°/decade of phase which places the crossover frequency

(when the gain is zero dB) extremely high because the gain only starts falling again due to the high frequency

pole (not modeled or shown in figure). The phase will be below -180° at the crossover frequency which means

there is no phase margin (180° + phase at crossover frequency) causing system instability. Even if the output

pole is below the RHP zero, the phase will still reach -180° before the crossover frequency in most cases yielding

instability.

LM3424-Q1

I

LED

High-Side

Sense Amplifier

R

HSP

HSN

C

FS

V

SNS

R

SNS

R

Thermal Foldback Current

Error Amplifier

HSN

R

FS

sets ö

P3

R

CSH

To PWM

Comparator

1.24 V

R

O

C

CMP

sets ö

COMP

P2

Figure 25. Compensation Circuitry

To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the

crossover frequency. A simple compensator using a single capacitor at the COMP pin (C_CMP) will add a dominant

pole to the system, which will ensure adequate phase margin if placed low enough. At high duty cycles (as

shown in Figure 24), the RHP zero places extreme limits on the achievable bandwidth with this type of

compensation. However, because an LED driver is essentially free of output transients (except catastrophic

failures open or short), the dominant pole approach, even with reduced bandwidth, is usually the best approach.

The dominant compensation pole (ω_P2) is determined by C_CMPand the output resistance (R_O) of the error

amplifier (typically 5 MΩ):

1

ω_P2=

5 x 10⁶Ω x C_CMP

(18)

It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate

switching noise and, in some cases, provide better gain margin. This pole can be placed across R_SNSto filter the

ESL of the sense resistor at the same time. Figure 25 shows how the compensation is physically implemented in

the system.

The high frequency pole (ω_P3) can be calculated:

1

w_P3

=

R_FSxC_FS

(19)

The total system transfer function becomes:

≈

’

÷

◊

s

w_Z1

∆

1-

∆

«

T = T_U0

x

≈

’

÷

◊

≈

∆

«

’

≈

∆

«

’

÷

◊

s

w_P1

s

w_P2

s

w_P3

∆

÷

∆

1+

x 1+

∆

÷

«

◊

(20)

The resulting compensated loop gain frequency response shown in Figure 26 indicates that the system has

adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability:

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Feature Description (continued)

90

80

60

ö

P2

45

0

40

GAIN

-45

-90

-135

-180

-225

-270

20

ö

Z1

P1

0

PHASE

ö

P3

-20

-40

-60

-80

60°Phase Margin

1e-1

1e1

1e3

1e5

1e7

FREQUENCY (Hz)

Figure 26. Compensated Loop Gain Frequency Response

7.3.8 Start-Up Regulator and Soft-Start

The LM3424-Q1 includes a high voltage, low dropout bias regulator. When power is applied, the regulator is

enabled and sources current into an external capacitor (C_BYP) connected to the V_CCpin. The recommended

bypass capacitance for the V_CCregulator is 2.2 µF to 3.3 µF. The output of the V_CCregulator is monitored by an

internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage and the

supply is also internally current limited.

The LM3424-Q1 also has programmable soft-start, set by an external capacitor (C_SS), connected from SS to

GND. For C_SSto affect start-up, C_REF> C_NTCmust be maintained so that the converter does not start in foldback

mode. Figure 27 shows the typical start-up waveforms for the LM3424-Q1 assuming C_REF> C_NTC

.

V

CMP

0.9V

0

t

CO

VCC

CMP

0.9V

0.7V

0

t

CO

VCC

SS

t

CMP-SS

Figure 27. Start-up Waveforms

First, C_BYPis charged to be above V_CCUVLO threshold (~4.2V). The C_VCCcharging time (t_VCC) can be estimated

as:

4.2V

25 mA

t_VCC

xC_BYP168W xC

=

BYP

=

(21)

Assuming there is no C_SSor if C_SSis less than 40% of C_CMP, C_CMPis then charged to 0.9V over the charging

time (t_CMP) which can be estimated as:

0.9V

25 mA

t_CMP

x C_CMP36 kW xC

=

CMP

=

(22)

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Feature Description (continued)

Once C_CMP= 0.9V, the part starts switching to charge C_Ountil the LED current is in regulation. The C_Ocharging

time (t_CO) can be roughly estimated as:

V_O

I_LED

t_CO

C

_Ox

=

(23)

If C_SSis greater than 40% of C_CMP, the compensation capacitor will only charge to 0.7V over a smaller C_CMP

charging time (t_CMP-SS) which can be estimated as:

0.70V

25 mA

t_CMP-SS

x C_CMP28kW xC

=

CMP

=

(24)

Then COMP will clamp to SS, forcing COMP to rise (the last 200 mV before switching begins) according to the

C_SScharging time (t_SS) which can be estimated as:

0.2V

10mA

t_SS

xC_SS20 kW xC

=

SS

=

(25)

The system start-up time (t_SUor t_SU-SS) is defined as:

C_SS< 0.4 x C_CMP

t_SU

t

+

CO

=

+

VCC

CMP

(26)

(27)

C_SS> 0.4 x C_CMP

t_SU-SS

t

+

CO

=

+

VCC

CMP-SS

SS

As a general rule of thumb, standard smooth startup operation can be achieved with C_SS= C_CMP

.

7.3.9 Overvoltage Lockout (OVLO)

The LM3424-Q1 can be configured to detect an output (or input) over-voltage condition via the OVP pin. The pin

features a precision 1.24V threshold with 20 µA (typical) of hysteresis current as shown in Figure 28. When the

OVLO threshold is exceeded, the GATE pin is immediately pulled low and a 20 µA current source provides

hysteresis to the lower threshold of the OVLO hysteretic band.

If the LEDs are referenced to a potential other than ground (floating), as in the buck-boost and buck

configuration, the output voltage (V_O) should be sensed and translated to ground by using a single PNP as

shown in Figure 29.

The over-voltage turn-off threshold (V_TURN-OFF) is defined:

Ground Referenced

≈

’

R_OV+ R_OV2

1

∆

«

÷

◊

V_TURN-OFF= 1.24Vx

Floating

V_TURN-OFF= 1.24Vx

R_OV1

(28)

(29)

≈

’

+ R_OV2

0.5 x R_OV1

∆

«

÷

R_OV1

◊

In the ground referenced configuration, the voltage across R_OV2is V_O- 1.24 V whereas in the floating

configuration it is V_O- 620 mV where 620 mV approximates V_BEof the PNP.

The over-voltage hysteresis (V_HYSO) is defined:

V_HYSO= 20 mA x R_OV2

(30)

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Feature Description (continued)

LM3424-Q1

V_IN

20 mA

R

UV2

UV1

nDIM

UVLO

1.24 V

R

UVH

R

(optional)

Figure 28. Overvoltage Protection Circuitry

LED+

R

OV2

LM3424-Q1

LED-

OVP

R

OV1

Figure 29. Floating Output OVP Circuitry

7.3.10 Input Undervoltage Lockout (UVLO)

The nDIM pin is a dual-function input that features an accurate 1.24V threshold with programmable hysteresis as

shown in Figure 30. This pin functions as both the PWM dimming input for the LEDs and as a V_INUVLO. When

the pin voltage rises and exceeds the 1.24V threshold, 20 µA (typical) of current is driven out of the nDIM pin into

the resistor divider providing programmable hysteresis.

LM3424-Q1

V_IN

20 mA

R

UV2

UV1

nDIM

UVLO

1.24 V

R

UVH

R

(optional)

Figure 30. UVLO Circuit

When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra series

resistor to set the hysteresis. This allows the standard resistor divider to have smaller resistor values minimizing

PWM delays due to a pull-down MOSFET at the nDIM pin (see PWM Dimming section). In general, at least 3V of

hysteresis is preferable when PWM dimming, if operating near the UVLO threshold.

The turn-on threshold (V_TURN-ON) is defined as follows:

≈

’

÷

◊

R_UV+ R_UV2

1

∆

«

V_TURN_O-N= 1.24Vx

R_UV1

(31)

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Feature Description (continued)

The hysteresis (V_HYS) is defined as follows:

7.3.10.1 UVLO Only

V_HYS20 mA xR

=

UV2

(32)

(33)

7.3.10.2 PWM Dimming and UVLO

≈

∆

«

(

)’

÷

◊

R_UVHx R_UV1+ R_UV2

∆

20mA x R

V_HYS

=

+

UV2

÷

R_UV1

7.3.11 PWM Dimming

The active low nDIM pin can be driven with a PWM signal which controls the main NFET and the dimming FET

(dimFET). The brightness of the LEDs can be varied by modulating the duty cycle of this signal. LED brightness

is approximately proportional to the PWM signal duty cycle, (that is, 30% duty cycle at approximately 30% LED

brightness). This function can be ignored if PWM dimming is not required by using nDIM solely as a V_INUVLO

input as described in the Input Undervoltage Lockout (UVLO) section or by tying it directly to V_CCor V_IN.

Inverted

PWM

V_IN

LM3424-Q1

D

DIM

R

UV2

nDIM

R

UVH

R

UV1

Q

DIM

Standard

PWM

Figure 31. PWM Dimming Circuit

Figure 31 shows how the PWM signal is applied to nDIM:

1. Connect the dimming MOSFET (Q_DIM) with the drain to the nDIM pin and the source to GND. Apply an

external logic-level PWM signal to the gate of Q_DIM

.

2. Connect the anode of a Schottky diode (D_DIM) to the nDIM pin. Apply an inverted external logic-level PWM

signal to the cathode of the same diode.

The DDRV pin is a PWM output that follows the nDIM PWM input signal. When the nDIM pin rises, the DDRV pin

rises and the PWM latch reset signal is removed allowing the main MOSFET Q1 to turn on at the beginning of

the next clock set pulse. In boost and buck-boost topologies, the DDRV pin is used to control a N-channel

MOSFET placed in series with the LED load, while it would control a P-channel MOSFET in parallel with the load

for a buck topology.

The series dimFET will open the LED load, when nDIM is low, effectively speeding up the rise and fall times of

the LED current. Without any dimFET, the rise and fall times are limited by the inductor slew rate and dimming

frequencies above 1 kHz are impractical. Using the series dimFET, dimming frequencies up to 30 kHz are

achievable. With a parallel dimFET (buck topology), even higher dimming frequencies are achievable.

When using the PWM functionality in a boost regulator, the PWM signal drives a ground referenced FET.

However, with buck-boost and buck topologies, level shifting circuitry is necessary to translate the PWM dim

signal to the floating dimFET as shown in Figure 32 and Figure 33.

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Feature Description (continued)

When using a series dimFET to PWM dim the LED current, more output capacitance is always better. A general

rule of thumb is to use a minimum of 40 µF when PWM dimming. For most applications, this will provide

adequate energy storage at the output when the dimFET turns off and opens the LED load. Then when the

dimFET is turned back on, the capacitance helps source current into the load, improving the LED current rise

time.

A minimum on-time must be maintained in order for PWM dimming to operate in the linear region of its transfer

function. Because the controller is disabled during dimming, the PWM pulse must be long enough such that the

energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and

buck-boost regulators, the minimum dimming pulse length in seconds (t_PULSE) is:

2 x I_LEDx V_OX L1

t_PULSE

=

2

V_IN

(34)

Even maintaining a dimming pulse greater than t_PULSE, preserving linearity at low dimming duty cycles is difficult.

Several modifications are suggested for applications requiring low dimming duty cycles. Since nDIM rising

releases the latch but does not trigger the on-time specifically, there will be an effective jitter on the rising edge of

the LED current. This jitter can be easily removed by tying the PWM input signal through the synchronization

network at the RT pin (shown in ), forcing the on-time to synchronize with the nDIM pulse.

The second helpful modification is to remove the C_FScapacitor and R_FSresistor, eliminating the high frequency

compensation pole. This should not affect stability, but it will speed up the response of the CSH pin, specifically

at the rising edge of the LED current when PWM dimming, thus improving the achievable linearity at low dimming

duty cycles.

Inverted

PWM

V_IN

LM3424-Q1

D

DIM

R

UV2

nDIM

R

UVH

R

UV1

Q

DIM

Standard

PWM

Figure 32. Buck-Boost Level-Shifted PWM Circuit

LM3424-Q1

R

SNS

100 kW

10 V

Q2

100 nF

DDRV

Figure 33. Buck Level-Shifted PWM Circuit

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Feature Description (continued)

7.3.12 Thermal Shutdown

The LM3424-Q1 includes thermal shutdown. If the die temperature reaches approximately 165°C the device will

shut down (GATE pin low), until it reaches approximately 140°C where it turns on again.

7.4 Device Functional Modes

There are no additional device functional modes for this part.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Inductor

The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy

is stored in the inductor and transfered to the load in different ways (as an example, buck-boost operation is

detailed in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the

switching subinterval (t_ONor t_OFF) determines the inductor current ripple (Δi_L-PP). In the design process, L1 is

chosen to provide a desired Δi_L-PP. For a buck regulator the inductor has a direct connection to the load, which is

good for a current regulator. This requires little to no output capacitance therefore Δi_L-PPis basically equal to the

LED ripple current Δi_LED-PP. However, for boost and buck-boost regulators, there is always an output capacitor

which reduces Δi_LED-PP, therefore the inductor ripple can be larger than in the buck regulator case where output

capacitance is minimal or completely absent.

In general, Δi_LED-PPis recommended by manufacturers to be less than 40% of the average LED current (I_LED).

Therefore, for the buck regulator with no output capacitance, Δi_L-PPshould also be less than 40% of I_LED. For the

boost and buck-boost topologies, Δi_L-PPcan be much higher depending on the output capacitance value.

However, Δi_L-PPis suggested to be less than 100% of the average inductor current (I_L) to limit the RMS inductor

current.

L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable

RMS inductor current (I_L-RMS).

8.1.2 LED Dynamic Resistance

When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus R_SNS

.

LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the

forward voltage of a single LED (V_LED) by the forward current (I_LED) leads to an incorrect calculation of the

dynamic resistance of a single LED (r_LED). The result can be 5 to 10 times higher than the true r_LEDvalue.

Figure 34. Dynamic Resistance

Obtaining r_LEDis accomplished by referring to the manufacturer's LED I-V characteristic. It can be calculated as

the slope at the nominal operating point as shown in Figure 34. For any application with more than 2 series

LEDs, R_SNScan be neglected allowing r_Dto be approximated as the number of LEDs multiplied by r_LED

.

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Application Information (continued)

8.1.3 Output Capacitor

For boost and buck-boost regulators, the output capacitor (C_O) provides energy to the load when the recirculating

diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a buck topology will

simply reduce the LED current ripple (Δi_LED-PP) below the inductor current ripple (Δi_L-PP). In all cases, C_Ois sized

to provide a desired Δi_LED-PP. As mentioned in the Inductor section, Δi_LED-PPis recommended by manufacturers to

be less than 40% of the average LED current (I_LED).

C_Oshould be carefully chosen to account for derating due to temperature and operating voltage. It must also

have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current

rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested.

8.1.4 Input Capacitors

The input capacitance (C_IN) provides energy during the discontinuous portions of the switching period. For buck

and buck-boost regulators, C_INprovides energy during t_ONand during t_OFF, the input voltage source charges up

C_INwith the average input current (I_IN). For boost regulators, C_INonly needs to provide the ripple current due to

the direct connection to the inductor. C_INis selected given the maximum input voltage ripple (Δv_IN-PP) which can

be tolerated. Δv_IN-PPis suggested to be less than 10% of the input voltage (V_IN).

An input capacitance at least 100% greater than the calculated C_INvalue is recommended to account for derating

due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to

minimize the large current draw from the input voltage source during the rising transistion of the LED current

waveform.

The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the

best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R

dieletric rating is suggested.

For most applications, it is recommended to bypass the V_INpin with an 0.1 µF ceramic capacitor placed as close

as possible to the pin. In situations where the bulk input capacitance may be far from the LM3424-Q1 device, a

10 Ω series resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a

150 kHz filter to eliminate undesired high frequency noise.

8.1.5 Main MOSFET and Dimming MOSFET

The LM3424-Q1 requires an external NFET (Q1) as the main power MOSFET for the switching regulator. Q1 is

recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe

operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the

switch node due to the diode parasitic capacitance and the lead inductance. The current rating is recommended

to be at least 10% higher than the average transistor current. The power rating is then verified by calculating the

power loss given the RMS transistor current and the NFET on-resistance (R_DS-ON).

When PWM dimming, the LM3424-Q1 requires another MOSFET (Q2) placed in series (or parallel for a buck

regulator) with the LED load. This MOSFET should have a voltage rating greater than the output voltage (V_O)

and a current rating at least 10% higher than the nominal LED current (I_LED) . The power rating is simply V_O

multiplied by R_DS-ON, assuming 100% dimming duty cycle (continuous operation) will occur.

In general, the NFETs should be chosen to minimize total gate charge (Q_g) when f_SWis high and minimize R_DS-ON

otherwise. This will minimize the dominant power losses in the system. Frequently, higher current NFETs in

larger packages are chosen for better thermal performance.

8.1.6 Re-Circulating Diode

A re-circulating diode (D1) is required to carry the inductor current during t_OFF. The most efficient choice for D1 is

a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 is

recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe

operation during the ringing of the switch node and a current rating at least 10% higher than the average diode

current. The power rating is verified by calculating the power loss through the diode. This is accomplished by

checking the typical diode forward voltage from the I-V curve on the product datasheet and multiplying by the

average diode current. In general, higher current diodes have a lower forward voltage and come in better

performing packages minimizing both power losses and temperature rise.

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Application Information (continued)

8.1.7 Switching Frequency

The switching frequency of the LM3424-Q1 is programmed using an external resistor (R_T) connected from the

RT pin to GND as shown in Figure 35.

Alternatively, an external PWM signal can be applied to the RT pin through a filter (R_FLTand C_FLT) and an AC-

coupling capacitor (C_AC) to synchronize the part to an external clock as shown in Figure 35. If the external PWM

signal is applied at a frequency higher than the base frequency set by the R_Tresistor, the internal oscillator is

bypassed and the switching frequency becomes the synchronized frequency. The external synchronization signal

should have a pulse width of 100 ns, an amplitude between 3 V and 6 V, and be AC coupled to the RT pin with a

ceramic capacitor (C_AC= 100 pF). A 10-MHz RC filter (R_FLT= 150 Ω and C_FLT= 100 pF) should be placed

between the PWM signal and C_ACto eliminate unwanted high frequency noise from coupling into the RT pin.

The switching frequency is defined:

1

f_SW

=

-

-8

1.4 x 10 ¹⁰xR_T1.95 x 10

-

(35)

See the Typical Characteristics section for a plot of R_Tvs. f_SW

.

LM3424-Q1

External Synchronization

Start t_ON

R

FLT

C

AC

RT

Oscillator

PWM

C

FLT

R

T

Figure 35. Timing Circuitry

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8.2 Typical Applications

8.2.1 Basic Topology Schematics

L1

D1

V_IN

C

IN

R

HSP

1

2

20

19

18

17

16

VIN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

FS

R

SNS

R

HSN

R

UV2

EN

R

FS

C

R

SLP

CMP

3

COMP

CSH

R

CSH

4

C

OUT

R

OV2

R

T

I_LED

5

RT/SYNC

nDIM

VCC

GATE

GND

DDRV

OVP

VS

C

BYP

R

UVH

6

15

Q1

R

UV1

C

SS

7

14

13

12

11

R

LIM

SS

R

GAIN

8

Q2

TGAIN

TSENSE

TREF

9

DAP

C

OV

R

OV1

R

C

REF1

10

R

BIAS

REF2

REF

NTC

C

NTC

Q3

PWM

Figure 36. Boost Regulator (V_IN< V_O)

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Typical Applications (continued)

V_IN

C

IN

R

HSP

1

2

20

19

18

17

16

VIN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

FS

R

SNS

R

HSN

R

UV2

EN

R

FS

C

CMP

R

C

OUT

SLP

3

COMP

CSH

R

PU

D2

R

CSH

4

R

OV2

Q2

I_LED

DIM

R

T

D1

5

RT/SYNC

nDIM

VCC

GATE

GND

DDRV

OVP

VS

L1

C

BYP

Q5

R

UVH

6

15

14

13

12

11

Q1

C

R

UV1

SS

7

R

LIM

SS

R

GAIN

8

TGAIN

TSENSE

TREF

DIM

C

DIM

9

DAP

R

C

R

C

REF1

OV1

OV

10

R

BIAS

REF2

REF

Q3

PWM

NTC

C

NTC

Figure 37. Buck Regulator (V_IN> V_O)

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Typical Applications (continued)

D1

LED+

V_IN

L1

C

IN

I_LED

DIM

C

OUT

R

HSP

Q2

1

2

20

19

18

17

16

VIN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

R

SNS

FS

R

HSN

R

UV2

EN

V_IN

R

FS

C

R

CMP

SLP

3

COMP

CSH

LED+

R

CSH

4

R

PU

Q7

R

DIM

OV2

R

T

5

RT/SYNC

nDIM

VCC

GATE

GND

DDRV

OVP

VS

Q6

Q4

C

BYP

D2

R

UVH

6

15

Q5

Q1

V_IN

R

UV1

C

SS

7

14

13

12

11

R

LIM

SER

SS

R

GAIN

8

TGAIN

TSENSE

TREF

9

DAP

R

C

OV

OV1

R

C

REF1

10

R

REF2

REF

R

BIAS

Q3

PWM

NTC

C

NTC

Figure 38. Buck-Boost Regulator

8.2.1.1 Design Requirements

Number of series LEDs: N

Single LED forward voltage: V_LED

Single LED dynamic resistance: r_LED

Nominal input voltage: V_IN

Input voltage range: V_IN-MAX, V_IN-MIN

Switching frequency: f_SW

Current sense voltage: V_SNS

Average LED current: I_LED

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Typical Applications (continued)

Inductor current ripple: Δi_L-PP

LED current ripple: Δi_LED-PP

Peak current limit: I_LIM

Input voltage ripple: Δv_IN-PP

Output OVLO characteristics: V_TURN-OFF, V_HYSO

Input UVLO characteristics: V_TURN-ON, V_HYS

Thermal foldback characteristics: T_BK, T_END

Total start-up time: t_TSU

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Operating Point

Given the number of series LEDs (N), the forward voltage (V_LED) and dynamic resistance (r_LED) for a single LED,

solve for the nominal output voltage (V_O) and the nominal LED string dynamic resistance (r_D):

V_O= N´ V_LED

(36)

r_D= N´r_LED

(37)

Solve for the ideal nominal duty cycle (D):

Buck

V_O

D =

V

IN

(38)

(39)

(40)

Boost

V_O- V

IN

D =

V_O

Buck-Boost

V_O

D =

V_O+ V

IN

Using the same equations, find the minimum duty cycle (D_MIN) using maximum input voltage (V_IN-MAX) and the

maximum duty cycle (D_MAX) using the minimum input voltage (V_IN-MIN). Also, remember that D' = 1 - D.

8.2.1.2.2 Switching Frequency

Set the switching frequency (f_SW) by solving for R_T:

1+1.95x10^-8x f_SW

1.40x10^-10x f_SW

R_T=

(41)

8.2.1.2.3 Average LED Current

For all topologies, set the average LED current (I_LED) knowing the desired current sense voltage (V_SNS) and

solving for R_SNS

:

V_SNS

I_LED

R_SNS

=

(42)

If the calculated R_SNSis too far from a desired standard value, then V_SNSwill have to be adjusted to obtain a

standard value.

Setup the suggested signal current of 100 µA by assuming R_CSH= 12.4 kΩ and solving for R_HSP

:

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Typical Applications (continued)

I_LEDx R_CSHx R_SNS

R_HSP

=

1.24V

(43)

If the calculated R_HSPis too far from a desired standard value, then R_CSHcan be adjusted to obtain a standard

value.

8.2.1.2.4 Thermal Foldback

For all topologies, set the thermal foldback breakpoint (T_BK) by finding corresponding R_NTC-BKfrom manufacturer's

datasheet and solving for R_BIAS

:

R_REF2

R_BIAS= R_NTC-BK

x

R_REF1

(44)

The easiest approach is to set R_REF1= R_REF2, therefore setting R_BIAS= R_NTC-BKwill properly set T_BK. Remember,

capacitance is recommended at the TSENSE and TREF pins, so ensure C_REF> C_NTCto prevent start-up in

foldback.

Then set the thermal foldback endpoint (T_END) by finding the corresponding R_NTC-ENDfrom manufacturer's

datasheet and solving for R_GAIN

:

≈

’

÷

◊

R_REF1

R_NTC-END

∆

-

x 2.45V

∆

R_REF1

R

R_NTC-ENDR

+

BIAS

+

REF2

«

R_GAIN

=

I_CSH

(45)

8.2.1.2.5 Inductor Ripple Current

Set the nominal inductor ripple current (Δi_L-PP) by solving for the appropriate inductor (L1):

Buck

(

)

V - V_OxD

IN

L1

=

üi_L-PPx f_SW

(46)

(47)

Boost and Buck-boost

V x D

IN

L1=

x f_SW

üi_L-PP

To set the worst case inductor ripple current, use V_IN-MAXand D_MINwhen solving for L1.

The minimum allowable inductor RMS current rating (I_L-RMS) can be calculated as:

Buck

2

DI_L-PP

≈

∆

«

’

1

12

I_L-RMS= I_LED

x

1 +

x

÷

I_LED

◊

(48)

(49)

Boost and Buck-Boost

2

DI_L-PPx D'

I_LED

≈

’

÷

1

12

x

1 +

x

I_L-RMS

=

∆

I_LED

D'

«

◊

8.2.1.2.6 LED Ripple Current

Set the nominal LED ripple current (Δi_LED-PP), by solving for the output capacitance (C_O):

Buck

Di_L-PP

8 x f_SWx r_Dx Di_LED-PP

C_O=

(50)

33

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Typical Applications (continued)

I_LEDx D

C_O=

r_Dxüi_LED-PPx f_SW

(51)

To set the worst case LED ripple current, use D_MAXwhen solving for C_O. Remember, when PWM dimming it is

recommended to use a minimum of 40 µF of output capacitance to improve performance.

The minimum allowable RMS output capacitor current rating (I_CO-RMS) can be approximated:

Buck

üi_LED-PP

I_{CO- RMS}

=

12

(52)

(53)

Boost and Buck-Boost

D_MAX

I_CO-RMS= I_LED

x

1-D_MAX

8.2.1.2.7 Peak Current Limit

Set the peak current limit (I_LIM) by solving for the transistor path sense resistor (R_LIM):

245 mV

R_LIM

=

I_LIM

(54)

8.2.1.2.8 Slope Compensation

For all topologies, the preferred method to set slope compensation is to ensure any duty cycle is attainable for

the nominal V_Oand chosen L by solving for R_SLP

:

1.5x10¹³x L1

R_SLP

=

V_OxR_TxR_LIM

(55)

8.2.1.2.9 Loop Compensation

Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the

necessary loop compensation can be determined.

First, the uncompensated loop gain (T_U) of the regulator can be approximated:

Buck

1

T_U= T_U0

x

≈

’

÷

◊

s

∆

1+

∆

w_P1

«

(56)

Boost and Buck-Boost

≈

’

÷

◊

s

w_Z1

∆ -

1

∆

«

T_U= T_U0x

≈

’

÷

◊

s

w_P1

∆

1+

∆

«

(57)

(58)

Where the pole (ω_P1) is approximated:

Buck

1

w_P1=

r_Dx C_O

Boost

2

w_P1=

r_Dx C_O

(59)

34

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Typical Applications (continued)

Buck-Boost

1+D

w_P1=

r_Dx C_O

(60)

And the RHP zero (ω_Z1) is approximated:

Boost

Å²

r_DxD

L1

w_Z1=

(61)

(62)

Buck-Boost

Å²

r_DxD

w_Z1=

DxL1

And the uncompensated DC loop gain (T_U0) is approximated:

Buck

500Vx R_CSHx R_SNS

R_HSPx R_LIM

620V

I_LEDx R_LIM

T_U0

=

(63)

(64)

Boost

T_U0

Å

D x 500V x R_CSHx R_SNS

Å

D x 310V

I_LEDx R_LIM

=

2 x R_HSPx R_LIM

Buck-Boost

Å

D x 500Vx R_CSHx R_SNS

Å

D x 620V

T_U0

=

(

)

(

)

1+D x R_HSPx R_LIM

1+D xI_LEDx R_LIM

(65)

For all topologies, the primary method of compensation is to place a low frequency dominant pole (ω_P2) which will

ensure that there is ample phase margin at the crossover frequency. This is accomplished by placing a capacitor

(C_CMP) from the COMP pin to GND, which is calculated according to the lower value of the pole and the RHP

zero of the system (shown as a minimizing function):

min(w_P1,w_Z1)

w_P2

=

5 xT_U0

(66)

1

C_CMP

=

w_P2x 5x10⁶

(67)

If analog dimming is used, C_CMPshould be approximately 4x larger to maintain stability as the LEDs are dimmed

to zero.

A high frequency compensation pole (ω_P3) can be used to attenuate switching noise and provide better gain

margin. Assuming R_FS= 10Ω, C_FSis calculated according to the higher value of the pole and the RHP zero of

the system (shown as a maximizing function):

(

)

w_P3max w ,w x10

=

P1

Z1

(68)

1

C_FS

=

10 xw_P3

(69)

The total system loop gain (T) can then be written as:

Buck

1

T = T_U0

x

≈

’

÷

◊

≈

∆

«

’

÷

◊

≈

∆

«

’

÷

◊

s

w_P1

s

w_P3

∆

1+

x 1+

∆

w_P2

«

(70)

35

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Typical Applications (continued)

≈

’

÷

◊

s

w_Z1

∆

1-

∆

«

T = T_U0

x

≈

’

÷

◊

≈

∆

«

’

≈

∆

«

’

÷

◊

s

w_P1

s

w_P2

s

w_P3

∆

÷

∆

1+

x 1+

∆

÷

«

◊

(71)

8.2.1.2.10 Input Capacitance

Set the nominal input voltage ripple (Δv_IN-PP) by solving for the required capacitance (C_IN):

Buck

I_LEDx (1 - D) x D

C_IN

Boost

C_IN

=

DV_IN-PPx f_SW

(72)

(73)

(74)

Di_L-PP

=

8 x DV_IN-PPx f_SW

Buck-Boost

I_LEDx D

C_IN

=

DV_IN-PPx f_SW

Use D_MAXto set the worst case input voltage ripple, when solving for C_INin a buck-boost regulator and D_MID= 0.5

when solving for C_INin a buck regulator.

The minimum allowable RMS input current rating (I_CIN-RMS) can be approximated:

Buck

I

_{CIN- RMS}= I_LEDx D_MIDx(1-D_MID

)

(75)

(76)

Boost

Di_L-PP

I_CIN-RMS

Buck-Boost

=

12

D_MAX

I_CIN-RMS= I_LED

x

1-D_MAX

(77)

8.2.1.2.11 NFET

The NFET voltage rating should be at least 15% higher than the maximum NFET drain-to-source voltage (V_T-

_MAX):

Buck

V_{T- MAX}= V

IN- MAX

(78)

(79)

(80)

Boost

V

_{T- MAX}= V_O

Buck-Boost

_{T- MAX}= V_{IN- MAX}+ V_O

V

The current rating should be at least 10% higher than the maximum average NFET current (I_T-MAX):

Buck

I_T-MAX= D_MAXx I_LED

(81)

Boost and Buck-Boost

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Typical Applications (continued)

D_MAX

I_T-MAX

=

x I_LED

1 - D_MAX

(82)

(83)

Approximate the nominal RMS transistor current (I_T-RMS) :

Buck

I

_{T- RMS}= I_LEDx D

Boost and Buck-Boost

I

^LEDx D

I_{T- RMS}

=

Å

D

(84)

(85)

Given an NFET with on-resistance (R_DS-ON), solve for the nominal power dissipation (P_T):

P = I_{T- RMS}²x R_DSON

T

8.2.1.2.12 Diode

The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (V_RD-MAX):

Buck

V_RD-MAX= V_IN-MAX

(86)

Boost

V_RD-MAX= V_O

(87)

(88)

Buck-Boost

V_RD-MAX= V_IN-MAX+ V_O

The current rating should be at least 10% higher than the maximum average diode current (I_D-MAX):

Buck

I_D-MAX= (1 - D_MIN) x I_LED

(89)

(90)

Boost and Buck-Boost

I_D-MAX= I_LED

Replace D_MAXwith D in the I_D-MAXequation to solve for the average diode current (I_D). Given a diode with forward

voltage (V_FD), solve for the nominal power dissipation (P_D):

P_D= I_DxV_FD

(91)

8.2.1.2.13 Output OVLO

For boost and buck-boost regulators, output OVLO is programmed with the turn-off threshold voltage (V_TURN-OFF

)

and the desired hysteresis (V_HYSO). To set V_HYSO, solve for R_OV2

:

V_HYSO

R_OV2

=

20mA

(92)

To set V_TURN-OFF, solve for R_OV1

:

Boost

1.24V x R_OV2

R_OV1

=

V_TURN-OFF- 1.24V

(93)

Buck-Boost

R_OV1

1.24V x R_OV2

=

V_{TURN- OFF}- 620 mV

(94)

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Typical Applications (continued)

A small filter capacitor (C_OVP= 47 pF) should be added from the OVP pin to ground to reduce coupled switching

noise.

8.2.1.2.14 Input UVLO

For all topologies, input UVLO is programmed with the turn-on threshold voltage (V_TURN-ON) and the desired

hysteresis (V_HYS).

Method 1: If no PWM dimming is required, a two resistor network can be used. To set V_HYS, solve for R_UV2

:

V_HYS

20 mA

R_UV2

=

(95)

To set V_TURN-ON, solve for R_UV1

:

1.24Vx R_UV2

R_UV1

=

V_{TURN- ON}- 1.24V

(96)

Method 2: If PWM dimming is required, a three resistor network is suggested. To set V_TURN-ON, assume R_UV2

10 kΩ and solve for R_UV1as in Method 1. To set V_HYS, solve for R_UVH

=

:

(

)

R_UV1x V_HYS- 20 mA x R_UV2

R_UVH

=

(

)

20 mA x R_UV1+ R_UV2

(97)

8.2.1.2.15 Soft-Start

For all topologies, if soft-start is desired, find the start-up time without C_SS(t_SU):

t_SU

t

+

CO

=

+

VCC

CMP

(98)

Then, if the desired total start-up time (t_TSU) is larger than t_SU, solve for the base start-up time (t_SU-SS-BASE),

assuming that a C_SSgreater than 40% of C_CMPwill be used:

V

I_LED

O

t_SU-SS-BASE168W xC

28 kW xC

xC_O

=

+

CMP

BYP

(99)

Then solve for C_SS

:

10mA

0.2V

( )

x t_TSU-t_SU-SS-BASE

C_SS

=

(100)

8.2.1.2.16 PWM Dimming Method

PWM dimming can be performed several ways:

Method 1: Connect the dimming MOSFET (Q₃) with the drain to the nDIM pin and the source to GND. Apply an

external PWM signal to the gate of Q_DIM. A pull down resistor may be necessary to properly turn off Q₃.

Method 2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to the

cathode of the same diode.

The DDRV pin should be connected to the gate of the dimFET with or without level-shifting circuitry as described

in the PWM Dimming section. The dimFET should be rated to handle the average LED current and the nominal

output voltage.

8.2.1.2.17 Analog Dimming Method

Analog dimming can be performed several ways:

Method 1: Place a potentiometer in place of the thermistor in the thermal foldback circuit shown in the Thermal

Foldback and Analog Dimming section.

Method 2: Place a potentiometer in series with the R_CSHresistor to dim the LED current from the nominal I_LEDto

near zero.

Method 3: Connect a controlled current source as detailed in the Thermal Foldback and Analog Dimming section

to the CSH pin. Increasing the current sourced into the CSH node will decrease the LEDs from the nominal I_LED

to zero current in the same manner as the thermal foldback circuit.

38

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Typical Applications (continued)

8.2.2 Buck-Boost Application

10 V œ 70 V

V_IN

D1

L1

C

IN

R

HSP

1

2

20

19

18

17

16

V_IN

HSP

HSN

SLOPE

IS

LM3424-Q1

1 A

I_LED

HSN

R

UV2

EN

C

OUT

C

R

CMP

SLP

3

COMP

CSH

R

CSH

4

C

R

SNS

FS

R

T

V_IN

5

R

FS

RT/SYNC

nDIM

V_CC

C

BYP

6

15

14

13

12

11

GATE

GND

DDRV

OVP

V_S

Q1

R

C

SS

UV1

R

7

R

OV2

LIM

SS

R

GAIN

8

Q2

TGAIN

TSENSE

TREF

V_IN

9

DAP

R

C

OV1

OV

R

C

REF1

10

R

REF2

REF

R

BIAS

NTC

C

NTC

Figure 39. Buck-Boost Application

8.2.2.1 Design Requirements

N = 6

V_LED= 3.5V

r_LED= 325 mΩ

V_IN= 24V

V_IN-MIN= 10V

V_IN-MAX= 70V

f_SW= 500 kHz

V_SNS= 100 mV

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Typical Applications (continued)

I_LED= 1A

Δi_L-PP= 700 mA

Δi_LED-PP= 12 mA

Δv_IN-PP= 100 mV

I_LIM= 6A

V_TURN-ON= 10V

V_HYS= 3V

V_TURN-OFF= 40V

V_HYSO= 10V

T_BK= 70°C

T_END= 120°C

t_TSU= 30 ms

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Operating Point

Solve for V_Oand r_D:

V_ONx V

6x 3.5V 21V

=

LED

(101)

(102)

r_DN x r

6 x 325 mW 1.95W

=

LED

Solve for D, D', D_MAX, and D_MIN

:

V_O

V_O+V

21V

21V + 24V

D =

=

= 0.467

IN

(103)

(104)

D' 1- D 1- 0.467 0.533

=

V_O

21V

=

D_MIN

=

= 0.231

V_O+ V_IN-MAX

21V + 70V

(105)

(106)

V_O

=

21V

21V +10V

D_MAX

=

= 0.677

V_O+V

IN-MIN

8.2.2.2.2 Switching Frequency

Solve for R_T:

1+1.95 x 10^-8x f_SW

1+1.95 x 10^-8x 500 kHz

1.4 x 10^-¹⁰x 500 kHz

R_T

=

14.4 kΩ

1.4 x 10^-¹⁰x f_SW

(107)

The closest standard resistor is 14.3 kΩ therefore f_SWis:

1

f_SW

=

-

-8

1.4 x 10 ¹⁰xR_T1.95 x 10

-

1

f_SW

504 kHz

=

-

8

-

1.4 x 10 ¹⁰x14.3 kΩ 1.95 x 10

-

(108)

(109)

The chosen component from step 2 is:

R_T= 14.3 kW

8.2.2.2.3 Average LED Current

Solve for R_SNS

:

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Typical Applications (continued)

V

I_LED

100 mV

1A

SNS

R_SNS

0.1W

=

(110)

(111)

Assume R_CSH= 12.4 kΩ and solve for R_HSP

:

I_LEDxR_CSHx R_SNS

1.24V

1Ax12.4 kW x 0.1W

R_HSP

=

=1.0 kW

1.24V

The closest standard resistor for R_SNSis actually 0.1Ω and for R_HSPis actually 1 kΩ therefore I_LEDis:

1.24Vx R_HSP

R_SNSx R_CSH

1.24V x1.0 kW

0.1W x12.4 kW

I_LED

=

=1.0A

(112)

The chosen components from step 3 are:

R_SNS0.1W

=

R_CSH12.4 kW

=

R_HSP

R

1kW

=

HSN

(113)

8.2.2.2.4 Thermal Foldback

Find the resistances corresponding to T_BKand T_END(R_NTC-BK= 24.3 kΩ and R_NTC-END= 7.15 kΩ) from the

manufacturer's datasheet. Assuming R_REF1= R_REF2= 49.9 kΩ, then R_BIAS= R_NTC-BK= 24.3 kΩ.

Solve for R_GAIN

:

≈

’

÷

◊

R_REF1

R_{NTC- END}

∆

-

x 2.45V

∆

R_REF1

R

R_{NTC -END}R

+

BIAS

+

REF2

«

R_GAIN

=

I_CSH

≈

’

1

2

7.15 kW

∆

÷

-

x 2.45V

7.15 kW+24.3kW

«

◊

R_GAIN

6.68 kW

=

100 mA

(114)

(115)

The chosen components from step 4 are:

R_GAIN6.81kΩ

=

R_BIAS24.3 kΩ

=

R_REF1

R

49.9 kΩ

=

REF2

8.2.2.2.5 Inductor Ripple Current

Solve for L1:

V x D

24Vx0.467

Di_L-PPx f_SW700 mA x504kHz

IN

32 mH

=

L1=

=

(116)

(117)

The closest standard inductor is 33 µH therefore Δi_L-PPis:

V x D

24Vx 0.467

L1x f_SW33 mHx504 kHz

IN

674 mA

=

Di_{L- PP}

=

Determine minimum allowable RMS current rating:

≈

∆

«

Å’²

Di_L-PPx D

I

1

12

^LEDx 1+

÷

x

I_L-RMS

=

÷

I_LED

Å

D

◊

2

674 mA x 0.533

1

≈

’

1A

1.89A

x

=

x 1+

∆

÷

I_L-RMS

12

1A

0.533

«

◊

(118)

41

The chosen component from step 5 is:

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Typical Applications (continued)

L1= 33 mH

(119)

8.2.2.2.6 Output Capacitance

Solve for C_O:

I_LEDx D

C_O=

r_Dx Di_LED-PPx f_SW

1A x 0.467

1.95W x 12 mA x504 kHz

=

= 39.6 mF

C_O

(120)

(121)

The closest capacitance totals 40 µF therefore Δi_LED-PPis:

I_LEDx D

Di_LED-PP

=

r_Dx C_Ox f_SW

1A x 0.467

1.95W x x 504 kHz

Di_LED-PP

12 mA

=

40 mF

Determine minimum allowable RMS current rating:

D_MAX

1- D_MAX

0.677

1- 0.677

x

I

_CO-RMS=I_LED

=1A

=1.45A

(122)

(123)

The chosen components from step 6 are:

C_O= 4 x 10 mF

8.2.2.2.7 Peak Current Limit

Solve for R_LIM

:

245 mV 245 mV

R_LIM

=

= 0.041W

I_LIM

6A

(124)

The closest standard resistor is 0.04 Ω therefore I_LIMis:

245 mV 245 mV

I_LIM

=

= 6.13A

R_LIM

0.04W

(125)

(126)

The chosen component from step 7 is:

R_LIM= 0.04W

8.2.2.2.8 Slope Compensation

Solve for R_SLP

:

1.5 x 10¹³xL1

V_OxR_TxR_LIM

13

R_SLP

=

1.5e x33μH

41.2 kΩ

=

R_SLP

=

21 V x14.3 kΩ x0.04 Ω

(127)

(128)

The chosen component from step 8 is:

R_SLP41.2 kΩ

=

8.2.2.2.9 Loop Compensation

ω_P1is approximated:

rad

sec

1+D

r_DxC_O

1.467

1.95W x 40 mF

w_P1=

=

=19k

(129)

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Typical Applications (continued)

ω_Z1is approximated:

Å²

1.95W x0.533²

rad

sec

r_Dx D

w_Z1=

=

= 36k

DxL1 0.467x 33mH

(130)

(131)

T_U0is approximated:

Å

0.533x620V

1.467x1A x 0.04W

D x 620V

T_U0=

=

= 5630

(

)

1 D xI_LEDx R_LIM

+

To ensure stability, calculate ω_P2:

rad

sec

19k

min(w_P1,w_Z1)

w_P1

rad

sec

w_P2=

=

= 0.675

5 xT_U0

5 x5630 5 x 5630

(132)

(133)

Solve for C_CMP

:

1

C_CMP

=

= 0.30μF

ω_P2x 5 x 10⁶Ω

rad

0.675

x 5 x 10⁶Ω

sec

To attenuate switching noise, calculate ω_P3:

w_P3(maxw ,w ) x10 _Z1x10

w

=

P1

Z1

rad

sec

rad

sec

w_P336k

x10 360k

=

(134)

(135)

Assume R_FS= 10Ω and solve for C_FS

:

1

C_FS

=

= 0.28 mF

10W

x w

rad

sec

P3

10W x

360k

The chosen components from step 9 are:

C_CMP= 0.33mF

R_FS=10W

C_FS= 0.27mF

(136)

(137)

8.2.2.2.10 Input Capacitance

Solve for the minimum C_IN:

I_LEDx D

Dv_IN-PPx f_SW

1A x 0.467

100 mV x 504kHz

C_IN=

=

= 9.27mF

To minimize power supply interaction a 200% larger capacitance of approximately 20 µF is used, therefore the

actual Δv_IN-PPis much lower. Since high voltage ceramic capacitor selection is limited, four 4.7 µF X7R capacitors

are chosen.

Determine minimum allowable RMS current rating:

D_MAX

1- D_MAX

0.677

1- 0.677

x

I

_IN-RMS=I_LED

=1A

=1.45A

(138)

(139)

The chosen components from step 10 are:

C_IN= 4 x 4.7 mF

8.2.2.2.11 NFET

Determine minimum Q1 voltage rating and current rating:

V_T-MAX70V 21V 91V

V

=

O

=

+

=

IN- MAX

(140)

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Typical Applications (continued)

0.677

1- 0.677

I_T-MAX

x1A 2.1A

=

(141)

A 100V NFET is chosen with a current rating of 32A due to the low R_DS-ON= 50 mΩ. Determine I_T-RMSand P_T:

I_LED

1A

0.533

I_T-RMS

D

0.467 1.28A

x

=

x

=

Å

D

(142)

(143)

P_T

I

²x R_DSON1.28A²x 50 mW 82 mW

= =

T- RMS

=

The chosen component from step 11 is:

Q1 ç 32A, 100V, DPAK

(144)

8.2.2.2.12 Diode

Determine minimum D1 voltage rating and current rating:

_RD-MAX= V_IN-MAX+ V_O= 70V +21V = 91V

I_D-MAX1A

V

(145)

(146)

I

=

LED

A 100V diode is chosen with a current rating of 12A and V_DF= 600 mV. Determine P_D:

I x V 1A x 600 mV 600 mW

P

=

D

FD

(147)

(148)

The chosen component from step 12 is:

D1 ç 12A, 100V, DPAK

8.2.2.2.13 Input UVLO

Solve for R_UV2

:

V_HYS

3V

m

R_UV2

=

=150kW

m

20 A 20 A

(149)

(150)

The closest standard resistor is 150 kΩ therefore V_HYSis:

V_HYS

R

x20mA 150 kW x20 mA 3V

=

UV2

Solve for R_UV1

:

1.24Vx R_UV2

1.24Vx150kW

10V -1.24V

R_UV1

=

= 21.2 kW

V_{TURN- ON}-1.24V

(151)

The closest standard resistor is 21 kΩ making V_TURN-ON

:

(

)

1.24Vx R_UV1+ R_UV2

V_TURN-ON

=

R_UV1

(

)

1.24Vx 21kW +150kW

V_TURN-ON

= 10.1V

21kW

(152)

(153)

The chosen components from step 13 are:

R_UV121kW

=

R_UV2150 kW

=

8.2.2.2.14 Output OVLO

Solve for R_OV2

:

V_HYSO

10V

m

R_OV2

=

= 500kW

m

20 A 20 A

(154)

The closest standard resistor is 499 kΩ therefore V_HYSOis:

44

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Typical Applications (continued)

m

V_HYSO

R

x 20 A 499 kW x 20 A 9.98V

=

OV2

(155)

(156)

Solve for R_OV1

:

1.24Vx R_OV2

1.24Vx 499kW

40V - 0.62V

R_OV1

=

= 15.7 kW

V_TURN-OFF- 0.62V

The closest standard resistor is 15.8 kΩ making V_TURN-OFF

:

(

)

1.24Vx 0.5x R_OV1+ R_OV2

V_TURN-OFF

=

R_OV1

(

)

1.24Vx 0.5x15.8 kW +499kW

V_TURN-OFF

= 39.8V

15.8 kW

(157)

(158)

The chosen components from step 14 are:

R_OV1= 15.8 kW

R_OV2= 499 kW

8.2.2.2.15 Soft-Start

Solve for t_SU

:

V_O

I_LED

t_SU

168W x C

36 kW xC

x C_O

=

+

CMP

BYP

21V

1A

x 40 mF

t_SU168W x2.2 mF 36 kW x0.33 mF

+

=

+

t_SU13.1 ms

=

(159)

(160)

If t_SUis less than t_TSU, solve for t_SU-SS-BASE

:

V_O

t_SU-SS-BASE

168W x C

28 kW xC

x C_O

I_LED

=

+

CMP

BYP

21V

1A

x 40 mF

t_{SU-SS- BASE}168W x2.2 mF 28 kW x0.33 mF

+

=

+

t_{SU-SS- BASE}10.5 ms

=

Solve for C_SS

:

(

)

(

t_TSU-t_SU-SS-BASE

)

30 ms-10.5 ms

975 nF

C_SS

=

20 kW

(161)

(162)

The chosen component from step 15 is:

C_SS1mF

=

Table 1. Bill of Materials

QTY

PART ID

LM3424

C_BYP

PART VALUE

MANUFACTURER

PART NUMBER

1

2

1

4

1

Boost controller

TI

LM3424MH

2.2 µF X7R 10% 16V

0.33 µF X7R 10% 25V

0.27 µF X7R 10% 25V

4.7 µF X7R 10% 100V

10 µF X7R 10% 50V

MURATA

TDK

GRM21BR71C225KA12L

GRM21BR71E334KA01L

GRM21BR71E274KA01L

C5750X7R2A475K

C_CMP, C_NTC

C_FS

C_IN

C_O

TDK

C4532X7R1H106K

C_OV

47 pF COG/NPO 5% 50V AVX

08055A470JAT2A

C_REF, C_SS

1 µF X7R 10% 25V

MURATA

GRM21BR71E105KA01L

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Typical Applications (continued)

Table 1. Bill of Materials (continued)

QTY

1

PART ID

D1

PART VALUE

Schottky 100V 12A

33 µH 20% 6.3A

NMOS 100V 32A

PNP 150V 600 mA

24.3 kΩ 1%

MANUFACTURER

PART NUMBER

VISHAY

COILCRAFT

FAIRCHILD

VISHAY

TDK

12CWQ10FNPBF

1

L1

MSS1278-333MLB

FDD3682

1

Q1

1

Q2

MMBT5401

1

R_BIAS

R_CSH

R_FS

CRCW080524K3FKEA

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08056K81FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080515K8FKEA

CRCW0805499KFKEA

CRCW080549K9FKEA

CRCW080516K5FKEA

WSL2512R1000FEA

CRCW080514K3FKEA

CRCW080521K0FKEA

CRCW0805150KFKEA

NTCG204H154J

1

12.4 kΩ 1%

1

10Ω 1%

1

R_GAIN

R_HSP, R_HSN

R_LIM

6.81 kΩ 1%

2

1.0 kΩ 1%

1

0.04Ω 1% 1W

15.8 kΩ 1%

1

R_OV1

R_OV2

R_REF1, R_REF2

R_SLP

1

499 kΩ 1%

2

49.9 kΩ 1%

1

16.5 kΩ 1%

1

R_SNS

R_T

0.1Ω 1% 1W

14.3 kΩ 1%

1

R_UV1

R_UV2

NTC

21 kΩ 1%

1

150 kΩ 1%

1

Thermistor 100 kΩ 5%

8.2.2.3 Application Curve

100

95

90

85

80

75

70

0

16

32

48

(V)

64

80

V

IN

Figure 40. Efficiency vs. Input Voltage

46

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8.2.3 Boost Application

8 V œ 28 V

V_IN

D1

L1

C

IN

R

HSP

1

2

20

19

18

17

16

V_IN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

R

SNS

FS

R

HSN

R

UV2

EN

R

FS

C

R

CMP

SLP

3

COMP

CSH

R

CSH

4

1 A

R

T

C

OUT

5

I_LED

RT/SYNC

nDIM

V_CC

C

BYP

R

UVH

6

15

14

13

12

11

GATE

GND

DDRV

OVP

V_S

Q1

R

C

SS

UV1

7

R

LIM

SS

R

GAIN

8

TGAIN

TSENSE

TREF

Q2

R

OV2

OV1

9

DAP

R

C

OV

R

C

REF1

10

R

REF2

REF

R

BIAS

NTC

C

NTC

Q3

PWM

Figure 41. Boost Application

8.2.3.1 Design Requirements

•

Input: 8 V to 28 V

Output: 9 LEDs at 1A

65°C - 100°C Thermal Foldback

PWM Dimming up to 30 kHz

700 kHz Switching Frequency

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8.2.3.2 Detailed Design Procedure

Table 2. Bill of Materials

QTY

1

0

4

1

2

1

2

1

2

1

2

1

2

1

2

1

PART ID

LM3424

C_BYP

PART VALUE

MANUFACTURER

PART NUMBER

Boost controller

TI

LM3424MH

2.2 µF X7R 10% 16V

0.1 µF X7R 10% 25V

DNP

MURATA

GRM21BR71C225KA12L

GRM21BR71E104KA01L

C_CMP

C_FS

C_IN

4.7 µF X7R 10% 100V

10 µF X7R 10% 50V

TDK

C5750X7R2A475K

C4532X7R1H106K

08055A470JAT2A

C_OUT

C_OV

47 pF COG/NPO 5% 50V AVX

C_NTC, C_SS

C_REF

0.27 µF X7R 10% 25V

1 µF X7R 10% 25V

Schottky 60V 5A

33 µH 20% 6.3A

NMOS 60V 8A

NMOS 60V 115mA

19.6 kΩ 1%

MURATA

GRM21BR71E274KA01L

GRM21BR71E105KA01L

CDBC560-G

MURATA

COMCHIP

COILCRAFT

VISHAY

ON-SEMI

VISHAY

TDK

D1

L1

MSS1278-333MLB

SI4436DY

Q1, Q2

Q3

2N7002ET1G

R_BIAS

CRCW080519K6FKEA

CRCW080512K4FKEA

CRCW08050000Z0EA

CRCW08056K49FKEA

CRCW08051K00FKEA

WSL2512R0600FEA

CRCW0805499KFKEA

CRCW080549K9FKEA

WSL2512R1000FEA

CRCW080510K0FKEA

CRCW080514K3FKEA

CRCW08051K82FKEA

CRCW080517K8FKEA

NTCG204H154J

R_CSH, R_OV1

R_FS

12.4 kΩ 1%

0Ω 1%

R_GAIN

R_HSP, R_HSN

R_LIM

6.49 kΩ 1%

1.0 kΩ 1%

0.06Ω 1% 1W

499 kΩ 1%

R_OV2

R_REF1, R_REF2

R_SNS

49.9 kΩ 1%

0.1Ω 1% 1W

R_SLP, R_UV2

R_T

10.0 kΩ 1%

14.3 kΩ 1%

R_UV1

1.82 kΩ 1%

R_UVH

17.8 kΩ 1%

NTC

Thermistor 100 kΩ 5%

48

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SNVSB96 –JULY 2019

8.2.4 Buck-Boost Application

10 V œ 30 V

V_IN

D1

L1

C

IN

2 A

I_LED

R

HSP

1

2

20

19

18

17

V_IN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

OUT

R

HSN

R

UV2

EN

Q2

R

DIM

C

R

CMP

SLP

3

C

COMP

CSH

FS

SNS

V_IN

R

CSH

R

FS

4

R

F

R

T

R

Q7

PU

C

F

5

16

C

RT/SYNC

nDIM

V_CC

R

OV2

DIM

BYP

R

UVH

6

15

14

13

12

11

Q6

Q4

GATE

GND

DDRV

OVP

V_S

Q1

C

B

D2

R

C

SS

UV1

7

Q5

R

LIM

R

SER

SS

V_IN

R

GAIN

8

TGAIN

TSENSE

TREF

9

DAP

R

C

OV1

OV

R

C

REF1

10

R

REF2

REF

R

BIAS

R

POT

C

NTC

Q3

PWM

Figure 42. Buck-Boost Application

8.2.4.1 Design Requirements

•

Input: 10V to 30V

Output: 4 LEDs at 2A

PWM Dimming up to 10 kHz

Analog Dimming

600-kHz Switching Frequency

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LM3424-Q1

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8.2.4.2 Detailed Design Procedures

Table 3. Bill of Materials

QTY

PART ID

LM3424

C_B

PART VALUE

MANUFACTURER

PART NUMBER

1

Boost controller

TI

LM3424MH

100 pF COG/NPO 5%

50V

MURATA

GRM2165C1H101JA01D

1

3

1

0

4

1

4

1

2

1

3

2

1

2

1

C_BYP

2.2 µF X7R 10% 16V

1 µF X7R 10% 25V

0.1 µF X7R 10% 25V

DNP

MURATA

GRM21BR71C225KA12L

GRM21BR71E105KA01L

GRM21BR71E104KA01L

C_CMP, C_REF, C_SS

C_F

C_FS

C_IN

6.8 µF X7R 10% 50V

0.47 µF X7R 10% 25V

10 µF X7R 10% 50V

TDK

C5750X7R1H685K

GRM21BR71E474KA01L

C4532X7R1H106K

08055A470JAT2A

12CWQ10FNPBF

BZX84C10LT1G

C_NTC

MURATA

TDK

C_OUT

C_OV

47 pF COG/NPO 5% 50V AVX

D1

Schottky 100V 12A

Zener 10V 500mA

22 µH 20% 7.2A

NMOS 60V 8A

NMOS 60V 260mA

PNP 40V 200 mA

PNP 150V 600 mA

NPN 300V 600 mA

NPN 40V 200 mA

49.9 kΩ 1%

VISHAY

D2

ON-SEMI

COILCRAFT

VISHAY

L1

MSS1278-223MLB

SI4436DY

Q1, Q2

Q3

ON-SEMI

FAIRCHILD

VISHAY

2N7002ET1G

Q4

MMBT5087

Q5

MMBT5401

Q6

MMBTA42

Q7

MMBT6428

R_BIAS, R_REF1, R_REF2

R_CSH, R_T

R_F

CRCW080549K9FKEA

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08050000Z0EA

CRCW080510K0FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080518K2FKEA

CRCW0805499KFKEA

3352P-1-503

12.4 kΩ 1%

VISHAY

10Ω 1%

VISHAY

R_FS

0Ω 1%

VISHAY

R_GAIN, R_UV2

R_HSP, R_HSN

R_LIM

10.0 kΩ 1%

VISHAY

1.0 kΩ 1%

VISHAY

0.04Ω 1% 1W

18.2 kΩ 1%

VISHAY

R_OV1

VISHAY

R_OV2

499 kΩ 1%

VISHAY

R_POT

50 kΩ potentiometer

4.99 kΩ 1%

BOURNS

VISHAY

R_PU

CRCW08054K99FKEA

CRCW0805499RFKEA

CRCW080534K0FKEA

WSL2512R0500FEA

CRCW08051K43FKEA

CRCW080517K4FKEA

R_SER

499Ω 1%

VISHAY

R_SLP

34.0 kΩ 1%

VISHAY

R_SNS

0.05Ω 1% 1W

1.43 kΩ 1%

VISHAY

R_UV1

VISHAY

R_UVH

17.4 kΩ 1%

VISHAY

50

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SNVSB96 –JULY 2019

8.2.5 Boost Application

18 V œ 38 V

V_IN

D1

L1

C

IN

R

HSP

1

2

20

19

18

17

16

V_CC

V_IN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

R

SNS

FS

R

HSN

EN

V_S

R

FS

C

Q4

Q3

R

SLP

CMP

3

COMP

CSH

R

MAX

Q2

R

4

C

OUT

700 mA

I_LED

V_CC

R

T

ADJ

R

BIAS2

CSH

5

RT/SYNC

nDIM

V_CC

R

UV2

C

BYP

6

15

14

13

12

11

GATE

GND

DDRV

OVP

V_S

Q1

R

C

SS

UV1

7

R

LIM

SS

R

GAIN

8

TGAIN

TSENSE

TREF

R

OV2

OV1

9

DAP

V_S

C

OV

R

C

REF1

10

R

REF2

REF

R

BIAS

NTC

C

NTC

Figure 43. Boost Application

8.2.5.1 Design Requirements

•

Input: 18V to 38V

Output: 12 LEDs at 700mA

85°C - 125°C Thermal Foldback

Analog Dimming

700 kHz Switching Frequency

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LM3424-Q1

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8.2.5.2 Detailed Design Procedure

Table 4. Bill of Materials

QTY

1

3

1

4

1

3

1

3

1

2

1

PART ID

PART VALUE

MANUFACTURER

PART NUMBER

LM3424

Boost controller

TI

LM3424MH

C_BYP

2.2 µF X7R 10% 16V

1 µF X7R 10% 25V

0.33 µF X7R 10% 25V

0.1 µF X7R 10% 25V

4.7 µF X7R 10% 100V

10 µF X7R 10% 50V

MURATA

TDK

GRM21BR71C225KA12L

GRM21BR71E105KA01L

GRM21BR71E334KA01L

GRM21BR71E104KA01L

C5750X7R2A475K

C4532X7R1H106K

08055A470JAT2A

CDBC560-G

C_CMP, C_REF, C_SS

C_NTC

C_FS

C_IN

C_OUT

TDK

C_OV

47 pF COG/NPO 5% 50V AVX

D1

Schottky 60V 5A

47 µH 20% 5.3A

NMOS 60V 8A

NPN 40V 200 mA

Dual PNP 40V 200mA

100 kΩ potentiometer

9.76 kΩ 1%

COMCHIP

L1

COILCRAFT

VISHAY

FAIRCHILD

BOURNS

VISHAY

TDK

MSS1278-473MLB

SI4436DY

Q1

Q2

MMBT3904

Q3, Q4 (dual pack)

R_ADJ

FFB3906

3352P-1-104

R_BIAS

CRCW08059K76FKEA

CRCW080517K4FKEA

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW08056K55FKEA

CRCW08051K00FKEA

WSL2512R0600FEA

CRCW0805499KFKEA

CRCW080549K9FKEA

CRCW080510K0FKEA

WSL2512R1500FEA

CRCW0805100KFKEA

NTCG204H154J

R_BIAS2

17.4 kΩ 1%

R_CSH, R_OV1, R_UV1

R_FS

12.4 kΩ 1%

10Ω 1%

R_GAIN

6.55 kΩ 1%

R_HSP, R_HSN, R_MAX

R_LIM

1.0 kΩ 1%

0.06Ω 1% 1W

499 kΩ 1%

R_OV2

R_REF1, R_REF2

R_SLP, R_T

R_SNS

49.9 kΩ 1%

10.0 kΩ 1%

0.15Ω 1% 1W

100 kΩ 1%

R_UV2

NTC

Thermistor 100 kΩ 5%

52

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SNVSB96 –JULY 2019

8.2.6 Buck-Boost Application

10V œ 70V

V_IN

D1

L1

C

IN

R

HSP

1

2

20

19

18

17

16

500 mA

I_LED

V_IN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

OUT

R

HSN

R

UV2

EN

C

R

CMP

SLP

3

Q2

DIM

COMP

CSH

R

CSH

4

C

FS

R

SNS

V_IN

R

T

R

FS

R

F

5

RT/SYNC

nDIM

V_CC

C

BYP

Q7

R

C

UVH

PU

F

6

15

14

13

12

11

GATE

GND

DDRV

OVP

V_S

Q1

R

OV2

DIM

R

C

SS

UV1

Q6

Q4

7

SS

C

B

D2

R

SER

R

GAIN

Q5

8

TGAIN

TSENSE

TREF

V_IN

9

DAP

R

C

OV1

OV

R

C

REF1

10

R

REF2

REF

R

BIAS

C

NTC

Q3

PWM

Figure 44. Buck-Boost Application

8.2.6.1 Design Requirements

•

Input: 10 V to 70 V

Output: 6 LEDs at 500 mA

PWM Dimming up to 10 kHz

5-s Fade-up

MOSFET R_DS-ONSensing

700-kHz Switching Frequency

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53

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LM3424-Q1

SNVSB96 –JULY 2019

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8.2.6.2 Detailed Design Procedure

Table 5. Bill of Materials

QTY

PART ID

LM3424

C_B

PART VALUE

MANUFACTURER

PART NUMBER

1

Boost controller

TI

LM3424MH

100 pF COG/NPO 5%

50V

MURATA

GRM2165C1H101JA01D

1

2

1

0

4

1

4

1

2

1

3

1

3

2

1

C_BYP

2.2 µF X7R 10% 16V

1 µF X7R 10% 25V

0.01 µF X7R 10% 25V

0.1 µF X7R 10% 25V

DNP

MURATA

GRM21BR71C225KA12L

GRM21BR71E105KA01L

GRM21BR71E103KA01L

GRM21BR71E104KA01L

C_CMP, C_SS

C_REF

C_F

C_FS

C_IN

4.7 µF X7R 10% 100V

10 µF X7R 10% 10V

10 µF X7R 10% 50V

TDK

C5750X7R2A475K

GRM21BR71A106KE51L

C4532X7R1H106K

08055A470JAT2A

12CWQ10FNPBF

BZX84C10LT1G

C_NTC

MURATA

TDK

C_OUT

C_OV

47 pF COG/NPO 5% 50V AVX

D1

Schottky 100V 12A

Zener 10V 500mA

68 µH 20% 4.3A

NMOS 100V 32A

NMOS 60V 260mA

PNP 40V 200mA

PNP 150V 600 mA

NPN 300V 600mA

NPN 40V 200mA

49.9 kΩ 1%

VISHAY

D2

ON-SEMI

COILCRAFT

FAIRCHILD

ON-SEMI

FAIRCHILD

VISHAY

L1

MSS1278-683MLB

FDD3682

Q1, Q2

Q3

2N7002ET1G

Q4

MMBT5087

Q5

MMBT5401

Q6

MMBTA42

Q7

MMBT6428

R_BIAS, R_REF1, R_REF2

CRCW080549K9FKEA

CRCW080512K4FKEA

CRCW08050000Z0EA

CRCW080510K0FKEA

CRCW08051K00FKEA

CRCW080515K8FKEA

CRCW0805499KFKEA

CRCW08054K99FKEA

CRCW0805499RFKEA

WSL2512R2000FEA

CRCW080524K3FKEA

CRCW08051K43FKEA

CRCW080517K4FKEA

R_CSH

12.4 kΩ 1%

VISHAY

R_FS

0Ω 1%

VISHAY

R_GAIN, R_T, R_UV2

R_HSP, R_HSN

R_OV1

10.0 kΩ 1%

VISHAY

1.0 kΩ 1%

VISHAY

15.8 kΩ 1%

VISHAY

R_OV2

499 kΩ 1%

VISHAY

R_PU

4.99 kΩ 1%

VISHAY

R_SER

499Ω 1%

VISHAY

R_SNS

0.2Ω 1% 1W

24.3 kΩ 1%

VISHAY

R_SLP

VISHAY

R_UV1

1.43 kΩ 1%

VISHAY

R_UVH

17.4 kΩ 1%

VISHAY

54

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8.2.7 Buck Application

15 V œ 50 V

V_IN

L1

C

IN

R

HSP

1

2

20

19

18

17

16

V_IN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

R

FS

SNS

R

HSN

R

UV2

EN

R

FS

C

O

R

CMP

SLP

3

COMP

CSH

R

D2

PU

R

CSH

4

R

OV2

Q2

1.25 A

I_LED

R

T

D1

5

RT/SYNC

nDIM

V_CC

L1

C

BYP

Q4

R

UVH

6

15

14

13

12

11

GATE

GND

DDRV

OVP

V_S

Q1

R

C

SS

UV1

C

DIM

7

R

LIM

SS

R

GAIN

8

TGAIN

TSENSE

TREF

9

DAP

R

C

OV1

OV

R

C

REF1

10

R

REF2

REF

R

BIAS

R

POT

C

NTC

Q3

PWM

Figure 45. Buck Application

8.2.7.1 Design Requirements

•

Input: 15 V to 50 V

Output: 3 LEDS AT 1.25 A

PWM Dimming up to 50 kHz

Analog Dimming

700-kHz Switching Frequency

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8.2.7.2 Detailed Design Procedure

Table 6. Bill of Materials

QTY

1

2

0

1

4

0

1

3

1

2

1

2

1

PART ID

LM3424

C_BYP

PART VALUE

MANUFACTURER

PART NUMBER

Boost controller

2.2 µF X7R 10% 16V

0.1 µF X7R 10% 25V

DNP

TI

LM3424MH

MURATA

GRM21BR71C225KA12L

GRM21BR71E104KA01L

C_CMP, C_DIM

C_FS

C_NTC

0.33 µF X7R 10% 25V

4.7 µF X7R 10% 100V

DNP

MURATA

TDK

GRM21BR71E334KA01L

C5750X7R2A475K

C_IN

C_OUT

C_OV

47 pF COG/NPO 5% 50V AVX

08055A470JAT2A

GRM21BR71E105KA01L

12CWQ10FNPBF

BZX84C10LT1G

C_REF, C_SS

D1

1 µF X7R 10% 25V

Schottky 100V 12A

Zener 10V 500mA

22 µH 20% 7.3A

NMOS 60V 8A

PMOS 30V 6.2A

NMOS 60V 115mA

PNP 150V 600 mA

49.9 kΩ 1%

MURATA

VISHAY

ON-SEMI

COILCRAFT

VISHAY

ON-SEMI

FAIRCHILD

VISHAY

BOURNS

VISHAY

D2

L1

MSS1278-223MLB

SI4436DY

Q1

Q2

SI3483DV

Q3

2N7002ET1G

Q4

MMBT5401

R_BIAS, R_REF1, R_REF2

R_CSH

CRCW080549K9FKEA

CRCW080512K4FKEA

CRCW08050000OZEA

CRCW080510K0FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080521K5FKEA

CRCW0805499KFKEA

3352P-1-503

12.4 kΩ 1%

R_FS

0Ω 1%

R_GAIN, R_T

R_HSP, R_HSN

R_LIM

10.0 kΩ 1%

1.0 kΩ 1%

0.04Ω 1% 1W

21.5 kΩ 1%

R_OV1

R_OV2

499 kΩ 1%

R_POT

50 kΩ potentiometer

100 kΩ 1%

R_PU, R_UV2

R_SLP

CRCW0805100KFKEA

CRCW080536K5FKEA

WSL2512R0800FEA

CRCW080511K5FKEA

36.5 kΩ 1%

R_SNS

0.08Ω 1% 1W

11.5 kΩ 1%

R_UV1

56

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8.2.8 Buck-Boost Application

15 V œ 60 V

V_IN

D1

L1

C

IN

R

HSP

1

2

20

19

18

17

16

V_IN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

OUT

R

HSN

2.5 A

I_LED

R

UV2

EN

C

R

CMP

SLP

3

COMP

CSH

R

CSH

4

R

T

C

FS

R

SNS

5

C

FLT

C

AC

RT/SYNC

nDIM

V_CC

V_IN

SYNC

C

BYP

R

FS

R

FLT

6

15

GATE

GND

DDRV

OVP

V_S

Q1

R

OV2

R

C

SS

UV1

7

14

13

12

11

R

LIM

SS

R

Q2

V_IN

GAIN

8

TGAIN

TSENSE

TREF

9

DAP

R

C

OV1

OV

R

REF1

10

R

REF2

C

REF

R

BIAS

NTC

C

NTC

Figure 46. Buck-Boost Application

8.2.8.1 Design Requirements

•

Input: 15 V to 60 V

Output: 8 LEDs at 2.5 A

80°C to 110°C Thermal Foldback

500-kHz Switching Frequency

External Synchronization > 500 kHz

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8.2.8.2 Detailed Design Procedure

Table 7. Bill of Materials

QTY

PART ID

LM3424

PART VALUE

MANUFACTURER

PART NUMBER

1

2

Boost controller

TI

LM3424MH

C_AC, C_FLT

100 pF COG/NPO 5%

50V

MURATA

GRM2165C1H101JA01D

1

3

1

4

1

2

1

2

1

2

1

C_BYP

2.2 µF X7R 10% 16V

0.33 µF X7R 10% 25V

0.1 µF X7R 10% 25V

4.7 µF X7R 10% 100V

10 µF X7R 10% 50V

MURATA

TDK

GRM21BR71C225KA12L

GRM21BR71E334KA01L

GRM21BR71E104KA01L

C5750X7R2A475K

C_CMP, C_NTC, C_SS

C_FS

C_IN

C_OUT

TDK

C4532X7R1H106K

C_OV

47 pF COG/NPO 5% 50V AVX

08055A470JAT2A

C_REF

1 µF X7R 10% 25V

Schottky 100V 12A

22 µH 20% 7.2A

NMOS 100V 32A

PNP 150V 600 mA

11.5 kΩ 1%

MURATA

GRM21BR71E105KA01L

12CWQ10FNPBF

D1

VISHAY

COILCRAFT

FAIRCHILD

VISHAY

TDK

L1

MSS1278-223MLB

Q1

FDD3682

Q2

MMBT5401

R_BIAS

R_CSH, R_OV1

R_FS

CRCW080511K5FKEA

CRCW080512K4FKEA

CRCW080510R0FKEA

CRCW0805150RFKEA

CRCW08055K49FKEA

CRCW08051K00FKEA

WSL2512R0400FEA

CRCW080515K8FKEA

CRCW0805499KFKEA

CRCW080549K9FKEA

CRCW080520K5FKEA

CRCW080514K3FKEA

CRCW080513K7FKEA

CRCW0805150KFKEA

NTCG204H154J

12.4 kΩ 1%

10Ω 1%

R_FLT

150Ω 1%

R_GAIN

R_HSP, R_HSN

R_LIM, R_SNS

R_OV1

5.49 kΩ 1%

1.0 kΩ 1%

0.04Ω 1% 1W

15.8 kΩ 1%

R_OV2

499 kΩ 1%

R_REF1, R_REF2

R_SLP

49.9 kΩ 1%

20.5 kΩ 1%

R_T

14.3 kΩ 1%

R_UV1

13.7 kΩ 1%

R_UV2

150 kΩ 1%

NTC

Thermistor 100 kΩ 5%

58

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8.2.9 SEPIC Application

9 V œ 36 V

V_IN

D1

L1

C

IN

C

SEP

L2

R

HSP

1

2

20

19

18

17

16

V_IN

HSP

HSN

SLOPE

IS

LM3424-Q1

C

R

SNS

FS

R

HSN

R

UV2

EN

R

FS

C

R

CMP

SLP

3

COMP

CSH

R

CSH

4

750 mA

I_LED

R

T

C

OUT

5

RT/SYNC

nDIM

V_CC

C

BYP

R

UVH

6

15

14

13

12

11

GATE

GND

DDRV

OVP

V_S

Q1

R

C

SS

UV1

7

R

LIM

SS

R

GAIN

8

TGAIN

TSENSE

TREF

Q2

R

OV2

OV1

9

DAP

R

C

OV

R

C

REF1

10

R

REF2

REF

R

BIAS

NTC

C

NTC

Q3

PWM

Figure 47. SEPIC Application

8.2.9.1 Design Requirements

•

Input: 9 V to 36 V

Output: 5 LEDs at 750 mA

60°C to 120°C Thermal Foldback

PWM Dimming up to 30 kHz

500-kHz Switching Frequency

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8.2.9.2 Detailed Design Procedure

Table 8. Bill of Materials

QTY

1

3

0

4

1

2

1

2

1

2

1

PART ID

LM3424

C_BYP

PART VALUE

MANUFACTURER

PART NUMBER

Boost controller

2.2 µF X7R 10% 16V

0.47 µF X7R 10% 25V

DNP

TI

LM3424MH

MURATA

GRM21BR71C225KA12L

GRM21BR71E474KA01L

C_CMP, C_NTC, C_SS

C_FS

C_IN

4.7 µF X7R 10% 100V

10 µF X7R 10% 50V

1.0 µF X7R 10% 100V

47 pF COG/NPO 5% 50V

1 µF X7R 10% 25V

Schottky 60V 5A

68 µH 20% 4.3A

NMOS 60V 8A

NMOS 60V 115 mA

23.7 kΩ 1%

TDK

C5750X7R2A475K

C4532X7R1H106K

C4532X7R2A105K

08055A470JAT2A

C_OUT

TDK

C_SEP

TDK

C_OV

AVX

C_REF

MURATA

COMCHIP

COILCRAFT

VISHAY

ON-SEMI

VISHAY

TDK

GRM21BR71E105KA01L

CDBC560-G

D1

L1, L2

Q1, Q2

Q3

DO3340P-683

SI4436DY

2N7002ET1G

R_BIAS

R_CSH

CRCW080523K7FKEA

CRCW080512K4FKEA

CRCW08050000OZEA

CRCW08059K31FKEA

CRCW0805750RFKEA

WSL2512R0400FEA

CRCW080515K8FKEA

CRCW0805499KFKEA

CRCW080549K9FKEA

CRCW080520K0FKEA

WSL2512R1000FEA

CRCW080514K3FKEA

CRCW08051K62FKEA

CRCW080510K0FKEA

CRCW080516K9FKEA

NTCG204H154J

12.4 kΩ 1%

R_FS

0Ω 1%

R_GAIN

R_HSP, R_HSN

R_LIM

9.31 kΩ 1%

750Ω 1%

0.04Ω 1% 1W

15.8 kΩ 1%

R_OV1

R_OV2

499 kΩ 1%

R_REF1, R_REF2

R_SLP

49.9 kΩ 1%

20.0 kΩ 1%

R_SNS

0.1Ω 1% 1W

R_T

14.3 kΩ 1%

R_UV1

1.62 kΩ 1%

R_UV2

10.0 kΩ 1%

R_UVH

16.9 kΩ 1%

NTC

Thermistor 100 kΩ 5%

60

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9 Power Supply Recommendations

9.1 Input Supply Current Limit

It is important to set the output current limit of your input supply to an appropriate value to avoid delays in your

converter analysis and optimization. If not set high enough, current limit can be tripped during start up or when

your converter output power is increased, causing a foldback or shut-down condition. It is a common oversight

when powering up a converter for the first time.

10 Layout

10.1 Layout Guidelines

The performance of any switching regulator depends as much upon the layout of the PCB as the component

selection. Following a few simple guidelines will maximimize noise rejection and minimize the generation of EMI

within the circuit.

Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing these

paths. The main path for discontinuous current in the LM3424-Q1 buck regulator contains the input capacitor

(C_IN), the recirculating diode (D1), the N-channel MOSFET (Q1), and the sense resistor (R_LIM). In the LM3424-Q1

boost regulator, the discontinuous current flows through the output capacitor (C_O), D1, Q1, and R_LIM. In the buck-

boost regulator both loops are discontinuous and should be carefully laid out. These loops should be kept as

small as possible and the connections between all the components should be short and thick to minimize

parasitic inductance. In particular, the switch node (where L1, D1, and Q1 connect) should be just large enough

to connect the components. To minimize excessive heating, large copper pours can be placed adjacent to the

short current path of the switch node.

The RT, COMP, CSH, IS, TSENSE, TREF, HSP, and HSN pins are all high-impedance inputs which couple

external noise easily, therefore the loops containing these nodes should be minimized whenever possible.

In some applications the LED or LED array can be far away (several inches or more) from the LM3424-Q1, or on

a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or

separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce the

effects of parasitic inductance on the AC impedance of the capacitor.

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10.2 Layout Example

Note critical paths and component placement:

Minimize power loop containing discontinuous currents

Minimize signal current loops (components close to IC)

ñ

Ground plane under IC for signal routing helps minimize noise coupling

discontinuous switching frequency currents

V_IN

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

Input

Power

VIN

LM3424-Q1

HSP

HSN

SLOPE

IS

GND

EN

COMP

CSH

I_LED

RT/SYNC

nDIM

SS

VCC

GATE

GND

DDRV

OVP

VS

PWM

TGAIN

TSENSE

TREF

TEMP

DAP

STAR GROUND

10

Power Ground

Figure 48. Layout Recommendation

62

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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MECHANICAL DATA

PWP0020A

MXA20A (Rev C)

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM3424QMHX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	用于驱动 LED、具有热折返功能的汽车类恒流 N 沟道控制器 \| PWP \| 20 \| -40 to 125 驱动控制器光电二极管接口集成电路
文件：	总67页 (文件大小：1559K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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