LM3475MF/NOPB [TI]
10V、滞后 PFET 降压控制器 | DBV | 5 | -40 to 125;
| 型号： | LM3475MF/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10V、滞后 PFET 降压控制器 | DBV | 5 | -40 to 125 控制器 开关 光电二极管 |
| 文件： | 总26页 (文件大小：905K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM3475
SNVS239C –OCTOBER 2004–REVISED OCTOBER 2015
LM3475 Hysteretic PFET Buck Controller
1 Features
3 Description
The LM3475 is a hysteretic P-FET buck controller
1
•
•
•
•
Easy-to-Use Control Methodology
0.8 V to VIN Adjustable Output Range
High Efficiency (90% Typical)
designed to support a wide range of high efficiency
applications in a very small SOT-23-5 package. The
hysteretic control scheme has several advantages,
including simple system design with no external
compensation, stable operation with a wide range of
components, and extremely fast transient response.
Hysteretic control also provides high efficiency
operation, even at light loads. The PFET architecture
allows for low component count as well as 100% duty
cycle and ultra-low dropout operation.
±0.9% (±1.5% Over Temperature) Feedback
Voltage
•
•
•
•
100% Duty Cycle Capable
Maximum Operating Frequency up to 2 MHz
Internal Soft-Start
Enable Pin
Device Information(1)
2 Applications
PART NUMBER
LM3475
PACKAGE
BODY SIZE (NOM)
•
•
•
•
•
•
•
TFT Monitor
SOT-23 (5)
1.60 mm × 2.90 mm
Auto PC
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Vehicle Security
Navigation Systems
Notebook Standby Supply
Battery Powered Portable Applications
Distributed Power Systems
Typical Application
[1
10 mH
v1
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V
= 5V
IN
V
OUT
= 2.5V/2A
C
OUT
C
IN
100 mF
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3475
SNVS239C –OCTOBER 2004–REVISED OCTOBER 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
Power Supply Recommendations...................... 16
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Ratings ........................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1 Device Support...................................................... 18
11.2 Community Resources.......................................... 18
11.3 Trademarks........................................................... 18
11.4 Electrostatic Discharge Caution............................ 18
11.5 Glossary................................................................ 18
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2013) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision A (March 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format. ........................................................................................................... 1
2
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SNVS239C –OCTOBER 2004–REVISED OCTOBER 2015
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
5
1
FB
PGATE
2
GND
3
4
9b
VIN
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
1
FB
I
Feedback input. Connect to a resistor divider between the output and GND.
Ground.
GND
2
G
Enable. Pull this pin above 1.5 V (typical) for normal operation. When EN is low, the device
enters shutdown mode.
EN
3
O
VIN
4
5
P
Power supply input.
PGATE
O
Gate drive output for the external PFET.
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6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
See
MIN
−0.3
−0.3
−0.3
−0.3
MAX
16
UNIT
V
VIN
PGATE
FB
16
V
5
V
EN
16
V
(3)
Power dissipation
440
215
220
1150
mW
Vapor phase (60 s)
Infrared (15 s)
Lead temperature
°C
°C
Tstg
Storage temperature
−65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal
resistance, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PD_MAX = (TJ_MAX - TA)/θJA. The maximum power dissipation of 0.44 W is determined using TA = 25°C, θJA = 225°C/W, and
TJ_MAX = 125°C.
6.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Ratings
MIN
2.7
NOM
MAX
10
UNIT
V
Supply voltage
TJ
Operating junction temperature
-40
125
°C
6.4 Thermal Information
LM3475
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
164.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
115.3
27.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
12.8
ψJB
26.5
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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6.5 Electrical Characteristics
Typical limits are for TJ = 25°C, unless otherwise specified, VIN = EN = 5.0 V. Maximum and minimum specification limits are
specified by design, test, or statistical analysis.
PARAMETER
TEST CONDITIONS
MIN
170
4
TYP
MAX
UNIT
IQ
Quiescent current
EN = VIN (PGATE
TJ = 25°C
260
Open)
TJ = −40°C to +125°C
TJ = 25°C
320
µA
EN = 0V
7
TJ = −40°C to +125°C
10
VFB
TJ = 25°C
0.8
Feedback voltage
V
TJ = −40°C to +125°C
0.788
0.812
%ΔVFB/ΔVIN Feedback voltage line
2.7 V < VIN < 10 V
0.01
%/V
regulation
VHYST
Comparator hysteresis 2.7 V < VIN < 10 V
TJ = 25°C
21
21
50
28
32
mV
nA
−40°C to +125°C
IFB
FB bias current
TJ = 25°C
−40°C to +125°C
Increasing
600
1.8
Enable threshold
voltage
TJ = 25°C
1.5
V
VthEN
−40°C to +125°C
1.2
Hysteresis
365
mV
µA
IEN
Enable leakage current
TJ = 25°C
0.025
EN = 10 V
−40°C to +125°C
1
Source
ISOURCE = 100 mA
2.8
1.8
RPGATE
Driver resistance
Ω
Sink
ISink = 100 mA
Source
VPGATE = 3.5 V
CPGATE = 1 nF
0.475
1.0
IPGATE
Driver output current
A
Sink
VPGATE = 3.5 V
CPGATE = 1 nF
TSS
Soft-start time
2.7 V < VIN < 10 V (EN Rising)
PGATE Open
4
180
ms
ns
TONMIN
VUVD
Minimum on-time
Undervoltage detection Measured at the FB
Pin
TJ = 25°C
0.56
V
−40°C to +125°C
0.487
0.613
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6.6 Typical Characteristics
Unless specified otherwise, all curves taken at VIN = 5 V, VOUT = 2.5 V, L = 10 µH, COUT = 100 µF, ESR = 100 mΩ, and TA =
25°C.
Figure 1. Quiescent Current vs Input Voltage
Figure 2. Feedback Voltage vs Temperature
Figure 3. Hysteresis Voltage vs Input Voltage
Figure 4. Hysteresis Voltage vs Temperature
98
100
96
94
80
60
40
20
92
90
88
86
84
0
4
5
6
7
8
9
10
0.5
1
1.5
2
OUTPUT CURRENT (A)
INPUT VOLTAGE (V
)
IN
IOUT = 2 A
Figure 5. Efficiency vs Load Current
Figure 6. Efficiency vs Input Voltage
6
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Typical Characteristics (continued)
Unless specified otherwise, all curves taken at VIN = 5 V, VOUT = 2.5 V, L = 10 µH, COUT = 100 µF, ESR = 100 mΩ, and TA =
25°C.
1 ms/DIV
2 ms/DIV
Figure 7. Start Up
Figure 8. Output Ripple Voltage
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7 Detailed Description
7.1 Overview
The LM3475 is a buck (step-down) DC-DC controller that uses a hysteretic control architecture, which results in
Pulse Frequency Modulated (PFM) regulation. The hysteretic control scheme does not utilize an internal
oscillator. Switching frequency depends on external components and operating conditions. Operating frequency
decreases at light loads, resulting in excellent efficiency compared to PWM architectures. Because switching is
directly controlled by the output conditions, hysteretic control provides exceptional load transient response.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Hysteretic Control Circuit
The LM3475 uses a comparator-based voltage control loop. The voltage on the feedback pin is compared to a
0.8V reference with 21mV of hysteresis. When the FB input to the comparator falls below the reference voltage,
the output of the comparator goes low. This results in the driver output, PGATE, pulling the gate of the PFET low
and turning on the PFET.
With the PFET on, the input supply charges COUT and supplies current to the load through the PFET and the
inductor. Current through the inductor ramps up linearly, and the output voltage increases. As the FB voltage
reaches the upper threshold (reference voltage plus hysteresis) the output of the comparator goes high, and the
PGATE turns the PFET off. When the PFET turns off, the catch diode turns on, and the current through the
inductor ramps down. As the output voltage falls below the reference voltage, the cycle repeats. The resulting
output, inductor current, and switch node waveforms are shown in Figure 9.
8
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Feature Description (continued)
V
IN
t
t
OFF
ON
-V
D
Switch Voltage
Inductor Current
I
out
DI
L
t
d
V
V
OUT
OUT
V
HYST
ripple
(DC)
t
d
Output Voltage
Figure 9. Hysteretic Waveforms
7.3.2 Soft-Start
The LM3475 includes an internal soft-start function to protect components from excessive inrush current and
output voltage overshoot. As VIN rises above 2.7 V (typical), the internal bias circuitry becomes active. When EN
goes high, the device enters soft-start. During soft-start, the reference voltage is ramped up to the nominal value
of 0.8 V in approximately 4ms. Duty cycle and output voltage will increase as the reference voltage is ramped up.
7.3.3 Under Voltage Detection
When the output voltage falls below 70% (typical) of the normal voltage, as measured at the FB pin, the device
turns off PFET and restarts a new soft-start cycle. In short circuit, the PFET is always on, and the converter is
effectively a resistor divider from input to output to ground. Whether the part restarts depends on the power path
resistance and the short circuit resistance. This feature should not be considered as overcurrent protection or
output short circuit protection.
7.3.4 PGATE
During switching, the PGATE pin swings from VIN (off) to ground (on). As input voltage increases, the time it
takes to slew the gate of the PFET on and off also increases. Also, as the PFET gate voltage approaches VIN,
the PGATE current driving capability decreases. This can cause a significant additional delay in turning the
switch off when using a PFET with a low threshold voltage. These two effects will increase power dissipation and
reduce efficiency. Therefore, a PFET with relatively high threshold voltage and low gate capacitance is
recommended.
7.3.5 Minimum On or Off Time
To ensure accurate comparator switching, the LM3475 imposes a blanking time after each comparator state
change. This blanking time is 180 ns typically. Immediately after the comparator goes high or low, it will be held
in that state for the duration of the blanking time. This helps keep the hysteretic comparator from improperly
responding to switching noise spikes (See Reducing Switching Noise) and ESL spikes (See Output Capacitor
Selection) at the output.
At very low or very high duty cycle operation, maximum frequency will be limited by the blanking time. The
maximum operating frequency can be determined by the following equations:
FMAX = D / tonmin
(1)
FMAX = (1-D) / toffmin
where
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Feature Description (continued)
•
•
D is the duty cycle, defined as VOUT/VIN, and tonmin
toffmin is the sum of the blanking time, the propagation delay time, and the PFET delay time (see Figure 9) (2)
7.3.6 Enable Pin (EN)
The LM3475 provides a shutdown function via the EN pin to disable the device. The device is active when the
EN pin is pulled above 1.5 V (typ) and in shutdown mode when EN is below 1.135 V (typ). In shutdown mode,
total quiescent current is less than 10 µA. The EN pin can be directly connected to VIN for always-on operation.
7.4 Device Functional Modes
The LM3475 operates in discontinuous conduction mode at light load current and continuous conduction mode at
heavy load current. In discontinuous conduction mode, current through the inductor starts at zero and ramps up
to the peak, then ramps down to zero. The next cycle starts when the FB voltage reaches the reference voltage.
Until then, the inductor current remains zero. Operating frequency is low, as are switching losses. In continuous
conduction mode, current always flows through the inductor and never ramps down to zero.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM3475 employs a hysteretic control architecture; which provides excellent load transient response and
efficiency even at light loads, as compared to its PWM architectures. No external compensation is required which
results in a simple design and low component count. A typical schematic is described in the next section.
8.2 Typical Application
[1
10 mH
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V
= 5V
IN
V
OUT
= 2.5V/2A
C
OUT
C
IN
100 mF
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10 mF
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Figure 10. Full Demo Board Schematic
8.2.1 Design Requirements
To properly size the components for the application, the designer needs the following parameters: input voltage
range, output voltage, output current range, and required switching frequency. These four main parameters affect
the choices of component available to achieve a proper system behavior. Although hysteretic control is a simple
control scheme, the operating frequency and other performance characteristics depend on external conditions
and components. If the inductance, output capacitance, ESR, VIN, or Cff is changed, there will be a change in
the operating frequency and possibly output ripple. Therefore, care must be taken to select components which
will provide the desired operating range.
8.2.2 Detailed Design Procedure
Table 1. Bill of Materials
DESIGNATOR
DESCRIPTION
10 µF, 16 V, X5R
100 µF, 6 V, Ta
1 nF, 25 V, X7R
Schottky, 20 V, 2 A
10 µH, 3.1 A
PART NUMBER
EMK325BJ106MN
TPSY107M006R0100
VJ1206Y102KXXA
CMSH2-20L
VENDOR
TAIYO YUDEN
AVX
CIN
COUT
CFF
D1
Vishay
Central Semiconductor
Sumida
L1
CDRH103R100
Si2343
Q1
30 V, 2.5 A
Vishay
RFB2
RFB1
1 kΩ, 0805, 1%
2.15 kΩ, 0805, 1%
CRW08051001F
CRCW08052151F
Vishay
Vishay
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8.2.2.1 Setting Output Voltage
The output voltage is programmed using a resistor divider between VOUT and GND as shown in Figure 11. The
feedback resistors can be calculated as follows:
R1 + R2
x VFB
VOUT
=
R2
where
•
Vfb is 0.8 V typically
(3)
The feedback resistor ratio, α = (R1+R2) / R2, will also be used below to calculate output ripple and operating
frequency.
PGATE
V
OUT
L
PMOS_drv
+
C
OUT
C
ff
R1
FB
+
-
R2
Hyst Comp
+
-
Reference
Voltage
V
= 21 mV
= 0.8V
HYST
V
FB
PGATE
Figure 11. Hysteretic Window
8.2.2.2 Setting Operating Frequency and Output Ripple
Although hysteretic control is a simple control scheme, the operating frequency and other performance
characteristics depend on external conditions and components. If the inductance, output capacitance, ESR, VIN,
or Cff is changed, there will be a change in the operating frequency and possibly output ripple. Therefore, care
must be taken to select components which will provide the desired operating range. The best approach is to
determine what operating frequency is desirable in the application and then begin with the selection of the
inductor and output capacitor ESR. The design process usually involves a few iterations to select appropriate
standard values that will result in the desired frequency and ripple.
Without the feedforward capacitor (Cff), the operating frequency (F) can be approximately calculated using the
formula:
(VIN - VOUT) x ESR
VOUT
VIN
x
F =
(VHYST x a x L) + (VIN x delay x ESR)
where
•
•
Delay is the sum of the LM3475 propagation delay time and the PFET delay time
The propagation delay is 90ns typically
(4)
(5)
Minimum output ripple voltage can be determined using the following equation:
VOUT_PP = VHYST ( R1 + R2 ) / R2
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8.2.2.3 Using a Feed-forward Capacitor
The operating frequency and output ripple voltage can also be significantly influenced using a speed up
capacitor, Cff, as shown in Figure 11. Cff is connected in parallel with the high side feedback resistor, R1. The
output ripple causes a current to be sourced or sunk through this capacitor. This current is essentially a square
wave. Since the input to the feedback pin (FB) is a high impedance node, the bulk of the current flows through
R2. This superimposes a square wave ripple voltage on the FB node. The end result is a reduction in output
ripple and an increase in operating frequency. When adding Cff, calculate the formula above with α= 1. The value
of Cff depends on the desired operating frequency and the value of R2. A good starting point is 1nF ceramic at
100kHz decreasing linearly with increased operating frequency. Also note that as the output voltage is
programmed below 1.6V, the effect of Cff will decrease significantly.
8.2.2.4 Inductor Selection
The most important parameters for the inductor are the inductance and the current rating. The LM3475 operates
over a wide frequency range and can use a wide range of inductance values. Minimum inductance can be
calculated using the following equation:
VIN - VSD - VOUT
D
x
L =
F
DI
where
•
•
D is the duty cycle, defined as VOUT/VIN
ΔI is the allowable inductor ripple current
(6)
Maximum allowable inductor ripple current should be calculated as a function of output current (IOUT) as shown
below:
ΔImax = IOUT x 0.3
The inductor must also be rated to handle the peak current (IPK) and RMS current given by:
IPK = (IOUT + ΔI/2) x 1.1
(7)
(8)
DI2
2
IRMS
=
IOUT
+
3
The inductance value and the resulting ripple is one of the key parameters controlling operating frequency.
8.2.2.5 Output Capacitor Selection
Once the desired operating frequency and inductance value are selected, ESR must be selected based on
Equation 4. This process may involve a few iterations to select standard ESR and inductance values.
In general, the ESR of the output capacitor and the inductor ripple current create the output ripple of the
regulator. However, the comparator hysteresis sets the first order value of this ripple. Therefore, as ESR and
ripple current vary, operating frequency must also vary to keep the output ripple voltage regulated. The hysteretic
control topology is well suited to using ceramic output capacitors. However, ceramic capacitors have a very low
ESR, resulting in a 90° phase shift of the output voltage ripple. This results in low operating frequency and
increased output ripple. To fix this problem a low value resistor could be added in series with the ceramic output
capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance
provide highly accurate control over the output voltage ripple. Another method is to add an external ramp at the
FB pin as shown in Figure 12. By proper selection of R1 and C2, the FB pin sees faster voltage change than the
output ripple can cause. As a result, the switching frequency is higher while the output ripple becomes lower. The
switching frequency is approximately:
VIN
F =
2p x R1 x C2 x VHYS
(9)
Other types of capacitor, such as Sanyo POSCAP, OS-CON, and Nichicon ’NA’ series are also recommended
and may be used without additional series resistance. For all practical purposes, any type of output capacitor
may be used with proper circuit verification.
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Capacitors with high ESL (equivalent series inductance) values should not be used. As shown in Figure 9, the
output ripple voltage contains a small step at both the high and low peaks. This step is caused by and is directly
proportional to the output capacitor’s ESL. A large ESL, such as in an electrolytic capacitor, can create a step
large enough to cause abnormal switching behavior.
8.2.2.6 Input Capacitor Selection
A bypass capacitor is required between VIN and ground. It must be placed near the source of the external PFET.
The input capacitor prevents large voltage transients at the input and provides the instantaneous current when
the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current
rating. Follow the manufacturer’s recommended voltage de-rating. RMS current and power dissipation (PD) can
be calculated with the equations below:
IOUT
VOUT x (VIN - VOUT
)
IRMS_CIN
=
VIN
(10)
[1
10 mH
v1
{i2343
V
IN
V
OUT
= 0.9V/2A
C
OUT
C
IN
10 mF
100 mF
51
ꢀ
w1
200k
tD!Ç9
R
FB1
4
2
1
V
Db5
IN
1.27k
/1
3ꢂꢁ nC
[a3475
3
9b
C.
R
FB2
/2
3ꢁ0 pC
10k
Figure 12. External Ramp
8.2.2.7 Diode Selection
The catch diode provides the current path to the load during the PFET off time. Therefore, the current rating of
the diode must be higher than the average current through the diode, which be calculated as shown:
ID_AVE = IOUT x (1 − D)
(11)
The peak voltage across the catch diode is approximately equal to the input voltage. Therefore, the diode’s peak
reverse voltage rating should be greater than 1.3 times the input voltage.
A Schottky diode is recommended, since a low forward voltage drop will improve efficiency.
For high temperature applications, diode leakage current may become significant and require a higher reverse
voltage rating to achieve acceptable performance.
8.2.2.8 P-Channel MOSFET Selection
The PFET switch should be selected based on the maximum Drain-Source voltage (VDS), Drain current rating
(ID), maximum Gate-Source voltage (VGS), on resistance (RDSON), and Gate capacitance. The voltage across the
PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must
be selected to provide some margin beyond the sum of the input voltage and Vd.
Since the current flowing through the PFET is equal to the current through the inductor, ID must be rated higher
than the maximum IPK. During switching, PGATE swings the PFET’s gate from VIN to ground. Therefore, A PFET
must be selected with a maximum VGS larger than VIN. To insure that the PFET turns on completely and quickly,
refer to the PGATE section.
14
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The power loss in the PFET consists of switching losses and conducting losses. Although switching losses are
difficult to precisely calculate, the equation below can be used to estimate total power dissipation. Increasing
RDSON will increase power losses and degrade efficiency. Note that switching losses will also increase with lower
gate threshold voltages.
PDswitch = RDSONx (IOUT)2x D + F x IOUTx VINx (ton + toff)/2
where
•
•
•
ton = FET turn on time
toff = FET turn off time
A value of 10ns to 50ns is typical for ton and toff
(12)
Note that the RDSON has a positive temperature coefficient. At 100°C, the RDSON may be as much as 150% higher
than the value at 25°C.
The Gate capacitance of the PFET has a direct impact on both PFET transition time and the power dissipation in
the LM3475. Most of the power dissipated in the LM3475 is used to drive the PFET switch. This power can be
calculated as follows:
The amount of average gate driver current required during switching (IG) is:
IG = Qg x F
(13)
And the total power dissipated in the device is:
IqVIN + IGVIN
where
•
Iq is typically 260µA as shown in Electrical Characteristics
(14)
As gate capacitance increases, operating frequency may need to be reduced, or additional heat sinking may be
required to lower the power dissipation in the device.
In general, keeping the gate capacitance below 2000 pF is recommended to keep transition times (switching
losses), and power losses low.
8.2.2.9 Reducing Switching Noise
Although the LM3475 employs internal noise suppression circuitry, external noise may continue to be excessive.
There are several methods available to reduce noise and EMI.
MOSFETs are very fast switching devices. The fast increase in PFET current coupled with parasitic trace
inductance can create unwanted noise spikes at both the switch node and at VIN. Switching noise will increase
with load current and input voltage. This noise can also propagate through the ground plane, sometimes causing
unpredictable device performance. Slowing the rise and fall times of the PFET can be very effective in reducing
this noise. Referring to Figure 13, the PFET can be slowed down by placing a small (1-Ω to 10-Ω) resistor in
series with PGATE. However, this resistor will increase the switching losses in the PFET and will lower efficiency.
Therefore it should be kept as small as possible and only used when necessary. Another method to reduce
switching noise (other than good PCB layout, see Layout) is to use a small RC filter or snubber. The snubber
should be placed in parallel with the catch diode, connected close to the drain of the PFET, as shown in
Figure 13. Again, the snubber should be kept as small as possible to limit its impact on system efficiency. A
typical range is a 10-Ω to 100-Ω resistor and a 470-pF to 2.2-nF ceramic capacitor.
RPGATE
v1
5
tD!Ç9
3.3W
CSNUB
[1
ꢀ1
RSNUB
Figure 13. PGATE Resistor and Snubber
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8.2.3 Application Curves
Figure 14. Load Transient Response with External Ramp
(Circuit from Figure 12)
Figure 15. Load Transient Response
(Typical Application Circuit from Figure 16)
9 Power Supply Recommendations
The LM3475 controller is designed to operate from various DC power supplies. VIN input should be protected
from reversal voltage and voltage dump over 16 volts. The impedance of the input supply rail should be low
enough that the input current transient does not cause drop below VIN UVLO level. If the input supply is
connected by using long wires, additional bulk capacitance may be required in addition to normal input capacitor.
10 Layout
10.1 Layout Guidelines
PC board layout is very important in all switching regulator designs. Poor layout can cause EMI problems, excess
switching noise and poor operation.
As shown in Figure 16, place the ground of the input capacitor as close as possible to the anode of the diode.
This path also carries a large AC current. The switch node, the node connecting the diode cathode, inductor, and
PFET drain, should be kept as small as possible. This node is one of the main sources for radiated EMI.
The feedback pin is a high impedance node and is therefore sensitive to noise. Be sure to keep all feedback
traces away from the inductor and the switch node, which are sources of noise. Also, the resistor divider should
be placed close to the FB pin. The gate pin of the external PFET should be located close to the PGATE pin.
TI also recommends using a large, continuous ground plane, particularly in higher current applications.
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10.2 Layout Example
GND
RFB2
RFB1
CFF
L1
0 Ω
Vout
EN
Vin
Figure 16. Layout Example (2:1 Scale)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM3475MF/NOPB
LM3475MFX/NOPB
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
1000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
S65B
S65B
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3475MF/NOPB
LM3475MFX/NOPB
SOT-23
SOT-23
DBV
DBV
5
5
1000
3000
178.0
178.0
8.4
8.4
3.2
3.2
3.2
3.2
1.4
1.4
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3475MF/NOPB
LM3475MFX/NOPB
SOT-23
SOT-23
DBV
DBV
5
5
1000
3000
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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