LM358LVIDR [TI]
双路、5.5V、1MHz 运算放大器 | D | 8 | -40 to 125;
| 型号： | LM358LVIDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、5.5V、1MHz 运算放大器 | D | 8 | -40 to 125 放大器 运算放大器 |
| 文件： | 总50页 (文件大小：3099K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM321LV, LM324LV, LM358LV
ZHCSI65E –SEPTEMBER 2018 –REVISED FEBRUARY 2022
LM321LV、LM358LV、LM324LV 行业标准低电压运算放大器
1 特性
3 说明
• 适用于成本敏感型系统的行业标准放大器
• 低输入失调电压：±1mV
• 共模电压范围包括接地
LM3xxLV 系列包括单路 LM321LV、双路 LM358LV 和
四路 LM324LV 运算放大器。这些器件由 2.7V 至 5.5V
的低电压供电。
• 单位增益带宽：1MHz
• 低宽带噪声：40nV/√Hz
在成本敏感型低压应用中，这些运算放大器可作为
LM321、LM358 和LM324 的替代产品。部分应用为大
型电器、烟雾探测器和个人电子产品。LM3xxLV 器件
在低电压下可提供比 LM3xx 器件更佳的性能，并且功
耗更低。这些运算放大器具有单位增益稳定性，并且在
过驱情况下不会出现相位反转。ESD 设计为 LM3xxLV
系列提供了至少2kV 的HBM 规格。
• 低静态电流：90µA/通道
• 单位增益稳定
• 可在2.7V 至5.5V 的电源电压范围内工作
• 提供单通道、双通道和四通道型号
• 严格的ESD 规格：2kV HBM
• 工作温度范围：–40°C 至125°C
LM3xxLV 系列采用行业标准封装。这些封装包括
SOT-23、SOIC、VSSOP 和TSSOP 封装。
2 应用
• 无线电器
• 不间断电源
• 电池组、充电器和测试设备
• 电源模块
• 环境传感器信号调节
• 现场变送器：温度传感器
• 示波器、数字万用表、测试设备
• 机架式服务器
• HVAC：暖通空调
• 直流电机控制
• 低侧电流感测
器件信息
器件型号(1)
LM321LV
封装尺寸（标称值）
1.60mm × 2.90mm
1.25mm × 2.00mm
3.91mm × 4.90mm
1.60mm × 2.90mm
3.00mm × 4.40mm
3.00mm × 3.00mm
8.65mm × 3.91mm
4.40mm × 5.00mm
4.20 mm × 2.00 mm
封装
SOT-23 (5)
SC70 (5)
SOIC (8)
SOT-23 (8)
TSSOP (8)
VSSOP (8)
SOIC (14)
TSSOP (14)
SOT-23 (14)
LM358LV
LM324LV
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
RF
RG
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
单极低通滤波器
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS944
LM321LV, LM324LV, LM358LV
ZHCSI65E –SEPTEMBER 2018 –REVISED FEBRUARY 2022
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内容
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 修订历史记录.....................................................................2
5 引脚配置和功能................................................................. 3
6 规格................................................................................... 6
6.1 绝对最大额定值...........................................................6
6.2 ESD 额定值.................................................................6
6.3 建议运行条件.............................................................. 6
6.4 热性能信息：LM321LV............................................... 7
6.5 热性能信息：LM358LV............................................... 7
6.6 热性能信息：LM324LV............................................... 7
6.7 电气特性......................................................................8
6.8 典型特性......................................................................9
7 详细说明.......................................................................... 14
7.1 概述...........................................................................14
7.2 功能方框图................................................................14
7.3 特性说明....................................................................14
7.4 器件功能模式............................................................ 15
8 应用和实现.......................................................................16
8.1 应用信息....................................................................16
8.2 典型应用....................................................................16
9 电源相关建议...................................................................18
9.1 输入和ESD 保护.......................................................18
10 布局............................................................................... 19
10.1 布局指南..................................................................19
10.2 布局示例..................................................................19
11 器件和文档支持..............................................................20
11.1 文档支持..................................................................20
11.2 接收文档更新通知................................................... 20
11.3 支持资源..................................................................20
11.4 商标.........................................................................20
11.5 Electrostatic Discharge Caution..............................20
11.6 术语表..................................................................... 20
12 机械、封装和可订购信息...............................................21
4 修订历史记录
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (September 2019) to Revision E (February 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 向器件信息表中添加了SOT-23 (DYY) 封装...................................................................................................... 1
• 向引脚配置和功能部分中添加了DYY (SOT-23) 信息.........................................................................................3
• 向热性能信息：LM324LV 表中添加了DYY (SOT-23)........................................................................................ 7
Changes from Revision C (May 2019) to Revision D (September 2019)
Page
• 删除了数据表中SOT-23 (DDF) 封装的全部预发布说明..................................................................................... 1
Changes from Revision B (February 2019) to Revision C (May 2019)
Page
• 向器件信息表中添加了SOT-23 (DDF) 封装...................................................................................................... 1
• 向引脚配置和功能部分中添加了DDF (SOT-23) 信息.........................................................................................3
• 向热性能信息：LM358LV 表中添加了DDF (SOT-23)........................................................................................ 7
Changes from Revision A (January 2019) to Revision B (February 2019)
Page
• 更改了LM321LVIDBV (SOT-23) 引脚图以匹配LM321LVIDCK (SC70) 引脚排列..............................................3
Changes from Revision * (September 2018) to Revision A (January 2019)
Page
• 将数据表标题从LM3xxLV... 更改为LM321LV、LM358LV、LM324LV... ...........................................................1
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5 引脚配置和功能
IN+
Vœ
1
2
3
5
V+
INœ
4
OUT
Not to scale
图5-1. LM321LV DBV 和DCK 封装
5 引脚SOT-23 和SC70
（顶视图）
表5-1. 引脚功能：LM321LV
引脚
I/O
说明
名称
编号
3
1
4
2
I
IN–
反相输入
IN+
I
同相输入
OUT
V–
V+
O
I 或—
I
输出
负（低）电源或接地（对于单电源供电）
正（高）电源
5
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OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
Not to scale
图5-2. LM358LV D、DGK、PW 和DDF 封装
8 引脚SOIC、VSSOP、TSSOP 和SOT-23
（顶视图）
表5-2. 引脚功能：LM358LV
引脚
I/O
说明
名称
编号
2
I
I
IN1–
IN1+
反相输入，通道1
同相输入，通道1
反相输入，通道2
同相输入，通道2
输出，通道1
3
6
5
1
7
4
8
I
IN2–
IN2+
OUT1
OUT2
V–
I
O
O
输出，通道2
I 或— 负（低）电源或接地（对于单电源供电）
V+
I
正（高）电源
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OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
OUT4
IN4œ
IN4+
Vœ
13
12
11
10
9
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
Not to scale
图5-3. LM324LV D、PW 和DYY 封装
14 引脚SOIC、TSSOP 和SOT-23
（顶视图）
表5-3. 引脚功能：LM324LV
引脚
I/O
说明
名称
编号
2
I
I
IN1–
IN1+
反相输入，通道1
同相输入，通道1
反相输入，通道2
同相输入，通道2
反相输入，通道3
同相输入，通道3
反相输入，通道4
同相输入，通道4
输出，通道1
3
6
I
IN2–
IN2+
IN3–
IN3+
IN4–
IN4+
OUT1
OUT2
OUT3
OUT4
V–
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
7
输出，通道2
8
输出，通道3
14
11
4
输出，通道4
I 或— 负（低）电源或接地（对于单电源供电）
V+
I
正（高）电源
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6 规格
6.1 绝对最大额定值
在工作结温范围内测得（除非另有说明）(1)
最小值
最大值
单位
0
6
V
电源电压，([V+] –[V–])
(V+) + 0.5
(V+) –(V–) + 0.2
10
V
V
(V–) –0.5
共模
差分
电压(2)
信号输入引脚
电流(2)
-10
-55
-65
mA
输出短路(3)
持续
150
150
150
°C
°C
°C
温度，TA
运行结温，TJ
贮存温度，Tstg
(1) 超出绝对最大额定值下所列的值的应力可能会对器件造成永久损坏。这些仅仅是压力额定值，并不表示器件在这些条件下以及在建议运
行条件以外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。
(2) 输入引脚被二极管钳制至电源轨。摆幅超过电源轨0.5V 的输入信号的电流必须限制在10mA 或者更少。
(3) 对地短路，每个封装对应一个放大器。
6.2 ESD 额定值
值
单位
人体放电模型(HBM)，符合ANSI/ESDA/JEDEC JS-001 标准(1)
充电器件模型(CDM)，符合JEDEC 规范JESD22-C101(2)
±2000
V(ESD)
V
静电放电
±1000
(1) JEDEC 文档JEP155 指出：500V HBM 时能够在标准ESD 控制流程下安全生产。
(2) JEDEC 文件JEP157 指出：250V CDM 可实现在标准ESD 控制流程下安全生产。
6.3 建议运行条件
在工作结温范围内测得（除非另有说明）
最小值
最大值
单位
VS
VIN
TA
2.7
5.5
V
电源电压[(V+) –(V–)]
输入引脚电压范围
额定温度
V
(V–) –0.1
(V+) –1
-40
125
°C
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6.4 热性能信息：LM321LV
LM321LV
热指标(1)
DBV (SOT-23)
5 引脚
232.9
DCK (SC70)
5 引脚
239.6
单位
RθJA
RθJC(top)
RθJB
ψJT
°C/W
°C/W
°C/W
°C/W
°C/W
结至环境热阻
153.8
148.5
结至外壳（顶部）热阻
结至电路板热阻
100.9
82.3
77.2
54.5
结至顶部特征参数
结至电路板特征参数
100.4
81.8
ψJB
(1) 有关新旧热指标的更多信息，请参阅半导体和IC 封装热指标。
6.5 热性能信息：LM358LV
LM358LV
热指标(1)
D (SOIC)
DGK (VSSOP)
PW (TSSOP)
DDF (SOT-23)
单位
8 引脚
8 引脚
8 引脚
8 引脚
RθJA
207.9
201.2
200.7
183.7
°C/W
°C/W
结至环境热阻
Rθ
92.8
85.7
95.4
112.5
结至外壳（顶部）热阻
JC(top)
RθJB
ψJT
129.7
26
122.9
21.2
128.6
27.2
98.2
18.8
97.6
°C/W
°C/W
°C/W
结至电路板热阻
结至顶部特征参数
结至电路板特征参数
127.9
121.4
127.2
ψJB
(1) 有关新旧热指标的更多信息，请参阅半导体和IC 封装热指标。
6.6 热性能信息：LM324LV
LM324LV
热指标(1)
D (SOIC)
PW (TSSOP)
14 引脚
148.3
DYY (SOT-23)
14 引脚
154.6
单位
14 引脚
102.1
56.8
RθJA
RθJC(top)
RθJB
ψJT
°C/W
°C/W
°C/W
°C/W
°C/W
结至环境热阻
68.1
86.3
结至外壳（顶部）热阻
结至电路板热阻
58.5
92.7
67.3
20.5
16.9
9.8
结至顶部特征参数
结至电路板特征参数
58.1
91.8
67.1
ψJB
(1) 有关新旧热指标的更多信息，请参阅半导体和IC 封装热指标。
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6.7 电气特性
在VS = (V+) –(V–) = 2.7V 至5.5V（±1.35V 至±2.75V）、TA = 25°C、RL = 10kΩ（连接至VS/2）并且VCM = VOUT = VS/2
条件下测得（除非另有说明）
参数
测试条件
最小值
典型值
最大值
单位
失调电压
VS = 5V
±1
±3
±5
VOS
mV
输入失调电压
OS 温漂
电源抑制比
VS = 5V，TA = –40°C 至125°C
TA = –40°C 至125°C
dVOS/dT
PSRR
±4
µV/°C
dB
V
80
100
VS = 2.7 V 至5.5V，VCM = (V–)
输入电压范围
VCM
V
(V–) –0.1
(V+) –1
共模电压范围
无相位反转
VS = 2.7V，(V–) –0.1V < VCM < (V+) –1V，
TA = –40°C 至125°C
84
92
CMRR
dB
共模抑制比
VS = 5.5V，(V–) –0.1V < VCM < (V+) –1V，
TA = –40°C 至125°C
63
输入偏置电流
IB
VS = 5V
±15
±5
pA
pA
输入偏置电流
输入失调电流
IOS
噪声
En
5.1
40
µVPP
输入电压噪声（峰峰值）
ƒ= 0.1Hz 至10Hz，VS = 5V
ƒ= 1kHz，VS = 5V
en
nV/√Hz
输入电压噪声密度
输入电容
CID
2
pF
pF
差分
共模
CIC
5.5
开环增益
110
125
VS = 2.7V，(V–) + 0.15V < VO < (V+) –0.15V，RL = 2kΩ
VS = 5.5V，(V–) + 0.15V < VO < (V+) –0.15V，RL = 2kΩ
AOL
dB
开环电压增益
频率响应
GBW
VS = 5V
1
75
1.5
4
MHz
°
增益带宽积
相位裕度
压摆率
VS = 5.5V，G = 1
φm
SR
VS = 5V
V/µs
精度达到0.1%，VS = 5V，2V 阶跃，G = 1，CL = 100pF
精度达到0.01%，VS = 5V，2V 阶跃，G = 1，CL = 100pF
VS = 5V，VIN × 增益> VS
tS
µs
µs
趋稳时间
5
tOR
1
过载恢复时间
VS = 5.5V，VCM = 2.5V，VO = 1VRMS，G = 1，f = 1kHz，
80kHz 测量BW
THD+N
0.005%
总谐波失真+ 噪声
输出
VOH
1
V
R
R
L ≥2kΩ，TA = –40°C 至125°C
L ≤10kΩ，TA = –40°C 至125°C
相对于正电源的电压输出摆幅
相对于负电源的电压输出摆幅
短路电流
VOL
ISC
ZO
40
±40
75
mV
mA
Ω
VS = 5.5V
VS = 5V，f = 1 MHz
1200
开环输出阻抗
电源
VS
2.7 (±1.35)
5.5 (±2.75)
150
V
额定电压范围
IO = 0mA，VS = 5.5 V
90
IQ
µA
每个放大器的静态电流
160
IO = 0mA，VS = 5.5V，TA = –40°C 至125°C
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6.8 典型特性
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ（连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得（除非另
有说明）
10
8
160
140
120
100
80
6
4
2
0
IB-
IB+
IOS
-2
-4
-6
-8
-10
60
40
20
VS = 5.5 V
VS = 2.5 V
0
-40
-20
0
20
40
60
80
100 120 140
-3 -2.5 -2 -1.5 -1 -0.5
0
Common-Mode Voltage (V)
0.5
1
1.5
2
2.5
3
Temperature (èC)
D008
D007
图6-2. 开环增益与温度间的关系
图6-1. IB 和IOS 与共模电压间的关系
100
80
60
40
20
0
120
160
140
120
100
80
100
80
60
40
20
0
60
40
Gain
Phase
20
-20
0
1k
10k
100k
Frequency (Hz)
1M
-3
-2
-1 0
Output Voltage (V)
1
2
3
D009
D010
CL = 10pF
图6-4. 开环电压增益与输出电压间的关系
图6-3. 开环增益和相位与频率间的关系
80
70
60
50
40
30
20
10
0
Gain = -1
Gain = 1
Gain = 10
Gain = 100
Gain = 1000
-10
-20
100
1k
10k 100k
Frequency (Hz)
1M
D011
CL = 10pF
图6-5. 闭环增益与频率间的关系
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6.8 典型特性
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ（连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得（除非另
有说明）
2
1.5
1
120
100
80
60
40
20
0
PSRR+
PSRR-
0.5
0
-40 èC
25 èC
85 èC
125 èC
-0.5
-1
-1.5
-2
-2.5
-3
0
5
10
15
20
25
30
Output Current (mA)
35
40
45
50
100
1k
10k
Frequency (Hz)
100k
1M
D012
D013
图6-6. 输出电压与输出电流间的关系（爪形）
图6-7. PSRR 与频率间的关系
120
100
80
60
40
20
0
120
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (èC)
D014
D015
图6-9. CMRR 与频率间的关系
VS=2.7 V 至5.5 V
图6-8. 直流PSRR 与温度间的关系
120
100
80
60
40
20
0
VS = 2.7 V
VS = 5.5 V
Time (1 s/div)
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D017
D016
图6-11. 0.1Hz 至10Hz 集成电压噪声
VCM = (V–) –0.1V 至(V+) –1.5V
图6-10. 直流CMRR 与温度间的关系
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6.8 典型特性
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ（连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得（除非另
有说明）
-50
140
120
100
80
-60
-70
60
-80
40
-90
20
RL = 2K
RL = 10K
-100
0
100
1k
Frequency (Hz)
10k
10
100
1k
Frequency (Hz)
10k
100k
D019
D018
VS = 5.5V
BW = 80kHz
VCM = 2.5V
G = 1
图6-12. 输入电压噪声频谱密度
VOUT = 0.5VRMS
图6-13. THD+N 与频率间的关系
0
100
90
80
70
60
G = +1, RL = 2 kW
G = +1, RL = 10 kW
G = -1, RL = 2 kW
G = -1, RL = 10 kW
-20
-40
-60
-80
-100
0.001
0.01
0.1
Amplitude (VRMS
1
2
2.5
3
3.5
4
Voltage Supply (V)
4.5
5
5.5
)
D020
D021
VS = 5.5V
BW = 80kHz
VCM = 2.5V
f = 1kHz
G = 1
图6-15. 静态电流与电源电压间的关系
图6-14. THD + N 与幅度间的关系
100
90
80
70
60
2000
1800
1600
1400
1200
1000
800
600
400
200
0
1k
10k
100k
Frequency (Hz)
1M
10M
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D023
D022
图6-17. 开环输出阻抗与频率间的关系
图6-16. 静态电流与温度间的关系
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6.8 典型特性
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ（连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得（除非另
有说明）
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
Overshoot (+)
Overshoot (–)
Overshoot (+)
Overshoot (–)
0
0
0
200
400 600
Capacitance Load (pF)
800
1000
0
200
400 600
Capacitance Load (pF)
800
1000
D024
D025
G = 1
VIN = 100mVpp
VIN = 100mVpp
G = –1
图6-18. 小信号过冲与容性负载间的关系
图6-19. 小信号过冲与容性负载间的关系
90
VOUT
VIN
80
70
60
50
40
30
20
10
0
Time (100 ms/div)
0
200
400 600
Capacitance Load (pF)
800
1000
D027
D026
G = 1
VIN = 6.5 VPP
图6-20. 相位裕度与容性负载间的关系
图6-21. 无相位反转
VOUT
VIN
VOUT
VIN
Time (20 ms/div)
Time (10 ms/div)
D028
D029
G = -10
VIN = 600 mVPP
G = 1
VIN = 100 mVPP
CL = 10pF
图6-22. 过载恢复
图6-23. 小信号阶跃响应
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6.8 典型特性(continued)
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ（连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得（除非另
有说明）
VOUT
VIN
Time (1 μs/div)
Time (10 ms/div)
D031
D030
G = 1
CL = 100pF
2V 阶跃
G = 1
VIN = 4 VPP
CL = 10pF
图6-25. 大信号稳定时间（负）
图6-24. 大信号阶跃响应
80
60
40
20
0
-20
-40
-60
-80
Sinking
Sourcing
-40
-20
0
20
40
60
80
100
120
Time (1 ms/div)
Temperature (èC)
D033
D032
图6-27. 短路电流与温度间的关系
G = 1
CL = 100pF
2V 阶跃
图6-26. 大信号稳定时间（正）
140
120
100
80
0
-20
-40
-60
-80
60
-100
-120
-140
40
20
0
10M
1k
10k
100k
Frequency (Hz)
1M
10M
100M
Frequency (Hz)
1G
10G
D036
D035
图6-29. 通道分离
图6-28. 以同相输入为基准的电磁干扰抑制比(EMIRR+) 与频率间的
关系
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7 详细说明
7.1 概述
LM3xxLV 系列低功耗运算放大器适用于成本优化型系统。这些器件的工作电压范围为 2.7V 至 5.5V，具有单位增
益稳定特性，并且适用于各种通用应用。输入共模电压范围包括负电源轨，并支持将 LM3xxLV 系列用于许多单电
源应用。
7.2 功能方框图
V+
Reference
Current
VIN+
VIN-
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V-
(Ground)
7.3 特性说明
7.3.1 工作电压
LM3xxLV 系列的运算放大器的额定工作电压范围是 2.7V 至 5.5V。此外，许多规格在 –40°C 至 125°C 的温度范
围内都适用。电气特性部分展示了随着工作电压或温度而显著变化的参数。
7.3.2 共模输入范围包括接地
LM3xxLV 系列的输入共模电压范围扩展到负电源轨，低于正电源轨不到1V，整个供电电压范围为2.7V 至5.5V。
该性能通过 P 沟道差分对实现，如功能方框图所示。此外，还并联了一个互补的N 沟道差分对，以消除前几代运
算放大器常见的相位反转问题。不过，N 沟道对并未针对运行进行优化，并且在其运行期间性能会显著下降。TI
建议将在输入端施加的任何电压限制为至少比正电源轨 (V+) 低 1V，以确保运算放大器符合电气特性部分中详述
的规格。
7.3.3 过载恢复
过载恢复定义为运算放大器输出从饱和状态恢复到线性状态所需的时间。当输出电压由于高输入电压或高增益而
超过额定输出电压摆幅时，运算放大器的输出器件进入饱和区。器件进入饱和区后，输出器件中的电荷载体需要
时间回到线性状态。当电荷载体回到线性状态时，器件开始以指定的压摆率进行转换。因此，传播延迟（过载情
况下）等于过载恢复时间与转换时间之和。LM3xxLV 系列的过载恢复时间通常为1µs。
7.3.4 电气过应力
设计人员经常会问到关于运算放大器耐受电气过应力的问题。这些问题往往侧重于器件输入，但是也可能涉及到
电源电压引脚。这些不同的引脚功能均具有由特定半导体制造工艺和连接到引脚的特定电路的电压击穿特性所决
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定的电应力限制。此外，这些电路均内置内部静电放电 (ESD) 保护功能，可在产品组装之前和组装过程中保护电
路不受意外ESD 事件的影响。
能够充分了解该基本 ESD 电路及其与电气过应力事件的关联性会有所帮助。图 7-1 展示了 LM3xxLV 中包含的
ESD 电路。ESD 保护电路中涉及多个导流二极管，这些二极管从输入引脚和输出引脚连接回内部供电线路，并且
它们均连接到运算放大器内部的吸收器件。该保护电路在电路正常工作时处于未激活状态。
V+
Power Supply
ESD Cell
+IN
+
œ
OUT
œ IN
Vœ
图7-1. 等效内部ESD 电路
7.3.5 EMI 易感性和输入滤波
德州仪器 (TI) 已经开发出在 10MHz 至 6GHz 扩展宽频谱范围内准确测量和量化运算放大器抗扰度的功能。图
6-28 图说明了 LM3xxLV 系列的 EMI 滤波器在很宽的频率范围内的性能。更多详细信息请参阅可从 www.ti.com
下载的运算放大器的EMI 抑制比。
7.4 器件功能模式
LM3xxLV 系列具有单功能模式。只要电源电压在2.7 V (±1.35 V) 与5.5V (±2.75V) 之间，这些器件就会启动。
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8 应用和实现
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 应用信息
LM3xxLV 器件是一系列低功耗、成本优化型运算放大器。这些器件的工作电压为 2.7V 至 5.5V，单位增益稳定，
适合广泛的通用应用。输入共模电压范围包括负电源轨，并支持将LM3xxLV 用于任何单电源应用。
8.2 典型应用
图8-1 展示了低侧电流感测应用中配置的LM3xxLV 器件。
VBUS
ILOAD
ZLOAD
5 V
+
VOUT
Þ
+
RSHUNT
VSHUNT
RF
0.1 Ω
255 kΩ
Þ
RG
7.5 kΩ
图8-1. 低侧电流感测应用中的LM3xxLV 器件
8.2.1 设计要求
此设计的设计要求如下：
• 负载电流：0A 至1A
• 输出电压：3.5V
• 最大分流电压：100mV
8.2.2 详细设计过程
方程式1 提供了图8-1 中的电路传递函数：
VOUT = ILOAD ìRSHUNT ìGain
(1)
负载电流 (ILOAD) 在分流电阻器 (RSHUNT) 上产生压降。负载电流设置为 0A 至 1A。为了在最大负载电流下保持分
流电压低于100mV，使用方程式2 展示了允许的最大分流电阻器。
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
根据方程式2 计算出的RSHUNT 为100mΩ。ILOAD 和RSHUNT 产生的电压降由LM3xxLV 器件放大，从而产生大约
0V 至3.5V 的输出电压。LM3xxLV 产生必要输出电压时所需的增益根据方程式3 算出：
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V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
使用方程式3 计算出的所需增益为 35 V/V，该值由电阻器RF 和RG 设置。方程式4 调整电阻器RF 和RG 的阻值
大小，从而将LM3xxLV 器件的增益设置为35V/V。
R
(
)
F
Gain = 1+
R
G
(4)
8.2.3 应用曲线
将RF 选为255kΩ以及将RG 选为7.5kΩ，可提供等同于35V/V 的组合。图8-2 展示了图8-1 中所示电路测得的
传递函数。请注意，增益只是反馈和增益电阻器的函数。通过改变电阻器的比率来调整该增益，实际电阻器阻值
由设计人员希望建立的阻抗水平决定。阻抗水平决定了电流消耗、杂散电容的影响以及其他一些行为。并不存在
适用于每个系统的最佳阻抗选择，您必须选择适合您的系统参数的阻抗。
3.5
3
2.5
2
1.5
1
0.5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ILOAD (A)
1
Outp
图8-2. 低侧电流感测传递函数
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9 电源相关建议
LM3xxLV 系列的额定工作电压范围为 2.7V 至 5.5V（±1.35V 至 ±2.75V）；多种规格适用于 –40°C 至 125°C 的
温度范围。电气特性部分介绍了可能会随工作电压或温度而显著变化的参数。
CAUTION
电源电压大于6V 可能对器件造成永久损坏；请参阅绝对最大额定值表。
将 0.1µF 旁路电容器置于电源引脚附近，以减少来自高噪声电源或高阻抗电源的耦合误差。有关旁路电容器放置
位置的详细信息，请参阅布局指南部分。
9.1 输入和ESD 保护
LM3xxLV 系列在所有引脚上均整合了内部 ESD 保护电路。对于输入和输出引脚，这种保护主要包括输入和电源
引脚之间连接的导流二极管。只要电流如节 6.1 表中所述不超过 10mA，这些 ESD 保护二极管就能提供电路内输
入过驱保护。图 9-1 展示了如何通过将串联输入电阻器添加到被驱动的输入端来限制输入电流。添加的电阻器会
增加放大器输入端的热噪声，在对噪声敏感的应用中，该值必须非常小。
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
图9-1. 输入电流保护
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10 布局
10.1 布局指南
为了使器件具有最佳运行性能，请使用良好的印刷电路板(PCB) 布局实践，包括：
• 噪声可以通过整个电路的电源引脚和运算放大器本身的电源引脚传入模拟电路。旁路电容用于通过为局部模拟
电路提供低阻抗电源，以降低耦合噪声。
– 在每个电源引脚和接地端之间接入低等效串联电阻(ESR) 0.1µF 陶瓷旁路电容，并尽量靠近器件放置。针
对单电源应用，V+ 与接地端之间可以接入单个旁路电容器。
• 将电路中模拟和数字部分单独接地是最简单和最有效的噪声抑制方法之一。多层PCB 上的一层或多层通常专
门用于作为接地平面。接地层有助于散热和降低电磁干扰(EMI) 噪声拾取。注意在物理上分离数字接地和模拟
接地。使用热特征或EMI 测量技术来确定大部分接地电流流向何处，并确保将该路径从敏感的模拟电路引开。
更多详细信息，请参阅电路板布局技巧应用手册。
• 为了减少寄生耦合，请让输入走线尽可能远离电源或输出走线。如果这些走线不能保持分开，则以90 度角穿
过敏感走线比平行于噪声走线来排布走线要好得多。
• 应尽可能靠近器件放置外部元件，如图10-2 所示。使RF 和RG 接近反相输入可最大限度地减小寄生电容。
• 尽可能缩短输入走线。切记，输入走线是电路中最敏感的部分。
• 考虑在关键走线周围设定驱动型低阻抗保护环。这样可显著减少附近不同电势下的走线所产生的泄漏电流。
• 为获得最佳性能，建议在组装PCB 板后进行清洗。
• 任何精密集成电路都可能因湿气渗入塑料封装中而出现性能变化。请遵循所有的PCB 水清洁流程，建议将
PCB 组装烘干，以去除清洗时渗入器件封装中的湿气。大多数情形下，清洗后在85°C 下低温烘干30 分钟即
可。
10.2 布局示例
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
图10-1. 原理图表示：
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
RG
VIN 1
GND
RG
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
图10-2. 布局示例
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: LM321LV LM324LV LM358LV
LM321LV, LM324LV, LM358LV
ZHCSI65E –SEPTEMBER 2018 –REVISED FEBRUARY 2022
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
• 德州仪器(TI)，运算放大器的EMI 抑制比应用报告
• 德州仪器(TI)，电路板布局技巧应用手册
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 商标
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
20
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Product Folder Links: LM321LV LM324LV LM358LV
LM321LV, LM324LV, LM358LV
ZHCSI65E –SEPTEMBER 2018 –REVISED FEBRUARY 2022
www.ti.com.cn
12 机械、封装和可订购信息
下述页面包含机械、封装和订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航面板。
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: LM321LV LM324LV LM358LV
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM321LVIDBVR
LM321LVIDCKR
LM324LVIDR
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
D
5
5
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1SPF
1DH
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
SN
NIPDAU
SOIC
14
14
14
8
LM324LV
LM324L
LM324LV
L58L
LM324LVIDYYR
LM324LVIPWR
LM358LVIDDFR
LM358LVIDGKR
LM358LVIDR
ACTIVE SOT-23-THIN
ACTIVE TSSOP
ACTIVE SOT-23-THIN
DYY
PW
DDF
DGK
D
NIPDAU
SN
NIPDAU
ACTIVE
ACTIVE
ACTIVE
VSSOP
SOIC
8
NIPDAUAG | SN
NIPDAU | SN
NIPDAU | SN
1PKX
8
L358LV
358LV
LM358LVIPWR
TSSOP
PW
8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2022
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM321LVIDBVR
LM321LVIDCKR
LM324LVIDR
SOT-23
SC70
DBV
DCK
D
5
5
3000
3000
2500
3000
180.0
178.0
330.0
330.0
8.4
9.0
3.2
2.4
6.5
4.8
3.2
2.5
9.0
3.6
1.4
1.2
2.1
1.6
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q3
SOIC
14
14
16.4
12.4
16.0
12.0
LM324LVIDYYR
SOT-23-
THIN
DYY
LM324LVIPWR
LM358LVIDDFR
TSSOP
PW
14
8
2000
3000
330.0
180.0
12.4
8.4
6.9
3.2
5.6
3.2
1.6
1.4
8.0
4.0
12.0
8.0
Q1
Q3
SOT-23-
THIN
DDF
LM358LVIDGKR
LM358LVIDGKR
LM358LVIDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
2500
2500
2500
2000
2000
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
5.3
5.3
6.4
7.0
7.0
3.4
3.4
5.2
3.6
3.6
1.4
1.4
2.1
1.6
1.6
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
LM358LVIPWR
LM358LVIPWR
TSSOP
TSSOP
PW
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM321LVIDBVR
LM321LVIDCKR
LM324LVIDR
SOT-23
SC70
DBV
DCK
D
5
5
3000
3000
2500
3000
2000
3000
2500
2500
2500
2000
2000
210.0
190.0
356.0
336.6
366.0
210.0
366.0
366.0
356.0
356.0
366.0
185.0
190.0
356.0
336.6
364.0
185.0
364.0
364.0
356.0
356.0
364.0
35.0
30.0
35.0
31.8
50.0
35.0
50.0
50.0
35.0
35.0
50.0
SOIC
14
14
14
8
LM324LVIDYYR
LM324LVIPWR
LM358LVIDDFR
LM358LVIDGKR
LM358LVIDGKR
LM358LVIDR
SOT-23-THIN
TSSOP
DYY
PW
DDF
DGK
DGK
D
SOT-23-THIN
VSSOP
VSSOP
SOIC
8
8
8
LM358LVIPWR
LM358LVIPWR
TSSOP
PW
PW
8
TSSOP
8
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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