LM3631YFFR_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

LM3631

SNVS834 –AUGUST 2014

LM3631 Complete LCD Backlight and Bias Power

1 Features

2 Applications

Mobile Device LCD Backlighting and Bias

1

•

Drives up to Two Strings with Maximum of Eight

LEDs in Series

3 Description

–

Integrated Backlight Boost with 29-V Maximum

Output Voltage

The LM3631 is a complete LCD backlight and bias

power solution for mobile devices. This one-chip

solution has an integrated high-efficiency backlight

LED driver and positive/negative bias supplies for

LCD drivers addressing the power requirements of

high-definition LCDs. Integrated solution allows small

solution size while still maintaining high performance.

–

Two Low-Side Constant-Current LED Drivers

with 25-mA Maximum Output Current

•

Backlight Efficiency Up to 90%

11-Bit Linear or Exponential Dimming with up to

17-Bit Output Resolution

Capable of driving up to 16 LEDs, the LM3631 is

ideal for small- to medium-size displays. Two

additional programmable LDO regulator outputs can

be used to power display controller, LCD gamma

reference, or any additional peripherals.

•

External PWM Input for CABC Backlight

Operation

•

LCD Bias Efficiency > 85%

Programmable Positive LCD bias, 4-V to 6-V,

100-mA Maximum Output Current

A high level of integration and programmability allows

the LM3631 to address a variety of applications

without the need for hardware changes. Voltage

levels, backlight configuration, and power sequences

are all configurable through I²C interface.

•

Programmable Negative LCD bias, –4-V to –6-V,

80-mA Maximum Output Current

Two Positive Programmable LDO Reference

Outputs

–

4-V to 6-V, 50-mA Maximum Output Current

Device Information⁽¹⁾

1.8-V to 3.3-V, 80-mA Maximum Output

Current

PART NUMBER

PACKAGE

BODY SIZE (MAX)

LM3631

DSBGA (24)

2.585 mm x 1.885 mm

•

2.7-V to 5-V Input Voltage Range

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Simplified Schematic

Backlight Efficiency, 2P6S

L_SW

D1

95

90

85

80

75

70

65

+

-

C_IN

Up to 8 LEDs / string

C_OUT

V_IN

SW

VOUT

LED1

VIN

BST_SW

L_BST

LED2

C2

C_IN

SDA

C_FLY

C1

SCL

LM3631

nRST

BST_OUT

CP_VNEG

LDO_OREF

LDO_VPOS

LDO_CONT

V_NEG(-5.4V)

LCD_EN

PWM

60

VIN 2.7V

VIN 3.7V

VIN 5.0V

V_OREF(+4.0V to +6.0V)

V_POS(+5.4V)

55

50

OTP_SEL

FLAG

V_CONT(+1.8V)

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D007

GND_BST_SW

AGND

GND_SW

PGND

C_VPOS

C_NEGC_BST

C_OREF

C_CONT

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Table of Contents

8.3 Features Description............................................... 20

8.4 Device Functional Modes........................................ 34

8.5 Programming........................................................... 36

8.6 Register Maps......................................................... 40

Application and Implementation ........................ 46

9.1 Application Information............................................ 46

9.2 Typical Application .................................................. 46

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 Handling Ratings ...................................................... 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information ................................................. 6

7.5 Electrical Characteristics .......................................... 6

7.6 I²C Timing Requirements (SDA, SCL) .................. 10

7.7 Typical Characteristics............................................ 11

Detailed Description ............................................ 17

8.1 Overview ................................................................. 17

8.2 Functional Block Diagram ....................................... 19

9

10 Power Supply Recommendations ..................... 49

11 Layout................................................................... 49

11.1 Layout Guidelines ................................................ 49

11.2 Layout Example ................................................... 50

12 Device and Documentation Support ................. 51

12.1 Device Support...................................................... 51

12.2 Trademarks........................................................... 51

12.3 Electrostatic Discharge Caution............................ 51

12.4 Glossary................................................................ 51

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 51

4 Revision History

DATE

REVISION

NOTES

August 2014

*

Initial release.

2

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

5 Device Comparison Table

Table 1. Register Default Values

I²C Address

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x16

Register

Read/Write

R/W

R

OTP_SEL Low

0x01

OTP_SEL High

0x01

Device Control

LED Brightness LSB

LED Brightness MSB

Faults

0x00

Faults and Power-Good

Backlight Configuration 1

Backlight Configuration 2

Backlight Configuration 3

Backlight Configuration 4

Backlight Configuration 5

LCD_Configuration 1

LCD_Configuration 2

LCD_Configuration 3

LCD_Configuration 4

LCD_Configuration 5

LCD_Configuration 6

LCD_Configuration 7

LCD_Configuration 8

LCD_Configuration 9

FLAG Configuration

Revision (6 LSB bits only)

0x00

0xCF

0x07

0xCF

0x27

0xC7

0x49

0xC6

0x49

0x03

0x1E

0x01

0x1E

0x14

0xDC

0x20

0x1A

0x1E

0x0F

0x60

0x20

0x1E

0x05

0x50

0x00

0x09

0x01

Values in bold are OTP configurable.

Submit Documentation Feedback

3

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

6 Pin Configuration and Functions

DSBGA

24 BUMPS

F4

E4

D4

C4

B4

A4

F3

E3

D3

C3

B3

A3

F2

E2

D2

C2

B2

A2

F1

E1

D1

C1

B1

A1

F1

E1

D1

C1

B1

A1

F2

E2

D2

C2

B2

A2

F3

E3

D3

C3

B3

A3

F4

E4

D4

C4

B4

A4

TOP VIEW

BOTTOM VIEW

Pin Functions

DESCRIPTION

NUMBER

NAME

CP_VNEG

C2

A1

A2

Negative LCD bias supply voltage. Can be left unconnected if charge pump is disabled.

Inverting charge pump flying capacitor negative pin. Can be left unconnected if charge pump is

disabled.

A3

A4

PGND

C1

Power ground connection for boost converters and charge pump.

Inverting charge pump flying capacitor positive pin. Can be left unconnected if charge pump is

disabled.

B1

B2

B3

B4

LDO_OREF

PWM

LDO_OREF output voltage. Can be left unconnected if LDO is disabled.

PWM input for brightness control. Must be connected to GND if not used.

Serial data connection for I²C-compatible interface. Must be pulled high to VDDIO if not used.

SDA

BST_OUT

LCD bias boost output voltage. Internally connected to the input of CP_VNEG, LDO_VPOS, and

LDO_OREF.

C1

C2

C3

C4

D1

D2

D3

D4

E1

E2

E3

E4

F1

F2

F3

F4

LDO_VPOS

LDO_CONT

SCL

Positive LCD bias supply rail. Can be left unconnected if LDO is disabled.

Positive supply voltage for display panel controller. Can be left unconnected if disabled.

Serial clock connection for I²C-compatible interface. Must be pulled high to VDDIO if not used.

LCD bias boost switch pin.

BST_SW

AGND

Analog ground connection for control circuitry.

OTP_SEL

FLAG

Default setting selection. Must be tied to GND or to VDDIO.

Programmable interrupt flag. Open drain output. Can be left unconnected if not used.

LCD bias boost and inverting charge pump ground connection.

Input pin to internal LED current sink 2. Can be left unconnected if not used.

LCD enable input. Logic high turns on LCD bias voltages and backlight per sequencing settings.

Active low reset input.

GND_BST_SW

LED2

LCD_EN

nRST

VIN

Input voltage connection. Connect to 2.7-V to 5-V supply voltage.

Input pin to internal LED current sink 1. Can be left unconnected if not used.

Backlight boost output voltage. Output capacitor is connected to this pin.

Backlight boost switch pin.

LED1

VOUT

SW

GND_SW

Backlight boost ground connection.

4

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

–0.3

–7.0

–0.3

MAX

UNIT

Voltage on VIN, nRST, LCD_EN, PWM, SCL, SDA, FLAG, LDO_CONT, OTP_SEL

Voltage on BST_SW, BST_OUT, LDO_VPOS, LDO_OREF, C1

Voltage on CP_VNEG, C2

6

7

V

0.3

30

Voltage on SW, VOUT, LED1, LED2

Internally

limited

Continuous power dissipation

T_J(MAX)

Maximum junction temperature

Note⁽²⁾

150

°C

T_SOLDERING

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) For detailed soldering specifications and information, please refer to Texas Instruments Application Note 1112: DSBGA Wafer Level

Chip Scale Package (AN-1112).

7.2 Handling Ratings

PARAMETER

MIN

–45

MAX

150

UNIT

T_stg

Storage temperature range

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

except SW⁽¹⁾

–1000

1000

Electrostatic

discharge

V_(ESD)

Human body model (HBM), SW pin

–600

–500

600

500

V

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.7

0

NOM

MAX

UNIT

V

V_IN

Input voltage

3.7

5

Voltage on nRST, LCD_EN, PWM, SCL, SDA, FLAG, LDO_CONT, OTP_SEL

V_IN+ 0.3V with

5V max

V

Voltage on LDO_VPOS, LDO_OREF, C1

Voltage on BST_SW, BST_OUT

Voltage on CP_VNEG, C2

0

6.5

7

V

–6.5

0

V

Voltage on SW, VOUT, LED1, LED2

29

85

V

(1)

T_A

Operating ambient temperature

–40

°C

(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

125ºC), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA× P_D-MAX).

=

Submit Documentation Feedback

5

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

7.4 Thermal Information

DSBGA

(20 PINS)

63.5

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

0.3

9.4

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

1.6

Ψ_JB

9.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ T_A≤ 85°C), V_IN= 3.6 V,

V_POS= V_OREF= 5.4 V, V_NEG= –5.4 V, V_BST= 5.7 V, V_CONT= 3.3V.

PARAMETER

CURRENT CONSUMPTION

TEST CONDITION

MIN

TYP

MAX

UNIT

I_SD

Shutdown current

nRST = LOW, LCD_EN = LOW

1

µA

Quiescent current, device not

switching

nRST = HIGH, LCD_EN = LOW,

2.7 V ≤ V_IN≤ 5 V

I_Q

60

nRST = HIGH, LCD_EN = HIGH,

2.7 V ≤ V_IN≤ 5 V, no load,

Backlight disabled

mA

I_{LCD_EN}

1

DEVICE PROTECTION

V_INdecreasing

V_INincreasing

2.5

2.6

140

20

V

UVLO

Undervoltage lockout

TSD

Thermal shutdown⁽¹⁾

Hysteresis⁽¹⁾

°C

TSD(hyst)

LED CURRENT SINKS

Minimum output current

Brightness code 0x001

50

25

µA

Brightness code 0x7FF,

exponential mapping

mA

Maximum output current

Absolute LED current accuracy

I_LED1/2

Brightness code 0x7FF, linear

mapping

mA

25.3

2.7 V ≤ V_IN≤ 5.0 V, LED Currents

0.05 mA, 1 mA, 5 mA, 25 mA

(2)

I_ACCURACY

–3%

0%

3%

2.7 V ≤ V_IN≤ 5.0 V, LED Currents

0.05 mA, 1 mA, 5 mA, 25 mA

(2)

I_MATCH

LED1 to LED2 current matching

Current sink saturation voltage

3%

50

V_{HR_MIN}

I_LED= 95% of 5 mA

30

mV

V

BACKLIGHT BOOST CONVERTER

Backlight boost output overvoltage

protection

V_{OVP_BL}

2.7 V ≤ V_IN≤ 5 V, 29-V Option

28.8

88%

I_LED= 10 mA/string, 2P6S LED

configuration

(1)

η_{LED_DRIVE}

LED drive efficiency

1235AS-H-220M Inductor

I_LED= 25 mA

I_LED= 5 mA

I_SW= 250 mA

250

100

0.5

mV

Ω

Regulated current sink headroom

voltage

V_HR

R_DSON

I_CL

NMOS switch on resistance

Selectable NMOS switch current limit 900-mA setting

900

mA

(1) Typical value only for reference.

(2) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.

Matching is the maximum difference from the average. For the constant current sinks on the part (LED1 and LED2), the following is

determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of both outputs

(AVG). Matching number is calculated: (MAX - MIN)/AVG. The typical specification provided is the most likely norm of the matching

figure of all parts. LED current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different

definitions in use.

6

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Electrical Characteristics (continued)

Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ T_A≤ 85°C), V_IN= 3.6 V,

V_POS= V_OREF= 5.4 V, V_NEG= –5.4 V, V_BST= 5.7 V, V_CONT= 3.3V.

PARAMETER

TEST CONDITION

500-kHz mode

MIN

450

900

TYP

500

MAX

550

UNIT

ƒ_SW

Switching frequency

Maximum duty cycle

kHz

1-MHz mode

1000

94%

1100

D_MAX

LCD BIAS BOOST CONVERTER

LCD bias boost output overvoltage

V_{OVP_BST}

ƒ_{SW_BST}

6.8

V

protection

(1)

Switching frequency

Load current 100mA

2500

4.5

kHz

Minimum Bias boost output voltage

Maximum Bias boost output voltage

Output voltage step size

LCD_BST_OUT = 000000b

LCD_BST_OUT = 100101b

V

6.35

50

mV

(3)

Peak-to-peak ripple voltage

I_LOAD= 50 mA, C_BST= 10 µF

50

mVpp

V_IN+ 500 mVp-p AC square wave,

Tr = 100 mV/µs, 200 Hz, 12.5%

Duty, I_LOAD5 mA, C_IN= 10 µF,

C_BST= 10 µF

V_BST

(3)

BST_OUT line transient response

BST_OUT load transient response

–50

±25

50

mV

Load current step 0 mA - 150 mA,

T_RISE/FALL= 100 mA/µs, C_IN= 10

µF, C_BST= 10 µF

(3)

–150

150

mV

I_{CL_BST}

Valley current limit

1000

170

mA

High-side MOSFET on resistance

Low-side MOSFET on resistance

T_A= 25°C

R_{DSON_BST}

mΩ

T_A= 25°C

290

(4)

η_BST

Efficiency

80 mA < I_BST< 200 mA

C_BST= 20 µF

92%

Start-up time (BST_OUT), V_{BST_OUT}

= 10% to 90%

t_{ST_BST}

1000

µs

(5)

LCD POSITIVE BIAS OUTPUT (LDO_VPOS)

Minimum output voltage

LDO_VPOS_TARGET = 000000b

LDO_VPOS_TARGET = 101000b

4.0

6.0

50

V

Maximum output voltage

Output voltage step size

mV

Output voltage = 5.4 V, I_LOAD= 1

mA

Output voltage accuracy

V_POS

–1.5%

–25

1.5%

25

V_IN+ 500 mVp-p AC square wave,

Tr = 100 mV/µs, 200 Hz, I_LOAD25

mA, C_IN= 10 µF

LDO_VPOS line transient response

mV

(5)

LDO_VPOS load transient response

5 mA to 100 mA load transient,

T_RISE/FALL= 2 µs , C_VPOS= 10 µF

–100

100

20

mV

(5)

DC load regulation

1 mA ≤ I_LOAD≤ 100 mA

Power-good threshold, voltage

increasing

% of target V_POS

PG_RISING

95%

90%

Power-good threshold, voltage

% of target V_POS

PG_FALLING

decreasing

I_{POS_MAX}

I_{CL_VPOS}

Maximum output current

Output current limit

100

200

mA

V_BST= 6.3 V, V_POS= 6 V, C_VPOS

10 µF

=

(5)

(6)

I_{RUSH_PK_VPOS}

V_{DO_VPOS}

Peak start-up inrush current

LDO_VPOS dropout voltage

500

80

mA

mV

I_LOAD= 100 mA, V_POS= 4 V

(3) Limits set by characterization and/or simulation only.

(4) Typical value only for reference.

(5) Limits set by characterization and/or simulation only.

(6) V_BST– V_POSwhen V_POShas dropped 100 mV below target.

Submit Documentation Feedback

7

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Electrical Characteristics (continued)

Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ T_A≤ 85°C), V_IN= 3.6 V,

V_POS= V_OREF= 5.4 V, V_NEG= –5.4 V, V_BST= 5.7 V, V_CONT= 3.3V.

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

ƒ = 10 Hz to 500 kHz, I_LOAD= 50

mA, V_BSTto V_POS, 300 mV

minimum headroom

Power supply rejection ratio,

LDO_VPOS

PSRR_VPOS

25

dB

(5)

Start-up time LDO_VPOS, V_{LDO_VPOS}C_VPOS= 10 µF

= 10% to 90%

t_{ST_VPOS}

1

ms

(5)

Output pull-down resistor,

LDO_VPOS

LDO_VPOS pull-down enabled,

LDO_VPOS disabled

R_{PD_VPOS}

52

80

110

Ω

LCD NEGATIVE BIAS OUTPUT (CP_VNEG)

LCD bias negative charge-pump

V_{OVP_VNEG}

Below V_NEGoutput voltage target

–250

–1

mV

V

output overvoltage protection

LCD bias negative charge-pump

V_{SHORT_VNEG}

output short circuit protection

Minimum output voltage

Maximum output voltage

Output voltage step size

Output accuracy

CP_VNEG_TARGET = 101000b

CP_VNEG_TARGET = 000000b

–6.0

–4.0

50

V

mV

Output voltage = –5.4V

–1.5%

1.5%

I_LOAD= 50 mA,

C_VNEG= 10 µF

(5)

Peak-to-peak ripple voltage

60

mVpp

mV

V_NEG

V_IN+ 500 mVp-p AC square wave,

100 mV/µs 200 Hz, 12.5% DS at 5

mA

(5)

CP_VNEG line transient response

CP_VNEG load transient response

–50

±25

50

5 mA to 50 mA load transient,

T_RISE/FALL= 1 µs, C_VNEG= 10 µF

(5)

–100

100

mV

PG_RISING

Power good increasing

Power good decreasing

% of Target V_NEG

95%

90%

PG_FALLING

V_IN= 3,7V, V_BST= 5,7V V_NEG= -

5.4V, 20mA < I_LOAD< 80mA

η_CP

Efficiency⁽⁷⁾

92%

50

V_IN= 3.7 V, V_BST= 5.6 V,

V_NEG= –5.4V

mA

(8)

I_{NEG_MAX}

Maximum output current

V_IN= 3.7 V, V_BST= 5.7 V,

V_NEG= –5.4 V

80

mA

ms

(8)

I_{CL_VNEG}

t_{ST_VNEG}

Output current limit

150

Start-up time, CP_VNEG,

VCP_VNEG = 10 % to 90 %

V_NEG= –6V, C_VNEG= 10 µF

1

(8)

CP_VNEG Pull-Up Enabled,

CP_VNEG Disabled, V_BST> 4.8V

(8)

R_{PU_VNEG}

Output pull-up resistor, CP_VNEG

30

40

Ω

LCD GAMMA REFERENCE OUTPUT (LDO_OREF)

Minimum Output voltage

LDO_OREF_TARGET = 000000b

LDO_OREF_TARGET = 101000b

4.0

6.0

50

V

Maximum Output voltage

Output voltage step size

mV

I_{LOAD_LDO_OREF}< 5 mA, V_OREF

5.4V

=

Output accuracy

–1.5%

–50

1.5%

50

V_IN+ 500 mVp-p AC Square

Wave, 100 mV/µs 200 Hz at 5 mA,

C_IN= 10 µF

V_OREF

LDO_OREF line transient response

mV

(8)

5 mA to 50 mA load transient @ 2

µs T_RISE/FALL, C_IN= 10 µF

(8)

LDO_OREF load transient

–50

50

20

mV

1 mA ≤ I_{LOAD_LDO_OREF}

≤

(8)

DC load regulation

I_{LOAD_LDO_OREF_MAX}

PG_RISING

Power good increasing

% of target V_{LDO_OREF}

95%

(7) Typical value only for reference.

(8) Limits set by characterization and/or simulation only.

8

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Electrical Characteristics (continued)

Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ T_A≤ 85°C), V_IN= 3.6 V,

V_POS= V_OREF= 5.4 V, V_NEG= –5.4 V, V_BST= 5.7 V, V_CONT= 3.3V.

PARAMETER

TEST CONDITION

% of target V_{LDO_OREF}

MIN

TYP

90%

50

MAX

UNIT

PG_FALLING

I_{OREF_MAX}

I_{CL_OREF}

Power good decreasing

Maximum output current

Output current limit

mA

80

V_BIASBST= 5.8 V, V_OREF= 5.5 V,

C_OREF= 10 µF

(8)

(9)

I_{RUSH_PK_OREF}

Peak start-up inrush current

LDO_OREF dropout voltage

Power supply rejection ratio,

250

mA

I_{LOAD_LDO_OREF}

I_{LOAD_LDO_OREF_MAX}, V_{LDO_OREF}

4.0 V

=

V_{DO_OREF}

=

80

mV

F = 10 Hz to 500 kHz @ I_max/2

,

PSRR_OREF

V_{BST_OUT}to V_{LDO_OREF}, 300 mV

minimum headroom

25

dB

(8)

LDO_OREF

Start-up time, LDO_OREF,

VLDO_OREF = 10% to 90%

C_OREF= 10 µF, V_{LDO_OREF}= 5.5 V

t_{ST_OREF}

1

ms

(8)

Output pull-down resistor,

LDO_OREF

LDO_OREF pull-down enabled,

LDO_OREF disabled

R_{PD_OREF}

130

200

270

Ω

LCD CONTROLLER SUPPLY OUTPUT (LDO_CONT)

LDO_CONT_VOUT = 00

LDO_CONT_VOUT = 01

LDO_CONT_VOUT = 10

LDO_CONT_VOUT = 11

Output Voltage = 1.8 V, 1-mA load

1.8

2.3

2.8

3.3

Output voltage

V

Output accuracy

V_CONT

–2%

–50

2%

50

LDO_CONT line transient response

V_IN+ 500 mVp-p AC Square

Wave, 100 mV/µs 200 Hz at 5 mA

mV

(8)

LDO_CONT load transient response 5-mA to 80-mA load transient @ 2

–50

50

20

(8)

µs T_RISE/FALL

(8)

DC load regulation

1 mA ≤ I_{LOAD_LDO_CONT}≤ 80 mA

mV

mA

mV

I_{CONT_MAX}

I_{CL_CONT}

Maximum output current

Output current limit

80

130

(10)

V_{DO_CONT}

LDO_CONT dropout voltage

I_LOAD= 80 mA, V_CONT= 3.3 V

80

1

F = 10 Hz to 500 kHz @ I_max/2V_IN

to V_{LDO_CONT}, 300-mV minimum

headroom

Power supply rejection ratio,

PSRR_{LDO_CONT}

25

dB

(11)

LDO_CONT

Start-up time, LDO_CONT, V_CONT

=

V_CONT= 1.8 V

t_{ST_CONT}

ms

(11)

10% to 90%

Output pull-down resistor,

LDO_CONT

LDO_CONT pull-down enabled,

LDO_CONT disabled

R_{PD_CONT}

200

Ω

LOGIC INPUTS (PWM, NRST, LCD_EN, SCL, SDA, OTP_SEL)

V_IL

Input logic low

0

1.2

–1

0.4

V_IN

1

V

V_IH

Input logic high

Logic input current

I_INPUT

µA

LOGIC OUTPUTS (SDA, FLAG)

V_OL

Output logic low

I_OL= 3 mA

0

0.4

1

V

I_LEAKAGE

PWM INPUT

ƒ_{PWM_INPUT}

t_MIN

Output leakage current

µA

PWM input frequency

Minimum PWM ON/OFF time

PWM timeout⁽¹¹⁾

100

20000

Hz

ns

400

24

t_TIMEOUT

ms

(9) V_BST– V_OREFwhen V_OREFhas dropped 100 mV below target.

(10) V_IN– V_CONTwhen V_CONThas dropped 100 mV below target.

(11) Limits set by characterization and/or simulation only.

Submit Documentation Feedback

9

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

(1)

7.6 I²C Timing Requirements (SDA, SCL)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

kHz

µs

ƒ_SCL

1

Clock frequency

400

Hold time (repeated) START

condition

0.6

2

3

4

Clock low time

Clock high time

1.3

600

µs

ns

Set-up time for a repeated START

condition

5

6

7

8

9

Data hold time

50

100

ns

µs

Data set-up time

Rise time of SDA and SCL

Fall time of SDA and SCL

20 + 0.1C_b

15 + 0.1C_b

1.3

300

Set-Up time between a STOP and a

START condition

C_b

Capacitive load for each bus line

10

200

pF

(1) Limits set by characterization and/or simulation only

Figure 1. I²C Timing Parameters

10

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

7.7 Typical Characteristics

Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total

Efficiency defined as P_LED/ P_IN, where P_LEDis actual power consumed in LEDs.

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D001

D006

D008

D002

D007

D009

1235AS-H-220M 22-µH Inductor

2P6S LED Configuration

1235AS-H-220M 22-µH Inductor

2P6S LED Configuration

500-kHz Boost SW Frequency

Figure 2. Backlight Boost Efficiency

Figure 3. Backlight Total Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

1235AS-H-220M 22-µH Inductor

2P6S LED Configuration

1235AS-H-220M 22-µH Inductor

2P6S LED Configuration

1-MHz Boost SW Frequency

Figure 4. Backlight Boost Efficiency

Figure 5. Backlight Total Efficiency

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

VLF403210MT-100M 10-µH Inductor

2P6S LED Configuration

VLF403210MT-100M 10-µH Inductor

2P6S LED Configuration

500-kHz Boost SW Frequency

Figure 6. Backlight Boost Efficiency

Figure 7. Backlight Total Efficiency

Submit Documentation Feedback

11

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Typical Characteristics (continued)

Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total

Efficiency defined as P_LED/ P_IN, where P_LEDis actual power consumed in LEDs.

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D010

D011

VLF403210MT-100M 10-µH Inductor

2P6S LED Configuration

VLF403210MT-100M 10-µH Inductor

2P6S LED Configuration

1-MHz Boost SW Frequency

Figure 8. Backlight Boost Efficiency

Figure 9. Backlight Total Efficiency

3

2.8

2.6

2.4

2.2

2

3

2.8

2.6

2.4

2.2

2

1.8

1.6

1.4

1.2

1

1.8

1.6

1.4

1.2

1

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D003

D012

No load on LCD Bias

2P6S LED Configuration

500-kHz BL Boost SW Frequency

No load on LCD Bias

2P6S LED Configuration

1-MHz BL Boost SW Frequency

Figure 10. Device Current Consumption, Backlight Driving

Figure 11. Device Current Consumption, Backlight Driving

22

0.28

0.26

0.24

0.22

0.2

21

20

19

18

17

0.18

0.16

16

0.14

VIN 2.7V

VIN 3.7V

VIN 5.0V

15

14

VIN 3.7V

VIN 5.0V

0.12

0.1

0

5

10

15

20

25

30

35

40

45

50

0

2

4

6

8

10 12 14 16 18 20 22 24 26

LED Current (mA)

Load (mA)

D004

D005

2P6S LED Configuration

Figure 12. Backlight Boost Output Voltage

Figure 13. LED Driver Headroom Voltage

12

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Typical Characteristics (continued)

Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total

Efficiency defined as P_LED/ P_IN, where P_LEDis actual power consumed in LEDs.

27

24

21

18

15

12

9

0.2

0.18

0.16

0.14

0.12

0.1

VIN 2.7V

VIN 3.7V

VIN 5.0V

0.08

0.06

0.04

0.02

0

6

VIN 2.7V

VIN 3.7V

VIN 5.0V

3

0

2

4

6

8

10 12 14 16 18 20 22 24 26

LED Current (mA)

0

250 500 750 1000 1250 1500 1750 2000 2250

Step (DEC)

D013

D014

I²C Brightness Control

VLF403210MT-100M 10-µH Inductor

1-MHz BL Boost SW Frequency

2P6S LED Configuration

Figure 14. LED Current Matching

Figure 15. LED Current, Linear Control

100

95

90

85

80

75

70

65

60

55

50

27

24

21

18

15

12

9

6

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

3

0

250 500 750 1000 1250 1500 1750 2000 2250

Step (DEC)

0

20

40

60

80 100 120 140 160 180 200

Load (mA)

D015

D016

I²C Brightness Control

V_BSTset to 5.2 V

Figure 16. LED Current, Exponential Control

Figure 17. LCD Boost Efficiency

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

20

40

60

80 100 120 140 160 180 200

Load (mA)

0

20

40

60

80 100 120 140 160 180 200

Load (mA)

D017

D018

V_BSTset to 5.5 V

V_BSTset to 5.9 V

Figure 18. LCD Boost Efficiency

Figure 19. LCD Boost Efficiency

Submit Documentation Feedback

13

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Typical Characteristics (continued)

Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total

Efficiency defined as P_LED/ P_IN, where P_LEDis actual power consumed in LEDs.

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

D019

D020

V_NEGset to –5 V

V_NEGset to –5.5 V

Figure 20. V_NEGEfficiency

Figure 21. V_NEGEfficiency

100

95

90

85

80

75

70

65

60

55

50

5.3

5.28

5.26

5.24

5.22

5.2

5.18

5.16

5.14

5.12

5.1

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.6V

VIN 4.3V

0

10

20

30

40

50

60

70

80

0

50 100 150 200 250 300 350 400 450 500

Load (mA)

D021

D022

V_NEGset to –6 V

V_BSTset to 5.2 V

Figure 22. V_NEGEfficiency

Figure 23. LCD Boost Load Regulation

5.6

5.58

5.56

5.54

5.52

5.5

6

5.98

5.96

5.94

5.92

5.9

5.48

5.46

5.44

5.42

5.4

5.88

5.86

5.84

5.82

5.8

VIN 2.7V

VIN 3.6V

VIN 4.3V

VIN 2.7V

VIN 3.6V

VIN 4.3V

0

50 100 150 200 250 300 350 400 450 500

Load (mA)

0

50 100 150 200 250 300 350 400 450 500

Load (mA)

D023

D024

V_BSTset to 5.5 V

V_BSTset to 5.9 V

Figure 24. LCD Boost Load Regulation

Figure 25. LCD Boost Load Regulation

14

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Typical Characteristics (continued)

Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total

Efficiency defined as P_LED/ P_IN, where P_LEDis actual power consumed in LEDs.

-4.9

-4.92

-4.94

-4.96

-4.98

-5

-5.4

-5.42

-5.44

-5.46

-5.48

-5.5

-5.02

-5.04

-5.06

-5.08

-5.1

-5.52

-5.54

-5.56

-5.58

-5.6

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

D025

D026

V_NEGset to –5 V

V_NEGset to –5.5 V

Figure 26. V_NEGLoad Regulation

Figure 27. V_NEGLoad Regulation

-5.9

-5.92

-5.94

-5.96

-5.98

-6

5.05

5.04

5.03

5.02

5.01

5

-6.02

-6.04

-6.06

-6.08

-6.1

4.99

4.98

4.97

4.96

4.95

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

90 100

Load (mA)

D027

D028

V_NEGset to –6 V

V_POSset to 5 V

Figure 28. V_NEGLoad Regulation

Figure 29. V_POSLoad Regulation

5.55

5.54

5.53

5.52

5.51

5.5

6.05

6.04

6.03

6.02

6.01

6

5.49

5.48

5.47

5.46

5.45

5.99

5.98

5.97

5.96

5.95

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load (mA)

D029

D030

V_POSset to 5.5 V

V_POSset to 6 V

Figure 30. V_POSLoad Regulation

Figure 31. V_POSLoad Regulation

Submit Documentation Feedback

15

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Typical Characteristics (continued)

Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total

Efficiency defined as P_LED/ P_IN, where P_LEDis actual power consumed in LEDs.

5.05

5.04

5.03

5.02

5.01

5

5.55

5.54

5.53

5.52

5.51

5.5

4.99

4.98

4.97

4.96

4.95

5.49

5.48

5.47

5.46

5.45

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D031

D033

D035

D032

D034

D036

V_OREFset to 5 V

V_OREFset to 5.5 V

Figure 32. V_OREFLoad Regulation

Figure 33. V_OREFLoad Regulation

6.05

6.04

6.03

6.02

6.01

6

1.85

1.84

1.83

1.82

1.81

1.8

5.99

5.98

5.97

5.96

5.95

1.79

1.78

1.77

1.76

1.75

VIN 2.7V

VIN 3.7V

VIN 5.0V

VIN 2.7V

VIN 3.7V

VIN 5.0V

0

5

10

15

20

25

30

35

40

45

50

0

10

20

30

40

50

60

70

80

Load (mA)

V_OREFset to 6 V

V_CONTset to 1.8 V

Figure 34. V_OREFLoad Regulation

Figure 35. V_CONTLoad Regulation

2.85

2.84

2.83

2.82

2.81

2.8

3.35

3.34

3.33

3.32

3.31

3.3

2.79

2.78

2.77

2.76

2.75

3.29

3.28

3.27

3.26

3.25

VIN 3.7V

VIN 5.0V

VIN 3.7V

VIN 5.0V

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

V_CONTset to 2.8 V

V_CONTset to 3.3 V

Figure 36. V_CONTLoad Regulation

Figure 37. V_CONTLoad Regulation

16

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

8 Detailed Description

8.1 Overview

The LM3631 is a single-chip complete LCD power and backlight solution. It can drive up to two LED strings with

up to 8 LEDs each (up to 27 V typ.), with a maximum of 25 mA per string. The power for the LED strings comes

from a integrated asynchronous backlight boost converter with two selectable switching frequencies (500 kHz or

1 MHz) to optimize performance or solution area. LED current is regulated by two low-headroom current sinks.

Automatic voltage scaling adjust the output voltage of the backlight boost converter to minimize the LED driver

head room voltage.

The LCD bias power portion of the LM3631 consists of an LCD bias boost converter, inverting charge pump, and

three integrated LDOs. The device can generate all the required voltages for a LCD panel:

1. The LCD positive bias voltage V_POS(up to 6V). V_POSvoltage is post-regulated from the LCD bias boost

converter output voltage.

2. LCD negative bias voltage V_NEG(down to –6 V). V_NEGis generated from the LCD bias boost converter output

using a regulated inverting charge pump.

3. The third output V_OREFcan supply the LCD gamma (or VCOM reference) voltage. V_OREFis post-regulated

from the LCD bias boost converter output voltage.

4. The fourth output V_CONTcan be used to supply the display controller. V_CONTregulator is powered from the

VIN input.

The LM3631 flexible control interface consists from nRST active low reset input, LCD_EN enable input, PWM

input for content adaptive backlight control (CABC), and an I²C-compatible interface. In applications with limited

IO pin count the LCD_EN input pin function can be replaced with the LCD_EN I²C register bit. In this case the

LCD_EN pin needs to be connected to ground. OTP_SEL input can be used to select from two different factory-

programmed default One Time Programmable Memory (OTP) settings. The default OTP settings can be

overwritten using the I²C-compatible interface. Programmable settings include LED ramp up/down profiles, LED

output current and brightness control modes, enabling/disabling individual power supply outputs, and

programmable LCD output power up/down sequencing. Open drain FLAG output can be used to notify host

processor from various power-good signals or fault conditions.

Submit Documentation Feedback

17

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Overview (continued)

V_LED+

LCD

Diffuser

LCD Module

LCD Panel

Connector

Image Data

LED

Sinks_1,2

CABC

System

I²C Bus

PWM

Prox

ALS

EN_LCD

nRST

LM3631

Apps Processor

V+ BUS

Main Board

Figure 38. System Example

18

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

8.2 Functional Block Diagram

Up to 8 LEDs/String

with up to 27 V

VIN

+

C_IN

C_OUT

-

VIN

SW

VOUT

Programmable

Overvoltage Protection

Reference and

Thermal Shutdown

Programmable Current

Limit

Backligh Boost Converter

GND_SW

Global Active-low

Reset

nRST

Programmable

500 kHz/1 MHz

Oscillator

V

Voltage

HR

Feedback

LED1

LED2

OTP_SEL

OTP Memory

LED String Open/Short

Detection

FLAG

PWM

FLAG Control

(Power OK or Fault)

Backlight LED Control

1. 11-bit brightness

adjustment

LED Drivers

PWM Detector

With

Low Pass Filter

2. Exponential/Linear

Dimming

3. LED Current

Ramping

VIN

LDO_CONT

LDO_CONT (Panel

controller)

SDA

SCL

I²C Compatible

Interface

LDO_OREF

C1

LDO_OREF (Gamma

Reference, V_COM, V_CS

)

Power OK

Enable

CP_VNEG

(LCD Negative Bias)

LCD_EN

C2

LCD Bias Output

Sequencing Control

CP_VNEG

LCD Boost Converter

GND_BST_SW

LDO_VPOS

(LCD Postive Bias)

LDO_VPOS

Internal Logic

AGND

PGND

BST_SW

BST_OUT

+

VIN

-

Submit Documentation Feedback

19

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

8.3 Features Description

8.3.1 Backlight

The backlight is enabled by setting the BL_EN = 1 and a brightness value higher than zero. LCD bias power rails

need to reach their target voltages before the backlight can be started. Note that all bias voltages don't need to

be enabled to start up the backlight. For example, if only V_POSand V_NEGare required, the backlight can be

enabled once these voltages have reach their target voltages. In this case V_CONTand V_OREFcan be disabled. If

all four outputs (LDO_CONT, LDO_OREF, CP_VNEG, and LDO_VPOS) are disabled, the backlight can be

enabled once the LCD biast boost converter has settled. The LCD bias boost is always enabled when the

LCD_EN pin or bit is set high.

When the brightness value is '0', or BL_EN bit is ‘0’, the backlight is disabled. The BL_EN bit is '1' by default. The

backlight can be disabled at any time by setting the brightness value to zero or by writing the BL_EN bit to ‘0’.

LED driver LED2 can be separately enabled and disabled from the I²C register. LED driver LED1 is always

enabled when the backlight is turned on.

Table 2. Backlight Control

BRIGHTNESS VALUE (I²C AND/OR

BL_EN BIT

BACKLIGHT ON/OFF

EXTERNAL PWM)

0

1

0

≥1

0

OFF

ON

≥1

8.3.1.1 Backlight Brightness Control

Brightness can be controlled either by the I²C brightness register, with an external PWM control, or a

combination of both. BRT_MODE bits select the brightness control mode. Different brightness control modes are

shown in Table 3.

When controlling brightness through I²C, registers 0x01 and 0x02 are used. Registers 0x01 and 0x02 hold the

11-bit brightness data. Register 0x02 contains the 8 MSBs, and register 0x01 contains the 3 LSBs. The LED

current only transitions to the new level after a write is done to register 0x02.

When controlling brightness through I²C, setting brightness value to '0' shuts down the backlight. When

controlling the brightness with PWM input, if PWM input is low for a certain period of time (24 ms typ.), the

backlight shuts down. When using the combination of a PWM input and the I²C register, either option shuts down

the backlight.

NOTE

The backlight does not start before the LCD bias start-up sequence is finished even if

BL_EN bit is '1' and the brightness setting is ≥ 1.

Table 3. Brightness Control

BRT_MODE bits

BRIGHTNESS CONTROL

00

01

10

11

I²C register used for brightness control

PWM input duty cycle used for brightness control

I²C register code multiplied with PWM duty cycle before sloping

Sloped I²C register code multiplied with PWM duty cycle

20

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Up to 8 LEDs/string

with up to 27V

Up to 8 LEDs/string

with up to 27V

V

OUT

V

OUT

Digital

Domain

Analog

Domain

Digital

Domain

Analog

Domain

High Efficiency

Boost Regulator

High Efficiency

Boost Regulator

EN_ADVANCED_SLOPE

min

DAC_i

I

LED2

min

LED1

PWM input signal

PWM

detector

Curve

bending

DAC_i

Sloper

Mapper

I

LED2

LED1

2

Curve

bending

Dither

Sloper

Mapper

DAC

Driver_1

Driver_2

I

C BRT Reg

Dither

DAC

Driver_1

MAPPER_SEL

HYSTERESIS

[1:0]

SLOPE[3:0]

MAPPER_SEL

SLOPE[3:0]

DITHER[3:0]

Figure 39. Brightness Control with

BRT_MODE bit 00

Figure 40. Brightness Control with

BRT_MODE bit 01

Up to 8 LEDs/string

with up to 27V

Up to 8 LEDs/string

with up to 27V

V

OUT

V

OUT

Digital

Domain

Analog

Domain

Digital

Domain

Analog

Domain

High Efficiency

Boost Regulator

High Efficiency

Boost Regulator

EN_ADVANCED_SLOPE

Curve

MAPPER_SEL

Mapper

EN_ADVANCED_SLOPE

min

DAC_i

min

Driver_1

Driver_2

I

LED2

LED1

DAC_i

2

Sloper

Mapper

I

LED2

I

C

BRT Reg

LED1

bending

2

Curve

bending

Sloper

I

C BRT Reg

Driver_1

DAC

Dither

DAC

Dither

MAPPER_SEL

PWM input signal

PWM

detector

SLOPE[3:0]

DITHER[3:0]

HYSTERESIS

[1:0]

DITHER[3:0]

PWM input signal

PWM

detector

HYSTERESIS

[1:0]

Figure 41. Brightness Control with

BRT_MODE bit 10

Figure 42. Brightness Control with

BRT_MODE bit 11

8.3.1.1.1 LED Current With Brightness Selection '00'

When LED brightness is controlled from the I²C brightness registers, the 11-bit brightness data directly controls

the LED current in LED1 and LED2. LED mapping can be selected as either linear or exponential. When this

mode is selected setting PWM input to 0 does not disable the backlight.

With exponential mapping the 11-bit code-to-current response is approximated by the equation:

I_LED= 50 µA × 1.003040572^{I2C BRT CODE}(for codes > 0)

(1)

This equation is valid for I²C brightness codes between 1 and 2047. Code 0 disables the backlight. Resolution

achieved at the output is maximum 16-bit at low brightness levels and additional 1 bit can be achieved with the

dithering resulting in up to 17-bit output resolution. Step sizes increase when the current increases with the

exponential control.

Figure 43 and Figure 44 detail the exponential response of the LED current vs. brightness code. Figure 43 shows

the response on a linear Y axis while Figure 44 shows the response on a log Y axis to show the low current

levels at the lower codes.

Submit Documentation Feedback

21

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

25

20

15

10

5

100

10

1

0.1

0.01

0

256

512

768

1024

1280

1536

1792

2048

0

256

512

768

1024

1280

1536

1792

2048

11-Bit Brightness Code

C001

C002

Figure 43. Exponential Response of the LED Current vs

Brightness Code

Figure 44. Response of the LED Current vs Brightness

Code on a Log Y Axis

With linear mapping the 11-bit code to current response is approximated by the equation:

I_LED= 37.67 µA + 12.33 µA × I2C BRT CODE (for codes > 0)

(2)

This equation is valid for codes between 1 and 2047. Code 0 disables the backlight.

8.3.1.1.2 LED Current With Brightness Selection '01'

When LED brightness is controlled from the PWM, the PWM duty cycle directly controls the LED current in LED1

and LED2. LED mapping can be selected to be either linear or exponential. When this mode is selected, setting

the I²C brightness register to 0 does not disable the backlight.

With exponential mapping the PWM duty cycle-to-current response is approximated by the equation:

I_LED= 50 µA × 1.003040572^{2047 × PWM D/C}(PWM D/C ≠ 0)

(3)

Equation 3 is valid for PWM duty cycles other than 0. Duty cycle 0 disables the backlight.

With linear mapping the PWM duty cycle-to-current response is approximated by the equation:

I_LED= 37.67 µA + (12.33 µA × 2047 × PWM D/C) (PWM D/C ≠ 0)

(4)

Equation 4 is valid for PWM duty cycles other than 0. Duty cycle 0 disables the backlight.

8.3.1.1.3 LED Current With Brightness Selections '10' and '11'

When LED brightness is controlled with the combination of the I²C register and the PWM duty cycle, the

multiplication result of I²C register value and PWM duty cycle controls the LED current in LED1 and LED2. LED

mapping can be selected as either linear or exponential.

With exponential mapping the multiplication result-to-current response is approximated by the equation:

I_LED= 50 µA × 1.003040572^{I2C BRT CODE × PWM D/C}

(5)

Equation 5 is valid for brightness values other than 0. Brightness value (PWM D/C or I2C BRT CODE) 0 disables

the backligh.

With linear mapping the PWM duty cycle-to-current response is approximated by the equation:

I_LED= 37.67 µA + (12.33 µA × I2C BRT CODE × PWM D/C)

(6)

Equation 6 is valid for brightness values other than 0. Brightness value (PWM D/C or I2C BRT CODE) 0

programs 0 current.

The key difference between the two brightness modes is how the PWM input affects the LED output current.

When brightness mode is '10', changing PWM value causes LED current to slope form the current value to the

new value. With the brightness setting '11', a change in PWM value causes an instant change in the LED current.

This makes brightness setting '11' suitable for CABC operation.

8.3.1.2 Linear Slope and Advanced Slope

Sloper smooths the transition from one brightness value to another. Slope time can be adjusted from 0 ms to

4000 ms with SLOPE[3:0] bits. Slope time is used for sloping up and down. Slope time always remains the same

regardless of the amount of change in brightness. Advanced slope makes brightness changes smooth for the

human eye.

22

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Dithering function further smooths the slope by jumping between two adjacent current values. Dithering

frequency can be programmed with DITHER_FREQ_SEL[3:0] bits. Dithering function can be disabled with

DISABLE_DITHER bit.

Sloper

Input

Brightness

Time

Brightness

Output

Steady state with or without dithering

Normal

slope

Advanced

slope

Time

Slope

Time

If dither is enabled it will

be used during transition

to enable smooth effect.

Figure 45. Sloper

Table 4. Slope Times

SLOPE BITS[3:0]

SLOPE TIME (ms)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0, slope function disabled, immediate brightness change

1

2

5

10

20

50

100

250

500

750

1000

1500

2000

3000

4000

8.3.1.3 Mapper

The mapper block maps the digital word into current code which is set for the LED driver. The user can select

whether the mapping is exponential or linear with the LINEAR_MAPPER bit.

Exponential control is tailored to the response of the human eye such that the perceived change in brightness

during ramp up or ramp down is linear.

Submit Documentation Feedback

23

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

8.3.1.4 PWM Detector and PWM Input

The PWM detector block measures the duty cycle in the PWM pin. The PWM period is measured from the

rising/falling edge to the next rising/falling edge. PWM edge detection can be selected as rising or falling from

register 0x08 bit 7. PWM polarity can be changed with register 0x08 bit 6. The PWM input block timeout is 24 ms

after the last rising edge, which should be taken into account for 0% and 100% brightness settings (for setting

100% brightness, high level of PWM input signal should be at least 24 ms). Minimum on and off times for PWM

input signal are 400 ns.

PWM input resolution is defined by the PWM detector sampling rate (24 MHz typ.). Resolution depends on the

input signal frequency — for example, with 10-kHz PWM input frequency the resolution is 11-bit. If a higher input

frequency is used, the resolution is lower. The minimum recommended PWM frequency is 100 Hz, and maximum

recommended PWM frequency is 20 kHz.

PWM hysteresis selection sets the minimum allowable change to the input. If a smaller change is detected, it is

ignored. With hysteresis the constant changing between two brightness values is avoided if there is small jitter in

the input signal. Hysteresis is selected with HYSTERESIS bits in register 0x08. Using a higher hysteresis setting

is recommended with high PWM input frequencies.

The PWM detector is disabled in I²C brightness mode to minimize current consumption.

8.3.2 Backlight Boost Converter

The LM3631 can drive two LED strings with up to 8 LEDs per string. The high voltage required by the LED

strings is generated with an asynchronous backlight boost converter. An adaptive voltage control loop

automatically adjusts the output voltage based on the voltage over the LED drivers LED1 and LED2.

The LM3631 has two switching frequency modes (high and low). These are set via the Boost Frequency Select

bit. The nominal low- and high-frequency set points are 500 kHz and 1 MHz, respectively. Operation in low-

frequency mode results in better efficiency at lighter load currents due to the decreased switching losses.

Operation in high-frequency mode gives better efficiency at higher load currents due to the reduced inductor

current ripple and the resulting lower conduction losses in the MOSFETs and inductor.

LED1

LED2

VOUT

SW

BL_BST_OVP [1:0]

LIGHT

LOAD

BOOST_SEL_I [1:0]

BOOST_SEL_P [1:0]

OVP

V_HR

(Feedback)

R

S

R

-

GM

+

V_REF

R

GATE

DRIVER

OCP

CURRENT

SENSE

LED Driver

BL_BST_FREQ [0]

OFF/BLANK TIME

PULSE GENERATOR

CURRENT RAMP

GENERATOR

GM

ꢀ

BOOST OSCILLATOR

PEAK_CURR_LIM [1:0]

INDUCTOR [0]

Figure 46. Backlight Boost Block Diagram

24

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

8.3.2.1 Headroom Voltage

Saturation voltage of the LED drivers depends on the output current setting. In order to optimize LED drive

efficiency, while maintaining good LED current accuracy, the LED-driver-regulated headroom voltage (V_HR) is

kept slightly above LED driver saturation voltage. To maintain good LED current accuracy with lower current

settings, LED driver size is scaled down for the lower current settings (below 1/16 of max current). In order to

ensure that both current sinks remain in regulation when there is a mismatch in string voltages, the boost

converter output voltage is regulated based on the LED driver with lower headroom voltage. For example, if the

LEDs connected to LED1 require 25 V at the programmed current, and the LEDs connected to LED2 require

25.5 V at the programmed current, the voltage at LED1 is V_HR+ 0.5 V, and the voltage at LED2 is V_HR

.

0.3

0.25

0.2

0.15

0.1

0.05

0

0.01

0.1

1

10

100

String LED Current (mA)

D001

Figure 47. Regulated Headroom vs LED Current

8.3.2.2 Automatic Switching Frequency Shift

To take advantage of frequency vs load dependent losses, the LM3631 has an automatic frequency-select mode.

In automatic frequency-select mode the switching-frequency bit is automatically changed based on the

programmed LED current. The threshold (or LED Brightness Code) at which the frequency switchover occurs is

programmable via the AUTOFREQ_THRESHOLD. This register contains an 8-bit code which is compared

against the 8 MSB’s of the brightness code (BRT[10:3]). When BRT[10:3] > AUTOFREQ_THRESH[7:0], the

Boost Frequency Select Bit is set to a ‘1’, and the device operates in high-frequency mode. When BRT[10:3] ≤

AUTOFREQ_THRESH[7:0], the Frequency Select Bit is automatically set to ‘0’, and the device operates in low-

frequency mode.

When automatic frequency-select mode is disabled, the switching frequency operates at the programmed high-

or low-frequency setting across the entire LED current range.

8.3.2.3 Inductor Select Bit

The LM3631 can operate with a 10-µH or 22-µH inductor. However, the LM3631 backlight boost-control loop

requires adjustment of internal loop compensation parameters based on the inductance value selected for the

application. This is done through the INDUCTOR bit. For 10-µH inductors, the INDUCTOR bit must be set to '1'.

For a 22-µH inductor, the INDUCTOR bit should be set to ‘0’.

8.3.2.4 PI-Compensator

The LM3631 backlight boost converter internal loop-compensation parameters (SEL_I[1:0] and SEL_P[1:0]) are

factory-selected to optimize performance and stability for most backlight configurations. These settings should

not need adjustment. If these settings are changed, application needs to be carefully evaluated to ensure stability

and performance in all operating conditions.

Submit Documentation Feedback

25

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

8.3.3 Backlight Protection and Faults

8.3.3.1 Overvoltage Protection (OVP) and Open-Load Fault Protection

The LM3631 provides an OVP that monitors the LED boost output voltage (V_OUT) and protects OUT and SW

from exceeding safe operating voltages. The OVP threshold can be set with the I²C register bits. The OVP limit

can be set to 17 V, 21 V, 25 V, or 29 V. The OVP monitor differentiates between two overvoltage conditions and

responds accordingly as outlined below:

Case 1 (OVP Threshold hit and (VLED1 and VLED2 ) > 40 mV): In steady-state operation with V_OUTnear the

OVP threshold (V_OVP), a rapid change in V_INor brightness code can result in a momentary transient

excursion of V_OUTabove the OVP threshold. In this case the boost circuitry is disabled until V_OUT

drops below V_OVP- V_HYST. Once this happens the boost is re-enabled, and steady state regulation

can commence. If the OVP pulse length is over 1 ms, an OVP fault is set.

Case 2 (OVP Threshold hit and (VLED1 and VLED2 ) < 40 mV): When one or all of the LED strings is open,

the boost converter drives V_OUTabove V_OVPand at the same time the open string(s) current sink

headroom voltage(s) drops to 0. When LM3631 detects three pulses (if V_OUT> V_OVPand (V_LED1or

V_LED2) < 40 mV), the OVP Fault flag (BL_OVPFLT) is set. If the OVP pulse length is over 1 ms, an

OVP fault is set. The flag is cleared with rising LCD_EN or an I²C write.

8.3.3.2 Overcurrent Protection (OCP) and Overcurrent Protection Fault

The LM3631 has 4 selectable OCP thresholds. The programmable options are 600 mA, 700 mA, 800 mA, or 900

mA. The OCP threshold is a cycle-by-cycle current limit detected in the low-side NFET. Once the threshold is

reached, the NFET turns off for the remainder of the switching period.

8.3.3.2.1 Overcurrent Protection Fault Flag (BL_OCPFLT)

If enough OCP threshold events occur the Overcurrent Protection Fault (BL_OCPFLT) flag is set. To avoid

transient conditions from inadvertently setting the BL_OCPFLT Flag, a Pulse Density Counter monitors OCP

threshold events over a 128-µs period. If the Pulse Density Counter counts 2 or more OCP events during the

128-µs period, the pulse density count is considered true. If 8 consecutive 128-µs periods occur where the pulse

density count is true (1024 µs total), the BL_OCPFLT fault is set. Fault is cleared by rising edge of the LCD_EN

or an I²C write '1' to the BL_OCPFLT bit.

NOTE

The OCP signaling is ignored for 4 ms after the backlight boost is started or the brightness

value is changed.

8.3.3.2.2 Short Circuit Fault Flag (BL_SCFLT)

If an OCP fault has occurred, and the headroom voltage is too low (VLED1 or VLED2 < 40 mV), the Short Circuit

Fault (BL_SCFLT) fault is set, and all power is shut down. The fault must be cleared to enable power — it is

cleared by the rising edge of the LCD_EN or by an I²C write '1' to the BL_SCFLT bit.

NOTE

The OCP signaling is ignored for 4 ms after the backlight boost is started or the brightness

value is changed.

8.3.4 LCD Bias

8.3.4.1 Display Bias Power (V_POS, V_NEG, V_OREF

)

A single high-efficiency boost converter provides a positive voltage rail, V_{BST_OUT}, which serves as the power rail

for the LCD V_POSand V_NEGbiases, as well as for an additional regulated output V_OREF. This can be used to

supply the display gamma reference, V_COMand V_CSvoltages.

•

The V_POSoutput LDO, LDO_VPOS, has a programmable range from 4 V up to 6 V with 50-mV steps and can

supply up to 100 mA.

•

The V_NEGoutput, CP_VNEG, is generated from a regulated, inverting charge pump and has an adjustable

26

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

range of –6 V up to –4 V with 50-mV steps and a maximum load of 80 mA. During start-up there is a

minimum delay of 500 µs due to biasing the flycap.

•

The V_OREFoutput LDO, LDO_OREF, has programmable range from 4 V to 6 V, further adjustable in 50-mV

increments and can supply up to 50 mA.

The boost voltage can be selected from the an I²C register. When selecting suitable boost-output voltage, the

following estimation can be used V_BST= max(V_{LDO_VPOS}, |V_{CP_VNEG}|,V_{LDO_OREF}) + 200 mV (with lower currents) or

+ 300 mV (with higher currents). When the device input voltage (V_IN) > sets the LCD boost output voltage, the

boost voltage goes to V_IN+ 100 mV.

Table 5. LCD Boost V_OUT

LCD_BOOST_VOUT BITS

000 000

000 001

000 010

000 011

000 100

000 101

000 110

...

LCD BOOST OUTPUT VOLTAGE (V)

4.50

4.55

4.60

4.65

4.70

4.75

4.80

...

011 111

100 000

100 001

100 010

100 011

100 100

100 101

6.05

6.10

6.15

6.20

6.25

6.30

6.35

Submit Documentation Feedback

27

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

LCD Controller

Supply Output

LDO_CONT

V_CONT

LDO_CONT

BST_OUT

VIN

10 µF

V_OUT

BST_SW

LCD Bias Boost

Converter

+

V_IN

10 µF

C_IN

10 µF

±

LCD Gamma

Reference Output

LDO_OREF

V_OREF

10 µF

V_POS

LCD Positive

Bias Output

LDO_VPOS

C1

10 µF

C2

LCD Negative

Bias Output

CP_VNEG

V_NEG

CP_VNEG

10 µF

Figure 48. LCD Boost

8.3.4.2 Display Bias Power Sequencing (V_POS, V_NEG, V_OREF, V_CONT

)

The LM3631 supports configurable output power-up and power-down timing for V_POS, V_NEG, V_CONTand V_OREF

.

The LED current sinks can start up after the bias voltages power ok signals (or after the timeout period has

elapsed (20 ms typ.)) and shuts down before the bias power-down sequence begins. The bias power-down

sequence does not start until after the LED current sinks have turned off.

The trigger for the power-up sequence is either a change from logic LOW to logic HIGH on the LCD_EN pin or

the Display Bias Outputs bit. The trigger for the power-down sequence is either a change from logic HIGH to

logic LOW on the LCD_EN pin or the Display Bias Outputs bit. The pull-downs or pull-ups for each output, if

enabled, disengage immediately upon start-up of each respective output and re-engages immediately upon

shutdown of each respective output.

Table 6. Start-Up and Shutdown Delays

START-UP DELAY SETTING (LDO_OREF_SU_DLY,

LDO_VPOS_SU_DLY, CP_VNEG_SU_DLY) (ms)

SHUTDOWN DELAY SETTING (LDO_OREF_SD_DLY,

LDO_VPOS_SD_DLY, CP_VNEG_SD_DLY) (ms)

0000 = 0

0001 = 1

0010 = 2

0011 = 3

0100 = 4

0101 = 5

0110 = 6

0111 = 7

1000 = 8

0000 = 0

0001 = 1

0010 = 2

0011 = 3

0100 = 4

0101 = 5

0110 = 6

0111 = 7

1000 = 8

28

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Table 6. Start-Up and Shutdown Delays (continued)

START-UP DELAY SETTING (LDO_OREF_SU_DLY,

SHUTDOWN DELAY SETTING (LDO_OREF_SD_DLY,

LDO_VPOS_SU_DLY, CP_VNEG_SU_DLY) (ms)

LDO_VPOS_SD_DLY, CP_VNEG_SD_DLY) (ms)

1001 = 9

1010 = 10

1011 = 11

1100 = 12

1101 = 13

1110 = 14

1111 = 15

1001 = 9

1010 = 10

1011 = 11

1100 = 12

1101 = 13

1110 = 14

1111 = 15

LDO_CONT start-up/shutdown delay has a 3-bit programmable range.

Table 7. LDO_CONT Start-Up/Shutdown Delays

LDO_CONT START-UP/SHUTDOWN DELAY SETTING

START-UP/SHUTDOWN DELAY (ms)

(LDO_CONT_SU_DLY, LDO_CONT_SD_DLY)

000

001

010

011

100

101

110

111

0

2

5

10

20

50

100

200

LDO_OREF_SD_DLY

ULVO_OK

LDO_CONT_

SU_DLY

LDO_OREF_

SU_DLY

LDO_VPOS_SD_DLY

VIN

nRST

LCD_EN

LDO_CONT

BST_OUT

LDO_OREF

BST_PWROK

(Internal Signal)

LDO_VPOS

CP_VNEG

BSTOK

LDO_VPOS_SU_DLY

CP_VNEG_

SD_DLY

LDO_CONT_

SD_DLY

CP_VNEG_SU_DLY

Figure 49. General LCD Bias Power Sequence Without Backlight

Submit Documentation Feedback

29

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Last bias

power OK

LDO_OREF_SD_DLY

ULVO_OK

SU_DLY

LDO_CONT_

SU_DLY

LDO_VPOS_SD_DLY

LDO_OREF_SU_DLY

VIN

nRST

LCD_EN

LDO_CONT

BST_OUT

LCD bias and

Backlight ON

LDO_OREF

BST_PWROK

(Internal Signal)

LDO_VPOS

CP_VNEG

BSTOK

LDO_VPOS_SU_DLY

CP_VNEG_SU_DLY

CP_VNEG_

SD_DLY

LDO_CONT_

SD_DLY

Backlight

LED sinks

turned off

Figure 50. General LCD Bias Power Sequence With Backlight

8.3.4.2.1 Start-Up and Shutdown Delays

SU_DLY

Start-up delay from LCD_EN = HIGH to start up of the internal references, bias, and oscillator.

LDO_CONT_SU_DLY Delay between the time LDO_CONT signal starts to rise ‘HIGH’, and the time before

BST_OUT starts to rise. LDO_CONT delay can be adjusted with LDO_CONT_SU_DLY I²C register

start-up delay bits. In case LDO_CONT is disabled, BST_OUT starts to rise after LCD_EN is set

‘HIGH’.

BSTOK

Bias boost startup delay. Time between the time when BST_OUT voltage starts to rise and the time

when BST_PWROK (internal) signal rises to ‘HIGH’.

LDO_OREF_SU_DLY Delay between the time when BST_PWROK signal rises to ‘HIGH’ and LDO_OREF

signal starts to rise. Delay can be adjusted with I²C register start-up delay bits

LDO_OREF_SU_DLY.

LDO_VPOS_SU_DLY Delay between the time when BST_PWROK signal rises to ‘HIGH’ and LDO_VPOS

signal starts to rise. Delay can be adjusted with I²C register start-up delay bits

LDO_VPOS_SU_DLY.

CP_VNEG_SU_DLY Delay between the time when BST_PWROK signal rises to ‘HIGH’ and CP_VNEG signal

starts to fall. Delay can be adjusted with I²C register start-up delay bits CP_VNEG_SU_DLY. Note

that there is a minimum delay of 500 µs (typ.) due to biasing of the flycap.

CP_VNEG_SD_DLY Delay between the time when LCD_EN signal is set LOW and the time when CP_VNEG

signal starts to rise. Delay can be adjusted with I²C register off delay bits CP_VNEG_SD_DLY.

30

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

LDO_VPOS_SD_DLY Delay between the time when LCD_EN signal is set LOW and the time when

LDO_VPOS signal starts to fall. Delay can be adjusted with I²C register off delay bits

LDO_VPOS_SD_DLY.

LDO_OREF_SD_DLY Delay between the time when LCD_EN signal is set LOW and the time when

LDO_OREF signals start to fall. Delay can be adjusted with I²C register off delay bits

LDO_OREF_SD_DLY.

LDO_CONT_SD_DLY After last of the LDO_OREF, CP_VNEG, or LDO_VPOS shutdown time has ended

LDO_CONT signal starts to fall in case it is enabled.

8.3.4.2.2 Special Conditions During Display Bias Power Sequencing

Short nRST Condition During Shutdown Sequence If nRST is logic LOW for longer than the deglitch time, all

appropriate outputs are sequenced down completely. If nRST is toggled or is held at logic HIGH

before the all outputs are shutdown, the shutdown sequencing continues to turn off all outputs and

set all the internal registers to the default state. Note that if nRST is toggled or is held at logic HIGH

before all outputs are shut down, and FLAG pin is configured as fault, there are small glitches in the

FLAG line after nRST is set HIGH.

Thermal Fault During Shutdown Sequence A thermal fault, when the die temperature is greater than T_SD

,

shuts down all outputs. When the die temperature drops by T_{SD(HYSTERESIS)}, the outputs can be re-

started by toggling LCD_EN or the “LCD_EN” bit of register 0x00.

Backlight Sequence During LCD Bias Start-up Sequence Backlight cannot be enabled before LCD bias start-

up sequence is complete. If the backlight is enabled (via either the PWM or I²C register) before the

LCD bias start-up sequence is complete, the backlight start-up sequence starts after LCD bias

start-up sequence is complete.

8.3.4.3 Active Discharge

An active discharge is implemented for each output rail (LDO_OREF, LDO_VPOS, LDO_CONT and CP_VNEG)

with internal switch resistance. The discharge function is programmable by I²C interface and is triggered by

LCD_EN = “LOW”. During power-up, each output programmed to be actively discharged (at power-down) is

actively discharged as long as it is not enabled internally.

8.3.4.4 LCD Bias Protection

The LM3631 provides OVP that monitors the LCD Bias boost output voltage (V_OUT) and protects BST_OUT and

BST_SW from exceeding safe operating voltages. The OVP threshold can be set with the I²C register bits. If

there is an LCD bias overvoltage fault, an LCD_OVPFLT fault is set. The fault is cleared with the rising edge of

LCD_EN or an I²C write '1' to the LCD_OVPFLT bit.

LDO_VPOS has an OCP that limits the maximum current drawn to 200 mA (typ.). If the fault condition persists

over 2 ms, the LCD is shut down according to the normal shutdown sequence, and an LDO_VPOS_FLT fault is

set. The fault must be cleared to enable power; the fault is cleared with rising edge of LCD_EN or an I²C write '1'

to LDO_VPOS_FLT bit.

LDO_OREF has OCP that limits the maximum current drawn to 80 mA (typ.). If the fault condition persists over 2

ms, the LCD is shut down according to the normal shutdown sequence, and an LDO_OREF_FLT fault is set. The

fault must be cleared to enable powers; the fault is cleared with rising edge of LCD_EN or I²C write '1' to

LDO_OREF_FLT bit.

CP_VNEG has a short-circuit and OVP feature, which monitors the charge-pump voltage.

•

If the charge-pump voltage goes 250 mv (typ.) below its target set-point, the charge pump is shut down. If the

OVP persists for 2 ms, all bias outputs are turned off following the normal shutdown sequence, and a

NEG_CP_OVP fault is set. The fault must be cleared, to re-enable the outputs, with the rising edge of

LCD_EN or an I²C write '1' to NEG_CP_OVP bit.

•

If the charge-pump voltage goes over –1 V, the charge pump is shut down, and a NEG_CP_SC fault gets set.

The fault must be cleared, to re-enable the outputs, with rising edge of LCD_EN or an I²C write '1' to

NEG_CP_SC.

Submit Documentation Feedback

31

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

8.3.5 Display Controller Power (V_{LDO_CONT}

)

The LM3631 supports an additional regulated output V_{LDO_CONT}which can supply, for example, the display’s

controller voltage. The LDO_CONT has a 2-bit programmable range with 1.8-V, 2.3-V, 2.8-V and 3.3-V values

and can supply up to 80 mA. This LDO is powered directly from V_INvoltage.

NOTE

When the LDO voltage is set to 2.8 V, V_INvoltage must be kept over 2.8 V to ensure LDO

proper functionality. Similarly, when LDO voltage is set to 3.3 V, the battery voltage must

be kept over 3.3 V to ensure LDO proper functionality.

LDO_CONT has an OCP feature. If the OCP fault condition persists over 2 ms, a fault is set. LDO_CONT limits

the current. Fault is cleared with rising edge of LCD_EN or an I²C write '1' to the LDO_CONT_FLT bit.

8.3.6 RESET Register

I²C register 0x14 is the register reset. Writing FFh into this register resets all I²C register values to default values.

Default values are described in Table 1.

8.3.7 nRST Input

The nRST input is a global hardware enable for the LM3631. This pin must be pulled to logic HIGH to enable the

device and the I²C-compatible interface. This pin is high-impedance and cannot be left floating. When this pin is

at logic LOW, the LM3631 is placed in shutdown, the I²C-compatible interface is disabled, and the internal

registers are reset to their default state. It is recommended that V_INhas risen above a 2.7-V before setting nRST

HIGH.

8.3.8 FLAG Pin

The FLAG pin can be used as an indicator to the application processor when the LM3631 encounters, for

example, OVP. The fault conditions which set the FLAG pin to pull low can be programmed via I²C. Additionally,

the power-good flag can be set to trigger from the flag for the bias voltages.

The FLAG pin is an open-drain output. When this pin is used, a pullup resistor is needed. If not used, this pin can

be left floating.

Table 8. FLAG Pin Configuration

FLAG PIN CONFIGURATION BITS

FLAG PIN INFORMATION

00

Flag disabled, no flag indication

Power-Good state, selectable with Power-Good flag control bits

(PG_FLAG_CTRL)

01

10

11

Backlight on state

Fault state

8.3.9 Power-Good Flag

The Power-Good flag can be used to indicate an application processor power-good situation of the bias voltages.

The Power-Good flag information can be selected with Power-Good Flag control bits (PG_FLAG_CTRL). This

information can be directed to the FLAG pin with FLAG pin configuration bits.

NOTE

When nRST is pulled low before the power sequence is complete, the Power-Good Flag

indication is triggered even though the condition (described in Table 9) to trigger that the

Power-Good flag is not fulfilled. When the Power-Good configuration is '00' (after last

supply reaches target), LDO_VPOS, CP_VNEG, and LDO_OREF all need to be enabled.

32

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Table 9. Power-Good Flag Configuration

POWER-GOOD FLAG

CONFIGURATION BITS

FLAG PIN INFORMATION DURING START-UP

FLAG PIN INFORMATION DURING SHUTDOWN

Power-Good bit set to '1' after last supply reaches

target

Power-Good bit set to '0' after first supply falls below

target

00

Power-Good bit set to '1' after LDO_VPOS reaches Power-Good bit set to '0' after LDO_VPOS falls below

01

10

11

target

Power-Good bit set to '1' after CP_VNEG reaches

target

Power-Good bit set to '0' after CP_VNEG falls below

target

Power-Good bit set to '1' after LDO_OREF reaches Power-Good bit set to '0' after LDO_OREF falls below

target target

8.3.10 OTP_SEL Pin

The OTP selection pin is dedicated for selection between two different default setups. Setting this pin to VBATT

or GND selects the OTP from where the default setup is loaded. Note that this selection applies only for the

backlight and LCD configuration registers (registers from 0x05h to 0x12h).

8.3.11 Thermal Shutdown

The LM3631 has Thermal Shutdown protection which shuts down the backlight, all bias voltage outputs and

enters standby mode when the die temperature reaches or exceeds 140°C (typ.). When the die temperature falls

below 120°C (typ.), the LM3631 comes out of standby. The I²C interface remains active during a Thermal

Shutdown event. If a TSD fault occurs, TMPFLT fault is set — the fault is cleared by an I²C write '1' to TMPFLT

bit or by setting LCD_EN high.

8.3.12 Undervoltage Lockout

The LM3631 has an undervoltage lockout feature (UVLO), which indicates of the device operation at low input

voltages. If the supply voltage V_INis below the UVLO threshold, a UVLO fault is set. UVLO fault is cleared by an

I²C write '1' to UVLO bit. UVLO does not shut down the outputs.

UVLO rising threshold is 2.6 V (typ.), and UVLO falling threshold is 2.5 V (typ.).

Submit Documentation Feedback

33

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

8.4 Device Functional Modes

8.4.1 Modes of Operation

Shutdown: The LM3631 is in shutdown when nRST pin is low.

Standby:

After nRST pin is set high, and V_INis over UVLO limit, the LM3631 goes into Standby mode. Before

entering Standby mode, references and bias currents are enabled (bias delay typically 200 µs), and

registers are read from OTP (EPROM read delay typically 700 µs). In Standby mode references

and bias currents are enabled, and I²C writes are allowed. LCD powers, and backlight are disabled.

Normal mode: When LCD_EN is set to high (pin or bit), the start-up sequence is started. During the start-up

sequence LDO_CONT, LCD Boost, and LCD bias powers are started. If the LDO_CONT is

disabled, the start-up sequence goes directly to LCD Boost start-up.

•

LDO_CONT start-up: LDO_CONT is enabled. Programmable delay of 0 to 200 ms.

LCD Boost start-up: LCD Boost is enabled. Waits until Boost output voltage is reached

90% of target value.

•

LCD bias start-up enables, sequentially, LDO_VPOS, CP_VNEG, and LDO_OREF

according to start-up delay settings.

After the LCD bias start-up has completed, the LM3631 enters backlight start-up mode if

BL_EN bit is set to ‘1’, and the PWM brightness value is different than 0. Even if the

backlight is not enabled, LCD powers remains active. If the backlight is enabled, and BL_EN

bit is set to ‘0’ or PWM brightness value is set to 0, backlight is disabled. LCD powers

remains active.

If LCD_EN is set to ‘0’, the LM3631 shuts down backlight and bias powers and enters

Standby mode. During power down the backlight is shut down first if it was enabled. After

backlight shutdown is completed, the device enters LCD Bias shutdown. In LCD bias

shutdown LDO_VPOS, CP_VNEG, and LDO_OREF are shut down sequentially according to

shutdown delay settings. After the LDO_VPOS, CP_VNEG, and LDO_OREF shutdown

sequence is complete, LCD Boost and LDO_CONT (if it was enabled) are shut down.

LDO_CONT is shut down after adjustable delay (0 to 200 ms). Once LDO_CONT has shut

down, the LM3631 enters Standby mode.

In a fault situation (thermal, backlight boost short circuit, LDO_OREF overcurrent, VPOS

overcurrent, or CP short circuit), the device starts the shutdown sequence and enters

Standby mode.

34

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Device Functional Modes (continued)

Shutdown

UVLO fault

during startup

nRST = HIGH &

> UVLO

V

IN

Bias delay

(200 µs typ)

No UVLO fault

during startup

Eprom read

(700 µs typ)

eprom_read_done

Standby

LCD Bias Shutdown done

and

LDO_CONT disabled

LDO Cont

Shutdown done

LCD disable

LCD Bias

LCD_EN = 1 (pin or bit)

and no faults active

LDO_CONT enabled

LCD_EN = 1 (pin or bit)

and no faults active

LDO_CONT disabled

LDO_Cont

Start Up

LDO Cont

Shutdown

Shutdown done

LCD_Boost

Start Up

LCD Bias

Shutdown

LCD disable

BST_PWROK

LCD Bias

Start Up

LCD disable

Normal Operation

LCD bias

Startup done

LCD disable or

BL_EN=0 or PWM=0

Backlight

Shutdown

LCD Active

LCD enabled and

backlight shutdown

done

Power Good OK,

BL_EN=1 DQGꢀ3:00

Backlight startup done

Backlight

Startup

Figure 51. Modes of Operations

Submit Documentation Feedback

35

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

8.5 Programming

8.5.1 I²C-Compatible Serial Bus Interface

8.5.1.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines

should be connected to a positive supply via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave, depending

whether it generates or receives the serial clock (SCL).

8.5.1.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

Figure 52. Data Validity

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software), and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

Transmitter Stays off the

Bus During the Acknowledge Clock

Acknowledge Signal from Receiver

3...6

7

9

1

8

2

S

Start

Condition

Figure 53. Acknowledge Signal

36

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Programming (continued)

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy, and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

SDA

SCL

S

P

START condition

STOP condition

Figure 54. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

8.5.1.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

8.5.1.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked

out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the

master), but the SDA line is not pulled down.

8.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LM3631 operates as a slave device with the 7-bit

address. If an 8-bit address is used for programming, the 8th bit is '1' for read and '0' for write. The 7-bit address

for the LM3631 is 0x29.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device

should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the

first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the

slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

R/W

bit0

Bit7

bit6

bit5

bit4

bit3

bit2

bit1

I²C SLAVE address (chip address)

Figure 55. I²C Device Address

Submit Documentation Feedback

37

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Programming (continued)

Control Register Write Cycle

•

Master device generates start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master sends data byte to be written to the addressed register.

Slave sends acknowledge signal.

If master sends further data bytes the control register address is incremented by one after acknowledge

signal.

•

Write cycle ends when the master creates stop condition.

Control Register Read Cycle

•

Master device generates a start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal

Master device generates repeated start condition.

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

Slave sends acknowledge signal if the slave address is correct.

Slave sends data byte from addressed register.

If the master device sends acknowledge signal, the control register address is incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

Table 10. I²C Data Read/Write⁽¹⁾

ADDRESS MODE

<Slave Address><r/w =0>[Ack]

<Register Addr>[Ack]

<Slave Address><r/w = 1>[Ack]

Data Read

[Register Data]<Ack or NAck>

...additional reads from subsequent register address possible

<Slave Address><r/w = 0>[Ack]

<Register Addr>[Ack]

<Register Data>[Ack]

Data Write

...additional writes to subsequent register address possible

(1) < > = Data from master, [ ] = Data from slave

38

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

ack from slave

start MSB Chip id LSB

w

ack MSB Register Addr LSB ack MSB

Data

LSB ack stop

SCL

SDA

start

id = 010 1001b

w

ack

address = 02H

ack

address 02H data

ack stop

Figure 56. Register Write Format

When a READ function is to be accomplished, a WRITE function must precede the READ function, as show in

the Read Cycle waveform.

ack from slave

ack from slave repeated start

ack from slavedata from slave nack from master

Register

Addr

start MSB Chip id LSB

w

MSB

LSB

rs MSB Chip Address LSB

r

MSB Data LSB

stop

SCL

SDA

start

id = 010 1001b

w

ack

address = 00H

ack rs

id = 010 1001b

r ack address 00H data nack stop

Figure 57. Register Read Format

NOTE

w = write (SDA = 0), r = read (SDA = 1), ack = acknowledge (SDA pulled down by either

master or slave), rs = repeated start id = 7-bit chip address

Submit Documentation Feedback

39

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

8.6 Register Maps

Table 11. Device Control Register (0x00)

[Bit 1]

LCD_EN

[Bit 0]

BL_EN

[Bit 7]

[Bit 6]

[Bit 5]

[Bit 4]

[Bit 3]

[Bit 2]

0 = LCD

disabled

1 = LCD

enabled

0 = Backlight

disabled

1 = Backlight

enabled

Not Used

Table 12. LED Brightness Register LSB (0x01)

[Bits 2:0]

Brightness LSB

[Bit 7]

[Bit 6]

[Bit 5]

[Bit 4]

[Bit 3]

BRT[2:0]. Lower 3 bits (LSB's) of brightness code.

Concatenated with brightness bits in Register 0x02

(MSB).

Not Used

Table 13. LED Brightness Register MSB (0x02)

[Bits 7:0] Brightness MSB

BRT[10:3]. Upper 8 bits (MSB's) of brightness code. Concatenated with brightness bits in Register 0x01 (LSB).

Table 14. Faults Register (0x03)

[Bit 2]

[Bit 1]

[Bit 7]

BL_SCFLT

[Bit 6]

TMPFLT

[Bit 5]

BL_OCPFLT

[Bit 4]

BL_OVPFLT

[Bit 3]

LCD_OVPFLT

[Bit 0]

UVLO FLAG

LDO_OREF_F LDO_VPOS_F

LT

0 = normal

1 = fault,

backlight boost

overvoltage

protection limit protection limit

reached reached

0 = normal

1 = fault, LCD

boost

0 = normal

1 = device has

hit thermal

shutdown

0 = normal

1 = fault,

backlight boost

current limit

reached

0 = normal

1 = fault,

LDO_OREF

short circuit

condition

0 = normal

1 = fault,

LDO_VPOS

short circuit

condition

0 = normal

1 = backlight

short circuit

condition

0 = normal

1 = UVLO

event

overvoltage

threshold

Table 15. Faults and Power-Good Register (0x04)

[Bit 1]

LDO_CONT_F

LT

[Bit 3]

[Bit 2]

[Bit 0]

PG_FLAG

[Bit 7]

[Bit 6]

[Bit 5]

[Bit 4]

NEG_CP_SC NEG_CP_OVP

0 = normal

1 = fault,

0 = normal

1 = fault, LDO

Controller

current limit

reached

1 = fault,

negative

Power-Good

flag

Not Used

chargepump

overvoltage

short circuit

protection limit

condition

reached

Table 16. Backlight Configuration (Auto Frequency Threshold) Register 1 (0x05)

[Bits 7:0]

AUTO_FREQ_THRES

LED current threshold value. When the Auto Frequency Select Mode Bit is ‘1’ (Bit[3] in register 0x07), the 8 bit code in this register

(AUTOFREQ_THRESH) is compared against the MSB’s of the I²C Brightness code (BRT [10:3]), and this comparison is used to determine

whether the device operates in Low Frequency or High Frequency Mode.

1. When BRT[10:3] > AUTOFREQ_THRESH[7:0] , the Boost Frequency Select Bit is automatically set to ‘1’ forcing the device into High

Frequency Mode.

2. When BRT[10:3] ≤ AUTOFREQ_THRESH[7:0], the Boost Frequency Select Bit automatically set to ‘0’ and the device operates in Low

Frequency Mode.

40

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

[Bit 7]

SNVS834 –AUGUST 2014

Table 17. Backlight Configuration Register 2 (0x06)

[Bit 5]

LINEAR_MAP

PER

[Bit 3]

STRING_MOD

E

[Bit 2]

INDUCTOR

[Bits 1:0]

PEAK_CURR_LIM

[Bit 6]

[Bit 4]

0 = Inductor

typical value =

22 µH

1 = Inductor

typical value =

10 µH

0 = Both LED

strings enabled

1 = Only LED

string 1

0= Exponential

mapping in use

1 = Linear

00 = 600 mA

01 = 700 mA

10 = 800 mA

11 = 900 mA

Not Used

mapping in use

enabled

Table 18. Backlight Configuration Register 3 (0x07)

[Bit 0]

BL_BST_FRE

Q

[Bits 7:6]

SEL_I

[Bits 5:4]

SEL_P

[Bit 3]

BL_AUTOFRQ

[Bits 2:1]

BL_BST_OVP

0 = Manual

frequency

mode

1 = Auto

frequency

mode

Backlight Boost OVP target

00 = 17 V

Backlight boost compensator

adjustment. Select value

according to number of LEDs in

LED string.

Backlight Boost

frequency

0 = 500 kHz

1 = 1 MHz

Backlight boost compensator

adjustment. Select value

according to inductor

01 = 21 V

10 = 25 V

11 = 29 V

Table 19. Backlight Configuration Register 4 (0x08)

[Bit 7]

PWM_EDGE_D

ET_SEL

[Bit 6]

PWM

POLARITY

[Bit 1]

[Bit 0]

[Bits 5:4]

HYSTERESIS

[Bits 3:2]

BRT_MODE

EN__ADV_SL DISABLE_DIT

OPE

HER

PWM edge

detection

selection

Brightness mode selection

00 = I²C register used for

brightness control

PWM input hysteresis selection

(change in 11-bit brightness)

00 = 0.05% shift causes change

0 = PWM active

polarity LOW

0 = Advanced

slope disabled

1 = Advanced

slope enabled

0 = Dither

enabled

1 = Dither

disabled

0 = PWM

01 = PWM input duty cycle used

for brightness control

measured from

rising edge

1 = PWM

measured from

falling edge

1 = PWM active 01 = 0.1% shift causes change

10 = I²C code multiplied with

PWM duty cycle before sloping

11 = Sloped I²C brightness code

multiplied with PWM duty cycle

polarity HIGH

10 = 0.2% shift causes change

11 = 0.4% shift causes change

Table 20. Backlight Configuration Register 5 (0x09)

[Bits 7:4]

SLOPE

[Bits 3:0]

DITHER_FREQ_SEL

0000 = Slope function disabled, immediate brightness change

0001 = 1 ms

0010 = 2 ms

0011 = 5 ms

0100 = 10 ms

0101 = 20 ms

0110 = 50 ms

0111 = 100 ms

1000 = 250 ms

1001 = 500 ms

Dithering frequency selection

0000 = 62.5 kHz

0001 = 31.3 kHz

0010 = 15.6 kHz

0011 = 7.8 kHz

0100 = 3.9 kHz

0101 = 1.95 kHz

0110 = 977 Hz

1010 = 750 ms

0111 = 488 Hz

1000 = 244 Hz

1001 = 122 Hz

1011 = 1000 ms

1100 = 1500 ms

1101 = 2000 ms

1110 = 3000 ms

1111 = 4000 ms

Submit Documentation Feedback

41

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Table 21. LCD Configuration Register 1 (0x0A)

[Bit 6]

[Bit 5]

[Bit 4]

[Bit 3]

[Bit 2]

[Bit 0]

LDO_OREF_E

N

[Bit 1]

CP_VNEG_EN

[Bit 7]

LDO_CONT_S LDO_OREF_S CP_VNEG_SD LDO_VPOS_S LDO_VPOS_E

D_PULLDN

_PULLUP

D_PULLDN

N

0 =

LDO_CONT

pull-down

resistor

disabled

1 =

LDO_CONT

pull-down

resistor

LDO_OREF

pull-down

resistor

disabled

1 =

LDO_OREF

pull-down

resistor

LDO_VPOS

pull-down

resistor

disabled

1 =

LDO_VPOS

pull-down

resistor

0 = CP_VNEG

pull-up resistor

disabled

1 = CP_VNEG

pull-up resistor

enabled

0 =

LDO_VPOS

disabled

1 =

LDO_VPOS

enabled

0 = CP_VNEG

disabled

1 = CP_VNEG

enabled

LDO_OREF

disabled

1 =

LDO_OREF

enabled

Not Used

enabled

Table 22. LCD Configuration Register 2 (LDO_CONT) (0x0B)

[Bit 0]

LDO_CONT_E

N

[Bits 6:4]

LDO_CONT_SU_DELAY

[Bits 3:1]

LDO_CONT_SD_DELAY

[Bit 7]

LDO_CONT start-up delay

000 = 0 ms

LDO_CONT shutdown delay

000 = 0 ms

0 =

001 = 2 ms

010 = 5 ms

011 = 10 ms

100 = 20 ms

101 = 50 ms

110 = 100 ms

111 = 200 ms

001 = 2 ms

010 = 5 ms

011 = 10 ms

100 = 20 ms

101 = 50 ms

110 = 100 ms

111 = 200 ms

LDO_CONT

disabled

1 =

LDO_CONT

enabled

Not Used

Table 23. LCD Configuration Register 3 (0x0C)

[Bits 7:6]

[Bits 5:0]

LDO_CONT_VOUT

LCD_BST_OUT

LCD Boost output voltage

000 000 = 4.50 V

000 001 = 4.55 V

000 010 = 4.60 V

000 011 = 4.65 V

000 100 = 4.70 V

...

LDO_CONT output voltage

00 = 1.8 V

010 111 = 5.65 V

011 000 = 5.70 V

011 001 = 5.75 V

...

01 = 2.3 V

10 = 2.8 V

11 = 3.3 V

100 001 = 6.15 V

100 010 = 6.20 V

100 011 = 6.25 V

100 100 = 6.30 V

100 101 = 6.35 V

42

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Table 24. LCD Configuration Register 4 (LDO_VPOS) (0x0D)

[Bits 5:0]

LDO_VPOS_TARGET

[Bit 7]

[Bit 6]

000 000 = 4.00 V

000 001 = 4.05 V

000 010 = 4.10 V

000 011 = 4.15 V

000 100 = 4.20 V

...

011 011 = 5.35 V

011 100 = 5.40 V

011 101 = 5.45 V

...

Not Used

100 100 = 5.80 V

100 101 = 5.85 V

100 110 = 5.90 V

100 111 = 5.95 V

101 000 = 6.00 V

(6.00V is the maximum level regardless of the adjustment level above value '101 000')

Table 25. LCD Configuration Register 5 (CP_VNEG) (0x0E)

[Bits 5:0]

CP_VNEG_TARGET

[Bit 7]

[Bit 6]

000 000 = –4.00 V

000 001 = –4.05 V

000 010 = –4.10 V

000 011 = –4.15 V

000 100 = –4.20 V

...

011 011 = –5.35 V

011 100 = –5.40 V

011 101 = –5.45 V

Not Used

...

100 100 = –5.80 V

100 101 = –5.85 V

100 110 = –5.90 V

100 111 = –5.95 V

101 000 = –6.00 V

(–6.00V is the maximum level regardless of the adjustment level above value '101 000')

Table 26. LCD Configuration Register 6 (LDO_OREF) (0x0F)

[Bits 5:0]

LDO_OREF_TARGET

[Bit 7]

[Bit 6]

000 000 = 4.00 V

000 001 = 4.05 V

000 010 = 4.10 V

000 011 = 4.15 V

000 100 = 4.20 V

...

011 011 = 5.35 V

011 100 = 5.40 V

011 101 = 5.45 V

Not Used

...

100 100 = 5.80 V

100 101 = 5.85 V

100 110 = 5.90 V

100 111 = 5.95 V

101 000 = 6.00 V

(6.00V is the maximum level regardless of the adjustment level above value '101 000')

Submit Documentation Feedback

43

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Table 27. LCD Configuration Register 7 (LDO_VPOS Sequence Control) (0x10)

[Bits 7:4]

[Bits 3:0]

LDO_VPOS START-UP DELAY

LDO_VPOS SHUTDOWN DELAY

0000 = 0.0 ms

0001 = 1.0 ms

0010 = 2.0 ms

0011 = 3.0 ms

0100 = 4.0 ms

0101 = 5.0 ms

0110 = 6.0 ms

0111 = 7.0 ms

1000 = 8.0 ms

1001 = 9.0 ms

1010 = 10.0 ms

1011 = 11.0 ms

1100 = 12.0 ms

1101 = 13.0 ms

1110 =14.0 ms

1111 = 15.0 ms

0000 = 0.0 ms

0001 = 1.0 ms

0010 = 2.0 ms

0011 = 3.0 ms

0100 = 4.0 ms

0101 = 5.0 ms

0110 = 6.0 ms

0111 = 7.0 ms

1000 = 8.0 ms

1001 = 9.0 ms

1010 = 10.0 ms

1011 = 11.0 ms

1100 = 12.0 ms

1101 = 13.0 ms

1110 =14.0 ms

1111 = 15.0 ms

Table 28. LCD Configuration Register 8 (CP_VNEG Sequence Control) (0x11)

[Bits 7:4]

[Bits 3:0]

CP_VNEG START-UP DELAY (ms)

CP_VNEG SHUTDOWN DELAY (ms)

0000 = 0.0 ms

0001 = 1.0 ms

0010 = 2.0 ms

0011 = 3.0 ms

0100 = 4.0 ms

0101 = 5.0 ms

0110 = 6.0 ms

0111 = 7.0 ms

1000 = 8.0 ms

1001 = 9.0 ms

1010 = 10.0 ms

1011 = 11.0 ms

1100 = 12.0 ms

1101 = 13.0 ms

1110 =14.0 ms

1111 = 15.0 ms

0000 = 0.0 ms

0001 = 1.0 ms

0010 = 2.0 ms

0011 = 3.0 ms

0100 = 4.0 ms

0101 = 5.0 ms

0110 = 6.0 ms

0111 = 7.0 ms

1000 = 8.0 ms

1001 = 9.0 ms

1010 = 10.0 ms

1011 = 11.0 ms

1100 = 12.0 ms

1101 = 13.0 ms

1110 =14.0 ms

1111 = 15.0 ms

Table 29. LCD Configuration Register 9 (LDO_OREF Sequence Control) (0x12)

[Bits 7:4]

[Bits 3:0]

LDO_OREF START-UP DELAY

LDO_OREF SHUTDOWN DELAY

0000 = 0.0 ms

0001 = 1.0 ms

0010 = 2.0 ms

0011 = 3.0 ms

0100 = 4.0 ms

0101 = 5.0 ms

0110 = 6.0 ms

0111 = 7.0 ms

1000 = 8.0 ms

1001 = 9.0 ms

1010 = 10.0 ms

1011 = 11.0 ms

1100 = 12.0 ms

1101 = 13.0 ms

1110 =14.0 ms

1111 = 15.0 ms

0000 = 0.0 ms

0001 = 1.0 ms

0010 = 2.0 ms

0011 = 3.0 ms

0100 = 4.0 ms

0101 = 5.0 ms

0110 = 6.0 ms

0111 = 7.0 ms

1000 = 8.0 ms

1001 = 9.0 ms

1010 = 10.0 ms

1011 = 11.0 ms

1100 = 12.0 ms

1101 = 13.0 ms

1110 =14.0 ms

1111 = 15.0 ms

44

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Table 30. FLAG Configuration Register (0x13)

[Bit 4]

[Bits 3:2]

[Bits 1:0]

PG_FLAG_CONFIG

[Bit 7]

[Bit 6]

[Bit 5]

FLAG_PIN_POLAR

PG_FLAG_CTRL

ITY

00 = Power-Good set after last

supply reaches target

01 = Power-Good set after

LDO_VPOS

10 = Power-Good set after

CP_VNEG

11 = Power-Good set after

LDO_OREF

00 = FLAG disabled, no flag

indication

01 = Power-Good state, selectable

with PG_FLAG_CTRL bits

10 = Backlight ON state

11 = Fault state

0 =FLAG pin active

polarity LOW

1 = FLAG pin active

polarity HIGH

Not Used

Table 31. BOOT/RESET Register (0x14)

[Bit 7:0]

BOOT

Write FFh to set all I²C registers to RESET value

Table 32. Revision Register (0x16)

[Bit 5:3]

OTP

REVISION

[Bit 7:6]

DIE TRACEABILITY

[Bit 2:0]

DEVICE REVISION

Device OTP

Die Traceability Information

Revision

Device Revision Information

Information

Submit Documentation Feedback

45

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

9 Application and Implementation

9.1 Application Information

The LM3631 integrates an LCD backlight driver and LCD positive and negative bias voltage supplies into a single

device. The backlight boost converter generates the high voltage required for the LEDs. The LM3631 can drive

one or two LED strings with 4 to 8 white LEDs per string. Positive and negative bias voltages are post-regulated

from the LCD bias boost output voltage. In addition, for the LCD bias voltages, the device has two programmable

LDO regulator outputs which can be used to the power display controller, the LCD gamma reference, or any

additional peripherals within output-current capability.

LDC bias voltages can be used without the backlight. Pulling LCD_EN high starts the LCD bias boost regulator.

Once the LCD bias boost regulator has started up all voltage outputs can be enabled individually. The LM3631

can also be programmed to enable any voltage outputs automatically per a preset start-up sequence. The

backlight cannot be enabled until enabled bias voltages have settled.

9.2 Typical Application

L1

10/22µH

D1

C2

C6

C1

C7

10µF

0.1µF

2.2µF

100pF

SW

VOUT

LED1

LED2

VIN

C3

0.1µF

L2

1.5µH

Up to 8 LEDs / string

BST_SW

C4

10µF

C5

0.1µF

+

-

V

BST_OUT

IN

2.7V ± 5.0V

C8

C9

10µF

100pF

LM3631

SDA

SCL

SDA

C2

C1

C10

10µF

SCL

nRST

LCD_EN

PWM

V

(-5.4V)

NEG

CP_VNEG

LDO_OREF

LDO_VPOS

LDO_CONT

LCD_EN

PWM

(+4.0V to +6.0V)

OREF

(+5.4V)

POS

FLAG

(+1.8V)

CONT

OTP_SEL

C11

10µF

C12

C13

10µF

C14

10µF

GND_BST_SW

AGND

GND_SW

PGND

Figure 58. Typical Application Schematic

46

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

Typical Application (continued)

9.2.1 Design Requirements

Example requirements based on default register values (OTP_SEL = 1):

DESIGN PARAMETER

EXAMPLE VALUE

Input Voltage Range

Brightness Control

2.7 V to 4.5 V (Single Li-Ion cell battery)

I²C Register

LED Configuration

2 parallel, 6 series

LED Current

max 25 mA / string

Backlight Boost maximum voltage

Backlight boost SW frequency

Backlight Boost inductor

LCD boost output voltage

V_NEGoutput voltage

28 V

1MHz

10-µH, 900-mA saturation current

5.9 V

–5.4 V

V_POSoutput voltage

5.4 V

V_OREFoutput voltage

V_CONToutput voltage

LCD Boost inductor

5.6 V

1.8 V

1.5-µH, 1-A saturation current

9.2.2 Detailed Design Procedure

9.2.2.1 External Components

Table 33 shows examples of external components for the LM3631. Small 100-pF ceramic capacitors parallel with

boost-converter-output capacitors are optional and are used to reduce high-frequency noise generated by the

boost converters. Boost-converter dual-output capacitors can be replaced with a single capacitor of higher output

capacitance as long as the minimum effective capacitance requirement is met. DC bias effect of the ceramic

capacitors must be taken into consideration when choosing the output capacitors. This is especially true for the

high output-voltage backlight-boost converter.

Table 33. Recommended External Components

DESIGNATOR

(Figure 58)

DESCRIPTION

VALUE

EXAMPLE

NOTE

C1, C4, C8,

C10, C11, C12,

C13, C14

10 µF, 10V or

16V

Ceramic capacitor

EMK107BBJ106MA-T

C2, C3, C5

Ceramic capacitor

0.1 µF, 10V

GRM188R71H104KA93D

C2012X5R1H225K

2.2 µF, 35V or

50V

C6

Optional, only for HF interference

reduction.

C7, C9

L1

Ceramic capacitor

Inductor

100 pF, 50V

06035A101JAT2A

22 or 10 µH,

900mA

VLF403210MT-100M or 1235AS-

H-220M

L2

Inductor

1.5 µH

DFE252010R-H-1R5M

NSR0240P2T5G

D1

Schottky diode

40V, 200mA

9.2.2.2 Inductor Selection

Both of the LM3631 boost converters are internally compensated. The compensation parameters of the LCD bias

boost converter are fixed and set for a 1.5-µH inductor. The backlight boost converter has a selection bit to

choose between 10-µH or 22-µH inductors. The inductor typical inductance is selected with the INDUCTOR bit

(Register 0x06, bit 2). Effective inductance of the inductors should be ±20%.

Submit Documentation Feedback

47

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

There are two main considerations when choosing an inductor: the inductor should not saturate, and the inductor

current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current

rating specifications are followed by different manufacturers so attention must be given to details. Saturation

current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of

application should be requested from the manufacturer. The saturation current should be greater than the sum of

the maximum load current and the worst-case average-to-peak inductor current. The equation below shows the

worst case conditions.

I_OUTMAX

I_SAT

>

+ I_RIPPLE

'¶

V_IN

(V_OUT± V_IN)

x

Where I_RIPPLE

=

V_OUT

(2 x L x f)

(V_OUT± V_IN)

V_OUT

DQGꢀ'¶ꢀ= (1 - D)

Where D =

where

•

I_RIPPLE= peak inductor current

I_OUTMAX= maximum load current

V_IN= minimum input voltage in application

L = minimum inductor value including worst case tolerances

f = minimum switching frequency

V_OUT= output voltage

(7)

As a result the inductor should be selected according to the I_SAT. A more conservative and recommended

approach is to choose an inductor that has a saturation current rating greater than the maximum current limit.

The inductor’s resistance should be kept small for good efficiency.

See detailed information in “Understanding Boost Power Stages in Switch Mode Power Supplies”

http://focus.ti.com/lit/an/slva061/slva061.pdf. “Power Stage Designer™ Tools” can be used for the boost

calculation: http://www.ti.com/tool/powerstage-designer.

9.2.2.3 Boost Output Capacitor Selection

Two 2.2-μF capacitors are recommended for the backlight boost converter output capacitors. A single 2.2-μF

capacitor can be used for reducing solution size as long as the effective output capacitance is higher than 1 µF.

A high-quality ceramic type X5R or X7R is recommended. Voltage rating must be greater than the maximum

output voltage that is used.

For the LCD-bias-boost output two 10-μF capacitors are recommended. A high-quality ceramic type X5R or X7R

is recommended. Voltage rating must be greater than the maximum output voltage that is used.

The DC-bias effect of the capacitors must be taken into consideration when selecting the output capacitors. The

effective capacitance of a ceramic capacitor can drop down to less than 10% with maximum rated DC bias

voltage depending on capacitor type. Note that with a same voltage applied, the capacitors with higher voltage

rating suffer less from the DC-bias effect than capacitors with lower voltage rating.

9.2.2.4 Backlight Boost Diode Selection

A Schottky diode should be used for the output diode. Peak repetitive current should be greater than inductor

peak current to ensure reliable operation. Average current rating should be greater than the maximum output

current. Reverse breakdown voltage of the Schottky diode should be significantly larger than the maximum

output voltage.

9.2.2.5 Charge Pump Capacitor Selection

Voltage ratings for the flying capacitor and output capacitor must be higher than the maximum output voltage.

Ceramic X5R/X7R capacitors are recommended. 10-V voltage rating and 10 µF capacitors are recommended for

both.

48

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

9.2.2.6 LDO Output Capacitor Selection

Voltage ratings for the LDO output capacitors must be higher than the maximum output voltage. Ceramic

X5R/X7R capacitors are recommended. 10-V voltage rating and 10-µF capacitors are recommended for all.

9.2.3 Application Curves

Figure 59 and Figure 60 show typical backlight start-up and shutdown curves using the LCD_EN pin control.

LCD_EN

2V/DIV

LCD_EN

2V/DIV

V_OUT

10V/DIV

V_OUT

10V/DIV

I_OUT

10V/DIV

I_OUT

10V/DIV

1ms/DIV

Figure 60. Backlight Shutdown with LCD_EN Pin Control

Figure 59. Backlight Start-up with LCD_EN Pin Control

Figure 61 and Figure 62 show the default start-up and shutdown waveforms with OTP_SEL = GND. LDO_CONT

pulldown is disabled by default causing V_CONTto float after shutdown.

V_BST

5V/DIV

V_BST

5V/DIV

V_CONT

5V/DIV

V_CONT

5V/DIV

V_POS

5V/DIV

V_POS

5V/DIV

V_NEG

5V/DIV

V_NEG

5V/DIV

2ms/DIV

Figure 61. Default LCD Bias Startup, OTP_SEL = GND.

Figure 62. Default LCD Bias Shutdown, OTP_SEL = GND.

10 Power Supply Recommendations

The LM3631 is designed to operate from an input voltage supply range between 2.7 V and 5 V. This input supply

must be well regulated and capable to supply the required input current. If the input supply is located far from the

LM3631 additional bulk capacitance may be required in addition to the ceramic bypass capacitors.

11 Layout

11.1 Layout Guidelines

•

Place the boost converters output capacitors as close to the output voltage and GND pins as possible.

Minimize the boost converter switching loops by placing the input capacitors and inductors close to GND and

switch pins.

•

If possible, route the switching loops on top layer only. For best efficiency, try to minimize copper on the

Submit Documentation Feedback

49

Product Folder Links: LM3631

LM3631

SNVS834 –AUGUST 2014

www.ti.com

Layout Guidelines (continued)

switch node to minimize switch pin parasitic capacitance while preserving adequate routing width.

•

VIN input voltage pin needs to be bypassed to ground with a low-ESR bypass capacitor. Place the capacitor

as close to VIN pin as possible

Place the output capacitors of the LDOs as close to output pins as possible. Also place the charge pump

flying capacitor and output capacitor close to respective pins.

Route the internal pins on the second layer. Use offset micro vias to go from top layer to mid layer1. Avoid

routing the signal traces directly under the switching loops of the boost converters.

11.2 Layout Example

L1

VIAs to VIN plane

D1

C1

C2

Route the

switching loops on

top layer if possible

C7

C6

GND

VOUT

GND on Top layer.

Connect to internal

ground plane with

multible VIAs

GND_

SW

nRST

FLAG

SCL

VOUT

LED1

LED2

AGND

LED1

C3

LCD_

EN

VIN

LED2

GND

GND_

BST_

SW

OTP_

SEL

BST_

SW

LDO_

CONT

LDO_

VPOS

C12

C13

C11

L2

C4

C5

C9

C8

BST_

OUT

LDO_

OREF

SDA

PWM

C2

VIAs to VIN plane

CP_

VNEG

C1

PGND

Route LDO_CONT

on internal layer

C10

GND

C14

50

Submit Documentation Feedback

Product Folder Links: LM3631

LM3631

www.ti.com

SNVS834 –AUGUST 2014

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Trademarks

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Documentation Feedback

51

Product Folder Links: LM3631

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jun-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM3631YFFR

DSBGA

YFF

24

3000

180.0

8.4

2.1

2.76

0.81

4.0

8.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jun-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

DSBGA YFF 24

SPQ

Length (mm) Width (mm) Height (mm)

182.0 182.0 20.0

LM3631YFFR

3000

Pack Materials-Page 2

D: Max = 2.585 mm, Min =2.524 mm

E: Max = 1.885 mm, Min =1.825 mm

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM3631YFFR
厂家：	TEXAS INSTRUMENTS
描述：	适用于 LCD 面板的集成式 WLED 背光驱动器和偏置电源 \| YFF \| 24 \| -40 to 85 驱动 CD 驱动器
文件：	总56页 (文件大小：1547K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM3631YFFR [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E