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LM3632A

ZHCSDN2 –APRIL 2015

LM3632A 集成单芯片背光、偏置电源和 1.5A 闪光灯 LED 驱动器

1 特性

3 说明

1

•

可驱动多达两个灯串（通常为 8 个串联的 LED）

LM3632A 器件集成了用于 LCD 面板背光照明和摄像

机闪光灯的白光发光二极管 (WLED) 驱动器以及用于

LCD 面板的偏置电源。该器件具备 LED 驱动器所需

的全套安全功能，并且效率高达 90%，正/负偏置电源

轨精度高达 1.5%。该器件最多能够驱动 16 个背光

LED，是中小型显示屏的理想选择。该器件可使用由

同步升压转换器供电的 1.5A 恒流 LED 驱动器来驱动

闪光灯。高侧闪光灯电流源支持 LED 阴极接地操作。

–

集成背光升压转换器，最高输出电压达 29V

两个低侧恒流 LED 驱动器，最高输出电流达

25mA

•

背光效率高达 90%

11 位指数或线性调光

具有外部脉宽调制 (PWM) 输入，可实现内容自适

应背光控制 (CABC) 背光操作

•

LCD 偏置电源效率 > 85%

LM3632A 兼具高集成度和可编程性，无需修改硬件即

可适应各类应用。

可编程的正 LCD 偏置电源（4V 至 6V），最大输

出电流达 50mA

器件信息⁽¹⁾

•

可编程的负 LCD 偏置电源（-6V 至 -4V），最大输

出电流达 50mA

器件型号

LM3632A

封装

封装尺寸（最大值）

•

1.5A 闪光灯 LED 升压转换器

闪光灯效率 > 85%

DSBGA (30)

2.47mm x 2.07mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

输入电压范围：2.7V 至 5V

空白

2 应用

•

智能手机 LCD 背光照明和偏置电源

小型平板电脑 LCD 背光照明和偏置电源

简化电路原理图

背光效率，2P7S

D1

L_BL

95

90

85

80

75

70

65

L_FL

C_{BL_OUT}

C_IN

FL_SW FL_SW

BL_SW

BL_OUT

BLED1

BLED2

VIN

L_LCM

V_BATT

LCM_SW

Up to 8 LEDs / String

SCL

FL_OUT

SDA

60

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

C_{FL_OUT}

STROBE

TX

55

50

FLED

LM3632

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

PWM

D007

C1

C2

EN

C_FLY

LCM_EN1

LCM_EN2

LCM_OUT

VPOS

C_LCM

C_VPOS

AGND

VNEG

BL_GND CP_GND FL_GND LCM_GND

C_VNEG

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSA63

LM3632A

ZHCSDN2 –APRIL 2015

www.ti.com.cn

7.4 Device Functional Modes........................................ 26

7.5 Programming........................................................... 26

7.6 Register Maps......................................................... 31

Application and Implementation ........................ 39

8.1 Application Information............................................ 39

8.2 Typical Application .................................................. 39

Power Supply Recommendations...................... 53

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information ................................................. 4

6.5 Electrical Characteristics .......................................... 5

6.6 I²C Timing Requirements (SDA, SCL) ..................... 8

6.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 13

7.3 Features Description............................................... 14

8

9

10 Layout................................................................... 53

10.1 Layout Guidelines ................................................ 53

10.2 Layout Example ................................................... 54

11 器件和文档支持 ..................................................... 55

11.1 器件支持................................................................ 55

11.2 文档支持................................................................ 55

11.3 商标....................................................................... 55

11.4 静电放电警告......................................................... 55

11.5 术语表 ................................................................... 55

12 机械、封装和可订购信息....................................... 55

7

4 修订历史记录

日期

修订版本

注释

2015 年 4 月

*

最初发布。

2

LM3632A

www.ti.com.cn

ZHCSDN2 –APRIL 2015

5 Pin Configuration and Functions

YFF Package

30-Pin DSBGA

Top View

A

B

C

D

E

F

1

2

3

4

5

Pin Functions

TYPE

DESCRIPTION

NUMBER

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

C1

C2

C3

C4

C5

D1

D2

D3

D4

D5

E1

E2

E3

E4

E5

F1

NAME

VPOS

O

-

Positive LDO output for LCM bias power

LCM bias boost output voltage

LCM_OUT

LCM_SW

BL_GND

BL_SW

LCM_EN2

LCM_EN1

EN

LCM bias boost switch connection

Backlight boost ground connection

Backlight boost switch connection

Enable for inverting charge pump output

Enable for positive LDO output

O

I

Active high chip enable

LCM_GND

BL_OUT

C1

-

LCM bias boost ground connection

Backlight boost output voltage

O

I/O

I

Inverting charge pump flying capacitor positive connection

Serial data connection for I²C- compatible interface

Flash interrupt input

SDA

TX

AGND

BLED1

CP_GND

SCL

-

Analog ground connection

O

-

Input pin to internal LED current sink 1

Inverting charge pump ground connection

Serial clock connection for I²C- compatible interface

Flash enable input

I

STROBE

PWM

I

PWM input for CABC current control

Input pin to internal LED current sink 2

Inverting charge pump flying capacitor negative connection

High-side current source output for flash LED

Flash boost output voltage

BLED2

C2

O

I

FLED

FL_OUT

FL_SW

VIN

Flash boost switch connection

Input voltage connection

VNEG

O

-

Inverting charge pump output voltage

High-side current source output for flash LED

Flash boost output voltage

F2

FLED

F3

FL_OUT

FL_SW

FL_GND

F4

Flash boost switch connection

F5

Flash boost ground connection

3

LM3632A

ZHCSDN2 –APRIL 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Voltage on VIN, FL_SW, FL_OUT, FLED, EN, LCM_EN1, LCM_EN2, PWM, STROBE, TX,

SCL, SDA

–0.3

6

V

Voltage on LCM_SW, LCM_OUT, VPOS, C1

Voltage on VNEG, C2

–0.3

–7

7

V

0.3

30

Voltage on BL_SW, BL_VOUT, BLED1, BLED2

Continuous power dissipation

–0.3

Internally limited

Maximum junction temperature, T_J(MAX)

Storage temperature, T_stg

150

°C

–45

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

MIN

MAX

5

UNIT

V

Input voltage, V_IN

2.7

(1)

Operating ambient temperature, T_A

–40

85

°C

(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125ºC), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA× P_D-MAX).

6.4 Thermal Information

LM3632A

THERMAL METRIC⁽¹⁾

YFF (DSBGA)

UNIT

30 PINS

58.6

0.2

R_θJA

R_θJC

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

8.3

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

1.4

Ψ_JB

8.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

4

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ZHCSDN2 –APRIL 2015

6.5 Electrical Characteristics

Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ T_A≤ 85°C), V_IN= 3.7 V,

V_VPOS= 5.5 V, V_VNEG= –5.4 V, V_{LCM_OUT}= 6 V.

PARAMETER

CURRENT CONSUMPTION

TEST CONDITION

MIN

TYP

MAX

UNIT

I_SD

Shutdown current

EN = 0

1

2

4

µA

Quiescent current, device not

switching

I_Q

EN = V_IN, LCD bias boost disabled

LCD bias boost enabled, no-load

10

I_{LCD_EN}

0.5

mA

DEVICE PROTECTION

TSD

Thermal shutdown

140

°C

BACKLIGHT LED CURRENT SINKS

Maximum output current in

BLED1/2

2.7 V ≤ V_IN≤ 5 V, linear or exponential

mode

mA

µA

I_{LED_MAX}

I_{LED_MIN}

I_ACCU

25

50

Minimum output current in

BLED1/2

2.7 V ≤ V_IN≤ 5 V, linear or exponential

mode

2.7 V ≤ V_IN≤ 5 V, 50 µA ≤ I_LED≤ 25

mA, linear or exponential mode

LED current accuracy⁽¹⁾

-3%

-2%

0.1%

3%

2%

LED1 to LED2 current

matching⁽¹⁾

2.7 V ≤ V_IN≤ 5 V, 300 µA ≤ I_LED≤ 25

mA, linear or exponential mode

I_MATCH

BACKLIGHT BOOST CONVERTER

Backlight boost output

V_{OVP_BL}

2.7 V ≤ V_IN≤ 5 V, 29 V option

28

28.75

87%

29.5

V

overvoltage protection

I_LED= 5 mA/string, V_IN= 3.7 V

Efficiency

Typical efficiency⁽²⁾

(2 x 7 LEDs), (P_OUT/P_IN

)

I_LED= 25 mA

250

100

30

mV

Regulated current sink

headroom voltage

V_HR

I_LED= 5 mA

V_{HR_MIN}

Current sink minimum headroom I_LED= 95% of nominal, I_LED= 5 mA

voltage

R_DSON

NMOS switch on resistance

NMOS switch current limit

I_SW= 100 mA

0.25

1000

500

Ω

I_CL

2.7 V ≤ V_IN≤ 5 V

900

450

900

1100

550

mA

ƒ_{SW_BLBOOST}

500-kHz mode

1-MHz mode

Switching frequency

kHz

1000

94%

1100

D_MAX

Maximum duty cycle

LCM BIAS BOOST CONVERTER

LCM bias boost output

overvoltage protection

2.7 V ≤ V_IN≤ 5 V

V_{OVP_LCM}

7

V

(3)

ƒ_{SW_LCMBST}

Switching frequency

2500

kHz

V

Bias boost output voltage range

Output voltage step size

4.5

6.4

50

mV

(3)

Peak-to-peak ripple voltage

I_LOAD= 5 mA & 50 mA, C_BST= 10 µF

mVpp

V_IN+ 500 mVp-p AC square wave, Tr =

100 mV/µs, 200 Hz, 12.5 % duty, I_LOAD

= 5 mA, C_IN= 10 µF

V_{LCM_OUT}

LCM_OUT line transient

response

–50

±25

50

mV

(3)

LCM_OUT load transient

response

Load current step 0 mA to 100 mA,

T_RISE/FALL= 100 mA/µs, C_IN= 10 µF

–150

150

mV

mA

(3)

I_{CL_LCMBST}

Valley current limit

1000

(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.

Matching is the maximum difference from the average. For the constant current sinks on the device (BLED1 and BLED2), the following

is determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of both outputs

(AVG). Matching number is calculated: (I_LED1– I_LED2)/(I_LED1+ I_LED2). The typical specification provided is the most likely norm of the

matching figure of all parts. Note that some manufacturers have different definitions in use.

(2) Typical value only for information.

(3) Limits set by characterization and/or simulation only.

5

LM3632A

ZHCSDN2 –APRIL 2015

www.ti.com.cn

Electrical Characteristics (continued)

Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ T_A≤ 85°C), V_IN= 3.7 V,

V_VPOS= 5.5 V, V_VNEG= –5.4 V, V_{LCM_OUT}= 6 V.

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

High-side MOSFET on

resistance

V_IN= V_GS= 5 V, T_A= 25°C

170

R_{DSON_LCMBST}

mΩ

Low-side MOSFET on

Resistance

V_IN= V_GS= 5 V, T_A= 25°C

290

V_{LCM_OUT}= 6 V, 5 mA < I_LCMBST< 100

mA

(2)

EFF_LCMBST

t_{ST_LCMBST}

Efficiency

92%

Start-up time (LCM_OUT),

V_{LCM_OUT}= 10% to 90%

C_{LCM_BST}= 10 µF

1000

6

µs

(3)

DISPLAY BIAS POSITIVE OUTPUT (VPOS)

Programmable output voltage

range

4

V

Output voltage step size

Output voltage accuracy

50

mV

Output voltage = 5.4 V

–1.5%

–50

1.5%

50

V_IN+ 500 mVp-p AC square wave, Tr =

100 mV/µs, 200 Hz, I_LOAD= 25 mA, C_IN

= 10 µF

V_VPOS

(3)

VPOS line transient response

mV

0 to 50 mA load transient, C_VPOS= 10

µF

(3)

VPOS load transient response

–50

50

20

(3)

DC load regulation

0 mA ≤ I_VPOS≤ 50 mA

mV

mA

I_{MAX_VPOS}

I_{CL_VPOS}

Maximum output current

Output current limit

50

80

V_{LCM_OUT}= 6.3 V, V_POS= 5.8 V, C_VPOS

= 10 µF

(3)

I_{RUSH_PK_VPOS}

V_{DO_VPOS}

Peak start-up inrush current

250

100

mA

mV

(4)

VPOS dropout voltage

I_VPOS= 50 mA, V_VPOS= 5.5 V

C_VPOS= 10 µF

500-µs setting

800-µs setting

500

800

Start-up time VPOS, V_VPOS

10% to 90%

=

t_{ST_VPOS}

µs

(3)

Output pull-down resistor

(VPOS)

VPOS disabled

R_{PD_VPOS}

30

80

110

Ω

DISPLAY BIAS NEGATIVE OUTPUT (VNEG)

LCM bias negative charge-pump Below V_VNEGoutput voltage target

output overvoltage protection

V_{OVP_VNEG}

–250

–750

mV

LCM bias negative charge-pump VNEG to CP_GND

output short circuit protection

V_{SHORT_VNEG}

Programmable output voltage

range

–6

–4

V

Output voltage step size

50

mV

Output accuracy

Output voltage = –5.4 V

–1.5%

1.5%

I_LOAD= 5 mA & 50 mA,

C_VNEG= 10 µF

Peak-to-peak ripple voltage⁽³⁾

60

mVpp

mV

V_VNEG

V_IN+ 500 mVp-p AC square wave, 100

mV/µs 200 Hz, 12.5% duty at 5 mA

VNEG line transient response⁽³⁾

VNEG load transient response⁽³⁾

Efficiency⁽²⁾

–50

±25

50

0 to 50 mA load transient,

T_RISE/FALL= 1 µs, C_VNEG= 10 µF

100

mV

V_IN= 3.7 V, V_{LCM_OUT}= 5.8 V,

V_VNEG= –5.4 V, I_VNEG> 5 mA

92%

V_IN= 3.7 V, V_{LCM_OUT}= 5.8 V,

V_VNEG= –5.4 V

I_{MAX_VNEG}

I_{CL_VNEG}

Maximum output current⁽³⁾

Output current limit⁽³⁾

50

75

mA

(4) V_{IN_VPOS}– V_VPOSwhen V_VPOShas dropped 100 mV below target.

6

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ZHCSDN2 –APRIL 2015

Electrical Characteristics (continued)

Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ T_A≤ 85°C), V_IN= 3.7 V,

V_VPOS= 5.5 V, V_VNEG= –5.4 V, V_{LCM_OUT}= 6 V.

PARAMETER

TEST CONDITION

MIN

TYP

350

400

MAX

UNIT

Q1

R_{DSON_VNEG}

Charge FET pump on resistance Q2

Q3

mΩ

Start-up time (V_VNEG), V_VNEG

10% to 90%⁽³⁾

=

V_VNEG= –6 V, C_VNEG= 10 µF

t_{ST_VNEG}

1

ms

R_{PU_VNEG}

Output pullup resistor, VNEG⁽³⁾

VNEG Disabled, V_{LCM_OUT}> 4.8 V

20

40

Ω

FLASH DRIVER BOOST

I_LED

Current source accuracy

1.5-A flash, V_{FL_OUT}= 4 V

ON threshold

1.4

4.85

4.75

1.5

5

1.6

5.1

5

A

V

Output overvoltage protection

trip point

V_OVP

OFF threshold

4.9

Current source regulation

voltage

1.5-A flash, V_{FL_OUT}= 4 V

V_HR

I_CL

275

mV

A

2.45

1.65

2.8

1.9

80

3.15

2.15

Switch current limit

R_NMOS

R_PMOS

NMOS switch on resistance

PMOS switch on resistance

I_NMOS= 1 A

I_PMOS= 1 A

mΩ

100

Input voltage monitor trip

threshold

V_VINM

2.76

2.9

3.04

V

LOGIC INPUTS (PWM, EN, LCM_EN1, LCM_EN2, SCL, SDA, TX, STROBE)

V_IL

V_IH

Input logic low

Input logic high

0

0.4

V_IN

V

1.2

LOGIC OUTPUTS (SDA)

V_OL

Output logic low

2.7 V ≤ V_IN≤ 5 V, I_OL= 3 mA

0

0.4

V

PWM INPUT

ƒ_{PWM_INPUT}

PWM input frequency⁽²⁾

100

6

20000

Hz

µs

PWM sampling frequency = 1 MHz

PWM sampling frequency = 4 MHz

PWM sampling frequency = 1 MHz

PWM sampling frequency = 4 MHz

Minimum PWM ON/OFF time⁽³⁾

1.5

25

3

PWM timeout⁽³⁾

ms

7

LM3632A

ZHCSDN2 –APRIL 2015

www.ti.com.cn

(1)

6.6 I²C Timing Requirements (SDA, SCL)

Over operating free-air temperature range (unless otherwise noted)(see Figure 1).

MIN

NOM

MAX

UNIT

kHz

µs

ƒ_SCL

1

Clock frequency

400

Hold time (repeated) START condition

Clock low time

0.6

1.3

2

µs

3

Clock high time

600

ns

4

Set-up time for a repeated START condition

Data hold time

600

ns

5

50

ns

6

Data set-up time

100

ns

7

Rise time of SDA and SCL

Fall time of SDA and SCL

Set-Up time between a STOP and a START condition

Capacitive load for each bus line

20 + 0.1C_b

15 + 0.1C_b

1.3

300

ns

8

ns

9

µs

C_b

10

200

pF

(1) Limits set by characterization and/or simulation only.

Figure 1. I²C Timing Parameters

8

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ZHCSDN2 –APRIL 2015

6.7 Typical Characteristics

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted.

25

20

15

10

25

20

15

10

5

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

5

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

256

512

768 1024 1280 1536 1792 2048

0

256

512

768 1024 1280 1536 1792 2048

Brightness Code

D017

D018

Figure 2. Backlight LED Current, Linear Control

Figure 3. Backlight LED Current, Exponential Control

0.5

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40qC

T_A= 25qC

T_A= 85qC

0.4

0.3

0.4

0.3

0.2

0.1

0.0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

0

5

10

15

20

25

0

5

10

15

20

25

I_LED(mA)

D019

D020

2p6s LEDs

Figure 4. Backlight LED Current Matching

Figure 5. Backlight LED Current Matching

3.0

2.0

3.0

2.0

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40qC

T_A= 25qC

T_A= 85qC

1.0

0.0

-1.0

-2.0

-3.0

-1.0

-2.0

-3.0

0

256

512

768 1024 1280 1536 1792 2048

0

256

512

768 1024 1280 1536 1792 2048

Brightness Code

D085

D086

2p6s LEDs

Figure 6. Backlight LED Current Accuracy

Figure 7. Backlight LED Current Accuracy

9

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ZHCSDN2 –APRIL 2015

www.ti.com.cn

Typical Characteristics (continued)

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted.

0.6

0.5

0.4

0.3

0.2

0.1

0.0

T_A= -40qC

T_A= 25qC

T_A= 85qC

0.5

0.4

0.3

0.2

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0.1

0.0

0

256

512

768 1024 1280 1536 1792 2048

0

256

512

768 1024 1280 1536 1792 2048

Brightness Code

D021

D022

2p6s LEDs

Figure 8. Backlight LED Current-Step Ratio

Figure 9. Backlight LED Current-Step Ratio

21

20

19

18

17

16

15

14

25

24

23

22

21

20

19

18

17

16

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D023

D024

2p6s LEDs

2p7s LEDs

Figure 10. Backlight Boost Voltage

Figure 11. Backlight Boost Voltage

0.28

0.25

0.22

0.20

0.18

0.15

0.12

0.10

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40qC

T_A= 25qC

T_A= 85qC

0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0

Load (mA)

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Step (DEC)

D025

D026

2p6s LEDs

ƒ = 4 MHz

Figure 12. Backlight Headroom Voltage

Figure 13. Flash LED Current

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Typical Characteristics (continued)

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted.

1.60

1.56

1.52

1.48

1.44

1.40

0.85

T_A= -40qC

T_A= 25qC

T_A= 85qC

T_A= -40qC

T_A= 25qC

T_A= 85qC

0.84

0.83

0.82

0.81

0.80

0.79

0.78

0.77

0.76

0.75

2.7

3.1

3.5

3.9

4.3

4.7

5.1

2.7

3.1

3.5

3.9

4.3

4.7

5.1

V_IN(V)

D027

D028

I_FLED= 1.5 A

ƒ = 4 MHz

I_FLED= 0.8 A

f = 4 MHz

Figure 14. Flash LED Current

Figure 15. Flash LED Current

0.40

0.400

T_A= -40qC

T_A= 25qC

T_A= 85qC

0.395

0.390

0.385

0.380

0.375

0.370

0.365

0.360

0.355

0.350

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

T_A= -40qC

T_A= 25qC

T_A= 85qC

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

2.7

3.1

3.5

3.9

V_IN(V)

4.3

4.7

5.1

Step (DEC)

D030

D029

ƒ = 4MHz

I_FLED= 375 mA

ƒ = 4 MHz

Figure 16. Torch LED Current

Figure 17. Torch LED Current

0.60

T_A= -40qC

T_A= 25qC

T_A= 85qC

0.55

0.50

0.45

0.40

0.35

0.30

0.25

2.7

3.0

3.3

3.6

3.9

4.2

4.5

4.8

V_IN(V)

D031

I_FLED= 1.5 A

ƒ = 4 MHz

V_FLED= 4 V

Figure 18. Flash Headroom Voltage

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7 Detailed Description

7.1 Overview

The LM3632A is a single-chip complete backlight, LCM power and flash solution. The device operates over the

2.7-V to 5-V input voltage range.

The LM3632A can drive up to two LED strings with up to 8 LEDs each (up to 28 V typical), with a maximum of 25

mA per string. The power for the LED strings comes from a integrated asynchronous backlight boost converter

with two selectable switching frequencies to optimize performance or solution area. LED current is regulated by

two low-headroom current sinks. Automatic voltage scaling adjusts the output voltage of the backlight boost

converter to minimize the LED driver headroom voltage. The 11-bit LED current is set via an I²C interface, via a

logic level PWM input, or a combination of both.

The LCM bias power portion of the LM3632A consists of a synchronous LCM bias boost converter, inverting

charge pump, and an integrated LDO. The LCM positive bias voltage V_POS(up to 6 V) is post-regulated from the

LCM bias boost converter output voltage. The LCM negative bias voltage V_NEG(down to –6 V) is generated from

the LCM bias boost converter output using a regulated inverting charge pump.

The flash driver consists of a synchronous boost converter and a 1.5-A constant current LED driver. The high-

side current source allows for grounded cathode LED operation providing flash current up to 1.5 A. An adaptive

regulation method ensures the current source remains in regulation and maximizes efficiency.

The LM3632A flexible control interface consists of an EN active low reset input, LCM_EN1 and LCM_EN2 inputs

for V_POSand V_NEGenable control, PWM input for content adaptive backlight control (CABC), a TX flash interrupt

input, and an I²C-compatible interface.

Additionally, there are two flag registers with flag and status bits. The user can read back these registers and

determine if a fault or warning message has been generated.

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7.2 Functional Block Diagram

BL_SW

BL_OUT

Programmable

Overvoltage Protection

(18 V, 22 V, 25 V, 29 V)

VIN

Reference and

Thermal Shutdown

Programmable

500 kHz/1 MHz Oscillator

BL_GND

Backlight Boost Converter

V

HR

EN

Global Active-low

Reset

Overcurrent

Protection

Feedback

BLED1

BLED2

PWM Detector

With

Backlight LED Control

PWM

Low Pass Filter

1. 11-bit brightness

adjustment

2. Exponential/Linear

Dimming

SDA

SCL

I²C Compatible

Interface

BL LED Drivers

3. LED Current

Ramping

Programmable

2 MHz/4 MHz Oscillator

FL_GND

FL_SW

Programmable

Current Limit

(1.9 A/2.8 A)

Flash Boost Converter

STROBE

TX

V

HR

Feedback

FL_OUT

FLED

Overvoltage

Protection

Flash LED

Control

Programmable

VINM

(8 Levels)

VIN

LCM_EN1

LCM_EN2

LCM Bias

Output Control

VPOS

(LCM Postive Bias)

VPOS

C1

Internal Logic

LCM Boost Converter

C2

VNEG

(LCM Negative Bias)

VNEG

CP_GND

AGND

LCM_SW

LCM_GND

LCM_OUT

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7.3 Features Description

7.3.1 Backlight

The backlight is enabled if the BL_EN bit (bit[0] in reg[0x0A]) is set to ‘1’, at least one of the backlight sink

outputs is enabled (bit[3] and/or bit[4] in reg[0x0A]), and the brightness value is different than 0. When the

brightness value is 0 or the BL_EN bit is ‘0’, the backlight is disabled.

7.3.1.1 Brightness Control

Brightness can be controlled either by the I²C brightness register or a combination of the external PWM control

and the I²C brightness register. The backlight truth table is shown in Table 1.

When controlling brightness through I²C, registers 0x04 and 0x05 are used. Registers 0x04 and 0x05 hold the

11-bit brightness data. Register 0x04 contains the 3 LSBs, and register 0x05 contains the 8 MSBs. The LED

current transitions to the new level after a write is done to register 0x05.

When controlling brightness through I²C, setting the brightness value to '0' shuts down the backlight. When

controlling the brightness with PWM input, if PWM input is low for a certain period of time (25 ms typ.), the

backlight shuts down. When using the combination of a PWM input and the I²C register, either option shuts down

the backlight.

Table 1. Backlight Truth Table

BL_EN

0x0A[0]

BLED1_EN

0x0A[4]

BLED2_EN

0x0A[3]

PWM_EN

0x09[6]

EN PIN

ACTION

0

1

X

0

1

X

0

1

0

1

X

0

1

0

X

0

1

Shutdown

Standby

Bias enable

BLED1 ramp to target current

BLED1 & BLED2 ramp-to-target current

BLED1 ramp to (target current × PWM duty cycle)

BLED1 & BLED2 ramp to (target current × PWM

duty cycle)

1

0

1

BLED1 & BLED2 ramp to (target current × PWM

duty cycle)

7.3.1.1.1 LED Current with PWM Disabled

When LED brightness is controlled from the I²C brightness registers, the 11-bit brightness data directly controls

the LED current in BLED1 and BLED2. LED mapping can be selected as either linear or exponential. When this

mode is selected, setting the PWM input to 0 does not disable the backlight.

With exponential mapping the 11-bit code-to-current response is approximated by the equation:

I_LED= 50 µA × 1.003040572^{I2C BRGT CODE}(for codes > 0)

(1)

Equation 1 is valid for I²C brightness codes between 1 and 2047. Code 0 disables the backlight. The Code-to-

LED current response realizes a 0.304% change in LED current per LSB of brightness code.

Figure 19 and Figure 20 detail the exponential response of the LED current vs. brightness code. Figure 19 shows

the response on a linear Y axis while Figure 20 shows the response on a log Y axis to show the low current

levels at the lower codes.

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25

100

10

20

15

10

5

1

0.1

0.01

0

256

512

768

1024

1280

1536

1792

2048

0

256

512

768

1024

1280

1536

1792

2048

11-Bit Brightness Code

C001

C002

Figure 19. Exponential Response of LED Current vs

Brightness Code

Figure 20. Response of LED Current vs Brightness Code

on a Log Y Axis

With linear mapping the 11-bit code to current response is approximated by the equation:

I_LED= 37.8055 µA + 12.1945 µA × I2C BRGT CODE (for codes > 0)

(2)

Equation 2 is valid for codes between 1 and 2047. Code 0 disables the backlight.

7.3.1.1.2 LED Current with PWM Enabled

When LED brightness is controlled with the combination of I²C register and the PWM duty cycle, the

multiplication result of I²C register value and PWM duty cycle controls the LED current in BLED1 and BLED2.

LED mapping can be selected as either linear or exponential.

With exponential mapping the multiplication result-to-current response is approximated by the equation:

I_LED= 50 µA × 1.003040572^{I2C BRGT CODE × PWM D/C}

(3)

Equation 3 is valid for brightness values other than 0. Brightness value 0 (PWM D/C or I2C BRGT CODE)

disables the backlight.

With linear mapping the PWM duty cycle-to-current response is approximated by the equation:

I_LED= 37.8055 µA + (12.1945 µA × I2C BRGT CODE × PWM D/C)

(4)

Equation 4 is valid for brightness values other than 0. Brightness value 0 (PWM D/C or I2C BRGT CODE)

disables the backlight.

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Up to 8 LEDs/string

with up to 28V

V

BL_OUT

Digital

Domain

Analog

Domain

High Efficiency

Boost Regulator

PWM Disabled

min

I

BLED2

BLED1

2

I C BRT Reg

Sloper

Mapper

Dither

DAC

Driver_1

Driver_2

BL_TRANSIENT_TIME[3:0]

MAPPER_SEL

Figure 21. Brightness Control with PWM Bit Disabled

Up to 8 LEDs/string

with up to 28V

V

BL_OUT

Digital

Domain

Analog

Domain

High Efficiency

Boost Regulator

PWM Enabled

MAPPER_SEL

Mapper

min

I

BLED2

BLED1

2

Sloper

I C BRT Reg

Dither

DAC

Driver_1

Driver_2

BL_TRANSIENT_TIME[3:0]

PWM input signal

PWM

detector

HYSTERESIS

[1:0]

Figure 22. Brightness Control with PWM Bit Enabled

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7.3.1.2 Sloper

The sloper smooths the transition from one brightness value to another. Slope time can be adjusted from 0 ms to

8000 ms with BL_TRANS[3:0] bits (see Table 9 for details). Transient time is used for sloping up and down.

Transient time always remains the same regardless of the amount of change in brightness.

Sloper

Input

Brightness

Time

Brightness

Output

Steady state

Normal

slope

Time

Slope

Time

Figure 23. Sloper

7.3.1.3 Mapper

The mapper block maps the digital word set for the LED driver into current code. The user can select whether

the mapping is exponential or linear with the BLED_MAP bit, register 0x02 bit[4].

Exponential control is tailored to the response of the human eye such that the perceived change in brightness

during ramp up or ramp down is linear.

7.3.1.4 PWM Input

The PWM detector block measures the duty cycle in the PWM pin. The PWM period is measured from the rising

edge to the next rising edge. PWM polarity can be changed with bit PWM_CONFIG, register 0x02 bit[3]. The

sample rate for the PWM input can be set to 1 MHz or 4 MHz with bit PWM_FREQ, register 0x03 bit[2]. The

choice of sample rate depends on three factors:

1. Required PWM resolution (input duty cycle to brightness code, with 11 bits max)

2. PWM input frequency

3. Efficiency

The PWM input block timeout is 25 ms for 1-MHz sampling frequency and 3 ms for 4-MHz sampling frequency,

measured from the last rising edge. This should be taken into account for 0% and 100% brightness settings (for

setting 100% brightness, the high level of PWM input signal should be greater than the PWM input timeout) and

for selecting the minimum PWM input signal frequency.

7.3.1.5 PWM Minimum On/Off Time

The minimum PWM input signal allowed for low and high pulse width is 6 µs for 1-MHz sampling frequency and

1.5 µs for 4-MHz sampling frequency. This should be taken into account when selecting the PWM input signal

frequency and maximum or minimum duty cycle. For example, if the PWM input signal frequency is 2 kHz (500

µs) and the 4-MHz sampling frequency is used, the maximum allowed on-time is: (500 – 1.5) µs = 498.5 µs. The

maximum duty cycle allowed is 100 × (498.5/500) = 99.7%. By comparison, following similar calculations, with a

PWM input signal frequency of 20 kHz the maximum allowed duty cycle is 97%.

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NOTE

If the Minimum Off Time requirement is violated, there may be a range of duty cycle

values in which flickering of the LEDs may occur or the LEDs may turn off completely. As

the duty cycle increases farther and approaches 100%, the LEDs will turn on at full

brightness level. This is due to the algorithm used by the device to detect 100% duty cycle

in conjunction with the minimum low pulse width requirement discussed in this section. To

avoid LED flickering and/or the LEDs turning off at high PWM duty cycles, the PWM

Minimum On/Off Time requirement should be met.

7.3.1.6 PWM Resolution and Input Frequency Range

The PWM input resolution depends on the input signal frequency. To achieve the full 11-bit maximum resolution

of PWM duty cycle to the LED brightness code, the input PWM duty cycle must be ≥ 11 bits, and the PWM

sample period (1/f_SAMPLE) must be smaller than the minimum PWM input pulse width. Figure 24 shows the

possible brightness code resolutions based on the input PWM frequency. The minimum recommended PWM

frequency is 100 Hz, and maximum recommended PWM frequency is 20 kHz.

12

Sample Freq = 1 MHz

Sample Freq = 4 MHz

10

8

6

4

100

1000

10000

100000

PWM Frequency (Hz)

D001

Figure 24. PWM Resolution and PWM Input Frequency

7.3.1.7 PWM Hysteresis

To prevent jitter in the input PWM signal from feeding through the PWM path and causing oscillations in the LED

current, the LM3632A offers 4 programmable PWM hysteresis settings. Hysteresis works by forcing a specific

number of 11-bit LSB code transitions to occur in the input duty cycle before the LED current changes. Table 9

describes the hysteresis. Hysteresis only applies during the change in direction of brightness currents. Once the

change in direction has taken place, the PWM input must overcome the required LSB(s) of the hysteresis setting

before the brightness change takes effect. Once the initial hysteresis has been overcome and the direction in

brightness change remains the same, the PWM-to-current response changes with no hysteresis. Hysteresis is

selected with the PWM_HYST bits, register 0x03 bits[1:0]. Changing the hysteresis value is recommended when

PWM input frequency increases.

7.3.1.8 PWM Timeout

The LM3632A PWM timeout feature turns off the backlight boost output when the PWM input is enabled and

there is no PWM pulse detected. The timeout duration depends on the PWM sample rate setting and defines the

minimum supported PWM input frequency. Table 2 summarizes the sample rate, timeout, and minimum

supported PWM frequency.

Table 2. PWM Timeout and Minimum Supported PWM Frequency vs PWM Sample Rate

MINIMUM SUPPORTED PWM

SAMPLE RATE

TIMEOUT

FREQUENCY

1 MHz

4 MHz

25 msec

3 msec

48 Hz

400 Hz

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7.3.1.9 Backlight Boost Converter

The high voltage required by the LED strings is generated with an asynchronous backlight boost converter. An

adaptive voltage control loop automatically adjusts the output voltage based on the voltage over the LED drivers

BLED1 and BLED2.

The LM3632A has two switching frequency modes, 500 kHz and 1 MHz. These are set via the BL_FREQ Select

bit, register 0x03 bit[7]. Operation in low-frequency mode results in better efficiency at lighter load currents due to

the decreased switching losses. Operation in high-frequency mode gives better efficiency at higher load currents

due to the reduced inductor current ripple and the resulting lower conduction losses in the MOSFETs and

inductor.

BL_OUT

BL_SW

BLED1

BLED2

BLED_OVP [1:0]

LIGHT

LOAD

OVP

V_HR

(Feedback)

R

S

R

-

G_M

+

R

GATE

DRIVER

V_REF

OCP

CURRENT

SENSE

LED Driver

BL_SW_FREQ

OFF/BLANK TIME

PULSE GENERATOR

CURRENT RAMP

GENERATOR

G_M

ꢀ

BOOST OSCILLATOR

PEAK_CURR_LIM

Figure 25. Backlight Boost Block Diagram

7.3.1.9.1 Headroom Voltage

In order to optimize efficiency, the LED driver-regulated headroom voltage (V_HR) changes with the programmed

LED current. This allows for increased solution efficiency as the dropout voltage of the LED driver changes.

Furthermore, in order to ensure that both current sinks remain in regulation when there is a mismatch in string

voltages, the minimum headroom voltage between V_BLED1and V_BLED2becomes the regulation point for the boost

converter. For example, if the LEDs connected to BLED1 require 25 V at the programmed current, and the LEDs

connected to BLED2 require 25.5 V at the programmed current, the voltage at BLED1 is V_HR+ 0.5 V, and the

voltage at BLED2 is V_HR. In other words, the cathode of the highest voltage LED string becomes the boost output

regulation point.

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0.28

0.26

0.24

0.22

0.2

0.18

0.16

0.14

0.12

0.1

0.08

0.05

0.5

5

50

C006

LED Currrent (mA)

Figure 26. Regulated Headroom vs LED Current

7.3.1.9.2 Backlight Protection and Faults

7.3.1.9.2.1 Overvoltage Protection (OVP) and Open-Load Fault Protection

The LM3632A provides an OVP that monitors the LED boost output voltage (V_{BL_OUT}) and protects BL_OUT and

BL_SW from exceeding safe operating voltages. The OVP threshold can be set to 18 V, 22 V, 25 V or 29 V with

register 0x02 bits[7:5]. Once an OVP event has been detected, the BL_OVP flag is set in the Flags1 register, and

the subsequent behavior depends on the state of bit BL_OVP_SET in the Enable Register: If BL_OVP_SET is

set to '0', as soon as V_{BL_OUT}falls below the backlight OVP threshold, the LM3632A begins switching again. If

BL_OVP_SET is set to '1' and the device detects three occurrences of V_{BL_OUT}> V_{OVP_BL}while any of the

enabled current sink headroom voltages drops below 40 mV, the BL_OVP flag is set, the Backlight Enable bit is

cleared, and the LM3632A enters standby mode. When the device is shut down due to a BL_OVP fault the

Flags1 register must be read back before the device can be reenabled.

7.3.1.9.2.2 Overcurrent Protection (OCP) and Overcurrent Protection Flag

The LM3632A has an OCP threshold of 1 A. The OCP threshold is a cycle-by-cycle current limit detected in the

low-side NFET. Once the threshold is reached, the NFET turns off for the remainder of the switching period. If

enough overcurrent events occur, the BL_OCP flag (register 0x10 bit[0]) is set. The flag can be cleared upon a

readback of register 0x10. To avoid transient conditions from inadvertently setting the BL_OCP flag, a pulse

density counter monitors BL_OCP events over a 128-µs time window. If 8 consecutive 128-µs windows of at

least 2 OCP events are detected, the BL_OCP flag is set.

7.3.2 LCM Bias

7.3.2.1 Display Bias Boost Converter (V_VPOS, V_VNEG

)

A single high-efficiency boost converter provides a positive voltage rail, V_{LCM_OUT}, which serves as the power rail

for the LCM VPOS and VNEG outputs.

•

The V_VPOSoutput LDO has a programmable range from 4 V up to 6 V with 50-mV steps and can supply up to

50 mA.

•

The V_VNEGoutput is generated from a regulated, inverting charge pump and has an adjustable range of –6 V

up to –4 V with 50-mV steps and a maximum load of 50 mA.

Boost voltage also has a programmable range from 4.5 V up to 6.4 V with 50-mV steps. Please refer to Table 19,

Table 20 and Table 21 for V_{LCM_OUT}, V_VPOSand V_VNEGvoltage settings. When selecting a suitable boost-output

voltage, the following estimation can be used: V_{LCM_OUT}= max(V_VPOS, |V_VNEG|) + V_HR, where V_HR= 300 mV for

lower currents and 400 mV for higher currents. When the device input voltage (V_IN) is greater than the

programmed LCM boost output voltage, the boost voltage goes to V_IN+ 100 mV. V_VPOS, and V_VNEGvoltage

settings cannot be changed while they are enabled. While the V_{LCM_OUT}target changes immediately upon a

register write, V_VPOSand V_VNEGregister setting targets take effect only after the outputs are disabled and re-

enabled.

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VIN

V_{LCM_OUT}

LCM_OUT

LCM Bias Boost

Converter

LCM_SW

10 µF

+

V_IN

C_IN

10 µF

±

LCM Positive

Bias Output

VPOS

V_VPOS

VPOS

C1

10 µF

C2

LCM Negative

Bias Output

VNEG

V_VNEG

VNEG

10 µF

Figure 27. LCM Boost Block Diagram

The LCM Bias outputs can be controlled either by pins LCM_EN1 and LCM_EN2 or register bits VPOS_EN and

VNEG_EN, register 0x0C bits[2:1]. Setting bit EXT_EN, register 0x0C bit[0], to '0' allows pins LCM_EN1 and

LCM_EN2 to control VPOS and VNEG, respectively, while setting this bit to '1' yields control to bits VPOS_EN

and VNEG_EN. Refer to Table 3 for LCM bias control information.

Table 3. LCM Bias Truth Table

LCM_EN2

LCM_EN1

EXT_EN

0x0C[0]

VNEG_EN

0x0C[1]

VPOS_EN AUTO_SEQ WAKE-UP

EN PIN

ACTION

Shutdown

0x0C[2]

0x0C[5]

0x0C[7]

0

1

X

0

1

X

0

1

0

X

1

X

0

Standby

External VPOS

External VNEG

External VPOS and VNEG

Independent

1

X

0

1

0

External VPOS and VNEG

Auto Sequence

1

X

0

1

0

1

0

X

0

Standby

I²C VPOS

I²C VNEG

I²C VPOS and VNEG

Independent

I²C VPOS and VNEG

Auto Sequence

1

X

0

1

0

1

0

1

0

1

X

0

1

X

0

1

0

X

1

Standby

Wake-up VPOS

Wake-up VNEG

Wake-up VPOS and

VNEG

1

X

1

X

1

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7.3.2.2 Auto Sequence Mode

If this mode is selected the LM3632A controls the turn-on and turn-off of VPOS and VNEG as shown in

Figure 28.

VPOS

VNEG

VPOS

VNEG

T_R=

500 µs

or

ꢀ1 ms

800 µs

Figure 28. Auto Sequence Timing

7.3.2.3 Wake-up Mode

If Wake-up mode is selected the LM3632A allows on/off control of both VPOS and VNEG with only one external

pin (LCM_EN2). Any combination of VPOS, VNEG, or both can be turned on based on the state of bits

VPOS_EN and VNEG_EN in register 0x0C. In this mode the internal shutdown timing of the VPOS and VNEG

blocks is modified to allow for lower quiescent current in standby mode, therefore reducing the average current

consumption during a sequence of on/off events.

7.3.2.4 Active Discharge

An optional active discharge is available for the VPOS and VNEG output rails. An internal switch resistance for

this discharge function is implemented on each output rail. The VPOS active discharge function is enabled with

register 0x0C bit[4] and the VNEG active discharge with register 0x0C bit[3].

NOTE

To avoid an unsafe operating condition when the active discharge function is enabled, a

minimum delay of 1 millisecond needs to be maintained between disabling and re-

enabling of the VNEG output.

7.3.2.5 LCM Bias Protection and Faults

The LCM Bias block of the LM3632A provides four protection mechanisms in order to prevent damage to the

device. Note that none of these have any effect on backlight or flash operation.

7.3.2.5.1 LCM Overvoltage Protection

The LM3632A provides OVP that monitors the LCM Bias boost output voltage (V_{LCM_OUT}) and protects

LCM_OUT and LCM_SW from exceeding safe operating voltages. The OVP threshold is set to 7 V (typical). If an

LCM Bias overvoltage condition is detected, the LCM_OVP flag, register 0x10 bit[5], is set. The flag can be

cleared with an I²C read back of the register. An LCM OVP condition will not cause the LCM Bias to shut down; it

is a report-only flag.

7.3.2.5.2 VNEG Overvoltage Protection

If the charge-pump voltage goes 250 mV (typical) below its target set-point, the LM3632A provides a mechanism

for preventing the voltage from increasing even further and damaging the device and sets the VNEG_OVP flag,

register 0x10 bit[4]. The flag can be cleared with an I²C readback of the register. A VNEG OVP condition will not

cause the charge pump to shut down; it is a report-only flag.

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NOTE

The VNEG_OVP flag may get set during VNEG start-up under light load and low VNEG

voltage settings due to VNEG voltage undershoot. After the flag is cleared via register

read back, the LM3632A detects VNEG OVP conditions properly.

7.3.2.5.3 VPOS Short Circuit Protection

If the current at VPOS exceeds 80 mA (typical), the LM3632A sets the VPOS_SHORT flag, register 0x10 bit[3].

A readback of register 0x10 is required to clear the flag. A VPOS_SHORT condition will not cause the LCM Bias

to shut down; it is a report-only flag.

7.3.2.5.4 VNEG Short Circuit Protection

If the voltage at VNEG goes within 750 mV (typical) from ground, the LM3632A sets the VNEG_SHORT flag,

register 0x10 bit[2]. A readback of register 0x10 is required to clear the flag. A VNEG_SHORT condition will not

cause the LCM Bias to shut down; it is a report-only flag.

7.3.3 Flash

7.3.3.1 Flash Boost Converter

The LM3632A incorporates a high-efficiency synchronous current-mode PWM boost converter that switches and

boosts the output to maintain at least V_HRacross the flash current source (FLED) over the 2.7-V to 5.5-V input

voltage range. The flash boost has two switching frequency modes, 2-MHz and 4-MHz. These are set via the

FL_FREQ Select bits, register 0x07 bits[7:6].

FL_SW

Overvoltage

Comparator

4 MHz or

2 MHz

Oscillator

VIN

-

+

V

REF

V

OVP

100 m:

FL_OUT

Input Voltage

Flash Monitor

I

LED

PWM

Control

80 m:

FLED

+

-

OUT-VHR

Error

Amplifier

Current Sense/

Current Limit

Slope

Compensation

Soft-Start

SDA

SCL

2

Control

Logic/

Registers

I

C

Interface

GND

ENABLE

STROBE

TX

Figure 29. Flash Boost Block Diagram

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7.3.3.2 Start-Up (Enabling The Device)

The flash LED output (FLED) can be enabled in flash or torch mode with the Enable Register and the STROBE

pin. The state of bit STROBE_EN, register 0x09 bit[4], determines if the FLED output is enabled by bit[1] of

register 0x0A or the STROBE pin. Table 4 contains the details for flash operation control. While a positive edge

is required at the STROBE pin in order to initiate a Torch or Flash event, the STROBE pin is level sensitive. That

means that the event is terminated as soon as the STROBE pin transitions low.

Table 4. Flash Truth Table

STROBE_EN

0x09[4]

STROBE

FLASH_EN

0x0A[1]

FLASH_MODE

0x0A[2]

EN PIN

ACTION

0

1

X

0

1

X

0

1

0

1

0

1

X

0

Shutdown

Standby

Int Torch

Int Flash

Standby

Ext Torch

Ext Flash

X

1

0

X

0

pos edge

1

On start-up, when V_OUTis less than V_INthe internal synchronous PFET turns on as a current source and delivers

200 mA (typical) to the output capacitor. During this time the current source (LED) is off. When the voltage

across the output capacitor reaches 2.2 V (typical) the current source turns on. At turn-on the current source

steps through each flash or torch level until the target LED current is reached. This gives the device a controlled

turn-on and limits inrush current from the V_INsupply.

7.3.3.3 Pass Mode

The LM3632A flash boost starts up in pass mode and stays there until boost mode is needed to maintain

regulation. If the voltage difference between V_{FL_OUT}and V_FLEDfalls below V_HR, the device switches to boost

mode. In pass mode the boost converter does not switch, and the synchronous PFET turns fully on bringing

V_{FL_OUT}up to V_IN− I_FLED× RPMOS. In pass mode the inductor current is not limited by the peak current limit.

7.3.3.4 Flash Mode

In flash mode, the LED current source (FLED) provides 15 target current levels from 100 mA to 1500 mA in 100

mA increments. The flash currents are adjusted via register 0x06 (see Table 12 for details). Once the flash

sequence is activated the current source (FLED) ramps up to the programmed flash current by stepping through

all current steps until the programmed current is reached. The headroom in the current source is regulated to

provide 100 mA to 1.5 A to the output. Whether the device is enabled in flash mode through the Enable Register

or through the STROBE pin, the Flash Enable bit in the Enable Register is cleared at the completion of the flash

event and needs to be re-written in order to perform the next internal or external flash event.

7.3.3.5 Torch Mode

In torch mode, the LED current source (FLED) provides 15 target current levels from 25 mA to 375 mA in 25-mA

increments. The torch currents are adjusted via register 0x06 (see Table 12 for details). Once the torch sequence

is activated the current source (FLED) ramps up to the programmed Torch current by stepping through all current

steps until the programmed current is reached. Torch mode is not affected by Flash Timeout or by a TX Interrupt

event.

7.3.3.6 Power Amplifier Synchronization (TX)

The TX pin is a Power Amplifier Synchronization input. This is designed to reduce the flash FLED current and

thus limit the battery current during high battery-current conditions such as PA transmit events. When the

LM3632A is engaged in a flash event, and the TX pin is pulled high, the FLED current is forced into torch mode

at the programmed torch current setting. If the TX pin is then pulled low before the flash pulse terminates, the

FLED current returns to the previous flash current level. At the end of the flash time-out, whether the TX pin is

high or low, the FLED current is turned off.

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7.3.3.7 VIN Monitor

The LM3632A has the ability to adjust the flash current based upon the voltage level present at the VIN pin. The

adjustable VINM threshold ranges from 2.6 V to 3.3 V in 100-mV steps. The Flags1 Register (0x0B) has the fault

flag set when the input voltage crosses the VINM value. Additionally, the VINM threshold sets the input voltage

boundary that forces the device to either transition into torch mode at the programmed torch current setting or

turn off the FLED current for the remaining flash duration. This decision is made based on the status of bit

VINM_MODE, register 0x09 bit[1]. In order to re-enable the LM3632A in torch or flash mode the VINM flag has to

be cleared. If the VINM flag is tripped during flash current ramp-up, and VINM mode is set to torch, the FLED

current is reduced not to the torch current setting but to the same percentage of the last flash current that was

reached during fash current ramp-up. For example, if the flash current setting is 1 A, the torch current setting is

100 mA and the maximum flash current that was reached before the VINM threshold was crossed is 700 mA, the

device will transition the flash current to 70 mA (70% of 100 mA).

7.3.3.8 Flash Fault Protections

7.3.3.8.1 Fault Operation

If the LM3632A enters a fault condition during flash, the device sets the appropriate flag in the Flags1 and Flags2

Registers (0x0B and 0x10) and places the flash block into standby by clearing the FLASH_EN bit in the Enable

Register. The flash block remains in shutdown until an I²C read of the Flag Registers is completed. Upon

clearing the flags/faults, flash can be restarted. If the fault is still present, the LM3632A re-enters the fault state

and enters standby again. Flash faults have no effect on Backlight or LCM control.

7.3.3.8.2 Flash Time-Out

The Flash Time-Out period sets the amount of time that the Flash Current is being sourced from the current

source (FLED). The LM3632A has 32 timeout levels ranging from 32 ms to 1024 ms (see Table 13 for more

detail). Once a flash event is completed, the FTO flag in Flags1 register (register 0x0B bit[1]) is set. If a flash

event is activated via the STROBE pin and STROBE transitions low after the end of the programmed flash

timeout, the flash event is terminated at the programmed flash timeout, and the FTO flag is set. If the STROBE

pin transitions low before the end of the programmed flash timeout, the flash event is terminated, and the FTO

flag is not set.

7.3.3.8.3 Overvoltage Protection (OVP)

The flash output voltage is limited to typically 4.9 V (see V_OVPSpec in Electrical Characteristics ). In situations

such as an open FLED, the LM3632A tries to raise the output voltage in order to keep the FLED current at its

target value. When V_{FL_OUT}reaches 4.9 V (typical), the overvoltage comparator trips and turns off the internal

NFET. When V_{FL_OUT}falls below the V_OVPOff threshold, the LM3632A begins switching again. The Flash Enable

bit is cleared, and the FLASH_OVP flag is set, when an OVP condition is present for three rising OVP edges.

This prevents momentary OVP events from forcing the device to shut down.

7.3.3.8.4 Current Limit

The LM3632A features two selectable flash inductor current limits that are programmable through the I²C-

compatible interface. When the inductor current limit is reached, the device terminates the charging phase of the

switching cycle. Switching resumes at the start of the next switching period. If the overcurrent condition persists,

the device operates continuously in current limit. Since the current limit is sensed in the NMOS switch, there is

no mechanism to limit the current when the device operates in pass mode (current does not flow through the

NMOS in pass mode). In boost mode or pass mode if V_{FL_OUT}falls below 2.3 V, the device stops switching, and

the PFET operates as a current source limiting the current to 200 mA. This prevents damage to the LM3632A

and excessive current draw from the battery during output short-circuit conditions. The Flash Enable bit is not

cleared upon a current limit event, but the FLASH_OCP flag (register 0x10 bit[1]) is set.

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7.3.3.8.5 FLED and/or FL_OUT Short Fault

The FLED short flag (FLED_SHORT) reads back a '1' if the device is active in flash or torch mode and the FLED

output experiences a short condition. The flash output short flag (FOUT_SHORT) reads back a '1' if the device is

active in flash or torch mode and the flash boost output experiences a short condition. A FLED short condition is

determined if the voltage at FLED goes below 500 mV (typical) while the device is in torch or flash mode. There

is a deglitch time of 256 μs before the LED Short flag is valid and a deglitch time of 2.048 ms before the FL_OUT

Short flag is valid. The FLED Short Fault can only be reset to '0' by removing power to the LM3632A, setting EN

to '0', setting the SW RESET bit to a '1', or by reading back the Flags1 Register (0x0B on device). The Flash

Enable bit is cleared upon a FLED and/or FL_OUT short fault.

7.3.4 Software RESET

Bit[7] (SWR_RESET) of the Enable Register (0x0A) is a software reset bit. Writing an '1' to this bit resets all I²C

register values to their default values. Once the LM3632A has finished resetting all registers, it auto-clears the

SWR_RESET bit.

7.3.5 EN Input

The EN pin is a global hardware enable for the LM3632A. This pin must be pulled to logic HIGH to enable the

device and the I²C-compatible interface. There is a 300-kΩ internal resistor between EN and GND. When this pin

is at logic LOW, the LM3632A is placed in shutdown, the I²C-compatible interface is disabled, and the internal

registers are reset to their default state. It is recommended that V_INhas risen above 2.7 V before setting EN

HIGH.

7.3.6 Thermal Shutdown (TSD)

The LM3632A has TSD protection which shuts down the backlight boost, both backlight current sinks, LCM Bias

Boost and outputs, inverting charge pump, flash boost, and flash current source when the die temperature

reaches or exceeds 140°C (typical). The I²C interface remains active during a TSD event. If a TSD fault occurs

the TSD fault is set, register 0x0B bit[0]. The fault is cleared by an I²C read of register 0x0B or by toggling the

EN pin.

7.4 Device Functional Modes

7.4.1 Modes of Operation

Shutdown: The LM3632A is in shutdown when the EN pin is low.

Standby:

After the EN pin is set high the LM3632A goes into standby mode. In standby mode, I²C writes are

allowed but references, bias currents, the oscillator, LCM powers, backlight and flash are all

disabled, to keep the quiescent supply current low (2 µA typ.).

Normal mode: All three main blocks of the LM3632A are independently controlled. For enabling each of the

blocks in all available modes, see Table 1, Table 3, and Table 4 .

7.5 Programming

7.5.1 I²C-Compatible Serial Bus Interface

7.5.1.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines

should be connected to a positive supply via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave, depending

whether it generates or receives the serial clock (SCL).

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Programming (continued)

7.5.1.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

Figure 30. Data Validity

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software), and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

Transmitter Stays off the

Bus During the Acknowledge Clock

Acknowledge Signal from Receiver

3...6

7

9

1

8

2

S

Start

Condition

Figure 31. Acknowledge Signal

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy, and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

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Programming (continued)

SDA

SCL

S

P

START condition

STOP condition

Figure 32. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

7.5.1.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

7.5.1.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked

out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the

master), but the SDA line is not pulled down.

7.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LM3632A operates as a slave device with the 7-bit

address. If an 8-bit address is used for programming, the 8th bit is '1' for read and '0' for write. The 7-bit address

for the device is 0x11.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device

should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the

first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the

slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

R/W

bit0

Bit7

bit6

bit5

bit4

bit3

bit2

bit1

I²C SLAVE address (chip address)

Figure 33. I²C Device Address

Control Register Write Cycle

Master device generates start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

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Programming (continued)

•

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master sends data byte to be written to the addressed register.

Slave sends acknowledge signal.

If master sends further data bytes the control register address is incremented by one after acknowledge

signal.

•

Write cycle ends when the master creates stop condition.

Control Register Read Cycle

•

Master device generates a start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal

Master device generates repeated start condition.

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

Slave sends acknowledge signal if the slave address is correct.

Slave sends data byte from addressed register.

If the master device sends acknowledge signal, the control register address is incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

Table 5. I²C Data Read/Write⁽¹⁾

ADDRESS MODE

<Slave Address><r/w =0>[Ack]

<Register Addr>[Ack]

<Slave Address><r/w = 1>[Ack]

Data Read

[Register Data]<Ack or NAck>

...additional reads from subsequent register address possible

<Slave Address><r/w = 0>[Ack]

<Register Addr>[Ack]

<Register Data>[Ack]

Data Write

...additional writes to subsequent register address possible

(1) < > = Data from master, [ ] = Data from slave

ack from slave

start msb Chip Address lsb

w

ack

msb Register Addr lsb

ack

msb

Data

lsb

ack stop

SCL

SDA

start

id = 001 0001b

w

ack

address = 02h

ack

address 02h data

ack stop

Figure 34. Register Write Format

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When a READ function is to be accomplished, a WRITE function must precede the READ function, as show in

the Read Cycle waveform.

ack from slave

ack from slave repeated start

ack from slavedata from slave nack from master

start msb Chip Address lsb

w

msb Register Add lsb

rs

msb Chip Address lsb

r

msb Data lsb

stop

SCL

SDA

start

id = 001 0001b

w

ack

address = 00h

ack rs

id = 001 0001b

r ack address 00h data nack stop

Figure 35. Register Read Format

NOTE

w = write (SDA = 0), r = read (SDA = 1), ack = acknowledge (SDA pulled down by either

master or slave), rs = repeated start id = 7-bit chip address

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7.6 Register Maps

Table 6. Register Default Values

I²C Address

0x01

Register Name

Read/Write

R

Power On/Reset Value

Revision Register

Backlight Configuration1 Register

Backlight Configuration2 Register

LED Brightness LSB Register

LED Brightness MSB Register

Flash/Torch Current Register

Flash Configuration Register

VIN Monitor Register

0x09

0x30

0x0D

0x07

0xFF

0x3E

0x2F

0x03

0x00

0x18

0x1E

0x1C

0x00

0x02

R/W

R

0x03

0x04

0x05

0x06

0x07

0x08

0x09

I/O Control Register

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

Enable Register

Flags1 Register

Display Bias Configuration Register

LCM Boost Bias Register

VPOS Bias Register

R/W

R

VNEG Bias Register

Flags2 Register

7.6.1 Revision (Address = 0x01) [reset = 0x05]

Figure 36. Revision Register

7

6

5

4

3

2

1

0

DEV_REV[5]

R-0

DEV_REV[4]

R-0

DEV_REV[3]

R-0

DEV_REV[2]

R-0

DEV_REV[1]

R-1

DEV_REV[0]

R-0

VENDOR[1]

R-0

VENDOR[0]

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. Revision Register Field Descriptions

Bit

7-2

1-0

Field

Type

R

Reset

000010

01

Description

DEV_REV[6:0]

VENDOR[1:0]

R

7.6.2 Backlight Configuration1 (Address = 0x02) [reset = 0x30]

Figure 37. Backlight Configuration1 Register

7

6

5

4

3

2

1

0

BLED_OVP[2] BLED_OVP[1] BLED_OVP[0]

R/W-0 R/W-0 R/W-1

BLED_MAP

R/W-1

PWM_CONFIG

R/W-0

Reserved

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. Backlight Configuration1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

BLED_OVP

R/W

001

Backlight OVP level select

000: 18 V

001: 22 V (Default)

010: 25 V

011: 29 V

Note: Codes 100 to 111 also map to 29 V

4

BLED_MAP

R/W

1

Sets the backlight LED mapping mode

0: Exponential

1: Linear (Default)

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Table 8. Backlight Configuration1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

PWM_CONFIG

R/W

0

Sets the polarity of the PWM input signal

0: Active High PWM Input (default)

1: Active Low PWM Input

2-0

Reserved

7.6.3 Backlight Configuration2 (Address = 0x03) [reset = 0x0D]

Figure 38. Backlight Configuration2 Register

7

6

5

4

3

2

1

0

BL_FREQ

R/W-0

BL_TRANS[3] BL_TRANS[2] BL_TRANS[1] BL_TRANS[0]

R/W-0 R/W-0 R/W-0 R/W-1

PWM_FREQ

R/W-1

PWM_HYST[1]

R/W-0

PWM_HYST[0]

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. Backlight Configuration2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BL_FREQ

R/W

0

Sets the backlight boost switch frequency

0: 500 kHz (Default)

1: 1 MHz

6-3

BL_TRANS[3:0]

R/W

001

Controls backlight LED ramping time. The transient time is a

constant time that the backlight takes to transition from an

existing programmed code to a new programmed code.

0000: 0

0001: 500 µs (Default)

0010: 750 µs

0011: 1 ms

0100: 2 ms

0101: 5 ms

0110: 10 ms

0111: 20 ms

1000: 50 ms

1001: 100 ms

1010: 250 ms

1011: 800 ms

1100: 1 s

1101: 2 s

1110: 4 s

1111: 8 s

2

PWM_FREQ

R/W

1

Sets PWM sampling frequency

0: 1 MHz

1: 4 MHz (Default)

1-0

PWM_HYST[1:0]

01

Sets the minimum change in PWM input duty cycle that results

in a change of backlight LED brightness level

00: 1 bit

01: 2 bits (Default)

10: 4 bits

11: 6 bits

7.6.4 Backlight Brightness LSB (Address = 0x04) [reset = 0x07]

Figure 39. Backlight Brightness LSB Register

7

6

5

4

3

2

1

0

Reserved

BL_BRT_

LSB[2]

BL_BRT_

LSB[1]

BL_BRT_

LSB[0]

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 10. Backlight Brightness LSB Register Field Descriptions

Bit

7-3

2-0

Field

Type

Reset

Description

Reserved

BL_BRT_LSB[2:0]

R/W

111

Lower 3 bits (LSB's) of brightness code. Concatenated with

brightness bits in Register 0x05 (MSB).

7.6.5 Backlight Brightness MSB (Address = 0x05) [reset = 0xFF]

Figure 40. Backlight Brightness MSB Register

7

6

5

4

3

2

1

0

BL_BRT_

MSB[7]

BL_BRT_

MSB[6]

BL_BRT_

MSB[5]

BL_BRT_

MSB[4]

BL_BRT_

MSB[3]

BL_BRT_

MSB[2]

BL_BRT_

MSB[1]

BL_BRT_

MSB[0]

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. Backlight Brightness MSB Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

BL_BRT_MSB[7:0]

R/W

11111111 Upper 8 bits (MSB's) of backlight brightness code. Concatenated

with brightness bits in Register 0x04 (LSB).

With linear mapping the 11-bit code to current response is

approximated by the equation:

I_LED=37.8055μA+12.1945μA×I2C_BRGT_CODE (for codes > 0).

With exponential mapping the 11-bit code-to-current response is

approximated by the equation:

I_LED=50μA×1.003040572^{I2C_BRGT_CODE}(for codes > 0).

These equations are valid for I2C brightness codes between 1

and 2047. Code 0 disables the backlight.

7.6.6 Flash/Torch Current (Address = 0x06) [reset = 0x3E]

Figure 41. Flash/Torch Current Register

7

6

5

4

3

2

1

0

TORCH_

BRT[3]

TORCH_

BRT[2]

TORCH_

BRT[1]

TORCH_

BRT[0]

FLASH_

BRT[3]

FLASH_

BRT[2]

FLASH_

BRT[1]

FLASH_

BRT[0]

R/W-0

R/W-1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. Flash/Torch Current Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

TORCH_BRT[3:0]

R/W

0011

Sets torch mode current level (25 mA per step)

0000: 25 mA

0001: 50 mA

0010: 75 mA

0011: 100 mA (Default)

....................

1101: 350 mA

1110: 375 mA

Note: Code 1111 also maps to 375 mA

3-0

FLASH_BRT[3:0]

R/W

1110

Sets flash mode current level (100 mA per step)

0000: 100 mA

0001: 200 mA

0010: 300 mA

0011: 400 mA

....................

1101: 1.4 A

1110: 1.5 A (Default)

Note: Code 1111 also maps to 1.5 A

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7.6.7 Flash Configuration (Address = 0x07) [reset = 0x2F]

Figure 42. Flash Configuration Register

7

6

5

4

3

2

1

0

FL_FREQ[1]

R/W-0

FL_FREQ[0]

R/W-0

FL_ILIMIT

R/W-1

FTO[4]

R/W-0

FTO[3]

R/W-1

FTO[2]

R/W-1

FTO[1]

R/W-1

FTO[0]

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. Flash Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

FL_FREQ[1:0]

R/W

00

Sets the flash boost switch frequency

00: 4 MHz (Default)

01: 2 MHz

Note: Codes 10 and 11 also map to 2 MHz

5

FL_ILIMIT

FTO[4:0]

R/W

1

Selects the switch current limit level for flash boost

0: 1.9 A

1: 2.8 A (Default)

4-0

01111

Selects the flash timeout duration (32 ms per step)

00000: 32 ms

00001: 64 ms

00010: 96 ms

00011: 128 ms

.....................

01110: 480 ms

01111: 512 ms (Default)

10000: 544 ms

.....................

11110: 992 ms

11111: 1024 ms

7.6.8 VIN Monitor (Address = 0x08) [reset = 0x03]

Figure 43. VIN Monitor Register

7

6

5

4

3

2

1

0

Reserved

VINM[2]

R/W-0

VINM[1]

R/W-1

VINM[0]

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. VIN Monitor Register Field Descriptions

Bit

7-3

2-0

Field

Type

Reset

Description

Reserved

VINM[2:0]

R/W

011

This field sets the VIN Monitor threshold level

000: 2.6 V

001: 2.7 V

010: 2.8 V

011: 2.9 V (Default)

100: 3 V

101: 3.1 V

110: 3.2 V

111: 3.3 V

7.6.9 I/O Control (Address = 0x09) [reset = 0x00]

Figure 44. I/O Control Register

7

6

5

4

3

2

1

0

Reserved

PWM_EN

R/W-0

Reserved

STROBE_EN

R/W-0

Reserved

TX_EN

R/W-0

VINM_MODE

R/W-0

VINM_EN

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 15. I/O Control Register Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

PWM_EN

6

R/W

0

This bit enables and disables the PWM input pin. If enabled, the

backlight LED current ramps up to

Target_Current*PWM_Duty_Cycle. If disabled, the PWM input is

ignored.

0: PWM disabled (Default)

1: PWM enabled

5

4

Reserved

STROBE_EN

R/W

0

Hardware flash enable

0: STROBE disabled (Default)

1: STROBE enabled

3

2

Reserved

TX_EN

R/W

0

Flash Interrupt mode enable

0: TX disabled (Default)

1: TX enabled

1

0

VINM_MODE

VINM_EN

Selects the VIN Monitor current reduction level

0: Flash driver returns to standby mode (Default)

1: Flash current reduced to programmed Torch current level

Set this bit to enable VIN Monitor function

0: Disabled (Default)

1: Enabled

7.6.10 Enable (Address = 0x0A) [reset = 0x00]

Figure 45. Enable Register

7

6

5

4

3

2

1

0

SWR_RESET

R/W-0

Reserved

BL_OVP_SET

R/W-0

BLED1_EN

R/W-0

BLED1/2_EN

R/W-0

FLASH_MODE

R/W-0

FLASH_EN

R/W-0

BL_EN

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. Enable Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SWR_RESET

R/W

0

Setting this bit resets all registers to their default values. Bit

auto-clears (returns to "0" upon device reset).

6

5

Reserved

R/W

0

BL_OVP_SET

0: Reports flag if OVP condition detected, but no action taken

(Default)

1: OVP causes shutdown

4

3

BLED1_EN

R/W

0

Backlight sink 1 enable only

0: Disabled (Default)

1: Enabled

BLED1/2_EN

Backlight sink 1 and sink 2 enable. Has priority over bit[4]

(BLED1_EN).

0: Backlight sink 2 disabled, backlight sink 1 status depends on

BLED1_EN bit status (Default)

1: Backlight sink 1 and sink 2 enabled regardless of BLED1_EN

bit status

2

1

0

FLASH_MODE

FLASH_EN

BL_EN

R/W

0

Selects Torch or Flash mode for flash LED output

0: Torch (Default)

1: Flash

Flash LED output enable

0: Disabled (Default)

1: Enabled

Backlight output enable

0: Disabled (Default)

1: Enabled

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7.6.11 Flags1 (Address = 0x0B) [reset = 0x00]

Figure 46. Flags1 Register

7

6

5

FOUT_SHORT

R-0

4

3

2

FLED_SHORT

R-0

1

0

BL_OVP

R-0

FLASH_OVP

R-0

VINM

R-0

TX

R-0

FTO

R-0

TSD

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. Flags1 Register Field Descriptions

Bit

7

Field

Type

R

Reset

Description

BL_OVP

FLASH_OVP

FOUT_SHORT

VINM

0

Backlight overvoltage protection fault or flag

Flash overvoltage protection fault or flag

Flash output short fault

6

R

5

R

4

R

VINM fault or flag

3

TX

R

TX Interrupt flag

2

FLED_SHORT

FTO

R

Flash LED short fault

1

R

Flash timeout flag

0

TSD

R

Thermal shutdown fault

7.6.12 Display Bias Configuration (Address = 0x0C) [reset = 0x18]

Figure 47. Display Bias Configuration Register

7

6

5

4

3

2

1

0

WAKE-UP

VPOS_TRANS

AUTOSEQ

VPOS_DISCH VNEG_DISCH

R/W-1 R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

VPOS_EN

R/W-0

VNEG_EN

R/W-0

EXT_EN

R/W-0

Table 18. Display Bias Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

7

WAKE-UP

R/W

0

Enables wake-up mode

0: Wake-up mode disabled (Default)

1: Wake-up mode enabled

6

5

4

3

VPOS_TRANS

AUTOSEQ

R/W

0

1

Controls positive display bias voltage (LDO) ramping time

0: 800 µs (Default)

1: 500 µs

Enables Auto-sequence

0: Auto-sequence disabled (Default)

1: Auto-sequence enabled

VPOS_DISCH

VNEG_DISCH

Positive display bias voltage (LDO) active discharge selection

0: Not discharged

1: Active discharge (Default)

Negative display bias voltage (inverting charge pump) active

discharge selection

0: Not discharged

1: Active discharge (Default)

2

1

0

VPOS_EN

VNEG_EN

EXT_EN

R/W

0

Positive display bias (LDO) enable

0: Disabled (Default)

1: Enabled

Negative display bias (inverting charge pump) enable

0: Disabled (Default)

1: Enabled

Setting this bit activates pins LCM_EN1 and LCM_EN2 to

enable VPOS and VNEG, respectively

0: VPOS and VNEG can only be enabled via bit VPOS_EN and

VNEG_EN, respectively (Default)

1: VPOS and VNEG can only be enabled via pin LCM_EN1 and

LCM_EN2, respectively

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7.6.13 LCM Boost Bias (Address = 0x0D) [reset = 0x1E]

Figure 48. LCM Boost Bias Register

7

6

5

4

3

2

1

0

Reserved

LCM_VBST[5] LCM_VBST[4] LCM_VBST[3] LCM_VBST[2] LCM_VBST[1] LCM_VBST[0]

R/W-0

R/W-1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. LCM Boost Bias Register Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

Description

Reserved

LCM_VBST[5:0]

R/W

011110

Sets the LCM Boost Voltage (50 mV per step)

000000: 4.5 V

000001: 4.55 V

000010: 4.6 V

....................

011101: 5.95 V

011110: 6 V (Default)

011111: 6.05 V

....................

100101: 6.35 V

100110: 6.4 V

Note: Codes 100111 to 111111 map to 6.4V

7.6.14 VPOS Bias (Address = 0x0E) [reset = 0x1E]

Figure 49. VPOS Bias Register

7

6

5

4

3

2

1

0

Reserved

VPOS[5]

R/W-0

VPOS[4]

R/W-1

VPOS[3]

R/W-1

VPOS[2]

R/W-1

VPOS[1]

R/W-1

VPOS[0]

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. VPOS Bias Register Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

Description

Reserved

VPOS[5:0]

R/W

011110

Sets the Positive Display Bias (LDO) Voltage (50 mV per step)

000000: 4 V

000001: 4.05 V

000010: 4.1 V

....................

011101: 5.45 V

011110: 5.5 V (Default)

011111: 5.55 V

....................

100111: 5.95 V

101000: 6 V

Note: Codes 101001 to 111111 map to 6 V

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ZHCSDN2 –APRIL 2015

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7.6.15 VNEG Bias (Address = 0x0F) [reset = 0x1C]

Figure 50. VNEG Bias Register

7

6

5

4

3

2

1

0

Reserved

VNEG[5]

R/W-0

VNEG[4]

R/W-1

VNEG[3]

R/W-1

VNEG[2]

R/W-1

VNEG[1]

R/W-0

VNEG[0]

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. VNEG Bias Register Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

Description

Reserved

VNEG[5:0]

R/W

011100

Sets the Negative Display Bias (inverting charge pump) Voltage

(–50 mV per step)

000000: –4 V

000001: –4.05 V

000010: -4.1 V

....................

011011: –5.35 V

011100: –5.4 V (Default)

011101: –5.45 V

....................

100111: –5.95 V

101000: –6 V

Note: Codes 101001 to 111111 map to –6 V

7.6.16 Flags2 (Address = 0x10) [reset = 0x00]

Figure 51. Flags2 Register

7

6

5

4

3

2

1

0

Reserved

LCM_OVP

R-0

VNEG_OVP

R-0

VPOS_SHORT VNEG_SHORT FLASH_OCP

R-0 R-0 R-0

BL_OCP

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. Flags2 Register Field Descriptions

Bit

7-6

5

Field

Type

Reset

Description

Reserved

LCM_OVP

VNEG_OVP

VPOS_SHORT

VNEG_SHORT

FLASH_OCP

BL_OCP

R

0

LCM boost overvoltage protection flag

VNEG overvoltage protection flag

4

3

VPOS short circuit protection flag

2

VNEG short circuit protection flag

1

Flash boost output overcurrent protection flag

Backlight boost overcurrent protection flag

0

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ZHCSDN2 –APRIL 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM3632A integrates an LCD backlight driver, LCM positive and negative bias voltage supplies, and a flash

driver into a single device. The backlight boost converter generates the high voltage required for the LEDs. The

device can drive one or two LED strings with 4 to 8 white LEDs per string. Positive and negative bias voltages

are post-regulated from the LCM bias boost output voltage. The flash driver can supply constant current of up to

a 1.5 A to the LED output. All three functions are independent of each other and can be enabled using their own

dedicated controls.

8.2 Typical Application

D1

L1

10 µH

C2

1 µF

L2

1 µH

C1

10 µF

FL_SW FL_SW

BL_SW

2.7 V ± 5 V

BL_OUT

BLED1

BLED2

VIN

V_BATT

L3

2.2 µH

LCM_SW

SCL

Up to 8 LEDs / String

FL_OUT

SDA

C3

10 µF

STROBE

TX

FLED

LM3632

D2

µC/µP

PWM

C1

C2

C_FLY

10 µF

EN

LCM_EN1

LCM_EN2

(6 V)

LCM_OUT

VPOS

C4

10 µF

(5.5 V)

(¤5.4V)

C5

10 µF

AGND

VNEG

BL_GND CP_GND FL_GND LCM_GND

C6

10 µF

Figure 52. Typical Application Schematic

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ZHCSDN2 –APRIL 2015

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Typical Application (continued)

8.2.1 Design Requirements

Example requirements are shown below:

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE

2.7 V to 4.5 V (single Li-Ion cell battery)

Brightness control

I²C Register

Backlight LED configuration

Backlight LED current

Backlight boost maximum voltage

Backlight boost SW frequency

Backlight boost inductor

LCM boost output voltage

V_VNEGoutput voltage

2 parallel, 6 series

max 25 mA / string

29 V

1 MHz

10 µH, 1-A saturation current

6 V

–5.4 V

5.5 V

V_VPOSoutput voltage

Flash LED current

1.5 A

Torch LED current

100 mA

8.2.2 Detailed Design Procedure

8.2.2.1 External Components

Table 23 shows examples of external components for the LM3632A. Boost converter output capacitors can be

replaced with dual output capacitors of lower capacitance as long as the minimum effective capacitance

requirement is met. DC bias effect of the ceramic capacitors must be taken into consideration when choosing the

output capacitors. This is especially true for the high output-voltage backlight-boost converter.

Table 23. Recommended External Components

DESIGNATOR

(Figure 52)

DESCRIPTION

VALUE

EXAMPLE

C1, C3, C4, C5, C6

Ceramic capacitor

Inductor

10 µF, 10 V

1 µF, 35 V

C1608X5R0J106M

C2012X7R1H105K125AB

VLF403212MT- 100M

DFE201610P-1R0M

VLS201612ET-2R2M

NSR0530P2T5G

C2

L1

L2

L3

D1

10 µH, 1 A

1 µH, 2.8 A

2.2 µH, 1 A

30 V, 500 mA

Inductor

Schottky diode

8.2.2.2 Inductor Selection

Both of the LM3632A boost converters are internally compensated. The compensation parameters are designed

for the inductance values listed on Table 23. Effective inductance of the inductors should be ±20%.

There are two main considerations when choosing an inductor: the inductor should not saturate, and the inductor

current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current

rating specifications are followed by different manufacturers so attention must be given to details. Saturation

current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of the

application should be requested from the manufacturer. The saturation current should be greater than the sum of

the maximum load current and the worst-case average-to-peak inductor current. When the boost device is

boosting (V_OUT> V_IN) the inductor is one of the largest area of efficiency loss in the circuit. Therefore, choosing

an inductor with the lowest possible series resistance is important, especially for the flash and LCM Bias

converters. For proper inductor operation and circuit performance, ensure that the inductor saturation and the

peak current limit setting of the LM3632A are greater than I_PEAKin Equation 5:

( )

_INx V_OUT- V

IN

I_LOADV_OUT

V

I_PEAK

=

x

+'I_L

where

'I_L=

K

V

2 x f_SWx L x V_OUT

IN

(5)

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See detailed information in “Understanding Boost Power Stages in Switch Mode Power Supplies”

http://focus.ti.com/lit/an/slva061/slva061.pdf. “Power Stage Designer™ Tools” can be used for the boost

calculation: http://www.ti.com/tool/powerstage-designer.

8.2.2.3 Boost Output Capacitor Selection

At least an 1-μF capacitor is recommended for the backlight boost converter output capacitor. A high-quality

ceramic type X5R or X7R is recommended. Voltage rating must be greater than the maximum output voltage that

is used. The effective output capacitance should always remain higher than 0.4 µF for stable operation.

For the LCM bias boost output a high-quality 10-μF ceramic type X5R or X7R capacitor is recommended.

Voltage rating must be greater than the maximum output voltage that is used.

The flash driver is designed to operate with a 10-μF ceramic output capacitor. When the boost converter is

running, the output capacitor supplies the load current during the boost converter's on-time. When the NMOS

switch turns off, the inductor energy is discharged through the internal PMOS switch, supplying power to the load

and restoring charge to the output capacitor. This causes a sag in the output voltage during the on-time and a

rise in the output voltage during the off-time. The output capacitor is therefore chosen to limit the output ripple to

an acceptable level depending on load current and input/output voltage differentials and also to ensure the

converter remains stable.

The DC-bias effect of the capacitors must be taken into consideration when selecting the output capacitors. The

effective capacitance of a ceramic capacitor can drop down to less than 10% with maximum rated DC bias

voltage. Note that with a same voltage applied, the capacitors with higher voltage rating suffer less from the DC-

bias effect than capacitors with lower voltage rating.

8.2.2.4 Input Capacitor Selection

Choosing the correct size and type of input capacitor helps minimize the voltage ripple caused by the switching

of the LM3632A boost converters and reduce noise on the boost converter's input pin that can feed through and

disrupt internal analog signals. In Figure 52 a 10-μF ceramic input capacitor works well. It is important to place

the input capacitor as close as possible to the LM3632A input (VIN) pin. This reduces the series resistance and

inductance that can inject noise into the device due to the input switching currents.

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8.2.3 Application Curves

8.2.3.1 Backlight Curves

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. Backlight System Efficiency is defined as PLED / PIN,

where PLED is actual power consumed in backlight LEDs.

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40qC

T_A= 25qC

T_A= 85qC

T_A= -40qC

T_A= 25qC

T_A= 85qC

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D001

D002

2p7s LEDs

ƒ = 500 kHz

2p7s LEDs

ƒ = 500 kHz

Figure 53. Backlight Boost Efficiency

Figure 54. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40qC

T_A= 25qC

T_A= 85qC

T_A= -40qC

T_A= 25qC

T_A= 85qC

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D003

D004

2p7s LEDs

ƒ = 1 MHz

2p7s LEDs

ƒ = 1 MHz

Figure 55. Backlight Boost Efficiency

Figure 56. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D005

D006

2p7s LEDs

ƒ = 500 kHz

2p7s LEDs

ƒ = 500 kHz

Figure 57. Backlight Boost Efficiency

Figure 58. Backlight System Efficiency

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Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. Backlight System Efficiency is defined as PLED / PIN,

where PLED is actual power consumed in backlight LEDs.

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D007

D008

2p7s LEDs

ƒ = 1 MHz

2p7s LEDs

ƒ = 1 MHz

Figure 59. Backlight Boost Efficiency

Figure 60. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40qC

T_A= 25qC

T_A= 85qC

T_A= -40qC

T_A= 25qC

T_A= 85qC

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D009

D010

2p6s LEDs

ƒ = 500 kHz

2p6s LEDs

ƒ = 500 kHz

Figure 61. Backlight Boost Efficiency

Figure 62. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40qC

T_A= 25qC

T_A= 85qC

T_A= -40qC

T_A= 25qC

T_A= 85qC

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D012

D011

2p6s LEDs

ƒ = 1 MHz

2p6s LEDs

ƒ = 1 MHz

Figure 64. Backlight System Efficiency

Figure 63. Backlight Boost Efficiency

43

LM3632A

ZHCSDN2 –APRIL 2015

www.ti.com.cn

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. Backlight System Efficiency is defined as PLED / PIN,

where PLED is actual power consumed in backlight LEDs.

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D013

D014

2p6s LEDs

ƒ = 500 kHz

2p6s LEDs

ƒ = 500 kHz

Figure 65. Backlight Boost Efficiency

Figure 66. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D015

D016

2p6s LEDs

ƒ = 1 MHz

2p6s LEDs

ƒ = 1 MHz

Figure 67. Backlight Boost Efficiency

Figure 68. Backlight System Efficiency

8.2.3.2 LCM Bias Curves

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. VPOS, VNEG and VPOS/VNEG Efficiency is defined

as POUT / PIN, where POUT is actual power consumed in VPOS, VNEG and (VPOS + VNEG) outputs, respectively.

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load (mA)

D051

D052

V_{LCM_OUT}= 4.5 V

Figure 69. LCM Boost Efficiency

V_{LCM_OUT}= 5 V

Figure 70. LCM Boost Efficiency

44

LM3632A

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ZHCSDN2 –APRIL 2015

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. VPOS, VNEG and VPOS/VNEG Efficiency is defined

as POUT / PIN, where POUT is actual power consumed in VPOS, VNEG and (VPOS + VNEG) outputs, respectively.

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

T_A= -40°C

T_A= 25°C

T_A= 85°C

TA = -40°C

T_A= 25°C

T_A= 85°C

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load (mA)

D053

D054

V_{LCM_OUT}= 5.5 V

Figure 71. LCM Boost Efficiency

V_{LCM_OUT}= 6 V

Figure 72. LCM Boost Efficiency

96

93

90

87

84

81

78

75

72

69

66

63

96

93

90

87

84

81

78

75

72

69

66

63

60

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 4.3 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load (mA)

D055

Load (mA)

D056

V_{LCM_OUT}= 4.8 V

Figure 73. LCM Boost Efficiency

V_{LCM_OUT}= 5.3 V

Figure 74. LCM Boost Efficiency

100

95

90

85

80

75

70

65

60

90

85

80

75

70

65

60

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40°C

T_A= 25°C

T_A= 85°C

0

10

20

30

40

50

60

70

80

90 100

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D0557

Load (mA)

D058

V_{LCM_OUT}= 5.9 V

Figure 75. LCM Boost Efficiency

V_VPOS= 4.5 V

V_{LCM_OUT}= 4.9 V

Figure 76. VPOS Efficiency

45

LM3632A

ZHCSDN2 –APRIL 2015

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Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. VPOS, VNEG and VPOS/VNEG Efficiency is defined

as POUT / PIN, where POUT is actual power consumed in VPOS, VNEG and (VPOS + VNEG) outputs, respectively.

90

85

80

75

70

65

60

90

85

80

75

70

65

60

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D060

Load (mA)

D0059

V_VPOS= 5.5 V

V_{LCM_OUT}= 5.9 V

V_VPOS= 5 V

V_{LCM_OUT}= 5.4 V

Figure 77. VPOS Efficiency

Figure 78. VPOS Efficiency

95

90

85

80

75

70

65

90

85

80

75

70

65

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 4.3 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D061

Load (mA)

D062

V_VPOS= 4.5 V

V_{LCM_OUT}= 4.9 V

V_VPOS= 5 V

V_{LCM_OUT}= 5.4 V

Figure 80. VPOS Efficiency

Figure 79. VPOS Efficiency

90

95

90

85

80

75

70

65

85

80

75

70

65

60

55

50

T_A= -40°C

T_A= 25°C

T_A= 85°C

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D064

D063

V_VNEG= –4.5 V

V_{LCM_OUT}= 4.9 V

V_VPOS= 5.5 V

V_{LCM_OUT}= 5.9 V

Figure 82. VNEG Efficiency

Figure 81. VPOS Efficiency

46

LM3632A

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ZHCSDN2 –APRIL 2015

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. VPOS, VNEG and VPOS/VNEG Efficiency is defined

as POUT / PIN, where POUT is actual power consumed in VPOS, VNEG and (VPOS + VNEG) outputs, respectively.

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D066

Load (mA)

D065

V_VNEG= –5.5 V

V_{LCM_OUT}= 5.9 V

V_VNEG= –5 V

V_{LCM_OUT}= 5.4 V

Figure 83. VNEG Efficiency

Figure 84. VNEG Efficiency

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 4.3 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D067

D068

V_VNEG= –4.5 V

V_{LCM_OUT}= 4.9 V

V_VNEG= –5 V

V_{LCM_OUT}= 5.4 V

Figure 85. VNEG Efficiency

Figure 86. VNEG Efficiency

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40°C

T_A= 25°C

T_A= 85°C

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D069

D070

V_VNEG= –5.5 V

V_{LCM_OUT}= 5.9 V

V_VPOS= 4.5 V

V_VNEG= –4.5 V

V_{LCM_OUT}= 4.9 V

Figure 87. VNEG Efficiency

Figure 88. VPOS/VNEG Efficiency

47

LM3632A

ZHCSDN2 –APRIL 2015

www.ti.com.cn

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. VPOS, VNEG and VPOS/VNEG Efficiency is defined

as POUT / PIN, where POUT is actual power consumed in VPOS, VNEG and (VPOS + VNEG) outputs, respectively.

90

85

80

75

70

65

60

90

85

80

75

70

65

60

55

50

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D071

D072

V_VPOS= 5 V

V_VNEG= –5 V

V_{LCM_OUT}= 5.4 V

V_VPOS= 5.5 V

V_VNEG= –5.5 V

V_{LCM_OUT}= 5.9 V

Figure 89. VPOS/VNEG Efficiency

Figure 90. VPOS/VNEG Efficiency

90

85

80

75

70

65

60

95

90

85

80

75

70

65

60

55

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 4.3 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D073

D074

V_VPOS= 4.5 V

V_VNEG= –4.5 V

V_{LCM_OUT}= 4.9 V

V_VPOS= 5 V

V_VNEG= –5 V

V_{LCM_OUT}= 5.4 V

Figure 91. VPOS/VNEG Efficiency

Figure 92. VPOS/VNEG Efficiency

95

90

85

80

75

70

65

60

55

5.06

5.04

5.02

5.00

4.98

4.96

4.94

T_A= -40°C

T_A= 25°C

T_A= 85°C

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

10

20

30

40

50

60

70

80

90 100

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D076

D075

V_{LCM_OUT}= 5 V

Figure 94. V_{LCM_OUT}Load Regulation

V_VPOS= 5.5 V

V_VNEG= –5.5 V

V_{LCM_OUT}= 5.9 V

Figure 93. VPOS/VNEG Efficiency

48

LM3632A

www.ti.com.cn

ZHCSDN2 –APRIL 2015

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. VPOS, VNEG and VPOS/VNEG Efficiency is defined

as POUT / PIN, where POUT is actual power consumed in VPOS, VNEG and (VPOS + VNEG) outputs, respectively.

5.58

5.56

5.54

5.52

5.5

6.09

6.07

6.05

6.03

6.01

5.99

5.97

5.95

5.93

5.91

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40°C

T_A= 25°C

T_A= 85°C

5.48

5.46

5.44

5.42

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load (mA)

D078

D077

V_{LCM_OUT}= 5.5 V

Figure 95. V_{LCM_OUT}Load Regulation

V_{LCM_OUT}= 6 V

Figure 96. V_{LCM_OUT}Load Regulation

4.56

4.54

4.52

4.50

4.48

4.46

4.44

5.06

5.04

5.02

5

T_A= -40°C

T_A= 25°C

T_A= 85°C

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

4.98

4.96

4.94

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D079

D081

V_VPOS= 4.5 V

V_{LCM_OUT}= 4.9 V

V_VPOS= 5 V

V_{LCM_OUT}= 5.4 V

Figure 97. V_VPOSLoad Regulation

Figure 98. V_VPOSLoad Regulation

5.56

5.54

5.52

5.50

5.48

5.46

5.44

-4.56

-4.54

-4.52

-4.50

-4.48

-4.46

-4.44

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D082

D080

V_VNEG= –4.5 V

V_{LCM_OUT}= 4.9 V

V_VPOS= 5.5 V

V_{LCM_OUT}= 5.9 V

Figure 100. V_VNEGLoad Regulation

Figure 99. V_VPOSLoad Regulation

49

LM3632A

ZHCSDN2 –APRIL 2015

www.ti.com.cn

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. VPOS, VNEG and VPOS/VNEG Efficiency is defined

as POUT / PIN, where POUT is actual power consumed in VPOS, VNEG and (VPOS + VNEG) outputs, respectively.

-5.06

-5.04

-5.02

-5.00

-4.98

-4.96

-4.94

-5.58

-5.56

-5.54

-5.52

-5.50

-5.48

-5.46

-5.44

-5.42

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40°C

T_A= 25°C

T_A= 85°C

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Load (mA)

D084

D083

V_VNEG= –5 V

V_{LCM_OUT}= 5.4 V

V_VNEG= –5.5 V

V_{LCM_OUT}= 5.9 V

Figure 101. V_VNEGLoad Regulation

Figure 102. V_VNEGLoad Regulation

8.2.3.3 Flash Curves

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. Flash System Efficiency defined as PLED / PIN, where

PLED is actual power consumed in flash LED.

100

95

90

85

80

75

70

90

85

80

75

70

65

T_A= -40qC

T_A= 25qC

T_A= 85qC

T_A= -40qC

T_A= 25qC

T_A= 85qC

2.7

3.1

3.5

3.9

4.3

4.7

5.1

2.7

3.1

3.5

3.9

4.3

4.7

5.1

V_IN(V)

D032

D033

I_FLED= 1.5 A

ƒ = 4 MHz

V_FLED= 3.5 V

I_FLED= 1.5 A

ƒ = 4 MHz

V_FLED= 3.5 V

Figure 103. Flash Boost Efficiency

Figure 104. Flash System Efficiency

100

95

90

85

80

75

90

85

80

75

70

65

T_A= -40qC

T_A= 25qC

T_A= 85qC

T_A= -40qC

T_A= 25qC

T_A= 85qC

2.7

3.2

3.7

4.2

4.7

5.1

2.7

3.1

3.5

3.9

4.3

4.7

5.1

V_IN(V)

D034

D035

I_FLED= 1.5 A

ƒ = 2 MHz

V_FLED= 3.5 V

I_FLED= 1.5 A

ƒ = 2 MHz

V_FLED= 3.5 V

Figure 105. Flash Boost Efficiency

Figure 106. Flash System Efficiency

50

LM3632A

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ZHCSDN2 –APRIL 2015

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. Flash System Efficiency defined as PLED / PIN, where

PLED is actual power consumed in flash LED.

100

98

96

94

92

90

88

86

90

85

80

75

70

65

60

T_A= -40qC

T_A= 25qC

T_A= 85qC

T_A= -40qC

T_A= 25qC

T_A= 85qC

2.7

3.1

3.5

3.9

4.3

4.7

5.1

2.7

3.1

3.5

3.9

4.3

4.7

5.1

V_IN(V)

D036

D037

I_FLED= 0.8 A

ƒ = 4 MHz

V_FLED= 3.2 V

I_FLED= 0.8 A

ƒ = 4 MHz

V_FLED= 3.2 V

Figure 107. Flash Boost Efficiency

Figure 108. Flash System Efficiency

100

98

96

94

92

90

88

86

90

85

80

75

70

65

60

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40qC

T_A= 25qC

T_A= 85qC

2.7

3.1

3.5

3.9

4.3

4.7

5.1

2.7

3.1

3.5

3.9

4.3

4.7

5.1

V_IN(V)

D038

D039

I_FLED= 0.8 A

ƒ = 2 MHz

V_FLED= 3.2 V

I_FLED= 0.8 A

ƒ = 2 MHz

V_FLED= 3.2 V

Figure 109. Flash Boost Efficiency

Figure 110. Flash System Efficiency

100

99

98

97

96

95

94

93

92

91

90

100

95

90

85

80

75

70

65

60

55

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

2.7

3.1

3.5

3.9

4.3

4.7

5.1

2.7

3.1

3.5

3.9

4.3

4.7

5.1

V_IN(V)

D040

D041

I_FLED= 375 mA

ƒ = 4 MHz

V_FLED= 3 V

I_FLED= 375 mA

ƒ = 4 MHz

V_FLED= 3 V

Figure 111. Torch Boost Efficiency

Figure 112. Torch System Efficiency

51

LM3632A

ZHCSDN2 –APRIL 2015

www.ti.com.cn

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. Flash System Efficiency defined as PLED / PIN, where

PLED is actual power consumed in flash LED.

100

99

98

97

96

95

94

93

92

91

90

95

90

85

80

75

70

65

60

55

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

2.7

3.1

3.5

3.9

4.3

4.7

5.1

2.7

3.1

3.5

3.9

4.3

4.7

5.1

V_IN(V)

D042

D043

I_FLED= 375 mA

ƒ = 4 MHz

V_FLED= 3 V

I_FLED= 375 mA

ƒ = 2 MHz

V_FLED= 3 V

Figure 113. Torch Boost Efficiency

Figure 114. Torch System Efficiency

100

98

96

94

92

90

88

86

84

90

88

86

84

82

80

78

76

74

72

70

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

I_LED(A)

D044

D045

ƒ = 4 MHz

Figure 115. Flash Boost Efficiency

ƒ = 4 MHz

Figure 116. Flash System Efficiency

100

98

96

94

92

90

88

86

84

90

88

86

84

82

80

78

76

74

72

70

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

I_LED(A)

D046

D047

ƒ = 2 MHz

Figure 117. Flash Boost Efficiency

ƒ = 2 MHz

Figure 118. Flash System Efficiency

52

LM3632A

www.ti.com.cn

ZHCSDN2 –APRIL 2015

9 Power Supply Recommendations

The LM3632A is designed to operate from an input voltage supply range between 2.7 V and 5 V. This input

supply must be well regulated and capable to supply the required input current. If the input supply is located far

from the LM3632A additional bulk capacitance may be required in addition to the ceramic bypass capacitors.

10 Layout

10.1 Layout Guidelines

•

Place the boost converters output capacitors as close to the output voltage and GND pins as possible.

Minimize the boost converter switching loops by placing the input capacitors and inductors close to GND and

switch pins.

•

If possible, route the switching loops on top layer only. For best efficiency, try to minimize copper on the

switch node to minimize switch pin parasitic capacitance while preserving adequate routing width.

VIN input voltage pin needs to be bypassed to ground with a low-ESR bypass capacitor. Place the capacitor

as close to VIN pin as possible.

Place the output capacitor of the LDO as close to the output pins as possible. Also place the charge pump

flying capacitor and output capacitor close to their respective pins.

Terminate the Flash LED cathode directly to the Flash GND pin of the LM3632A. If possible, route the LED

return with a dedicated path so as to keep the high amplitude LED current out of the GND plane.

Route the internal pins on the second layer. Use offset micro vias to go from top layer to mid-layer1. Avoid

routing the signal traces directly under the switching loops of the boost converters.

53

LM3632A

ZHCSDN2 –APRIL 2015

www.ti.com.cn

10.2 Layout Example

L_LCM

VIAs to

GND Plane

VINL

LCM_OUT LCM_SW

C_LCM

VIAs to

GND Plane

L_BL

C_{BL_OUT}

D1

VPOS

LCM_OUT

BL_GND

LCM_GND

AGND

BL_SW

VPOS

LCM_EN2

C1

LCM_SW

C_VPOS

BL_OUT

LCM_EN1

EN

BL_OUT

BLED1

C1

SDA

TX

BLED1

BLED2

SCL

STROBE

PWM

CP_GND

BLED2

C_FLY

FLED

FL_SW

C2

FL_OUT

VIN

C_IN

C2

C_VNEG

VNEG

FL_GND

VNEG

VIAs to

GND Plane

VIAs to

GND Plane

C_{FL_OUT}

FLED FL_OUT FL_SW

L_FL

VINL

54

LM3632A

www.ti.com.cn

ZHCSDN2 –APRIL 2015

11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.2 文档支持

11.2.1 相关文档


型号：	LM3632A
厂家：	TEXAS INSTRUMENTS
描述：	具有偏置电源和 1.5A LED 闪光灯驱动器的单芯片背光驱动闪光灯驱动器
文件：	总60页 (文件大小：2067K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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