LM3712XQBP-308/NOPB [TI]
2-CHANNEL POWER SUPPLY MANAGEMENT CKT, BGA9, MICRO, BUMP, SMD-9;
| 型号： | LM3712XQBP-308/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, BGA9, MICRO, BUMP, SMD-9 |
| 文件： | 总12页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE
LM3712
www.ti.com
SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
LM3712 Microprocessor Supervisory Circuits with Separate Watchdog Timer Output,
Power Fail Input and Manual Reset
Check for Samples: LM3712
1
FEATURES
DESCRIPTION
The LM3712 series of microprocessor supervisory
circuits provide the maximum flexibility for monitoring
power supplies and battery controlled functions in
systems without backup batteries. The LM3712 series
are available in a 9-bump DSBGA package.
2
•
Standard Reset Threshold Voltage: 3.08V
•
Custom Reset Threshold Voltages: For Other
Voltages between 2.2V and 5.0V in 10mV
Increments, Contact TI.
•
•
•
•
•
No External Components Required
Manual-Reset Input
Built-in features include the following:
Reset: Reset is asserted during power-up, power-
down, and brownout conditions. RESET is specified
down to VCC of 1.0V.
RESET Output
Precision Supply Voltage Monitor
Factory Programmable Reset and Watchdog
Timeout Delays
Manual Reset Input: An input that asserts reset when
pulled low.
•
•
•
Separate Watchdog Output
Power-Fail Input: A 1.225V threshold detector for
power fail warning, or to monitor a power supply other
Separate Power Fail Comparator
than VCC
.
Available in DSBGA Package for Minimum
Footprint
Watchdog Timer: The WDI (Watchdog Input)
monitors one of the µP's output lines for activity. If no
output transition occurs during the watchdog timeout
period, the watchdog output (WDO) pulls low.
•
•
±0.5% Reset Threshold Accuracy at Room
Temperature
±2% Reset Threshold Accuracy Over
Temperature Extremes
•
•
Reset Assertion Down to 1V VCC
28 µA VCC Supply Current
APPLICATIONS
•
•
•
•
Embedded Controllers and Processors
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
Typical Application
V
IN1
V
CC
V
CC
RESET
PFO
RESET
V
PFI
WDI
MR
IN2
mP
NMI
INT
bus
WDO
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
OBSOLETE
LM3712
SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
www.ti.com
Connection Diagram
VCC
NC
RESET
PFO
MR
PFI
1
2
WDO
C
WDI
A
GND
B
3
Figure 1. Top View
(looking from the coating side)
DSBGA 9 Bump Package
BPA09
PIN DESCRIPTIONS
Bump No.
Name
MR
Function
A1
B1
C1
Manual-Reset input. When MR is less than VMRT (Manual Reset Threshold) RESET is engaged.
Power Supply input.
VCC
RESET
Reset Logic Output. Pulses low for tRP (Reset Timeout Period) when triggered, and stays low whenever
VCC is below the reset threshold or when MR is below VMRT. It remains low for tRP after either VCC rises
above the reset threshold, or after MR input rises above VMRT
.
C2
C3
PFO
Power-Fail Logic Output. When PFI is below VPFTPFO goes low; otherwise, PFO remains high.
WDO
Watchdog Output. If no digital activity is detected on WDI (Watchdog Input) for a period exceeding tWD
this output pulls low.
,
B3
A3
GND
WDI
Ground reference for all signals.
Watchdog Input Transition Monitor: If no transition activity occurs for a period exceeding tWD (Watchdog
Timeout Period), reset is engaged.
A2
B2
PFI
NC
Power-Fail Comparator Input. When PFI is less than VPFT (Power-Fail Reset Threshold), the PFO goes
low; otherwise, PFO remains high.
No Connect. Test input used at factory only. Leave floating.
2
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OBSOLETE
LM3712
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SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
Block Diagram
V
CC
OPEN for 'Y'
versions;
CONNECT for 'X'
Reset
Comparator
versions
RESET
+
-
Reset Logic
and One-Shot
Timer
56k
LLO
Comparator
+
-
MR
PFI
Manual Reset
Comparator
+
-
PFO
1.225V
Reference
Transition
Detector
Watchdog
One-Shot
WDI
WDO
Table 1. Table Of Functions
Output
(X = totem-pole)
(Y = open-drain)
Active Low
Reset
Active
High Reset
Reset Timeout
Watchdog
Timeout Period
Manual
Reset
Power Fail
Comparator
Part Number
Period
LM3712
x
X, Y(1)
Customized
Customized
x
x
(1) = available upon request. Contact TI
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage (VCC
All Other Inputs
ESD Ratings(3)
)
−0.3V to 6.0V
−0.3V to VCC + 0.3V
1.5kV
Human Body Model
Machine Model
150V
Power Dissipation
See(4)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The Human Body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJ-A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperture is calculated
using:
spacer
Where the value of θJ-A for the DSBGA package is 220°C/W.
Copyright © 2000–2013, Texas Instruments Incorporated
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OBSOLETE
LM3712
SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
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OPERATING RATINGS(1)
Temperature Range
−40°C ≤ TJ ≤ 85°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed conditions.
ELECTRICAL CHARACTERISTICS
Limits in the standard typeface are for TJ = 25°C and limits in boldface type apply over full operating range. Unless otherwise
specified: VCC = +2.2V to 5.5V.
Symbol
Parameter
Conditions
Min
1.0
Typ
Max
Units
POWER SUPPLY
VCC
Operating Voltage
Range: VCC
5.5
50
V
ICC
VCC Supply Current
All inputs = VCC; all outputs floating
28
µA
RESET THRESHOLD
VRST
Reset Threshold
VCC falling
−0.5
−2
+0.5
+2
VRST
%
VCC falling: TA = 0°C to 70°C
−1.5
+1.5
VRSTH
tRP
Reset Threshold
Hysteresis
0.0032•VRST
mV
Reset Timeout Period
Reset Timeout Period = E, J, N, S
Reset Timeout Period = F, K, P, T
Reset Timeout Period = G, L, Q, U
Reset Timeout Period = H, M, R, V
1
20
140
1120
1.4
28
200
1600
2
40
280
2240
ms
µs
tRD
RESET
VOL
VCC to Reset Delay
RESET
VCC falling at 1mV/µs
20
VCC > 1.0V, ISINK = 50µA
0.3
0.3
0.3
0.3
0.4
VCC > 1.2V, ISINK = 100µA
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
V
VOH
RESET
0.8 VCC
0.8 VCC
CC − 1.5V
V
WDI
WDI
WDIT
Watchdog Input Current
−1
+1
µA
V
Watchdog Input
Threshold
0.2•VCC
1.225
0.8•VCC
tWD
Watchdog Timeout
Period
Watchdog Timeout Period = E, F, G, H
Watchdog Timeout Period = J, K, L, M
Watchdog Timeout Period = N, P, Q, R
Watchdog Timeout Period = S, T, U, V
4.3
71
1120
17900
6.2
102
1600
25600
9.3
153
2400
38400
ms
PFI/MR
VPFT
PFI Input Threshold
MR Input Threshold
1.200
2.0
1.225
1.250
0.8
V
V
VMRT
MR, Low
MR, High
VPFTH
VMRTH
/
PFI/MR Threshold
Hysteresis
PFI/MR falling: VCC = VRST MAX to 5.5V
0.0032•VRST
mV
IPFI
RMR
tMD
Input Current (PFI only)
MR Pull-up Resistance
MR to Reset Delay
MR Pulse Width
−75
75
75
nA
kΩ
µS
µS
35
56
12
tMR
25
4
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LM3712
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SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
Limits in the standard typeface are for TJ = 25°C and limits in boldface type apply over full operating range. Unless otherwise
specified: VCC = +2.2V to 5.5V.
Symbol
PFO, WDO
VOL
Parameter
Conditions
Min
Typ
Max
Units
PFO, WDO Output
Voltage
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
0.3
0.3
0.4
V
V
VOH
0.8 VCC
0.8 VCC
CC − 1.5V
V
LLO OUTPUT
VLLOT
LLO Output Threshold
1.01•VRST
1.02•VRST
1.03•VRST
(VLLO − VRST, VCC
falling)
VLLOTH
tCD
Low-Line Comparator
Hysteresis
0.0032•VRST
20
mV
µs
Low-Line Comparator
Delay
VCC falling at 1mV/µs
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OBSOLETE
LM3712
SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage
3.3V Supply Current vs Temperature
30
29
30
25
28
20
15
10
27
26
25
24
23
5
0
25
70
85
-40
0
5
1
3
4
2
Temperature (°C)
Supply Voltage (V)
Figure 2.
Figure 3.
Normalized Reset Threshold Voltage vs Temperature
Reset Timeout Period vs VCC
0.5
220
215
210
0.4
0.3
0.2
205
200
195
190
0.1
0
-0.1
-0.2
-0.3
185
180
-0.4
-0.5
-40
25
85
5.5
5
6
3.0
4.5
3.5
4
Temperature (°C)
Supply Voltage (V)
Figure 4.
Figure 5.
Max. Transient Duration vs Reset Comparator Overdrive
(VCC = 3.3V)
Reset Timeout Period vs Temperature
215
210
205
200
80
70
60
50
40
30
20
195
190
10
0
25
-40
85
10
100
1000
Temperature (°C)
Reset Comparator Overdrive (mV)
VRST - VCC
Figure 6.
Figure 7.
6
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OBSOLETE
LM3712
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SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Watchdog Timeout Period vs Temperature
(tWD programmed as 6.2ms)
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
85
25
-40
Temperature (oC)
Figure 8.
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LM3712
SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
www.ti.com
CIRCUIT INFORMATION
RESET OUTPUT
The Reset input of a µP initializes the device into a known state. The LM3712 microprocessor supervisory
circuits assert a forced reset output to prevent code execution errors during power-up, power-down, and
brownout conditions.
RESET is ensured valid for VCC > 1V. Once VCC exceeds the reset threshold, an internal timer maintains the
output for the reset timeout period. After this interval, reset goes high. The LM3712 offers an active-low RESET.
Any time VCC drops below the reset threshold (such as during a brownout), the reset activates. When VCC again
rises above the reset threshold, the internal timer starts. Reset holds until VCC exceeds the reset threshold for
longer than the reset timeout period. After this time, reset releases.
The Manual Reset input (MR) will initiate a forced reset also. See the MANUAL RESET INPUT (MR) section.
RESET THRESHOLD
The LM3712 family is available with a reset voltage of 3.08V. Other reset thresholds in the 2.20V to 5.0V range,
in steps of 10 mV, are available; contact TI for details.
MANUAL RESET INPUT (MR)
Many µP-based products require a manual reset capability, allowing the operator to initiate a reset. The MR input
is fully debounced and provides an internal 56 kΩ pull-up. When the MR input is pulled below VMRT (1.225V) for
more than 25 µs, reset is asserted after a typical delay of 12 µs. Reset remains active as long as MR is held low,
and releases after the reset timeout period expires after MR rises above VMRT. Use MR with digital logic to assert
or to daisy chain supervisory circuits. It may be used as another low-line comparator by adding a buffer.
POWER-FAIL COMPARATOR (PFI/PFO)
The PFI is compared to a 1.225V internal reference, VPFT. If PFI is less than VPFT, the Power Fail Output PFO
drops low. The power-fail comparator signals a falling power supply, and is driven typically by an external voltage
divider that senses either the unregulated supply or another system supply voltage. The voltage divider generally
is chosen so the voltage at PFI drops below VPFT several milliseconds before the main supply voltage drops
below the reset threshold, providing advanced warning of a brownout.
The voltage threshold is set by R1 and R2 and is calculated as follows:
(1)
Note this comparator is completely separate from the rest of the circuitry, and may be employed for other
functions as needed.
WATCHDOG TIMER INPUT (WDI)
The watchdog timer input monitors one of the microprocessor's output lines for activity. Each time a transition
occurs on this monitored line, the watchdog counter is reset. However, if no transition occurs and the timeout
period is reached, the LM3712 assumes that the microprocessor has locked up and the watchdog output WDO,
is activated.
WDI is a high impedance input. WDO is an active-low totem pole output.
SPECIAL PRECAUTIONS FOR THE DSBGA PACKAGE
As with most integrated circuits, the LM3712 is sensitive to exposure from visible and infrared (IR) light radiation.
Unlike a plastic encapsulated IC, the DSBGA package has very limited shielding from light, and some sensitivity
to light reflected from the surface of the PC board or long wavelength IR entering the die from the side may be
experienced. This light could have an unpredictable affect on the electrical performance of the IC. Care should
be taken to shield the device from direct exposure to bright visible or IR light during operation.
8
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OBSOLETE
LM3712
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SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
DSBGA MOUNTING
The DSBGA package requires specific mounting techniques which are detailed in TI Application Note AN-1112.
Referring to the section Surface Mount Technology (SMT) Assembly Considerations, it should be noted that
the pad style which must be used with the 9-pin package is the NSMD (non-solder mask defined) type.
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
Timing Diagrams
Figure 9. LM3712 Reset Time with MR
Figure 10. PFI Comparator Timing Diagram
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LM3712
SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
Typical Application Circuits
VIN2
www.ti.com
VIN1
R1
V
CC
RESET
INT
RESET
PFI
mP
GND
(
WDI
MR
WDO
PFO
R2
GND
R1
.
Power-Fail Reset Threshold, VPFT = 1.225
+ 1
(
Active Data Line
R2
Figure 11. Monitoring Two Critical Supplies Plus Dataline
1.8V
3.3
V
107k
332k
VI/O
Vcore
VCC
PFI
RESET
INT
RESET
WDO
WDI
MR
PFO
GND
3.3k
Active Data Line
Figure 12. Monitoring Two Supplies plus Manual Reset And Dataline
10
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LM3712
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SNVS151F –NOVEMBER 2000–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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