LM3940IT-33 [TI]
LM3940 1A Low Dropout Regulator for 5V to 3.3V Conversion;
| 型号： | LM3940IT-33 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM3940 1A Low Dropout Regulator for 5V to 3.3V Conversion |
| 文件： | 总18页 (文件大小：1864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM3940
www.ti.com
SNVS114E –MAY 1999–REVISED MARCH 2013
LM3940 1A Low Dropout Regulator for 5V to 3.3V Conversion
Check for Samples: LM3940
1
FEATURES
APPLICATIONS
2
•
•
•
•
•
•
Output voltage specified over temperature
Excellent load regulation
•
•
Laptop/Desktop Computers
Logic Systems
Specified 1A output current
Requires only one external component
Built-in protection against excess temperature
Short circuit protected
DESCRIPTION
The LM3940 is a 1A low dropout regulator designed to provide 3.3V from a 5V supply.
The LM3940 is ideally suited for systems which contain both 5V and 3.3V logic, with prime power provided from
a 5V bus.
Because the LM3940 is a true low dropout regulator, it can hold its 3.3V output in regulation with input voltages
as low as 4.5V.
The TO-220 package of the LM3940 means that in most applications the full 1A of load current can be delivered
without using an additional heatsink.
The surface mount DDPAK/TO-263 package uses minimum board space, and gives excellent power dissipation
capability when soldered to a copper plane on the PC board.
TYPICAL APPLICATION
*Required if regulator is located more than 1″ from the power supply filter capacitor or if battery power is used.
**See APPLICATION HINTS.
CONNECTION DIAGRAM
Figure 1. 3-Lead TO-220 Package
(Front View)
Figure 2. 3-Lead DDPAK/TO-263 Package
(Front View)
Drawing Number NDE00EB
Drawing Number KTT003B
Figure 3. 3-Lead SOT-223
(Front View)
Drawing Number DCY (R-PDSO-G4)
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
LM3940
SNVS114E –MAY 1999–REVISED MARCH 2013
www.ti.com
Figure 4. 16-Lead CDIP
(Top View)
Drawing Number NFE0016A
Figure 5. 16-Lead CLGA
(Top View)
Drawing Number NAC0016A
A. Pin 2 and pin 7 are fused to center DAP.
B. Pin 5 and 6 need to be tied together on PCB board.
Figure 6. 8-Lead WSON
(Top View)(A)(B)
Drawing Number NGN008A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature Range
−65°C to +150°C
260°C
Lead Temperature (Soldering, 5 seconds)
(2)
Power Dissipation
Internally Limited
7.5V
Input Supply Voltage
(3)
ESD Rating
2 kV
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of its rated operating conditions.
(2) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ, the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die
temperature, and the regulator will go into thermal shutdown. The value of θJA (for devices in still air with no heatsink) is 60°C/W for the
TO-220 package, 80°C/W for the DDPAK/TO-263 package, and 174°C/W for the SOT-223 package. The effective value of θJA can be
reduced by using a heatsink (see APPLICATION HINTS for specific information on heatsinking). The value of θJA for the WSON
package is specifically dependant on PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal
resistance and power dissipation for the WSON package, refer to Application Note AN-1187 SNOA401. The θJA rating for the WSON is
with a JESD51-7 test board having 6 thermal vias under the exposed pad.
(3) ESD rating is based on the human body model: 100 pF discharged through 1.5 kΩ.
(1)
Operating Ratings
Junction Temperature Range, TJ
−40°C to +125°C
Input Supply Voltage, VIN(MIN)
VO + VDO
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of its rated operating conditions.
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ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = 5V, IL = 1A, COUT = 33 μF.
(1)
Symbol
Parameter
Conditions
Typical
LM3940
min
Units
max
3.20
3.13
3.40
3.47
VO
Output Voltage
5 mA ≤ IL ≤ 1A
3.3
20
V
IL = 5 mA
4.5V ≤ VIN ≤ 5.5V
Line Regulation
Load Regulation
40
(1)
(2)
mV
50
80
50 mA ≤ IL ≤ 1A
35
35
IL (DC) = 100 mA
IL (AC) = 20 mA (rms)
f = 120 Hz
ZO
Output Impedance
mΩ
4.5V ≤ VIN ≤ 5.5V
IL = 5 mA
15
20
10
IQ
Quiescent Current
mA
VIN = 5V
IL = 1A
200
250
110
150
0.5
BW = 10 Hz–100 kHz
IL = 5 mA
en
Output Noise Voltage
μV (rms)
0.8
1.0
IL = 1A
V
Dropout Voltage
VDO
(2)
150
200
IL = 100 mA
RL = 0
110
1.7
mV
A
IL(SC)
Short Circuit Current
1.2
(1) All limits specified for TJ = 25°C are 100% tested and are used to calculate Outgoing Quality Levels. All limits at temperature extremes
are verified via correlation using standard Statistical Quality Control (SQC) methods.
(2) Dropout voltage is defined as the input-output differential voltage where the regulator output drops to a value that is 100 mV below the
value that is measured at VIN = 5V.
THERMAL PERFORMANCE
3-Lead TO-220
4
4
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal Resistance, Junction-to-Case, θJC
3-Lead DDPAK/TO-263
8-Lead WSON
6
3-Lead TO-220
60
80
35
Thermal Resistance, Junction-to-Ambient, θJA
3-Lead DDPAK/TO-263
(1)
8-Lead WSON
(1) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ, the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die
temperature, and the regulator will go into thermal shutdown. The value of θJA (for devices in still air with no heatsink) is 60°C/W for the
TO-220 package, 80°C/W for the DDPAK/TO-263 package, and 174°C/W for the SOT-223 package. The effective value of θJA can be
reduced by using a heatsink (see APPLICATION HINTS for specific information on heatsinking). The value of θJA for the WSON
package is specifically dependant on PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal
resistance and power dissipation for the WSON package, refer to Application Note AN-1187 SNOA401. The θJA rating for the WSON is
with a JESD51-7 test board having 6 thermal vias under the exposed pad.
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TYPICAL PERFORMANCE CHARACTERISTICS
Dropout Voltage
Dropout Voltage vs. Temperature
Figure 7.
Figure 8.
Output Voltage vs. Temperature
Quiescent Current vs. Temperature
Figure 9.
Figure 10.
Quiescent Current vs. VIN
Quiescent Current vs. Load
Figure 11.
Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Line Transient Response
Load Transient Response
Figure 13.
Figure 14.
Ripple Rejection
Low Voltage Behavior
Figure 15.
Figure 16.
Output Impedance
Peak Output Current
Figure 17.
Figure 18.
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APPLICATION HINTS
EXTERNAL CAPACITORS
The output capacitor is critical to maintaining regulator stability, and must meet the required conditions for both
ESR (Equivalent Series Resistance) and minimum amount of capacitance.
MINIMUM CAPACITANCE:
The minimum output capacitance required to maintain stability is 33 μF (this value may be increased without
limit). Larger values of output capacitance will give improved transient response.
ESR LIMITS:
The ESR of the output capacitor will cause loop instability if it is too high or too low. The acceptable range of
ESR plotted versus load current is shown in Figure 19. It is essential that the output capacitor meet these
requirements, or oscillations can result.
Figure 19. ESR Limits
It is important to note that for most capacitors, ESR is specified only at room temperature. However, the designer
must ensure that the ESR will stay inside the limits shown over the entire operating temperature range for the
design.
For aluminum electrolytic capacitors, ESR will increase by about 30X as the temperature is reduced from 25°C to
−40°C. This type of capacitor is not well-suited for low temperature operation.
Solid tantalum capacitors have a more stable ESR over temperature, but are more expensive than aluminum
electrolytics. A cost-effective approach sometimes used is to parallel an aluminum electrolytic with a solid
Tantalum, with the total capacitance split about 75/25% with the Aluminum being the larger value.
If two capacitors are paralleled, the effective ESR is the parallel of the two individual values. The “flatter” ESR of
the Tantalum will keep the effective ESR from rising as quickly at low temperatures.
HEATSINKING
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible operating conditions, the junction temperature must be within the range
specified under Absolute Maximum Ratings.
To determine if a heatsink is required, the power dissipated by the regulator, PD, must be calculated.
Figure 20 shows the voltages and currents which are present in the circuit, as well as the formula for calculating
the power dissipated in the regulator:
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IIN = IL + IG
PD = (VIN − VOUT) IL + (VIN) IG
Figure 20. Power Dissipation Diagram
The next parameter which must be calculated is the maximum allowable temperature rise, TR (max). This is
calculated by using the formula:
TR (max) = TJ (max) − TA (max)
Where: TJ (max)is the maximum allowable junction temperature, which is 125°C for commercial grade parts.
TA (max)is the maximum ambient temperature which will be encountered in the application.
Using the calculated values for TR(max) and PD, the maximum allowable value for the junction-to-ambient
thermal resistance, θ(JA), can now be found:
θ(JA) = TR (max)/PD
IMPORTANT: If the maximum allowable value for θ(JA) is found to be ≥ 60°C/W for the TO-220 package, ≥
80°C/W for the DDPAK/TO-263 package, or ≥174°C/W for the SOT-223 package, no heatsink is needed since
the package alone will dissipate enough heat to satisfy these requirements.
If the calculated value for θ(JA)falls below these limits, a heatsink is required.
HEATSINKING TO-220 PACKAGE PARTS
The TO-220 can be attached to a typical heatsink, or secured to a copper plane on a PC board. If a copper plane
is to be used, the values of θ(JA) will be the same as shown in the HEATSINKING TO-263 section for the
DDPAK/TO-263.
If a manufactured heatsink is to be selected, the value of heatsink-to-ambient thermal resistance, θ(H−A), must
first be calculated:
θ(H−A) = θ(JA) − θ(C−H) − θ(J−C)
Where: θ(J−C) is defined as the thermal resistance from the junction to the surface of the case. A value of 4°C/W
can be assumed for θ(J−C) for this calculation.
θ(C−H) is defined as the thermal resistance between the case and the surface of the heatsink. The value of
θ(C−H) will vary from about 1.5°C/W to about 2.5°C/W (depending on method of attachment, insulator, etc.).
If the exact value is unknown, 2°C/W should be assumed for θ(C−H)
.
When a value for θ(H−A) is found using the equation shown above, a heatsink must be selected that has a value
that is less than or equal to this number.
θ(H−A) is specified numerically by the heatsink manufacturer in the catalog, or shown in a curve that plots
temperature rise vs. power dissipation for the heatsink.
HEATSINKING DDPAK/TO-263 AND SOT-223 PACKAGE PARTS
Both the DDPAK/TO-263 (“KTT”) and SOT-223 (“DCY”) packages use a copper plane on the PCB and the PCB
itself as a heatsink. To optimize the heat sinking ability of the plane and PCB, solder the tab of the package to
the plane.
Figure 21 shows for the DDPAK/TO-263 the measured values of θ(JA) for different copper area sizes using a
typical PCB with 1 ounce copper and no solder mask over the copper area used for heatsinking.
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Figure 21. θ(JA) vs. Copper (1 ounce) Area for the DDPAK/TO-263 Package
As shown in Figure 21, increasing the copper area beyond 1 square inch produces very little improvement. It
should also be observed that the minimum value of θ(JA) for the DDPAK/TO-263 package mounted to a PCB is
32°C/W.
As a design aid, Figure 22 shows the maximum allowable power dissipation compared to ambient temperature
for the DDPAK/TO-263 device (assuming θ(JA) is 35°C/W and the maximum junction temperature is 125°C).
Figure 22. Maximum Power Dissipation vs. TAMB for the DDPAK/TO-263 Package
Figure 23 and Figure 24 show the information for the SOT-223 package. Figure 24 assumes a θ(JA) of 74°C/W
for 1 ounce copper and 51°C/W for 2 ounce copper and a maximum junction temperature of 125°C.
Figure 23. θ(JA) vs. Copper (2 ounce) Area for the SOT-223 Package
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Figure 24. Maximum Power Dissipation vs. TAMB for the SOT-223 Package
Please see AN1028 for power enhancement techniques to be used with the SOT-223 package.
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
LM3940IMP-3.3
ACTIVE
SOT-223
SOT-223
DCY
4
4
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
L52B
LM3940IMP-3.3/NOPB
ACTIVE
DCY
1000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
L52B
LM3940IMPX-3.3
ACTIVE
ACTIVE
SOT-223
SOT-223
DCY
DCY
4
4
2000
2000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
L52B
L52B
LM3940IMPX-3.3/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM3940IS-3.3
LM3940IS-3.3/NOPB
LM3940ISX-3.3
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
KTT
KTT
KTT
KTT
NDE
NDE
3
3
3
3
3
3
45
45
TBD
Call TI
CU SN
Call TI
CU SN
Call TI
CU SN
Call TI
Level-3-245C-168 HR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LM3940IS
-3.3 P+
DDPAK/
TO-263
Pb-Free (RoHS
Exempt)
LM3940IS
-3.3 P+
DDPAK/
TO-263
500
500
45
TBD
LM3940IS
-3.3 P+
LM3940ISX-3.3/NOPB
LM3940IT-3.3
DDPAK/
TO-263
Pb-Free (RoHS
Exempt)
Level-3-245C-168 HR
Call TI
LM3940IS
-3.3 P+
TO-220
TBD
LM3940IT
-3.3 P+
LM3940IT-3.3/NOPB
TO-220
45
Green (RoHS
& no Sb/Br)
Level-1-NA-UNLIM
LM3940IT
-3.3 P+
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3940IMP-3.3
SOT-223
DCY
DCY
DCY
DCY
KTT
4
4
4
4
3
1000
1000
2000
2000
500
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
24.4
7.0
7.0
7.0
7.0
7.5
7.5
7.5
7.5
2.2
2.2
2.2
2.2
5.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
24.0
Q3
Q3
Q3
Q3
Q2
LM3940IMP-3.3/NOPB SOT-223
LM3940IMPX-3.3 SOT-223
LM3940IMPX-3.3/NOPB SOT-223
LM3940ISX-3.3
DDPAK/
TO-263
10.75 14.85
LM3940ISX-3.3/NOPB DDPAK/
TO-263
KTT
3
500
330.0
24.4
10.75 14.85
5.0
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3940IMP-3.3
LM3940IMP-3.3/NOPB
LM3940IMPX-3.3
SOT-223
SOT-223
DCY
DCY
DCY
DCY
KTT
KTT
4
4
4
4
3
3
1000
1000
2000
2000
500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
45.0
45.0
SOT-223
LM3940IMPX-3.3/NOPB
LM3940ISX-3.3
SOT-223
DDPAK/TO-263
DDPAK/TO-263
LM3940ISX-3.3/NOPB
500
Pack Materials-Page 2
MECHANICAL DATA
NDE0003B
www.ti.com
MECHANICAL DATA
MPDS094A – APRIL 2001 – REVISED JUNE 2002
DCY (R-PDSO-G4)
PLASTIC SMALL-OUTLINE
6,70 (0.264)
6,30 (0.248)
3,10 (0.122)
2,90 (0.114)
4
0,10 (0.004)
M
3,70 (0.146)
3,30 (0.130)
7,30 (0.287)
6,70 (0.264)
Gauge Plane
1
2
3
0,25 (0.010)
0,84 (0.033)
0,66 (0.026)
0°–10°
2,30 (0.091)
0,10 (0.004)
M
4,60 (0.181)
0,75 (0.030) MIN
1,70 (0.067)
1,50 (0.059)
1,80 (0.071) MAX
0,35 (0.014)
0,23 (0.009)
Seating Plane
0,08 (0.003)
0,10 (0.0040)
0,02 (0.0008)
4202506/B 06/2002
NOTES: A. All linear dimensions are in millimeters (inches).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC TO-261 Variation AA.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
KTT0003B
TS3B (Rev F)
BOTTOM SIDE OF PACKAGE
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