LM43602AQPWPTQ1 [TI]
通过汽车级认证的 3.5V 至 36V、2A 同步降压电压转换器 | PWP | 16 | -40 to 125;
| 型号： | LM43602AQPWPTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 通过汽车级认证的 3.5V 至 36V、2A 同步降压电压转换器 | PWP | 16 | -40 to 125 转换器 |
| 文件： | 总46页 (文件大小：1854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM43602-Q1
ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
LM43602-Q1 3.5V 至 36V 2A 同步降压转换器
1 特性
3 说明
1
•
•
符合汽车应用要求 认证
具有符合 AEC-Q100 标准的下列结果：
LM43602-Q1稳压器是一款易于使用的同步降压直流/
直流转换器，能够驱动高达 2A 的负载电流，输入电压
范围为 3.5V 至 36V（最大绝对值 42V）。LM43602-
Q1 以极小的解决方案尺寸提供优异的效率、输出精度
和压降电压。扩展系列产品能够以引脚到引脚兼容封装
提供 0.5A、1A 和 3A 负载电流选项。采用峰值电流模
式控制来实现简单控制环路补偿和逐周期电流限制。可
选 功能 包括可编程开关频率、同步、电源正常标志、
精确使能、内部软启动、可扩展软启动和跟踪，可为各
种 应用提供灵活且易于使用的平台应用中对通道损失
进行线性补偿。轻载时的断续传导和自动频率调制可提
升轻载效率。此系列只需要很少的外部组件，并且引脚
排列可实现简单、最优的印刷电路板 (PCB) 布局布
线。保护 功能 包括热关断、VCC 欠压锁定、逐周期电
流限制和输出短路保护。LM43602-Q1 器件采用
HTSSOP (PWP) 16 引脚引线式封装 (6.6mm x 5.1mm
x 1.2mm)。LM43602A-Q1 版本针对 PFM 操作进行优
化，推荐用于新设计。该器件与 LM4360x 和
–
器件温度等级 2：环境工作温度范围为 –40°C
至 +125°C
•
•
•
•
•
稳压静态电流 27µA
可在轻负载条件下实现高效率（DCM 和 PFM）
符合 EN55022/CISPR 22 电磁干扰 (EMI) 标准
集成同步整流
可调频率范围：200kHz 至 2.2MHz（默认值为
500kHz）
•
•
•
与外部时钟频率同步
内部补偿
几乎可与陶瓷、固态电解、钽和铝质电容器的任一
组合一同工作时保持稳定
•
•
•
•
•
•
•
•
•
电源正常状态标志
软启动至预偏置负载
内部软启动：4.1ms
可由外部电容器延长的软启动时间
输出电压跟踪功能
LM4600x 系列引脚到引脚兼容。
程序系统欠压闭锁 (UVLO) 精确使能
具有断续模式的输出短路保护
过热关断保护
使用 LM43602-Q1 并借助 WEBENCH® 电源设计
器创建定制设计
器件信息
器件型号
LM43602-Q1
LM43602A-Q1
封装
HTSSOP (16)
HTSSOP (16)
封装尺寸
6.60mm x 5.10mm
6.60mm x 5.10mm
空白
空白
2 应用
•
•
•
•
•
AM 以下波段汽车应用
工业用电源
通用宽 VIN 稳压
高效负载点稳压
电信系统
简化原理图
辐射发射图
12VIN 至 3.3VOUT FS = 500kHz IOUT = 2A
L
80
Evaluation Board
VOUT
VIN
VIN
SW
70
60
50
40
30
20
10
0
EN 55022 Class B Limit
EN 55022 Class A Limit
COUT
CIN
LM43602Q
CBOOT
CBOOT
BIAS
ENABLE
PGOOD
SS/TRK
RT
CBIAS
CFF
RFBT
FB
VCC
SYNC
AGND
RFBB
CVCC
PGND
0
200
400
600
800
1000
C001
Frequency (MHz)
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSA83
LM43602-Q1
ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 20
Applications and Implementation ...................... 22
8.1 Application Information............................................ 22
8.2 Typical Applications ................................................ 22
Power Supply Recommendations...................... 33
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 7
6.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 36
11 器件和文档支持 ..................................................... 37
11.1 器件支持................................................................ 37
11.2 开发支持................................................................ 37
11.3 接收文档更新通知 ................................................. 37
11.4 社区资源................................................................ 37
11.5 商标....................................................................... 38
11.6 静电放电警告......................................................... 38
11.7 Glossary................................................................ 38
12 机械、封装和可订购信息....................................... 38
7
4 修订历史记录
Changes from Revision B (April 2017) to Revision C
Page
•
•
已添加 TI 参考设计的顶部导航图标 ........................................................................................................................................ 1
Changed MAX value for VBIAS rising threshold from "3.16" to "3.18" V ............................................................................... 5
Changes from Revision A (May 2015) to Revision B
Page
•
•
•
•
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•
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•
•
已添加 WEBENCH 链接 ......................................................................................................................................................... 1
添加了 LM43602A-Q1 版本 .................................................................................................................................................... 1
Added Maximum Operating Junction Temperature ............................................................................................................... 4
Updating RPGOOD value for EN = 3.3V and EN = 0V ......................................................................................................... 6
Updating EN Falling Threshold Curve ................................................................................................................................. 10
Updating EN Rising Threshold Curve ................................................................................................................................. 10
Updating EN Hysteresis Curve ............................................................................................................................................ 10
Added Equation 25 .............................................................................................................................................................. 28
Added Equation 26 .............................................................................................................................................................. 28
Changes from Original (April 2015) to Revision A
Page
•
•
•
•
•
•
•
•
已更改 器件从产品预览改为量产数据 ..................................................................................................................................... 1
已删除 “AM 以上波段”............................................................................................................................................................. 1
Added "BIAS pin voltage should not exceed VIN" to BIAS pin description ........................................................................... 3
Added TYPE column to Pin Functions table ......................................................................................................................... 3
Added "of 10000 hours" to FN 2 of table ............................................................................................................................... 4
Changed info in Vfb rows; in ILKG-FB changed value of from FB=1.011 V to 1.015 V ....................................................... 6
Changed The internal REF voltage is "1.011 V" to "1.015 V" .............................................................................................. 14
Changed VFB = "1.011 V" to "1.015 V" ................................................................................................................................ 24
2
Copyright © 2015–2017, Texas Instruments Incorporated
LM43602-Q1
www.ti.com.cn
ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
SW
SW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGND
PGND
VIN
CBOOT
VCC
VIN
PAD
EN
BIAS
SS/TRK
AGND
FB
SYNC
RT
PGOOD
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NUMBER
Switching output of the regulator. Internally connected to both power MOSFETs. Connect to
power inductor.
SW
1,2
P
P
P
Boot-strap capacitor connection for high-side driver. Connect a high quality 470-nF capacitor
from CBOOT to SW.
CBOOT
VCC
3
4
Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND.
Do not connect external loading to this pin. Never short this pin to ground during operation.
Optional internal LDO supply input. To improve efficiency, it is recommended to tie to VOUT
when 3.3 V ≤ VOUT ≤ 28 V, or tie to an external 3.3 V or 5 V rail if available. When used, place
a bypass capacitor (1 to 10 µF) from this pin to ground. Tie to ground when not in use. BIAS
pin voltage should not exceed VIN.
BIAS
5
P
Clock input to synchronize switching action to an external clock. Use proper high speed
termination to prevent ringing. Connect to ground if not used.
SYNC
RT
6
7
A
A
A
A
G
A
A
Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating
for 500 kHz default switching frequency.
Open drain output for power-good flag. Use a 10 kΩ to 100 kΩ pullup resistor to logic rail or
other DC voltage no higher than 12 V.
PGOOD
FB
8
Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do not
short this pin to ground during operation.
9
Analog ground pin. Ground reference for internal references and logic. Connect to system
ground.
AGND
SS/TRK
EN
10
11
12
Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a capacitor to
extend soft start time. Connect to external voltage ramp for tracking.
Enable input to the internal LDO and regulator. High = ON and low = OFF. Connect to VIN, or
to VIN through resistor divider,or to an external voltage or logic source. Do not float.
Supply input pins to internal LDO and high side power FET. Connect to power supply and
bypass capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND must be as
short as possible.
VIN
13,14
P
Power ground pins, connected internally to the low side power FET. Connect to system
ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.
PGND
PAD
15,16
-
G
Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path
of the die. Must be used for heat sinking to ground plane on PCB.
—
(1) P = Power, G = Ground, A = Analog
Copyright © 2015–2017, Texas Instruments Incorporated
3
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ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over the recommended operating junction temperature (TJ) range of –40°C to +125°C (unless otherwise noted)(1)
PARAMETER
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–3.5
–0.3
–0.3
–65
MAX
42(2)
VIN + 0.3
3.6
UNIT
VIN to PGND
EN to PGND
FB, RT, SS/TRK to AGND
PGOOD to AGND
SYNC to AGND
Input voltages
15
V
5.5
(3)
BIAS to AGND
30 or VIN
0.3
AGND to PGND
SW to PGND
VIN + 0.3
42
SW to PGND less than 10-ns transients
CBOOT to SW
Output voltages
V
5.5
VCC to AGND
3.6
Storage temperature, Tstg
150
°C
°C
Operating junction temperature
–40
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) At max duty cycle 0.01% of 10000 hours.
(3) Whichever is lower.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over the recommended operating junction temperature (TJ) range of –40°C to +125°C (unless otherwise noted)(1)
MIN
3.5
MAX
UNIT
VIN to PGND
36
VIN
1.1
12
EN
–0.3
–0.3
–0.3
–0.3
3.3
FB
Input voltages
PGOOD
V
BIAS input not used
BIAS input used
AGND to PGND
VOUT
0.3
(2)
28 or VIN
–0.1
1
0.1
28
Output voltage
Output current
Temperature
V
A
IOUT
0
2
Operating junction temperature, TJ
–40
125
°C
(1) Recommended Operation Conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For specified specifications, see Electrical Characteristics.
(2) Whichever is lower.
4
Copyright © 2015–2017, Texas Instruments Incorporated
LM43602-Q1
www.ti.com.cn
ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
6.4 Thermal Information
LM43602-Q1
THERMAL METRIC(1)(2)(3)
PWP (HTSSOP )
UNIT
16 PINS
38.9(4)
24.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
19.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJB
19.7
RθJC(bot)
1.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7;
(3) Thermal resistances were simulated on a 4 layer, JEDEC board.
(4) See Figure 64 for RθJA vs Copper Area curve.
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER
SUPPLY VOLTAGE (VIN PIN)
CONDITIONS
MIN
TYP
MAX
UNIT
VIN-MIN-ST
ISHDN
Minimum input voltage for startup
Shutdown quiescent current
3.8
3.1
V
VEN = 0 V
1.2
5
µA
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external
Operating quiescent current (non-
switching) from VIN
IQ-NONSW
10
µA
µA
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external
Operating quiescent current (non-
switching) from external VBIAS
IBIAS-NONSW
85
27
130
VEN = 3.3 V
IOUT = 0 A
IQ-SW
Operating quiescent current (switching) RT = open
VBIAS = VOUT = 3.3 V
µA
RFBT = 1 Meg
ENABLE (EN PIN)
Voltage level to enable the internal LDO
output VCC
VEN-VCC-H
VENABLE high level
VENABLE low level
VENABLE high level
1.2
2
V
V
V
Voltage level to disable the internal LDO
output VCC
VEN-VCC-L
0.525
2.42
Precision enable level for switching and
regulator output: VOUT
VEN-VOUT-H
2.2
Hysteresis voltage between VOUT
precision enable and disable thresholds
VEN-VOUT-HYS
ILKG-EN
VENABLE hysteresis
VEN = 3.3 V
–290
0.85
mV
µA
Enable input leakage current
1.75
INTERNAL LDO (VCC and BIAS PINS)
VCC
Internal LDO output voltage VCC
VIN ≥ 3.8 V
3.28
3.1
V
V
VCC rising threshold
Undervoltage lock out (UVLO)
thresholds for VCC
VCC-UVLO
Hysteresis voltage between rising and
falling thresholds
–520
2.94
–75
mV
V
VBIAS rising threshold
3.18
Internal LDO input change over
threshold to BIAS
VBIAS-ON
Hysteresis voltage between rising and
falling thresholds
mV
Copyright © 2015–2017, Texas Instruments Incorporated
5
LM43602-Q1
ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE (FB PIN)
TJ = 25ºC
1.012 1.015 1.019
0.999 1.015 1.032
VFB
Feedback voltage
V
TJ = –40ºC to 125 ºC
FB = 1.015 V
ILKG-FB
Input leakage current at FB pin
0.2
65
nA
THERMAL SHUTDOWN
Shutdown threshold
Recovery threshold
160
150
ºC
ºC
(1)
TSD
Thermal shutdown
CURRENT LIMIT AND HICCUP
IHS-LIMIT
ILS-LIMIT
SOFT START (SS/TRK PIN)
Peak inductor current limit
3.65
1.75
4.5
2
5.15
2.25
A
A
Inductor current valley limit
ISSC
Soft-start charge current
Soft-start discharge resistance
1.25
2
2.75
µA
RSSD
UVLO, TSD, OCP, or EN = 0 V
18
kΩ
POWER GOOD (PGOOD PIN)
Power-good flag over voltage tripping
threshold
VPGOOD-HIGH
% of FB voltage
% of FB voltage
110% 113%
Power-good flag under voltage tripping
threshold
VPGOOD-LOW
VPGOOD-HYS
77%
88%
6%
Power-good flag recovery hysteresis
% of FB voltage
VEN = 3.3 V
VEN = 0 V
69
150
350
PGOOD pin pulldown resistance when
power bad
RPGOOD
Ω
150
MOSFETS(2)
IOUT = 1 A
VBIAS = VOUT = 3.3 V
RDS-ON-HS
High-side MOSFET ON resistance
Low-side MOSFET ON resistance
120
65
mΩ
mΩ
IOUT = 1 A
VBIAS = VOUT = 3.3 V
RDS-ON-LS
(1) Ensured by design.
(2) Measured at the pins.
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
CURRENT LIMIT AND HICCUP
NOC
TOC
Hiccup wait cycles when LS current limit tripped
Hiccup retry delay time
32
Cycles
ms
5.5
SOFT START (SS/TRK PIN)
TSS
Internal soft-start time when SS pin open circuit
4.1
ms
POWER GOOD (PGOOD PIN)
TPGOOD-RISE Power-good flag rising transition deglitch delay
TPGOOD-FALL Power-good flag falling transition deglitch delay
220
220
µs
µs
6
Copyright © 2015–2017, Texas Instruments Incorporated
LM43602-Q1
www.ti.com.cn
ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SW (SW PIN)
Minimum high side MOSFET ON
time
(1)
tON-MIN
125
200
165
250
ns
ns
Minimum high side MOSFET OFF
time
(1)
tOFF-MIN
OSCILLATOR (SW and SYNC PINS)
FOSC-
DEFAULT
Oscillator default frequency
RT pin open circuit
425
500
580
kHz
Minimum adjustable frequency
200
2200
10%
kHz
kHz
FADJ
Maximum adjustable frequency
Frequency adjust accuracy
With 1% resistors at RT pin
VSYNC-HIGH Sync clock high level threshold
VSYNC-LOW Sync clock low level threshold
DSYNC-MAX Sync clock maximum duty cycle
DSYNC-MIN Sync clock minimum duty cycle
2
V
V
0.4
90%
10%
Mininum sync clock ON and OFF
TSYNC-MIN
time
80
ns
(1) Ensured by design.
Copyright © 2015–2017, Texas Instruments Incorporated
7
LM43602-Q1
ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
www.ti.com.cn
6.8 Typical Characteristics
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 6.8 µH and room temperature. Refer to Application
Performance Curves for bill of materials for other VOUT and FS combinations.
100
90
80
70
60
50
40
100
90
80
70
60
50
40
5VIN
5VIN
12VIN
24VIN
12VIN
24VIN
0.001
0.01
0.1
Current (A)
1
0
0.5
1
1.5
2
Current (A)
FS = 500 kHz
C001
C001
VOUT = 3.3 V
FS = 500 kHz
VOUT = 3.3 V
Figure 1. Efficiency at Room Temperature
Figure 2. Efficiency at Room Temperature
100
90
80
70
60
50
40
100
90
80
70
60
50
40
5VIN
12VIN
12VIN
24VIN
24VIN
1
0.001
0.01
0.1
Current (A)
1
0.001
0.01
0.1
Current (A)
C001
C001
VOUT = 3.3 V
FS = 500 kHz
VOUT = 5 V
FS = 500 kHz
Figure 3. Efficiency at 85°C
Figure 4. Efficiency at Room Temperature
100
90
80
70
60
50
100
90
80
70
60
50
40
12VIN
24VIN
12VIN
24VIN
1
40
0
0.5
1
1.5
2
0.001
0.01
0.1
Current (A)
Current (A)
FS = 500 kHz
C001
C001
VOUT = 5 V
VOUT = 5 V
FS = 500 kHz
Figure 5. Efficiency at Room Temperature
Figure 6. Efficiency at 85°C
8
Copyright © 2015–2017, Texas Instruments Incorporated
LM43602-Q1
www.ti.com.cn
ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 6.8 µH and room temperature. Refer to Application
Performance Curves for bill of materials for other VOUT and FS combinations.
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
5VIN
8VIN
12VIN
24VIN
12VIN
24VIN
0.001
0.01
0.1
Current (A)
1
0.001
0.01
0.1
Current (A)
1
C001
C004
VOUT = 3.3 V
FS = 500 kHz
VOUT = 5 V
FS = 500 kHz
Figure 7. VOUT Regulation
Figure 8. VOUT Regulation
3.5
3.4
3.3
3.2
3.1
3.0
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
0.1A
0.5A
1A
0.1A
0.5A
1A
1.5A
2A
1.5A
2A
2.9
3.5
3.7
3.9
4.1
4.3
4.5
5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00
VIN (V)
VIN (V)
C007
C007
VOUT = 3.3 V
FS = 500 kHz
VOUT = 5 V
FS = 500 kHz
Figure 9. Dropout Curve
Figure 10. Dropout Curve
1000000
1000000
100000
10000
1000
100000
0.1A
0.5A
1A
0.1A
0.5A
1A
1.5A
2A
1.5A
2A
10000
3.5
3.7
3.9
4.1
4.3
4.5
5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00
VIN (V)
VIN (V)
C007
C007
VOUT = 3.3 V
FS = 500 kHz
VOUT = 5 V
FS = 500 kHz
Figure 11. Frequency vs VIN
Figure 12. Frequency vs VIN
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 6.8 µH and room temperature. Refer to Application
Performance Curves for bill of materials for other VOUT and FS combinations.
2.000
1.950
1.900
1.850
1.800
1.750
1.700
1.650
1.600
2.200
2.150
2.100
2.050
2.000
1.950
1.900
5
20 35 50 65 80 95 110 125
5
20 35 50 65 80 95 110 125
œ40 œ25 œ10
œ40 œ25 œ10
Temperature (deg C)
Temperature (deg C)
C001
C001
Figure 13. EN Falling Threshold vs Junction Temperature
Figure 14. EN Rising Threshold vs Junction Temperature
1.020
310
300
290
280
270
260
250
1.015
1.010
1.005
1.000
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
5
20 35 50 65 80 95 110 125
œ40 œ25 œ10
Temperature (deg C)
Temperature (deg C)
C001
C001
Figure 16. FB Voltage vs Junction Temperature
Figure 15. EN Hysteresis vs Junction Temperature
4.200
2.200
2.100
2.000
1.900
1.800
4.100
4.000
3.900
3.800
3.700
3.600
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
Temperature (deg C)
Temperature (deg C)
C001
C001
Figure 17. HS Current Limit vs Junction Temperature
Figure 18. LS Current Limit vs Junction Temperature
10
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 6.8 µH and room temperature. Refer to Application
Performance Curves for bill of materials for other VOUT and FS combinations.
190
180
170
160
150
140
130
120
110
100
90
90
85
80
75
70
65
60
55
50
45
40
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
Temperature (deg C)
Temperature (deg C)
C001
C001
Figure 19. High Side FET On Resistance vs Junction
Temperature
Figure 20. Low Side FET On Resistance vs Junction
Temperature
112.0
107.0
111.5
111.0
110.5
110.0
109.5
109.0
106.5
106.0
105.5
105.0
104.5
104.0
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
Temperature (deg C)
Temperature (deg C)
C001
C001
Figure 21. PGOOD OVP Falling Threshold vs Junction
Temperature
Figure 22. PGOOD OVP Rising Threshold vs Junction
Temperature
92.0
91.0
90.0
89.0
88.0
87.0
86.0
98.0
97.0
96.0
95.0
94.0
93.0
92.0
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
œ40 œ25 œ10
5
20 35 50 65 80 95 110 125
Temperature (deg C)
Temperature (deg C)
C001
C001
Figure 23. PGOOD UVP Falling Threshold vs Junction
Temperature
Figure 24. PGOOD UVP Rising Threshold vs Junction
Temperature
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7 Detailed Description
7.1 Overview
The LM43602-Q1 regulator is an easy-to-use synchronous step-down DC-DC converter that operates from 3.5-V
to 36-V supply voltage. The device delivers up to 2-A DC load current with exceptional efficiency and thermal
performance in a very small solution size. An extended family is available in 0.5-A, 1-A, and 3-A load options in
pin-to-pin compatible packages.
The LM43602-Q1 employs fixed frequency peak current mode control with discontinuous conduction mode
(DCM) and pulse frequency modulation (PFM) mode at light load to achieve high efficiency across the load
range. The device is internally compensated, which reduces design time, and requires fewer external
components. The switching frequency is programmable from 200 kHz to 2.2 MHz by an external resistor RT. It is
default at 500 kHz without RT resistor. The LM43602-Q1 is also capable of synchronization to an external clock
within the 200-kHz to 2.2-MHz frequency range. The wide switching frequency range allows the device to be
optimized to fit small board space at higher frequency, or high efficient power conversion at lower frequency.
Optional features are included for more comprehensive system requirements, including power-good (PGOOD)
flag, precision enable, synchronization to external clock, extendable soft-start time, and output voltage tracking.
These features provide a flexible and easy to use platform for a wide range of applications. Protection features
include overtemperature shutdown, VCC undervoltage lockout (UVLO), cycle-by-cycle current limit, and short-
circuit protection with hiccup mode.
The family requires few external components and the pin arrangement was designed for simple, optimum PCB
layout. The LM43602-Q1 device is available in the HTSSOP / PWP 16-pin leaded package.
7.2 Functional Block Diagram
ENABLE
VCC
BIAS
LDO
VCC
Enable
VIN
Internal
SS
ISSC
Precision
Enable
CBOOT
SS/TRK
HS I Sense
+
EA
+
REF
œ
RC
CC
+ œ
TSD
UVLO
SW
PWM CONTROL LOGIC
PFM
PGood
Detector
PGOOD
OV/UV
Detector
Slope
Comp
FB
HICCUP
Cross Detector
Freq
Foldback
Zero
Oscillator
LS I Sense
AGND
FB
PGood
SYNC
RT
PGND
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7.3 Feature Description
7.3.1 Fixed Frequency Peak Current Mode Controlled Step-Down Regulator
The following operating description of the LM43602-Q1 refers to the Functional Block Diagram and to the
waveforms in Figure 25. The LM43602-Q1 is a step-down buck regulator with both high-side (HS) switch and
low-side (LS) switch (synchronous rectifier) integrated. The LM43602-Q1 supplies a regulated output voltage by
turning on the HS and LS NMOS switches with controlled ON time. During the HS switch ON time, the SW pin
voltage VSW swings up to approximately VIN, and the inductor current iL increases with a linear slope (VIN – VOUT
)
/ L. When the HS switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through
dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The control parameter of
buck converters are defined as duty cycle D = tON / TSW, where tON is the HS switch ON time and TSW is the
switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In
an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
V
SW
D = t
ON
/ T
SW
V
IN
t
t
OFF
ON
0
D1
t
-V
T
SW
iL
I
I
LPK
OUT
ûi
L
0
t
Figure 25. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LM43602-Q1 synchronous buck converter employs peak current mode control topology. A voltage feedback
loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage
offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the
ON time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency in Continuous Conduction Mode (CCM) and
Discontinuous Conduction Mode (DCM). At very light load, the LM43602-Q1 operates in PFM to maintain high
efficiency, and the switching frequency decreases with reduced load current.
7.3.2 Light Load Operation
DCM operation is employed in the LM43602-Q1 when the inductor current valley reaches zero. The LM43602-Q1
is in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS
switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET
at zero current and the conduction loss is lowered by not allowing negative current conduction. Power conversion
efficiency is higher in DCM than CCM under the same conditions.
In DCM, the HS switch ON time reduces with lower load current. When either the minimum HS switch ON time
(tON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency decreases to
maintain regulation. At this point, the LM43602-Q1 operates in PFM. In PFM, switching frequency is decreased
by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further
reduced in PFM operation due to less frequent switching actions.
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Feature Description (continued)
In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed at VOUT. Please refer to the Typical Characteristics for
typical DC offset at very light load. If the DC offset on VOUT is not acceptable for a given application, a static load
at output is recommended to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and
RFBB can also serve as a static load. In conditions with low VIN and/or high frequency, the LM43602-Q1 may not
enter PFM mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector.
Once the LM43602-Q1 is operating in PFM mode at higher VIN, it remains in PFM operation when VIN is reduced
7.3.3 Adjustable Output Voltage
The voltage regulation loop in the LM43602-Q1 regulates output voltage by maintaining the voltage on FB pin
(VFB) to be the same as the internal REF voltage (VREF). A resistor divider pair is needed to program the ratio
from output voltage VOUT to VFB. The resistor divider is connected from the VOUT of the LM43602-Q1 to ground
with the mid-point connecting to the FB pin.
VOUT
RFBT
FB
RFBB
Figure 26. Output Voltage Setting
The voltage reference system produces a precise voltage reference over temperature. The internal REF voltage
is 1.015 V typically. To program the output voltage of the LM43602-Q1 to be a certain value VOUT, RFBB can be
calculated with a selected RFBT by
VFB
RFBB
=
RFBT
VOUT - VFB
(1)
The choice of the RFBT depends on the application. RFBT in the range from 10 kΩ to 100 kΩ is recommended for
most applications. A lower RFBT value can be used if static loading is desired to reduce VOUT offset in PFM
operation. Lower RFBT reduces efficiency at very light load. Less static current goes through a larger RFBT and
might be more desirable when light load efficiency is critical. But RFBT larger than 1 MΩ is not recommended
because it makes the feedback path more susceptible to noise. Larger RFBT value requires more carefully
designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the
output voltage regulation. It is recommended to use divider resistors with 1% tolerance or better and temperature
coefficient of 100 ppm or lower.
If the resistor divider is not connected properly, output voltage cannot be regulated because the feedback loop is
broken. If the FB pin is shorted to ground, the output voltage is driven close to VIN because the regulator sees
very low voltage on the FB pin and tries to regulator it up. The load connected to the output could be damaged
under such a condition. Do not short FB pin to ground when the LM43602-Q1 is enabled. It is important to route
the feedback trace away from the noisy area of the PCB. For more layout recommendations, refer to the Layout
section.
7.3.4 Enable (EN)
Voltage on the EN pin (VEN) controls the ON or OFF operation of the LM43602-Q1. Applying a voltage less than
0.4 V to the EN input shuts down the operation of the LM43602-Q1. In shutdown mode the quiescent current
drops to typically 1.2 µA at VIN = 12 V.
The internal LDO output voltage VCC is turned on when VEN is higher than 1.2 V. Switching action and output
regulation are enabled when VEN is greater than 2.1 V (typical). The LM43602-Q1 supplies regulated output
voltage when enabled and output current up to 2 A.
The EN pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of the
LM43602-Q1 is to connect the EN pin to VIN pins directly. This allows self-start-up when VIN is within the
operation range.
14
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Feature Description (continued)
Many applications benefit from the employment of an enable divider RENT and RENB in Figure 27 to establish a
precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power
as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such
as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.
VIN
RENT
ENABLE
RENB
Figure 27. System UVLO by Enable Dividers
7.3.5 VCC, UVLO, and BIAS
The LM43602-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 3.2 V. The VCC pin is the output of the LDO must be properly bypassed. A high-
quality ceramic capacitor with 2.2-µF to 10-µF capacitance and 6.3 V or higher rated voltage should be placed as
close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin must not be
loaded, left floating, or shorted to ground during operation. Shorting VCC to ground during operation may cause
damage to the LM43602-Q1.
Undervoltage lockout (UVLO) prevents the LM43602-Q1 from operating until the VCC voltage exceeds 3.15 V
(typical). The VCC UVLO threshold has 575 mV of hysteresis (typically) to prevent undesired shuting down due to
temporary VIN droops.
The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the
LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO × (VIN-
– VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power
LDO
loss occur to supply the same output current. The BIAS input is designed to reduce the difference of the input
and output voltages of the LDO to reduce power loss and improve LM43602-Q1 efficiency, especially at light
load. TI recommends tying the BIAS pin to VOUT when VOUT ≥ 3.3 V. The BIAS pin must be grounded in
applications with VOUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to
reduce power loss. When used, a 1-µF to 10-µF high-quality ceramic capacitor is recommended to bypass the
BIAS pin to ground.
7.3.6 Soft Start and Voltage Tracking (SS/TRK)
The LM43602-Q1 has a flexible and easy to use start-up rate control pin: SS/TRK. Soft-start feature is to prevent
inrush current impacting the LM43602-Q1 and its supply when power is first applied. Soft-start is achieved by
slowly ramping up the target regulation voltage when the device is first enabled or powered up.
The simplest way to use the part is to leave the SS/TRK pin open circuit or floating. The LM43602-Q1 employs
the internal soft-start control ramp and start up to the regulated output voltage in 4.1 ms typically.
In applications with a large amount of output capacitors, or higher VOUT, or other special requirements the soft-
start time can be extended by connecting an external capacitor CSS from SS/TRK pin to AGND. Extended soft-
start time further reduces the supply current needed to charge up output capacitors and supply any output
loading. An internal current source (ISSC = 2.2 µA) charges CSS and generates a ramp from 0 V to VFB to control
the ramp-up rate of the output voltage. For a desired soft start time tSS, the capacitance for CSS can be found by
CSS = ISSC ì tSS
(2)
The LM43602-Q1 is capable of start up into prebiased output conditions. When the inductor current reaches
zero, the LS switch is turned off to avoid negative current conduction. This operation mode is also called diode
emulation mode. It is built-in by the DCM operation in light loads. With prebiased output voltage, the LM43602-
Q1 waits until the soft-start ramp allows regulation above the prebiased voltage and then follows the soft-start
ramp to regulation level.
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Feature Description (continued)
When an external voltage ramp is applied to the SS/TRK pin, the LM43602-Q1 FB voltage follows the ramp if the
ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the external
control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final voltage seen by the
SS/TRK pin should not fall below 1.2 V to avoid abnormal operation.
EXT RAMP
RTRT
SS/TRK
RTRB
Figure 28. Soft Start Tracking External Ramp
VOUT tracked to external voltage ramps has options of ramping up slower or faster than the internal voltage ramp.
VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. Figure 29
shows the case when VOUT ramps slower than the internal ramp, while Figure 30 shows when VOUT ramps faster
than the internal ramp. Faster start-up time may result in inductor current tripping current protection during start-
up. Use with special care.
Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 29. Tracking with Longer Start-up Time than the Internal Ramp
Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 30. Tracking with Shorter Start-up Time than the Internal Ramp
7.3.7 Switching Frequency (RT) and Synchronization (SYNC)
The switching frequency of the LM43602-Q1 can be programmed by the impedance RT from the RT pin to
ground. The frequency is inversely proportional to the RT resistance. The RT pin can be left floating and the
LM43602-Q1 operates at 500-kHz default switching frequency. The RT pin is not designed to be shorted to
ground. For a desired frequency, typical RT resistance can be found by Equation 3. Table 1 gives typical RT
values with a given FS.
RT(kΩ) = 40200 / Freq (kHz) – 0.6
(3)
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Feature Description (continued)
250
200
150
100
50
0
0
500
1000
1500
2000
2500
Switching Frequency (kHz)
C008
Figure 31. RT vs Frequency Curve
Table 1. Typical Frequency Setting RT Resistance
FS (kHz)
RT (kΩ)
200
200
350
115
500
78.7
53.6
39.2
26.1
19.6
17.8
750
1000
1500
2000
2200
The LM43602-Q1 switching action can also be synchronized to an external clock from 200 kHz to 2.2 MHz.
Connect an external clock to the SYNC pin, with proper high-speed termination, to avoid ringing. Ground the
SYNC pin if not used.
SYNC
EXT CLOCK
RTERM
Figure 32. Frequency Synchronization
The recommendations for the external clock include: high level no lower than 2 V, low level no higher than 0.4 V,
duty cycle between 10% and 90% and both positive and negative pulse width no shorter than 80 ns. When the
external clock fails at logic high or low, the LM43602-Q1 switches at the frequency programmed by the RT
resistor after a time-out period. It is recommended to connect a resistor RT to the RT pin such that the internal
oscillator frequency is the same as the target clock frequency when the LM43602-Q1 is synchronized to an
external clock. This allows the regulator to continue operating at approximately the same switching frequency if
the external clock fails.
The choice of switching frequency is usually a compromise between conversion efficiency and the size of the
circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch
transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows
use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient
response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching
frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.
It is related to the input voltage, output voltage, most frequent load current level(s), external component choices,
and circuit size requirement. The choice of switching frequency may also be limited if an operating condition
triggers TON-MIN or TOFF-MIN
.
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Feature Description (continued)
7.3.8 Minimum ON Time, Minimum OFF Time and Frequency Foldback at Dropout Conditions
Minimum ON time, TON-MIN, is the smallest duration of time that the HS switch can be on. TON-MIN value is typically
125 ns in the LM43602-Q1. Minimum OFF time, TOFF-MIN, is the smallest duration that the HS switch can be off.
TOFF-MIN is typically 200 ns in the LM43602-Q1.
In CCM operation, TON-MIN and TOFF-MIN limits the voltage conversion range given a selected switching frequency.
The minimum duty cycle allowed is
DMIN = TON-MIN × FS
(4)
And the maximum duty cycle allowed is
DMAX = 1 - TOFF-MIN × FS
(5)
Given fixed TON-MIN and TOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle. In the LM43602-Q1, frequency foldback scheme is employed to extend the maximum duty cycle when
TOFF-MIN is reached. The switching frequency decreases once longer duty cycle is needed under low VIN
conditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency by RT
or the synchronization clock. Such wide range of frequency foldback allows the LM43602-Q1 output voltage
stays in regulation with much lower supply voltage VIN. This leads to a lower effective dropout voltage. Refer to
Typical Characteristics for more details.
Given a output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size, and efficiency. The maximum operatable supply voltage can be found by Equation 6:
VIN-MAX = VOUT / (FS × TON-MIN
)
(6)
At lower supply voltage, the switching frequency decreases once TOFF-MIN is tripped. The minimum VIN without
frequency foldback can be approximated by Equation 7:
VIN-MIN = VOUT / (1 - FS × TOFF-MIN
)
(7)
Taking considerations of power losses in the system with heavy load operation, VIN-MIN is higher than the result
calculated in Equation 7 . With frequency foldback, VIN-MIN is lowered by decreased FS.
1000000
100000
0.1A
0.5A
1A
1.5A
2A
10000
5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00
VIN (V)
C007
Figure 33. VOUT = 5 V Fs = 500 kHz
Frequency Foldback at Dropout
7.3.9 Internal Compensation and CFF
The LM43602-Q1 is internally compensated with RC = 400 kΩ and CC = 50 pF as shown in Functional Block
Diagram. The internal compensation is designed such that the loop response is stable over the entire operating
frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can
be low with all ceramic capacitors. TI recommends an external feed-forward capacitor, CFF, be placed in parallel
with the top resistor divider RFBT for optimum transient performance.
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Feature Description (continued)
VOUT
CFF
RFBT
FB
RFBB
Figure 34. Feed-Forward Capacitor for Loop Compensation
The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of
the control loop to boost phase margin. The zero frequency can be found by Equation 8:
fZ-CFF = 1 / ( 2π × RFBT × CFF ).
(8)
An additional pole is also introduced with CFF at the frequency of:
fP-CFF = 1 / (2π × CFF × (RFBT // RFBB )).
(9)
Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The
zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps
maintaining proper gain margin at frequency beyond the crossover.
Designs with different combinations of output capacitors need different CFF. Different types of capacitors have
different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF.
Electrolytic capacitors have much larger ESR and the ESR zero frequency
fZ-ESR = 1 / (2π × ESR × COUT
)
(10)
would be low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic
capacitors at the output may not need any CFF.
The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If
the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple
too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, calculate CFF based on
output capacitors used in the system. At cold temperatures, the value of CFF might change based on the
tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To
avoid this, more capacitance can be added to the output or the value of CFF can be reduced. Refer to the
Detailed Design Procedure for the calculation of CFF.
7.3.10 Bootstrap Voltage (BOOT)
The driver of the HS switch requires a bias voltage higher than VIN when the HS switch is ON. The capacitor
connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (VSW
+
VCC). The boot diode is integrated on the LM43602-Q1 die to minimize bill of material (BOM). A synchronous
switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. A high-quality ceramic
0.47-µF, 6.3-V or higher capacitor is recommended for CBOOT
.
7.3.11 Power Good (PGOOD)
The LM43602-Q1 has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is
within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault
protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage.
Voltage detected by the PGOOD pin must never exceed 12 V. A resistor divider pair can be used to divide
voltage down from a higher potential. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.
When the FB voltage is within the power-good band, +4% above and –7% below the internal reference VREF
typically, the PGOOD switch will be turned off, and the PGOOD voltage will be pulled up to the voltage level
defined by the pullup resistor or divider. When the FB voltage is outside of the tolerance band, +10% above or
-13% below VREF typically, the PGOOD switch will be turned on, and the PGOOD pin voltage will be pulled low to
indicate power bad. Both rising and falling edges of the power-good flag have a built-in 220 µs (typical) deglitch
delay.
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Feature Description (continued)
7.3.12 Overcurrent and Short Circuit Protection
The LM43602-Q1 is protected from overcurrent conditions by cycle-by-cycle current limiting on both peak and
valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent overheating.
High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. Refer to
Functional Block Diagram for more details. The peak current of the HS switch is limited by the maximum EA
output voltage minus the slope compensation at every switching cycle. The slope compensation magnitude at the
peak current is proportional to the duty cycle.
When the LS switch is turned on, the current going through it is also sensed and monitored. The LS switch is not
turned OFF at the end of a switching cycle if its current is above the LS current limit ILS-LIMIT. The LS switch is
kept ON so that inductor current keeps ramping down, until the inductor current ramps below the LS current limit.
Then the LS switch is then turned OFF, and the HS switch turned on, after a dead time. If the current of the LS
switch is higher than the LS current limit for 32 consecutive cycles and the power-good flag is low, hiccup current
protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5.5 ms typically before
the LM43602-Q1 tries to start again. If overcurrent or short-circuit fault condition still exists, hiccup repeats until
the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,
prevents over heating and potential damage to the device.
Hiccup is only activated when power-good flag is low. Under non-severe overcurrent conditions when VOUT has
not fallen outside of the PGOOD tolerance band, the LM43602-Q1 reduces the switching frequency and keeps
the inductor current valley clamped at the LS current limit level. This operation mode allows slight overcurrent
operation during load transients without tripping hiccup. If power-good flag becomes low, hiccup operation starts
after LS current limit is tripped 32 consecutive cycles.
7.3.13 Thermal Shutdown
Thermal shutdown is a built-in self protection to limit junction temperature and prevent damages due to
overheating. Thermal shutdown turns off the device when the junction temperature exceeds 160°C typically to
prevent further power dissipation and temperature rise. Junction temperature reduces after thermal shutdown.
The LM43602-Q1 attempts to restart when the junction temperature drops to 150°C.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LM43602-Q1. When VEN is below 0.4 V, the device is
in shutdown mode. Both the internal LDO and the switching regulator are off. In shutdown mode the quiescent
current drops to 2.3 µA typically with VIN = 24 V. The LM43602-Q1 also employs undervoltage lockout protection.
If VCC voltage is below the UVLO level, the output of the regulator is turned off.
7.4.2 Standby Mode
The internal LDO has a lower enable threshold than the regulator. When VEN is above 1.2 V and below the
precision enable falling threshold (1.8 V typically), the internal LDO regulates the VCC voltage at 3.2 V. The
precision enable circuitry is turned on once VCC is above the UVLO threshold. The switching action and voltage
regulation are not enabled unless VEN rises above the precision enable threshold (2.1 V typically).
7.4.3 Active Mode
The LM43602-Q1 is in active mode when VEN is above the precision enable threshold and VCC is above its UVLO
level. The simplest way to enable the LM43602-Q1 is to connect the EN pin to VIN. This allows self start-up when
the input voltage is in the operation range: 3.5 V to 36 V. Refer to Enable (EN) and VCC, UVLO, and BIAS for
details on setting these operating levels.
20
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Device Functional Modes (continued)
In active mode, depending on the load current, the LM43602-Q1 is in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple;
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation;
3. Pulse frequency modulation (PFM) when switching frequency is decreased at very light load;
4. Foldback mode when switching frequency is decreased to maintain output regulation at lower supply voltage
VIN.
7.4.4 CCM Mode
CCM operation is employed in the LM43602-Q1 when the load current is higher than half of the peak-to-peak
inductor current. In CCM operation, the frequency of operation is fixed unless the the minimum HS switch ON-
time (TON_MIN) or OFF-time (TOFF_MIN) is exceeded. Output voltage ripple is at a minimum in this mode and the
maximum output current of 2 A can be supplied by the LM43602-Q1.
7.4.5 Light Load Operation
When the load current is lower than half of the peak-to-peak inductor current in CCM, the LM43602-Q1 operates
in DCM, also known as diode emulation mode (DEM). In DCM operation, the LS FET is turned off when the
inductor current drops to 0 A to improve efficiency. Both switching losses and conduction losses are reduced in
DCM, comparing to forced PWM operation at light load.
At even lighter current loads, PFM is activated to maintain high efficiency operation. When the HS switch ON
time reduces to TON_MIN or peak inductor current reduces to its minimum IPEAK-MIN, the switching frequency
reduces to maintain proper regulation. Efficiency is greatly improved by reducing switching and gate drive losses.
1000000
100000
10000
8V
12V
24V
36V
1000
0.001
0.01
0.1
Current (A)
1
C007
Figure 35. VOUT = 5 V Fs = 500 kHz
Pulse Frequency Mode Operation
7.4.6 Self-Bias Mode
For highest efficiency of operation, TI recommends that the BIAS pin be connected directly to VOUT when VOUT
≥
3.3 V. In this self-bias mode of operation, the difference between the input and output voltages of the internal
LDO are reduced and, therefore, the total efficiency is improved. These efficiency gains are more evident during
light load operation. During this mode of operation, the LM43602-Q1 operates with a minimum quiescent current
of 27 µA (typical). Refer to VCC, UVLO, and BIAS for more details.
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8 Applications and Implementation
8.1 Application Information
The LM43602-Q1 is a step-down DC-DC regulator. It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 2 A. The following design procedure can be used to select
components for the LM43602-Q1. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses
comprehensive databases of components. See ti.com for more details.
8.2 Typical Applications
The LM43602-Q1 only requires a few external components to convert from a wide voltage range of supply to a
fixed output voltage. Figure 36 shows a basic schematic when BIAS is connected to VOUT, and this is
recommended for VOUT ≥ 3.3 V. For VOUT < 3.3 V, connect BIAS to ground as shown in Figure 37.
L
VOUT
VIN
VIN
SW
COUT
CIN
LM43602Q
CBOOT
CBOOT
BIAS
ENABLE
PGOOD
CBIAS
CFF
RFBT
SS/TRK
RT
FB
VCC
SYNC
AGND
RFBB
CVCC
PGND
Figure 36. LM43602-Q1 Basic Schematic for VOUT ≥ 3.3 V, tie BIAS to VOUT
L
VOUT
VIN
VIN
SW
COUT
CIN
LM43602Q
CBOOT
CBOOT
BIAS
ENABLE
PGOOD
CFF
RFBT
SS/TRK
RT
FB
VCC
SYNC
AGND
RFBB
CVCC
PGND
Figure 37. LM43602-Q1 Basic Schematic for VOUT < 3.3 V, tie BIAS to Ground
The LM43602-Q1 also integrates a full list of optional features to aid system design requirements such as:
precision enable, VCC UVLO, programmable soft-start, output voltage tracking, programmable switching
frequency, clock synchronization, and power-good indication. Each application can select the features for a more
comprehensive design. A schematic with all features utilized is shown in Figure 38.
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Typical Applications (continued)
L
VOUT
RFBT CFF
RFBB
VIN
SW
VIN
COUT
LM43602Q
RENT
CIN
CBOOT
CBOOT
FB
ENABLE
RENB
VCC
CVCC
SS/TRK
RT
CSS
BIAS
RT
CBIAS
PGOOD
PGND
SYNC
AGND
RPG
RSYNC
Tie BIAS to PGND
when VOUT < 3.3 V
Figure 38. LM43602-Q1 Schematic With All Features
The external components have to fulfill the needs of the application, but also the stability criteria of the device
control loop. The LM43602-Q1 is optimized to work within a range of external components. The inductance and
capacitance of the LC output filter must be considered in conjunction, creating a double pole, responsible for the
corner frequency of the converter (see Output Filter And Loop Stability section). Table 2 can be used to simplify
the output filter component selection.
Table 2. L, COUT and CFF Typical Values
(2)
(3)(4)
(3)(4)
FS (kHz)
200
VOUT (V)
L (µH)(1)
8.2
3.3
1.5
0.68
18
COUT (µF)
560
470
220
150
250
150
100
47
CFF (pF)
none
none
none
none
560
RT (kΩ)
200
RFBB (kΩ)
100
1
1
500
80.6 or open
39.2
100
1000
2200
200
1
100
1
17.8
100
3.3
3.3
3.3
3.3
5
200
43.2
43.2
43.2
43.2
24.9
24.9
24.9
24.9
9.09
9.09
9.09
4.32
4.32
4.32
500
6.8
4.7
1.8
22
330
80.6 or open
39.2
1000
2200
200
330
220
17.8
200
100
47
680
200
500
5
10
470
80.6 or open
39.2
1000
2200
200
5
4.7
2.2
68
470
5
33
330
17.8
12
12
12
24
24
24
68
See(5)
200
500
27
47
680
80.6 or open
39.2
1000
200
15
33
470
68
68
See(5)
See(5)
See(5)
200
500
27
47
80.6 or open
39.2
1000
15
33
(1) Inductance value is calculated based on typical VIN value of 12 V.
(2) All the COUT values are after derating. Add more when using ceramics.
(3) RFBT = 0 Ω for VOUT = 1 V. RFBT = 100 kΩ for all other VOUT setting.
(4) For designs with RFBT other than 100 kΩ, adjust CFF so that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is
unchanged.
(5) High ESR COUT gives enough phase boost and CFF not needed.
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Typical Applications (continued)
8.2.1 Design Requirements
Detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 3 as the input parameters.
Table 3. Design Example Parameters
DESIGN PARAMETER
Input voltage VIN
VALUE
12 V typical, range from 3.5 V to 36 V
Output voltage VOUT
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
Soft-start time
3.3 V
400 mV
30 mV
2 A
500 kHz
10 ms
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM43602-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Set-Point
The output voltage of the LM43602-Q1 device is externally adjustable using a resistor divider network. The
divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 11 is
used to determine the output voltage of the converter:
VFB
RFBB
=
RFBT
VOUT - VFB
(11)
Choose the value of the RFBT to be 100 kΩ to minimize quiescent current to improve light load efficiency in this
application. With the desired output voltage set to be 3.3 V and the VFB = 1.015 V, the RFBB value can be
calculated using Equation 11. The formula yields a value of 43.478 kΩ. Choose the closest available value of
43.2 kΩ for the RFBB. Refer to Adjustable Output Voltage for more details.
8.2.2.3 Switching Frequency
The default switching frequency of the LM43602-Q1 device is set at 500 kHz when RT pin is open circuit. The
switching frequency is selected as 500 kHz in this application for one less passive components. If other
frequency is desired, use Equation 12 to calculate the required value for RT.
RT(kΩ) = 40200 / Freq (kHz) – 0.6
(12)
For 500 kHz, the calculated RT is 79.8 kΩ, and standard value of 80.6 kΩ can also be used to set the switching
frequency at 500 kHz.
24
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8.2.2.4 Input Capacitors
The LM43602-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. The typical recommended value for the high frequency decoupling capacitor is
between 4.7 µF to 10 µF. TI recommends a high-quality ceramic type X5R or X7R with sufficiency voltage rating.
The voltage rating must be greater than the maximum input voltage. To compensate the derating of ceramic
capactors, TI recommends a voltage rating of twice the maximum input voltage. Additionally, some bulk
capacitance can be required, especially if the LM43602-Q1 circuit is not located within approximately 5 cm from
the input voltage source. This capacitor is used to provide damping to the voltage spiking due to the lead
inductance of the cable or trace. The value for this capacitor is not critical but must be rated to handle the
maximum input voltage including ripple. For this design, a 10-µF, X7R dielectric capacitor rated for 100 V is used
for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 3 mΩ, and the
current rating is 3 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close
as possible to the device pins.
NOTE
DC bias effect: High capacitance ceramic capacitors have a DC bias effect, which has a
strong influence on the final effective capacitance. Therefore, the right capacitor value
must be chosen carefully. Package size and voltage rating in combination with dielectric
material are responsible for differences between the rated capacitor value and the
effective capacitance.
8.2.2.5 Inductor Selection
The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is
based on the desired peak-to-peak ripple current, ΔiL, that flows in the inductor along with the DC load current.
As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance
gives lower ripple current and hence lower output voltage ripple with the same output capacitors. Lower
inductance could result in smaller, less expensive component. An inductance that gives a ripple current of 20% to
40% of the 2 A at the typical supply voltage is a good starting point. ΔIL = (1/5 to 2/5) × IOUT. The peak-to-peak
inductor current ripple can be found by Equation 13 and the range of inductance can be found by Equation 14
with the typical input voltage used as VIN.
(VIN - VOUT )ìD
DiL =
L ìFS
(13)
(VIN - VOUT )ìD
0.4ìFS ìIL-MAX
(VIN - VOUT )ìD
0.2ìFS ìIL-MAX
Ç L Ç
(14)
D is the duty cycle of the converter which in a buck converter can be approximated as D = VOUT/VIN, assuming
no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance value comes
out in micro henries. The inductor ripple current ratio is defined by:
DiL
IOUT
r =
(15)
The second criterion is the inductor saturation current rating. The inductor must be rated to handle the maximum
load current plus the ripple current:
IL-PEAK = ILOAD-MAX + ΔiL/ 2
(16)
The LM43602-Q1 has both valley current limit and peak current limit. During an instantaneous short, the peak
inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should be
higher than the HS current limit. It is advised to select an inductor with a larger core saturation margin and
preferably a softer roll off of the inductance value over load current.
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In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely triggered. It also generates more conduction loss, because the RMS current is slightly
higher relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies
larger output voltage ripple with the same output capacitors. With peak current mode control, it is not
recommended to have too small of an inductor current ripple. A larger peak current ripple improves the
comparator signal to noise ratio.
Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core
losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and
preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when
the peak design current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current
and consequent output voltage ripple. Do not allow the core to saturate!
For the design example, a standard 6.8-μH inductor from Würth, Coiltronics, or Vishay can be used for the 3.3 V
output with plenty of current rating margin.
8.2.2.6 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. Use as little output capacitance as possible to
keep cost and size down. Choose the output capacitor (s), COUT, with care because it directly affects the steady
state output voltage ripple, loop stability and the voltage over/undershoot during load current transients.
The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the ESR of the output capacitors:
ΔVOUT-ESR =ΔiL × ESR
(17)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
ΔVOUT-C =ΔiL/ (8 × FS × COUT
)
(18)
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,
output capacitors provide the required charge before the inductor current can slew to the appropriate level. The
initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until
the control loop response increases or decreases the inductor current to supply the load. To maintain a small
overshoot or undershoot during a transient, small ESR and large capacitance are desired. But these also come
with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output
voltage deviation.
For a given input and output requirement, the following inequality gives an approximation for an absolute
minimum output capacitor required:
2
»
…
…
ÿ
Ÿ
≈
’
1
r
Å
Å
COUT
>
ì
ì(1+ D ) + D ì(1+ r)
∆
∆
÷
(
)
÷
(FS ìr ì DVOUT / IOUT
)
12
Ÿ
⁄
«
◊
(19)
Along with this for the same requirement, calculate the maximum ESR as per the following inequality:
Å
D
1
ESR <
ì( + 0.5)
FS ìCOUT
r
where
•
•
•
•
•
r = Ripple ratio of the inductor ripple current (ΔIL / IOUT
ΔVOUT = target output voltage undershoot
D’ = 1 – duty cycle
)
FS = switching frequency
IOUT = load current
(20)
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A general guideline for COUT range is that COUT must be larger than the minimum required output capacitance
calculated by Equation 19, and smaller than 10 times the minimum required output capacitance or 1 mF. In
applications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This limits
potential output voltage overshoots as the input voltage falls below the device normal operating range. To
optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback
resistor. For this design example, three 47-µF,10-V, X7R ceramic capacitors are used in parallel.
8.2.2.7 Feed-Forward Capacitor
The LM43602-Q1 is internally compensated and the internal R-C values are 400 kΩ and 50 pF, respectively.
Depending on the VOUT and frequency FS, if the output capacitor COUT is dominated by low ESR (ceramic types)
capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor
CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at the crossover
frequency without CFF. A simple estimation for the crossover frequency without CFF (fx) is shown in Equation 21,
assuming COUT has very small ESR.
4.35
fx =
VOUT ìCOUT
(21)
Equation 22 was tested for CFF:
1
1
CFF
=
ì
2pfx
RFBT ì(RFBT / /RFBB
)
(22)
Equation 22 indicates that the crossover frequency is geometrically centered on the zero and pole frequencies
caused by the CFF capacitor.
For designs with higher ESR, CFF is not needed when COUT has very high ESR; CFF calculated from Equation 22
must be reduced with medium ESR. Table 2 can be used as a quick starting point.
For the application in this design example, a 330-pF COG capacitor is selected.
8.2.2.8 Bootstrap Capacitors
Every LM43602-Q1 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor value is
0.47 μF and rated at 6.3 V or higher. The bootstrap capacitor is located between the SW pin and the CBOOT
pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for
temperature stability.
8.2.2.9 VCC Capacitor
The VCC pin is the output of an internal LDO for LM43602-Q1. The input for this LDO comes from either VIN or
BIAS (see Functional Block Diagram for LM43602-Q1). To insure stability of the part, place a minimum of 2.2-µF,
10-V capacitor from the VCC pin to ground.
8.2.2.10 BIAS Capacitors
For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light
load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO is
internally connected into VIN. Because this is an LDO, the voltage differences between the input and output
affects the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to the BIAS
pin as an input capacitor for the LDO.
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8.2.2.11 Soft-Start Capacitors
The user can left the SS/TRK pin floating, and the LM43602-Q1 will implement a soft-start time of 4.1 ms
typically. In order to use an external soft start capacitor, the capacitor must be sized so that the soft-start time is
longer than 4.1 ms. Use Equation 23 in order to calculate the soft start capacitor value:
CSS = ISSC ì tSS
where
•
•
•
CSS = Soft start capacitor value (µF)
ISS = Soft start charging current (µA)
tSS = Desired soft start time (s)
(23)
For the desired soft start time of 10 ms and soft start charging current of 2 µA, Equation 23 above yield a soft
start capacitor value of 0.02 µF.
8.2.2.12 Undervoltage Lockout Setpoint
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. RENT
is connected between VIN and the EN pin of the LM43602-Q1 device. RENB is connected between the EN pin
and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. Equation 24 can be used to determine the VIN
(UVLO) level.
VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB
(24)
The EN rising threshold (VENH) for LM43602 is set to be 2.2 V (typical). Choose the value of RENB to be 1 MΩ to
minimize input current from the supply. If the desired VIN UVLO level is at 5 V, the value of RENT can be
calculated using Equation 25:
RENT = (VIN-UVLO-RISING / VENH -1) × RENB
(25)
Equation 25 yields a value of 1.27 MΩ. The resulting falling UVLO threshold, equals 4.3 V, can be calculated by
Equation 26, where EN falling threshold (VENL) is 1.9 V (typical).
VIN-UVLO-FALLING = VENL × (RENB + RENT) / RENB
(26)
8.2.2.13 PGOOD
A typical pullup resistor value is 10 kΩ to 100 kΩ from PGOOD pin to a voltage no higher than 12 V. If it is
desired to pull up PGOOD pin to a voltage higher than 12 V, a resistor can be added from PGOOD pin to ground
to divide the voltage seen by the PGOOD pin to a value no higher than 12 V.
28
Copyright © 2015–2017, Texas Instruments Incorporated
LM43602-Q1
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ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
8.2.3 Application Performance Curves
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz and room temperature. See Application Performance
Curves for bill of materials for each VOUT and FS combination.
6.8 µH
100
3.3 VOUT
VIN
VIN
SW
4.7
µF
LM43602Q
90
80
70
60
50
40
0.47 µF
2.2 µF
120 µF
330 pF
CBOOT
FB
100 kΩ
ENABLE
SS/TRK
RT
VCC
43.2 kΩ
BIAS
SYNC
AGND
PGOOD
5VIN
PGND
12VIN
24VIN
0
0.5
1
1.5
2
Current (A)
FS = 500 kHz
C001
VOUT = 3.3 V
VOUT = 3.3 V
FS = 500 kHz
Figure 40. Efficiency at Room Temperature
Figure 39. BOM for VOUT = 3.3 V FS = 500 kHz
100
100
90
80
70
60
50
40
90
80
70
60
50
40
5VIN
5VIN
12VIN
24VIN
12VIN
24VIN
0.001
0.01
0.1
Current (A)
1
0.001
0.01
0.1
Current (A)
1
C001
C001
VOUT = 3.3 V
FS = 500 kHz
VOUT = 3.3 V
FS = 500 kHz
Figure 41. Efficiency at Room Temperature
Figure 42. Efficiency at 85°C
3
2.5
2
3
5VIN
5VIN
12VIN
24VIN
12VIN
24VIN
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.5
1
1.5
2
0
0.5
1
1.5
2
Current (A)
FS = 500 kHz
Current (A)
FS = 500 kHz
C001
C001
VOUT = 3.3 V
VOUT = 3.3 V
VIN = 24 V
Figure 43. Power Loss at Room Temperature
Figure 44. Power Loss at 85°C
Copyright © 2015–2017, Texas Instruments Incorporated
29
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ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
www.ti.com.cn
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz and room temperature. See Application Performance
Curves for bill of materials for each VOUT and FS combination.
3.5
3.4
3.3
3.2
3.1
3.0
2.9
1000000
100000
10000
1000
0.1A
0.5A
1A
0.1A
0.5A
1A
1.5A
2A
1.5A
2A
3.5
3.7
3.9
4.1
4.3
4.5
3.5
3.7
3.9
4.1
4.3
4.5
VIN (V)
VIN (V)
C007
C007
VOUT = 3.3 V
FS = 500 kHz
VOUT = 3.3 V
FS = 500 kHz
Figure 45. Dropout Voltage
Figure 46. Frequency vs VIN
1000000
100000
10000
1000
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
5VIN
12VIN
24VIN
5VIN
8VIN
12VIN
24VIN
0.001
0.01
0.1
1
0.001
0.01
0.1
Current (A)
1
Current (A)
C007
C001
VOUT = 3.3 V
FS = 500 kHz
VOUT = 3.3 V
FS = 500 kHz
Figure 47. Frequency vs Load
Figure 48. Regulation Curve
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VOUT (100 mV/DIV)
IOUT (0.5 A/DIV)
12VIN
18VIN
24VIN
Time (100µs/DIV)
65
75
85
95
105
115
125
Ambient Temperature (deg C)
C007
VOUT = 3.3 V
FS = 500 kHz
VIN = 12 V
VOUT = 3.3 V
Figure 50. Derating Curve
FS = 500 kHz
Figure 49. Load Transient
30
Copyright © 2015–2017, Texas Instruments Incorporated
LM43602-Q1
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ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz and room temperature. See Application Performance
Curves for bill of materials for each VOUT and FS combination.
10 µH
100
5 VOUT
VIN
VIN
SW
4.7
µF
LM43602Q
90
80
70
60
50
40
0.47 µF
2.2 µF
440 pF
100 µF
CBOOT
FB
100 kΩ
ENABLE
SS/TRK
RT
VCC
24.9 kΩ
BIAS
SYNC
AGND
PGOOD
PGND
12VIN
24VIN
0
0.5
1
1.5
2
Current (A)
FS = 500 kHz
C001
VOUT = 5 V
FS = 500 kHz
VOUT = 5 V
Figure 51. BOM for VOUT = 5 V FS = 500 kHz
Figure 52. Efficiency at Room Temperature
100
100
90
80
70
60
50
40
90
80
70
60
50
40
12VIN
12VIN
24VIN
1
24VIN
1
0.001
0.01
0.1
Current (A)
0.001
0.01
0.1
Current (A)
C001
C001
VOUT = 5 V
FS = 500 kHz
VOUT = 5 V
FS = 500 kHz
Figure 53. Efficiency at Room Temperature
Figure 54. Efficiency at 85°C Ambient Temperature
3
2.5
2
3
12VIN
24VIN
12VIN
2.5
24VIN
2
1.5
1
1.5
1
0.5
0
0.5
0
0
0.5
1
1.5
2
0
0.5
1
1.5
2
Current (A)
FS = 500 kHz
Current (A)
FS = 500 kHz
C001
C001
VOUT = 5 V
VOUT = 5 V
Figure 55. Power Dissipation at Room Temperature
Figure 56. Power Dissipation at 85C Ambient Temperature
Copyright © 2015–2017, Texas Instruments Incorporated
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Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz and room temperature. See Application Performance
Curves for bill of materials for each VOUT and FS combination.
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
1000000
100000
10000
0.1A
0.5A
1A
0.1A
0.5A
1A
1.5A
2A
1.5A
2A
5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00
5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00
VIN (V)
VIN (V)
C007
C007
VOUT = 5 V
FS = 500 kHz
VOUT = 5 V
FS = 500 kHz
Figure 57. Dropout Voltage
Figure 58. Frequency vs VIN
1000000
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
8VIN
12VIN
24VIN
100000
10000
1000
8V
12V
24V
36V
0.001
0.01
0.1
Current (A)
1
0.001
0.01
0.1
Current (A)
1
C007
C004
VOUT = 5 V
FS = 500 kHz
VOUT = 5 V
FS = 500 kHz
Figure 59. Frequency vs Load
Figure 60. Regulation Curve
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VOUT (100 mV/DIV)
IOUT (0.5 A/DIV)
12VIN
18VIN
24VIN
28VIN
Time (100µs/div)
65
75
85
95
105
115
125
Ambient Temperature (deg C)
C007
VOUT = 5 V
FS = 500 kHz
VOUT = 5 V
FS = 1 MHz
VIN = 12 V
Figure 62. Derating Curve
Figure 61. Load Transient 0.1 A to 1 A
32
Copyright © 2015–2017, Texas Instruments Incorporated
LM43602-Q1
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ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
9 Power Supply Recommendations
The LM43602-Q1 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This input
supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail should be low enough that an input current transient does not cause a high
enough drop at the LM43602-Q1 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LM43602-Q1 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-µF
or 100-µF electrolytic capacitor is a typical choice.
10 Layout
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. The following guidelines will help users design a PCB with the best power conversion performance,
thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
1. Place ceramic high frequency bypass CIN as close as possible to the LM43602-Q1 VIN and PGND pins.
Grounding for both the input and output capacitors should consist of localized top side planes that connect to
the PGND pins and PAD.
2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device
ground.
3. Minimize trace length to the FB pin net. Locate both feedback resistors, RFBT and RFBB close to the FB pin.
Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense is
made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other
side of a shieldig layer.
4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.
5. Have a single point ground connection to the plane. Route the ground connections for the feedback, soft-
start, and enable components to the ground plane. This prevents any switched or load currents from flowing
in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or
erratic output voltage ripple behavior.
6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking
to keep the junction temperature below 125°C.
10.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more EMI is generated. The key to minimize radiated EMI is to
identify pulsing current path and minimize the area of the path. In buck converters,the pulsing current path is
from the VIN side of the input capacitors to HS switch, to the LS switch, and then return to the ground of the input
capacitors, as shown in Figure 63.
.Ü/Y
/hbë9wÇ9w
L
ëLb
{í
VOUT
COUT
VIN
CIN
tDb5
tDb5
Iigh di/dt
current
Figure 63. Buck Converter High Δi/Δt Path
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Layout Guidelines (continued)
High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of
the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the
key to EMI reduction.
The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load
current without excessive heating. Use short, thick traces or copper pours (shapes) high current conduction path
to minimize parasitic resistance. Place the output capacitors close to the VOUT end of the inductor, closely
grounded to PGND pin and exposed PAD.
Place the bypass capacitors on VCC and BIAS pins as close as possible to the pins, respectively, and closely
ground to PGND and the exposed PAD.
10.1.2 Ground Plane and Thermal Considerations
TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the
AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins are
connected to the source of the internal LS switch. They must be connected directly to the grounds of the input
and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load
variations. PGND trace, as well as PVIN and SW traces, must be constrained to one side of the ground plane.
The other side of the ground plane contains much less noise and should be used for sensitive routes.
TI recommends providing adequate device heat sinking by utilizing the PAD of the device as the primary thermal
path. Use a recommended 4 by 3 array of 10-mil thermal vias to connect the PAD to the system ground plane
heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible for system
ground plane on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper
thickness for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough
copper thickness provides low current conduction impedance, proper shielding and lower thermal resistance.
The thermal characteristics of the LM43602-Q1 are specified using the parameter RθJA, which characterize the
junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is
dependant on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use Equation 27:
TJ = PD × RθJA + TA
where
•
•
•
•
•
TJ = junction temperature in °C
PD = VIN × IIN × (1 − efficiency) − 1.1 × IOUT × DCR
DCR = inductor DC parasitic resistance in Ω
RθJA = junction-to-ambient thermal resistance of the device in °C/W
TA = ambient temperature in °C
(27)
The maximum operating junction temperature of the LM43602-Q1 is 125°C. RθJA is highly related to PCB size
and layout, as well as enviromental factors such as heat sinking and air flow. Figure 64 shows measured results
of RθJA with different copper area on a 2-layer board and a 4-layer board.
34
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LM43602-Q1
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ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
Layout Guidelines (continued)
50.0
45.0
40.0
35.0
30.0
25.0
20.0
1W @ 0fpm - 2 layer
2W @ 0fpm - 2 layer
1W @ 0fpm - 4 layer
2W @ 0fpm - 4 layer
20mm x 20mm 30mm x 30mm 40mm x 40mm 50mm x 50mm
Copper Area
C007
Figure 64. RθJA vs Copper Area
2 oz Copper on Outer Layers and 1 oz Copper on Inner Layers
10.1.3 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and
CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the
trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace
from VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for
voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider should be routed away from the SW node path and the inductor to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. This provides further shielding for the
voltage feedback path from EMI noises.
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ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
www.ti.com.cn
10.2 Layout Example
VOUT distribution
point is away
from inductor
and past COUT
TO LOAD
VOUT
VOUT sense point
is away from
inductor and
past COUT
+
COUT
As much copper area as possible, for
better thermal performance
L
GND
1
PGND
PGND
VIN
SW
SW
16
Thermal Vias under DAP
15
2
3
4
5
6
7
8
Place ceramic
CBOOT
+
bypass caps close
to VIN and PGND
terminals
Place
CBOOT
14
bypass caps
close to
CIN
VIN
13
VIN
VCC
BIAS
terminals
PAD
(17)
CVCC
EN
12
11
10
9
SS/TRK
AGND
SYNC
RT
Route VOUT
Ground
bypass caps
to DAP
RFBB
CBIAS
sense trace
away from SW
and VIN
PGOOD
FB
nodes.
Preferably
shielded in an
alternative
layer
RFBT
CFF
GND Plane
As much copper area as possible, for better thermal performance
Figure 65. LM43602-Q1 Layout Example
36
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LM43602-Q1
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ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 开发支持
11.2.1 使用 WEBENCH® 工具创建定制设计
请单击此处，使用 LM43602-Q1 器件并借助 WEBENCH® 电源设计器创建定制设计。
1. 在开始阶段键入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.3 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
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ZHCSDR4C –APRIL 2015–REVISED OCTOBER 2017
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11.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据如有变更，恕
不另行通知和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
38
版权 © 2015–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM43602AQPWPRQ1
LM43602AQPWPTQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
16
16
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
43602AQ
NIPDAU
43602AQ
LM43602QPWPRQ1
LM43602QPWPTQ1
NRND
NRND
HTSSOP
HTSSOP
PWP
PWP
16
16
2000 RoHS & Green
250 RoHS & Green
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
43602Q1
43602Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Aug-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM43602AQPWPRQ1 HTSSOP PWP
LM43602QPWPRQ1 HTSSOP PWP
16
16
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Aug-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM43602AQPWPRQ1
LM43602QPWPRQ1
HTSSOP
HTSSOP
PWP
PWP
16
16
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016G
PowerPAD TM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
0.19
4.5
4.3
NOTE 4
16X
B
1.2 MAX
0.1
C A
B
0.18
0.12
TYP
SEE DETAIL A
2X 0.24 MAX
NOTE 6
2X 0.56 MAX
NOTE 6
THERMAL
PAD
0.25
GAGE PLANE
3.29
2.71
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
2.41
1.77
4218975/B 01/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
6. Features may not present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016G
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 10
(2.41)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED PAD
SEE DETAILS
16X (1.5)
SYMM
1
16
16X (0.45)
(0.95)
TYP
(5)
SYMM
(3.29)
SOLDER MASK
OPENING
14X (0.65)
9
8
(0.95) TYP
METAL COVERED
BY SOLDER MASK
(
0.2) TYP
VIA
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4218975/B 01/2016
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016G
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.41)
BASED ON
0.127 THICK
STENCIL
16X (1.5)
1
16
16X (0.45)
(3.29)
SYMM
BASED ON
0.127 THICK
STENCIL
14X (0.65)
(R0.05)
9
8
SYMM
(5.8)
SEE TABLE FOR
METAL COVERED
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.69 X 3.68
2.41 X 3.29 (SHOWN)
2.20 X 3.00
0.127
0.152
0.178
2.04 X 2.78
4218975/B 01/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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