LM4752 [TI]
11W 立体声、9V 至 32V 电源电压、模拟输入 AB 类音频放大器;
| 型号： | LM4752 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 11W 立体声、9V 至 32V 电源电压、模拟输入 AB 类音频放大器 放大器 音频放大器 |
| 文件： | 总28页 (文件大小：1191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM4752
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SNAS006E –FEBRUARY 1999–REVISED APRIL 2013
LM4752 Stereo 11W Audio Power Amplifier
Check for Samples: LM4752
1
FEATURES
DESCRIPTION
The LM4752 is a stereo audio amplifier capable of
delivering 11W per channel of continuous average
output power to a 4Ω load, or 7W per channel into 8Ω
using a single 24V supply at 10% THD+N.
2
•
•
•
•
•
•
•
•
•
Drives 4Ω and 8Ω Loads
Internal Gain Resistors (AV = 34 dB)
Minimum External Component Requirement
Single Supply Operation
The LM4752 is specifically designed for single supply
operation and a low external component count. The
gain and bias resistors are integrated on chip,
resulting in a 11W stereo amplifier in a compact 7 pin
TO-220 package. High output power levels at both
20V and 24V supplies and low external component
count offer high value for compact stereo and TV
Internal Current Limiting
Internal Thermal Protection
Compact 7-lead TO-220 Package
Low Cost-Per-Watt
Wide Supply Range 9V - 40V
applications.
A
simple mute function can be
implemented with the addition of a few external
components.
APPLICATIONS
•
•
•
•
Compact Stereos
Stereo TVs
Mini Component Stereos
Multimedia Speakers
KEY SPECIFICATIONS
•
Output Power at 10% THD+N with 1kHz into 4Ω
VCC = 24V 11 W (typ)
•
Output Power at 10% THD+N with 1kHz into 8Ω
VCC = 24V 7 W (typ)
•
•
Closed Loop Gain 34 dB (typ)
PO at 10% THD+N @ 1 kHz into 4Ω Single-
Ended DDPAK Package VCC = 12V 2.5 W (typ)
•
PO at 10% THD+N @ 1kHz into 8Ω Bridged
DDPAK Package VCC = 12V 5 W (typ)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM4752
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TYPICAL APPLICATION
Figure 1. Typical Audio Amplifier Application Circuit
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CONNECTION DIAGRAMS
Plastic Package (Top View)
See Package Number NDZ
7 Pin DDPAK Package (Top View)
See Package Number KTW
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
Supply Voltage
40V
±0.7V
Input Voltage
Input Voltage at Output Pins(4)
GND – 0.4V
Internally Limited
62.5W
Output Current
Power Dissipation(5)
ESD Susceptibility(6)
Junction Temperature
Soldering Information
Storage Temperature
2 kV
150°C
NDZ Package (10 sec)
250°C
−40°C to 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) All voltages are measured with respect to the GND pin (4), unless otherwise specified.
(4) The outputs of the LM4752 cannot be driven externally in any mode with a voltage lower than -0.4V below GND or permanent damage
to the LM4752 will result.
(5) For operating at case temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a
thermal resistance of θJC = 2°C/W (junction to case). Refer to the section DETERMINING MAXIMUM POWER DISSIPATION for more
information.
(6) Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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OPERATING RATINGS
Temperature Range TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +85°C
9V to 32V
Supply Voltage
θJC
θJA
2°C/W
79°C/W
ELECTRICAL CHARACTERISTICS
The following specifications apply to each channel with VCC = 24V, TA = 25°C unless otherwise specified.
LM4752
Units
(Limits)
Symbol
Itotal
Parameter
Conditions
Typical(1)
Limit(2)
Total Quiescent Power Supply Current VINAC = 0V, Vo = 0V, RL = ∞
10.5
20
7
mA(max)
mA(min)
W
Po
Output Power (Continuous
Average per Channel)
f = 1 kHz, THD+N = 10%, RL = 8Ω
f = 1 kHz, THD+N = 10%, RL = 4Ω
VCC = 20V, RL = 8Ω
7
10
W(min)
W
4
7
VCC = 20V, R L = 4Ω
W
f = 1 kHz, THD+N = 10%, RL = 4Ω
VS = 12V, DDPAK Pkg.
2.5
W
THD+N
VOSW
Total Harmonic Distortion plus Noise
Output Swing
f = 1 kHz, Po = 1 W/ch, RL = 8Ω
RL = 8Ω, V CC = 20V
RL = 4Ω, V CC = 20V
See Figure 1
0.08
15
%
V
14
V
Xtalk
Channel Separation
55
dB
f = 1 kHz, Vo = 4 Vrms, RL = 8Ω
See Figure 1
PSRR
Power Supply Rejection Ratio
50
dB
VCC = 22V to 26V, R L = 8Ω
VINAC = 0V
VODV
SR
Differential DC Output Offset Voltage
Slew Rate
0.09
2
0.4
V(max)
V/µs
RIN
Input Impedance
83
65
34
kΩ
PBW
A VCL
Power Bandwidth
3 dB BW at Po = 2.5W, RL = 8Ω
RL = 8Ω
kHz
Closed Loop Gain (Internally Set)
33
35
dB(min)
dB(max)
mVrms
ein
Noise
IHF-A Weighting Filter, RL = 8Ω
Output Referred
0.2
Io
Output Short Circuit Current Limit
VIN = 0.5V, R L = 2Ω
2
A(min)
(1) Typicals are measured at 25°C and represent the parametric norm.
(2) Limits ensure that all parts tested in production meet the stated values.
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TEST CIRCUIT
Figure 2. Test Circuit
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TYPICAL APPLICATION WITH MUTE
Figure 3. Application with Mute Function
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EQUIVALENT SCHEMATIC DIAGRAM
Figure 4.
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SYSTEM APPLICATION CIRCUIT
Figure 5. Circuit for External Components Description
EXTERNAL COMPONENTS DESCRIPTION
Components
Function Description
1, 2
3, 4
5, 6
7
Cs
Rsn
Csn
Cb
Provides power supply filtering and bypassing.
Works with Csn to stabilize the output stage from high frequency oscillations.
Works with Rsn to stabilize the output stage from high frequency oscillations.
Provides filtering for the internally generated half-supply bias generator.
8, 9
Ci
Input AC coupling capacitor which blocks DC voltage at the amplifier's input terminals. Also creates a high pass
filter with fc =1/(2 • π • Rin • Cin).
10, 11
12, 13
Co
Ri
Output AC coupling capacitor which blocks DC voltage at the amplifier's output terminal. Creunderates a high pass
filter with fc =1/(2 • π • Rout • Cout).
Voltage control - limits the voltage level to the amplifier's input terminals.
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TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Output Power
THD+N vs Output Power
Figure 6.
Figure 7.
THD+N vs Output Power
THD+N vs Output Power
Figure 8.
Figure 9.
THD+N vs Output Power
THD+N vs Output Power
Figure 10.
Figure 11.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power
THD+N vs Output Power
Figure 12.
Figure 13.
THD+N vs Output Power
THD+N vs Output Power
Figure 14.
Figure 15.
THD+N vs Output Power
THD+N vs Output Power
Figure 16.
Figure 17.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power
THD+N vs Output Power
Figure 18.
Figure 19.
THD+N vs Output Power
THD+N vs Output Power
Figure 20.
Figure 21.
THD+N vs Output Power
THD+N vs Output Power
Figure 22.
Figure 23.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power
THD+N vs Output Power
Figure 24.
Figure 25.
THD+N vs Output Power
THD+N vs Output Power
Figure 26.
Figure 27.
THD+N vs Output Power
THD+N vs Output Power
Figure 28.
Figure 29.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Power vs Supply Voltage
Output Power vs Supply Voltage
Figure 30.
Figure 31.
Frequency Response
THD+N vs Frequency
Figure 32.
Figure 33.
THD+N vs Frequency
Frequency Response
Figure 34.
Figure 35.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Channel Separation
PSRR vs Frequency
Figure 36.
Figure 37.
Supply Current vs Supply Voltage
Power Derating Curve
Figure 38.
Figure 39.
Power Dissipation vs Output Power
Power Dissipation vs Output Power
Figure 40.
Figure 41.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Power Dissipation vs Output Power
Power Dissipation vs Output Power
Figure 42.
Figure 43.
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APPLICATION INFORMATION
CAPACITOR SELECTION AND FREQUENCY RESPONSE
With the LM4752, as in all single supply amplifiers, AC coupling capacitors are used to isolate the DC voltage
present at the inputs (pins 2,6) and outputs (pins 1,7). As mentioned earlier in the EXTERNAL COMPONENTS
DESCRIPTION section these capacitors create high-pass filters with their corresponding input/output
impedances. The Typical Application Circuit shown in Figure 1 shows input and output capacitors of 0.1 μF and
1,000 μF respectively. At the input, with an 83 kΩ typical input resistance, the result is a high pass 3 dB point
occurring at 19 Hz. There is another high pass filter at 39.8 Hz created with the output load resistance of 4Ω.
Careful selection of these components is necessary to ensure that the desired frequency response is obtained.
The Frequency Response curves in the TYPICAL PERFORMANCE CHARACTERISTICS section show how
different output coupling capacitors affect the low frequency rolloff.
APPLICATION CIRCUIT WITH MUTE
With the addition of a few external components, a simple mute circuit can be implemented, such as the one
shown in Figure 3. This circuit works by externally pulling down the half supply bias line (pin 5), effectively
shutting down the input stage.
When using an external circuit to pull down the bias, care must be taken to ensure that this line is not pulled
down too quickly, or output “pops” or signal feedthrough may result. If the bias line is pulled down too quickly,
currents induced in the internal bias resistors will cause a momentary DC voltage to appear across the inputs of
each amplifier's internal differential pair, resulting in an output DC shift towards V SUPPLY. An R-C timing circuit
should be used to limit the pull-down time such that output “pops” and signal feedthroughs will be minimized. The
pull-down timing is a function of a number of factors, including the external mute circuitry, the voltage used to
activate the mute, the bias capacitor, the half-supply voltage, and internal resistances used in the half-supply
generator. Table 1 shows a list of recommended values for the external mute circuitry.
Table 1. Values for Mute Circuit
VMUTE
5V
R1
R2
C1
R3
CB
VCC
10 kΩ
20 kΩ
20 kΩ
10 kΩ
1.2 kΩ
910Ω
4.7 μF
4.7 μF
4.7 μF
360Ω
180Ω
180Ω
100 μF
100 μF
47 μF
21V–32V
15V–32V
22V–32V
VS
VS
OPERATING IN BRIDGE-MODE
Though designed for use as a single-ended amplifier, the LM4752 can be used to drive a load differentially
(bridge-mode). Due to the low pin count of the package, only the non-inverting inputs are available. An inverted
signal must be provided to one of the inputs. This can easily be done with the use of an inexpensive op-amp
configured as a standard inverting amplifier. An LF353 is a good low-cost choice. Care must be taken, however,
for a bridge-mode amplifier must theoretically dissipate four times the power of a single-ended type. The load
seen by each amplifier is effectively half that of the actual load being used, thus an amplifier designed to drive a
4Ω load in single-ended mode should drive an 8Ω load when operating in bridge-mode.
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Figure 44. Bridge-Mode Application
Figure 45. THD+N vs. POUT for Bridge-Mode Application
PREVENTING OSCILLATIONS
With the integration of the feedback and bias resistors on-chip, the LM4752 fits into a very compact package.
However, due to the close proximity of the non-inverting input pins to the corresponding output pins, the inputs
should be AC terminated at all times. If the inputs are left floating, the amplifier will have a positive feedback path
through high impedance coupling, resulting in a high frequency oscillation. In most applications, this termination
is typically provided by the previous stage's source impedance. If the application will require an external signal,
the inputs should be terminated to ground with a resistance of 50 kΩ or less on the AC side of the input coupling
capacitors.
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UNDERVOLTAGE SHUTDOWN
If the power supply voltage drops below the minimum operating supply voltage, the internal under-voltage
detection circuitry pulls down the half-supply bias line, shutting down the preamp section of the LM4752. Due to
the wide operating supply range of the LM4752, the threshold is set to just under 9V. There may be certain
applications where a higher threshold voltage is desired. One example is a design requiring a high operating
supply voltage, with large supply and bias capacitors, and there is little or no other circuitry connected to the
main power supply rail. In this circuit, when the power is disconnected, the supply and bias capacitors will
discharge at a slower rate, possibly resulting in audible output distortion as the decaying voltage begins to clip
the output signal. An external circuit may be used to sense for the desired threshold, and pull the bias line (pin5)
to ground to disable the input preamp. Figure 46 shows an example of such a circuit. When the voltage across
the zener diode drops below its threshold, current flow into the base of Q1 is interrupted. Q2 then turns on,
discharging the bias capacitor. This discharge rate is governed by several factors, including the bias capacitor
value, the bias voltage, and the resistor at the emitter of Q2. An equation for approximating the value of the
emitter discharge resistor, R, is given below:
R = (0.7V) / (CB • (V S / 2) / 0.1s)
(1)
Note that this is only a linearized approximation based on a discharge time of 0.1s. The circuit should be
evaluated and adjusted for each application.
As mentioned earlier in the Application Circuit with Mute section, when using an external circuit to pull down the
bias line, the rate of discharge will have an effect on the turn-off induced distortions. Please refer to the
Application Circuit with Mute section for more information.
Figure 46. External Undervoltage Pull-Down
THERMAL CONSIDERATIONS
HEAT SINKING
Proper heatsinking is necessary to ensure that the amplifier will function correctly under all operating conditions.
A heatsink that is too small will cause the die to heat excessively and will result in a degraded output signal as
the internal thermal protection circuitry begins to operate.
The choice of a heatsink for a given application is dictated by several factors: the maximum power the IC needs
to dissipate, the worst-case ambient temperature of the circuit, the junction-to-case thermal resistance, and the
maximum junction temperature of the IC. The heat flow approximation equation used in determining the correct
heatsink maximum thermal resistance is given below:
TJ–TA = P DMAX • (θJC + θCS + θ SA
)
where
•
•
•
•
•
•
PDMAX = maximum power dissipation of the IC
TJ(°C) = junction temperature of the IC
TA(°C) = ambient temperature
θJC(°C/W) = junction-to-case thermal resistance of the IC
θCS(°C/W) = case-to-heatsink thermal resistance (typically 0.2 to 0.5 °C/W)
θSA(°C/W) = thermal resistance of heatsink
(2)
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When determining the proper heatsink, the above equation should be re-written as:
θSA ≤ [ (TJ − TA) / PDMAX] − θ JC − θCS
(3)
DDPAK HEATSINKING
Surface mount applications will be limited by the thermal dissipation properties of printed circuit board area. The
DDPAK package is not recommended for surface mount applications with VS > 16V due to limited printed circuit
board area. There are DDPAK package enhancements, such as clip-on heatsinks and heatsinks with adhesives,
that can be used to improve performance.
Standard FR-4 single-sided copper clad will have an approximate Thermal resistance (θSA) ranging from:
1.5 × 1.5 in. sq.
2 × 2 in. sq.
20–27°C/W
16–23°C/W
(TA=28°C, Sine wave
testing, 1 oz. Copper)
The above values for θSA vary widely due to dimensional proportions (i.e. variations in width and length will vary
θSA).
For audio applications, where peak power levels are short in duration, this part will perform satisfactory with less
heatsinking/copper clad area. As with any high power design proper bench testing should be undertaken to
assure the design can dissipate the required power. Proper bench testing requires attention to worst case
ambient temperature and air flow. At high power dissipation levels the part will show a tendency to increase
saturation voltages, thus limiting the undistorted power levels.
DETERMINING MAXIMUM POWER DISSIPATION
For a single-ended class AB power amplifier, the theoretical maximum power dissipation point is a function of the
supply voltage, V S, and the load resistance, RL and is given by the following equation:
(single channel)
PDMAX (W) = [VS 2 / (2 • π2 • RL) ]
(4)
The above equation is for a single channel class-AB power amplifier. For dual amplifiers such as the LM4752,
the equation for calculating the total maximum power dissipated is:
(dual channel)
PDMAX (W) = 2 • [V S2 / (2 • π2 • RL) ]
(5)
(6)
(7)
or
VS2 / (π 2 • RL)
(Bridged Outputs)
PDMAX (W) = 4[VS2 / (2π2 • RL)]
HEATSINK DESIGN EXAMPLE
Determine the system parameters:
V S = 24VOperating Supply Voltage
RL = 4ΩMinimum load impedance
TA = 55°CWorst case ambient temperature
Device parameters from the datasheet:
T J = 150°CMaximum junction temperature
θJC = 2°C/WJunction-to-case thermal resistance
Calculations:
2 • PDMAX = 2 • [V S2 / (2 • π2 • RL) ] = (24V)2 / (2 • π2 • 4Ω) = 14.6W
θSA ≤ [ (TJ − TA) / PDMAX] − θ JC − θCS = [ (150°C − 55°C) / 14.6W ] − 2°C/W − 0.2°C/W = 4.3°C/W
(8)
(9)
Conclusion: Choose a heatsink with θSA ≤ 4.3°C/W.
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DDPAK HEATSINK DESIGN EXAMPLES
Example 1:(Stereo Single-Ended Output)
Given: TA=30°C
TJ=150°C
RL=4Ω
VS=12V
θJC=2°C/W
PDMAX from PD vs PO Graph:
P
DMAX ≈ 3.7W
(10)
(11)
Calculating PDMAX
:
PDMAX = VCC2 / (π2RL) = (12V)2 / π2(4Ω)) = 3.65W
Calculating Heatsink Thermal Resistance:
θSA < [(T J − TA) / PDMAX] − θJC − θCS
(12)
(13)
θSA < 120°C / 3.7W − 2.0°C/W − 0.2°C/W = 30.2°C/W
Therefore the recommendation is to use 1.5 × 1.5 square inch of single-sided copper clad.
Example 2:(Stereo Single-Ended Output)
Given: TA=50°C
TJ=150°C
RL=4Ω
VS=12V
θJC=2°C/W
PDMAX from PD vs PO Graph:
P
DMAX ≈ 3.7W
(14)
(15)
Calculating PDMAX
:
PDMAX = VCC2 / (π2RL) = (12V)2 / (π2(4Ω)) = 3.65W
Calculating Heatsink Thermal Resistance:
θSA < [(TJ − TA) / PDMAX] − θJC − θCS
(16)
(17)
θSA < 100°C / 3.7W − 2.0°C/W − 0.2°C/W = 24.8°C/W
Therefore the recommendation is to use 2.0 × 2.0 square inch of single-sided copper clad.
Example 3:(Bridged Output)
Given: TA=50°C
TJ=150°C
RL=8Ω
VS=12V
θJC=2°C/W
Calculating PDMAX
:
PDMAX = 4[VCC2 / (2π2RL)] = 4(12V)2 / (2π2(8Ω)) = 3.65W
(18)
Calculating Heatsink Thermal Resistance:
θSA < [(TJ − TA) / PDMAX] − θJC − θCS
(19)
(20)
θSA < 100°C / 3.7W − 2.0°C/W − 0.2°C/W = 24.8°C/W
Therefore the recommendation is to use 2.0 × 2.0 square inch of single-sided copper clad.
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LAYOUT AND GROUND RETURNS
Proper PC board layout is essential for good circuit performance. When laying out a PC board for an audio
power amplifer, particular attention must be paid to the routing of the output signal ground returns relative to the
input signal and bias capacitor grounds. To prevent any ground loops, the ground returns for the output signals
should be routed separately and brought together at the supply ground. The input signal grounds and the bias
capacitor ground line should also be routed separately. The 0.1 μF high frequency supply bypass capacitor
should be placed as close as possible to the IC.
PC BOARD LAYOUT—COMPOSITE
Figure 47.
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PC BOARD LAYOUT—SILK SCREEN
Figure 48.
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PC BOARD LAYOUT—SOLDER SIDE
Figure 49.
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 23
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM4752TS/NOPB
ACTIVE
DDPAK/
TO-263
KTW
7
45
RoHS-Exempt
& Green
SN
Level-3-245C-168 HR
0 to 70
LM4752TS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
KTW TO-263
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM4752TS/NOPB
7
45
502
25
8204.2
9.19
Pack Materials-Page 1
MECHANICAL DATA
KTW0007B
TS7B (Rev E)
BOTTOM SIDE OF PACKAGE
www.ti.com
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