LM4856ITLX/NOPB [TI]
IC,AUDIO AMPLIFIER,SINGLE,BGA,18PIN,PLASTIC;
| 型号： | LM4856ITLX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,AUDIO AMPLIFIER,SINGLE,BGA,18PIN,PLASTIC 放大器 商用集成电路 |
| 文件： | 总23页 (文件大小：1317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2004
LM4856
Integrated Audio Amplifier System
General Description
Key Specifications
n THD+N at 1kHz, 1.1W into 8Ω BTL
n THD+N at 1kHz, 60mW into 32Ω SE
n Single Supply Operation
1.0% (typ)
0.5% (typ)
2.6 to 5.0V
The LM4856 is an audio power amplifier system capable of
delivering 1.1W (typ) of continuous average power into a
mono 8Ω bridged-tied load (BTL) with 1% THD+N and
60mW (typ) per channel of continuous average power into
stereo 32Ω single-ended (SE) loads with 0.5% THD+N, us-
ing a 5V power supply.
Features
n 1.1W (typ) output power with 8Ω mono BTL load
n 60mW (typ) output power with stereo 32Ω SE loads
n I2C programmable 32 step digital volume control
n Eight distinct output modes
The LM4856 features a 32 step digital volume control and
eight distinct output modes. The digital volume control and
output modes are programmed through a two-wire I2C com-
patible control interface, that allows flexibility in routing and
mixing audio channels.
n micro-SMD and LLP surface mount packaging
n "Click and Pop" suppression circuitry
n Thermal shutdown protection
The LM4856 is designed for cellular phone, PDA, and other
portable handheld applications. It delivers high quality output
power from a surface-mount package and requires only
eight external components.
n Low shutdown current (0.1uA, typ)
The industry leading micro SMD package only utilizes 2mm
x 2.3mm of PCB space, making the LM4856 the most space
efficient audio sub system available today.
Applications
n Moblie Phones
n PDAs
Typical Application
20060732
FIGURE 1. Typical Audio Amplifier Application Circuit
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS200607
www.national.com
Connection Diagrams
18-Bump micro SMD Marking (ITL)
200607E4
Top View
X - Date Code
T - Die Traceability
G - Boomer Family
B7 - LM4856ITL
200607A9
Top View
(Bump-side down)
Order Number LM4856ITL
See NS Package Number TLA18AAA
LLP Package
18 Lead LLP Marking
20060701
Top View
NS - Std NS Logo
U - Wafer Fab Code
Z - Assembly Plant Code
XY - 2 Digit Date Code
TT - Die Run Traceability
L4856LQ - LM4856LQ
200607D3
Top View
Order Number LM4856LQ
See NS Package Number LQA24A for Exposed-DAP LLP
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2
Absolute Maximum Ratings (Note 2)
Thermal Resistance
θJA (typ) - LQA24A
θJC (typ) - LQA24A
θJA (typ) - TLA18AAA
θJC (typ) - TLA18AAA
42˚C/W
3.0˚C/W
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
48˚C/W (Note 9)
23˚C/W (Note 9)
Supply Voltage
6.0V
−65˚C to +150˚C
2.0kV
Storage Temperature
ESD Susceptibility (Note 4)
ESD Machine model (Note 7)
Junction Temperature (TJ)
Solder Information (Note 1)
Vapor Phase (60 sec.)
Infrared (15 sec.)
Operating Ratings (Note 3)
Temperature Range
200V
−40˚C to 85˚C
150˚C
Supply Voltage VDD
2.6V ≤ VDD ≤ 5.0V
Note 1: See AN-450 "Surface Mounting and their effects on Product Reli-
ability" for other methods of soldering surface mount devices.
215˚C
220˚C
Electrical Characteristics (Notes 3, 8)
The following specifications apply for VDD= 5.0V, TA= 25˚C unless otherwise specified.
Symbol
Parameter
Conditions
LM4856
Units
(Limits)
Typical
(Note 5)
Limits
(Notes 6,
11)
Output modes 1, 2, 3, 4, 5, 6, 7
VIN = 0V; No loads
7.5
8.5
11
12
mA (max)
mA (max)
IDD
Supply Current
Output modes 1, 2, 3, 4, 5, 6, 7
VIN = 0V; Loaded (Figure 1)
Output mode 0
ISD
Shutdown Current
0.1
5.0
2.0
40
µA (max)
mV (max)
VOS
Output Offset Voltage
VIN = 0V
SPKROUT; RL = 4Ω
THD+N = 1%; f = 1kHz, LM4856LQ
1.5
1.1
W
SPKROUT; RL = 8Ω
PO
Output Power
0.8
45
W (min)
THD+N = 1%; f = 1kHz
ROUT and LOUT; RL = 32Ω
THD+N = 0.5%; f = 1kHz
SPKROUT
60
mW (min)
%
0.5
f = 20Hz to 20kHz
POUT = 400mW; RL = 8Ω
ROUT and LOUT
Total Harmonic Distortion Plus
Noise
THD+N
NOUT
0.5
%
f = 20Hz to 20kHz
POUT = 15mW; RL = 32Ω
A-weighted (Note 10)
VRIPPLE = 200mVPP; f = 217Hz,
CB = 1.0µF
Output Noise
29
58
µV
54
dB (min)
Power Supply Rejection Ratio
SPKROUT
All audio inputs terminated into 50Ω;
Output referred Gain (BTL) = 12dB
Output Mode 1, 3, 5, 7
VRIPPLE = 200mVPP; f = 217Hz
CB = 1.0µF
PSRR
All audio inputs terminated into 50Ω;
Output referred Maximum gain setting
Output Mode 2, 3
Power Supply Rejection Ratio
ROUTand LOUT
68
60
56
59
54
dB (min)
dB (min)
dB (min)
V (min)
Output Mode 4, 5
Output Mode 6, 7
51
VIH
Logic High Input Voltage
0.7 x VDD
VDD
V (max)
3
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Electrical Characteristics (Notes 3, 8) (Continued)
The following specifications apply for VDD= 5.0V, TA= 25˚C unless otherwise specified.
Symbol
Parameter
Conditions
LM4856
Units
(Limits)
Typical
(Note 5)
Limits
(Notes 6,
11)
VIL
Logic Low Input Voltage
Digital Volume Range
0.4
GND
-35.1
-33.9
11.4
12.6
-41.1
-39.9
5.4
V (max)
V (min)
Input referred minimum gain
Input referred maximum gain
Input referred minimum gain
Input referred maximum gain
-34.5
12.0
-40.5
6.0
dB (min)
dB (max)
dB (min)
dB (max)
dB (min)
dB (max)
dB (min)
dB (max)
dB
(RIN and LIN
)
Digital Volume Range
(Phone_In_HS)
6.6
Digital Volume Stepsize
Digital Volume Stepsize Error
Phone_In_IHF Volume
1.5
0.1
12
0.6
11.4
12.6
dB ( max)
dB (min)
dB (max)
dB
BTL gain from Phone_In _IHF to
SPKROUT
Phone_In_IHF Mute Attenuation
Phone_In_IHF Input Impedance
Output Mode 2, 4, 6
100
20
15
25
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
˚C (min)
µs (min)
ns (min)
ns (min)
ns (min)
ns (min)
Maximum gain setting
Mininum gain setting
Maximum gain setting
Mininum gain setting
33.5
100
20
25
42
Phone_In_HS Input Impedance
RIN and LIN Input Impedance
75
125
15
25
100
170
75
125
150
2.5
100
0
TSD
t1
Thermal Shutdown Temperature
SCL (Clock) Period
t2
SDA to SCL Set-up Time
Data Out Stable Time
Start Condition Time
t3
t4
100
100
t5
Stop Condition Time
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4
Electrical Characteristics (Notes 2, 8)
The following specifications apply for VDD= 3.0V, TA= 25˚C unless otherwise specified.
Symbol
Parameter
Conditions
LM4856
Units
(Limits)
Typical
(Note 5)
Limits
(Notes 6,
11)
Output modes 1, 2, 3, 4, 5, 6, 7
VIN = 0V; No loads
6.5
7
10
11
mA (max)
mA (max)
IDD
Supply Current
Output modes 1, 2, 3, 4, 5, 6, 7
VIN = 0V; Loaded (Figure 1)
Output mode 0
ISD
Shutdown Current
0.1
5.0
430
2.0
40
µA (max)
mV (max)
mW
VOS
Output Offset Voltage
VIN = 0V
SPKROUT; RL = 4Ω
THD+N = 1%; f = 1kHz, LM4856LQ
SPKROUT; RL = 8Ω
340
22
300
18
mW (min)
mW (min)
%
PO
Output Power
THD+N = 1%; f = 1kHz
ROUT and LOUT; RL = 32Ω
THD+N = 0.5%; f = 1kHz
SPKROUT
0.5
f = 20Hz to 20kHz
POUT = 150mW; RL = 8Ω
ROUT and LOUT
Total Harmonic Distortion Plus
Noise
THD+N
NOUT
0.5
%
f = 20Hz to 20kHz
POUT = 10mW; RL = 32Ω
A-weighted (Note 10)
VRIPPLE = 200mVPP; f = 217Hz,
CB = 1.0µF
Output Noise
29
58
µV
55
dB (min)
Power Supply Rejection Ratio
SPKROUT
All audio inputs terminated into 50Ω;
Output referred Gain (BTL) = 12dB
Output Mode 1, 3, 5, 7
VRIPPLE = 200mVPP; f = 217Hz,
CB = 1.0µF
PSRR
Power Supply Rejection Ratio
ROUTand LOUT
All audio inputs terminated into 50Ω;
Output referred Maximum gain setting
Output Mode 2, 3
68
60
56
60
55
dB (min)
dB (min)
dB (min)
V (min)
V (max)
V (max)
V (min)
Output Mode 4, 5
Output Mode 6, 7
52
VIH
VIL
Logic High Input Voltage
Logic Low Input Voltage
0.7 x VDD
VDD
0.4
GND
5
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Electrical Characteristics (Notes 2, 8) (Continued)
The following specifications apply for VDD= 3.0V, TA= 25˚C unless otherwise specified.
Symbol
Parameter
Conditions
LM4856
Units
(Limits)
Typical
(Note 5)
Limits
(Notes 6,
11)
Input referred minimum gain
Input referred maximum gain
Input referred minimum gain
Input referred maximum gain
-34.5
12.0
-40.5
6.0
-35.1
-33.9
11.4
12.6
-41.1
-39.9
5.4
dB (min)
dB (max)
dB (min)
dB (max)
dB (min)
dB (max)
dB (min)
dB (max)
dB
Digital Volume Range
(RIN and LIN
)
Digital Volume Range
(Phone_In_HS)
6.6
Digital Volume Stepsize
Digital Volume Stepsize Error
Phone_In_IHF Volume
1.5
0.1
12
0.6
11.4
12.6
dB ( max)
dB (min)
dB (max)
dB
BTL gain from Phone_In _IHF to
SPKROUT
Phone _In_IHF Mute Attenuation Output Mode 2, 4, 6
Phone_In_IHF Input Impedance
100
20
15
25
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
˚C (min)
µs (min)
ns (min)
ns (min)
ns (min)
ns (min)
Maximum gain setting
33.5
100
20
25
42
Phone_In_HS Input Impedance
Mininum gain setting
75
125
15
Maximum gain setting
25
RIN and LIN Input Impedance
Mininum gain setting
100
170
75
125
150
2.5
100
0
TSD
t1
Thermal Shutdown Temperature
SCL (Clock) Period
t2
SDA to SCL Set-up Time
Data Out Stable Time
Start Condition Time
t3
t4
100
100
t5
Stop Condition Time
Note 2: Absolute Maximum Rating indicate limits beyond which damage to the device may occur.
Note 3: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor.
Note 5: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 7: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50Ω).
Note 8: All voltages are measured with respect to the ground pin, unless otherwise specified.
2
Note 9: The given θ and θ are for an LM4856 mounted on a demonstration board with a 4in area of 1oz printed circuit board copper ground plane.
JA
JC
Note 10: Please refer to the Output Noise vs Output Mode table in the Typical Performance Characteristics section for more details.
Note 11: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
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6
External Components Description
Components
Functional Description
1.
CIN
This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the amplifier’s
input terminals. CIN also creates a highpass filter with the internal resistor Ri (Input Impedance) at fc =
1/(2πRiCIN).
2.
3.
CS
CB
This is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps maintain
the LM4856’s PSRR.
This is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4856’s PSRR.
Typical Performance Characteristics
THD+N vs Frequency
LM4856LQ
THD+N vs Frequency
LM4856LQ
200607F0
200607F1
THD+N vs Frequency
THD+N vs Frequency
200607B1
200607G6
7
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Typical Performance Characteristics (Continued)
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
200607G7
200607G8
200607G9
200607H1
THD+N vs Frequency
200607B5
THD+N vs Frequency
200607H0
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8
Typical Performance Characteristics (Continued)
THD+N vs Output Power
LM4856LQ
THD+N vs Output Power
LM4856LQ
200607F2
200607F3
200607H2
200607H3
THD+N vs Output Power
THD+N vs Output Power
200607B9
THD+N vs Output Power
THD+N vs Output Power
200607C1
9
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Typical Performance Characteristics (Continued)
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Power Supply Rejection Ratio
200607C3
200607H4
200607H5
200607H6
Power Supply Rejection Ratio
200607C5
Power Supply Rejection Ratio
200607C7
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Typical Performance Characteristics (Continued)
Output Power vs Supply Voltage
Output Power vs Supply Voltage
200607H7
200607D7
Output Power vs Load Resistance
Output Power vs Load Resistance
200607D9
200607H8
Power Dissipation vs Output Power
Power Dissipation vs Output Power
200607E1
200607H9
11
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Typical Performance Characteristics (Continued)
Supply Current vs Supply Voltage
Channel Separation
200607C9
200607I2
Frequency Response
Frequency Response
200607D4
200607I0
Frequency Response
200607I1
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Typical Performance Characteristics (Continued)
Output Noise vs Output Mode (VDD = 3V, 5V)
Output Mode
SPKROUT
LOUT/ROUT
Output Noise
(µV)
Output Noise
(µV)
29
X
1
2
X
14 (G1 = 0dB)
18 (G1 = 6dB)
14 (G1 = 0dB)
18 (G1 = 6dB)
17 (G2 = 0dB)
43 (G2 = 12dB)
17(G2 = 0dB)
43 (G2 = 12dB)
22 (G2 = 0dB)
30 (G1 = 0dB)
47 (G1 = 6dB)
22 (G2 = 0dB)
30 (G1 = 0dB)
47 (G1 = 6dB)
3
4
5
6
29
X
29
X
7
29
G1 = gain from P to LOUT/ROUT
HS
G2 = gain from LIN/RIN to LOUT/ROUT
A - weighted filter used
13
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Application Information
I2C PIN DESCRIPTION
The “start” signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I2C bus to check the incoming ad-
dress against their own chip address.
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ADR: This is the address select input pin.
The 8-bit chip address is sent next, most significant bit first.
Each address bit must be stable while the clock level is high.
I2C INTERFACE
After the last bit of the address is sent, the master checks for
the LM4856’s acknowledge. The master releases the data
line high (through a pullup resistor). Then the master sends
a clock pulse. If the LM4856 has received the address
correctly, then it holds the data line low during the clock
pulse. If the data line is not low, then the master should send
a “stop” signal (discussed later) and abort the transfer.
The LM4856 uses a serial bus, which conforms to the I2C
protocol, to control the chip’s functions with two wires: clock
and data. The clock line is uni-directional. The data line is
bi-directional (open-collector) with a pullup resistor (typically
10kΩ).The maximum clock frequency specified by the I2C
standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4856.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
The I2C address for the LM4856 is determined using the
ADR pin. The LM4856’s two possible I2C chip addresses are
of the form 110110X10 (binary), where the X1 = 0, if ADR is
logic low; and X1 = 1, if ADR is logic high. If the I2C interface
is used to address a number of chips in a system and the
LM4856’s chip address can be changed to avoid address
conflicts.
The timing diagram for the I2C is shown in Figure 2. The data
is latched in on the stable high level of the clock and the data
line should be held high when not in use. The timing diagram
is broken up into six major sections:
After the data byte is sent, the master must generate another
acknowledge to see if the LM4856 received the data.
If the master has more data bytes to send to the LM4856,
then the master can repeat the previous two steps until all
data bytes have been sent.
The “stop” signal ends the transfer. To signal “stop”, the data
signal goes high while the clock signal is high.
200607F5
FIGURE 2. I2C Bus Format
200607F4
FIGURE 3. I2C Timing Diagram
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14
Application Information (Continued)
TABLE 1. Data Register
DATA
BIT
D7
D6
D5
D4
D3
D2
D1
D0
Function
Name
Volume Control
Output Mode Control
V4
0
V3
0
V2
0
V1
0
V0
0
M2
0
M1
0
M0
0
Default
TABLE 2. Output Mode Selection
M2 M1 M0 Handsfree Speaker Output Right Headphone Output Left Headphone Output Output Mode Number
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SD
SD
MUTE
SD
MUTE
0
1
2
3
4
5
6
7
12dB x PIHF
MUTE
G1 x PHS
G1 x PHS
12dB x PIHF
MUTE
G1 x PHS
G1 x PHS
G2 x R
G2 x L
12dB x PIHF
MUTE
G2 x R
G2 x L
(G1 x PHS) + (G2 x R)
(G1 x PHS) + (G2 x R)
(G1 x PHS) + (G2 x L)
(G1 x PHS) + (G2 x L)
12dB x PIHF
P
P
= External High Pass Phone_In_IHF
= Non Filtered Phone_In_HS
IHF
HS
R = R
IN
L = L
IN
SD = Shutdown
MUTE = Mute Mode
G1 = gain from P to L
and R
OUT
HS
OUT
G2 = gain from L and R to L
and R
IN
IN
OUT
OUT
G1 = G2 + 6dB
15
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Application Information (Continued)
TABLE 3. Volume Control
Gain (dB)
G2
IN, LIN
to
G1
PHS
V4
V3
V2
V1
V0
R
to
ROUT, LOUT
-34.5
-33.0
-31.5
-30.0
-28.5
-27.0
-25.5
-24.0
-22.5
-21.0
-19.5
-18.0
-16.5
-15.0
-13.5
-12.0
-10.5
-9.0
ROUT, LOUT
-40.5
-39.0
-37.5
-36.0
-34.5
-33.0
-31.5
-30.0
-28.5
-27.0
-25.5
-24.0
-22.5
-21.0
-19.5
-18.0
-16.5
-15.0
-13.5
-12.0
-10.5
-9.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-7.5
-6.0
-4.5
-3.0
-1.5
-7.5
0.0
-6.0
1.5
-4.5
3.0
-3.0
4.5
-1.5
6.0
0.0
7.5
1.5
9.0
3.0
10.5
12.0
4.5
6.0
EXPOSED-DAP MOUNTING CONSIDERATIONS
connected to a large plane of continuous unbroken copper.
This plane forms a thermal mass, heat sink, and radiation
area. Place the heat sink area on either outside plane in the
case of a two-sided or multi-layer PCB. (The heat sink area
can also be placed on an inner layer of a multi-layer board.
The thermal resistance, however, will be higher.) Connect
the DAP copper pad to the inner layer or backside copper
heat sink area with 6 (3 X 2) (LD) vias. The via diameter
should be 0.012in - 0.013in with a 1.27mm pitch. Ensure
efficient thermal conductivity by plugging and tenting the vias
with plating and solder mask, respectively.
The LM4856’s exposed-DAP (die attach paddle) package
(LD) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper area heatsink, copper traces, ground plane, and
finally, surrounding air. The result is a low voltage audio
power amplifier that produces 1.1W dissipation in a 8Ω load
at ≤ 1% THD+N. This high power is achieved through careful
consideration of necessary thermal design. Failing to opti-
mize thermal design may compromise the LM4856’s high
power performance and activate unwanted, though neces-
sary, thermal shutdown protection.
Best thermal performance is achieved with the largest prac-
tical copper heat sink area. If the heatsink and amplifier
share the same PCB layer, a nominal 2.5in2 (min) area is
necessary for 5V operation with a 4Ω load. Heatsink areas
The LD package must have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad is then, ideally,
www.national.com
16
under the same conditions. This increase in attainable output
power assumes that the amplifier is not current limited and
that the output signal is not clipped.
Application Information (Continued)
not placed on the same PCB layer as the LM4856 should be
5in2 (min) for the same supply voltage and load resistance.
The last two area recommendations apply for 25˚C ambient
temperature. Increase the area to compensate for ambient
temperatures above 25˚C. In all circumstances and under all
conditions, the junction temperature must be held below
150˚C to prevent activating the LM4856’s thermal shutdown
protection. Further detailed and specific information con-
cerning PCB layout and fabrication and mounting an LD
(LLP) is found in National Semiconductor’s AN1187.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
SPKROUT- and SPKROUT+ outputs at half-supply. This
eliminates the coupling capacitor that single supply, single-
ended amplifiers require. Eliminating an output coupling ca-
pacitor in a typical single-ended configuration forces a
single-supply amplifier’s half-supply bias voltage across the
load. This increases internal IC power dissipation and may
permanently damage loads such as speakers.
PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS
POWER DISSIPATION
Power dissipation is a major concern when designing a
successful single-ended or bridged amplifier.
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load imped-
ance decreases, load dissipation becomes increasingly de-
pendent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connec-
tions. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1Ω trace resistance reduces
the output power dissipated by a 4Ω load from 1.7W to 1.6W.
The problem of decreased load dissipation is exacerbated
as load impedance decreases. Therefore, to maintain the
highest load dissipation and widest output voltage swing,
PCB traces that connect the output pins to a load must be as
wide as possible.
A direct consequence of the increased power delivered to
the load by a bridge amplifier is higher internal power dissi-
pation. The LM4856 has a pair of bridged-tied amplifiers
driving a handsfree speaker, SPKROUT. The maximum in-
ternal power dissipation operating in the bridge mode is
twice that of a single-ended amplifier. From Equation (2),
assuming a 5V power supply and an 8Ω load, the maximum
SPKROUT power dissipation is 634mW.
2
PDMAX-SPKROUT = 4(VDD
)
/ (2π2 RL): Bridge Mode (2)
The LM4856 also has a pair of single-ended amplifiers driv-
ing stereo headphones, ROUT and LOUT. The maximum
internal power dissipation for ROUT and LOUT is given by
equation (3) and (4). From Equations (3) and (4), assuming
a 5V power supply and a 32Ω load, the maximum power
dissipation for LOUT and ROUT is 40mW, or 80mW total.
Poor power supply regulation adversely affects maximum
output power. A poorly regulated supply’s output voltage
decreases with increasing load current. Reduced supply
voltage causes decreased headroom, output signal clipping,
and reduced output power. Even with tightly regulated sup-
plies, trace resistance creates the same effects as poor
supply regulation. Therefore, making the power supply
traces as wide as possible helps maintain full output voltage
swing.
2
PDMAX-LOUT = (VDD
)
/ (2π2 RL): Single-ended Mode (3)
/ (2π2 RL): Single-ended Mode (4)
BRIDGE CONFIGURATION EXPLANATION
2
PDMAX-ROUT = (VDD
)
As shown in Figure 1, the LM4856 consists of three pairs of
output amplifier blocks (A4-A6). Amplifier block A6 consists
of a bridged-tied amplifier pair that drives SPKROUT. The
LM4856 drives a load, such as a speaker, connected be-
tween outputs, SPKROUT+ and SPKROUT-. In the amplifier
block A6, the output of the amplifier that drives SPKROUT-
serves as the input to the unity gain inverting amplifier that
drives SPKROUT+.
The maximum internal power dissipation of the LM4856
occurs when all 3 amplifiers pairs are simultaneously on; and
is given by Equation (5).
PDMAX-TOTAL
=
PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT
(5)
This results in both amplifiers producing signals identical in
magnitude, but 180˚ out of phase. Taking advantage of this
phase difference, a load is placed between SPKROUT- and
SPKROUT+ and driven differentially (commonly referred to
as ’bridge mode’). This results in a differential or BTL gain of:
The maximum power dissipation point given by Equation (5)
must not exceed the power dissipation given by Equation
(6):
PDMAX’ = (TJMAX - TA) / θJA
(6)
AVD = 2(Rf / Ri) = 2
(1)
The LM4856’s TJMAX = 150˚C. In the ITL package, the
LM4856’s θJA is 48˚C/W. In the LD package soldered to a
DAP pad that expands to a copper area of 2.5in2 on a PCB,
the LM4856’s θJA is 42˚C/W. At any given ambient tempera-
ture TA, use Equation (6) to find the maximum internal power
dissipation supported by the IC packaging. Rearranging
Equation (6) and substituting PDMAX-TOTAL for PDMAX’ results
in Equation (7). This equation gives the maximum ambient
Bridge mode amplifiers are different from single-ended am-
plifiers that drive loads connected between a single amplifi-
er’s output and ground. For a given supply voltage, bridge
mode has a distinct advantage over the single-ended con-
figuration: its differential output doubles the voltage swing
across the load. Theoretically, this produces four times the
output power when compared to a single-ended amplifier
17
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SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Application Information (Continued)
temperature that still allows maximum stereo power dissipa-
tion without violating the LM4856’s maximum junction tem-
perature.
Amplifying the lowest audio frequencies requires high value
input coupling capacitor (Ci in Figure 3). A high value capaci-
tor can be expensive and may compromise space efficiency
in portable designs. In many cases, however, the speakers
used in portable systems, whether internal or external, have
little ability to reproduce signals below 150Hz. Applications
using speakers with this limited frequency response reap
little improvement by using large input capacitor.
TA = TJMAX - PDMAX-TOTAL θJA
(7)
For a typical application with a 5V power supply and an 8Ω
load, the maximum ambient temperature that allows maxi-
mum stereo power dissipation without exceeding the maxi-
mum junction temperature is approximately 104˚C for the
IBL package.
The internal input resistor (Ri) and the input capacitor (Ci)
produce a high pass filter cutoff frequency that is found using
Equation (9).
TJMAX = PDMAX-TOTAL θJA + TA
(8)
fc = 1 / (2πRiCi)
(9)
Equation (8) gives the maximum junction temperature TJ
-
As an example when using a speaker with a low frequency
limit of 150Hz, Ci, using Equation (9) is 0.063µF. The 0.22µF
Ci shown in Figure 1 allows the LM4856 to drive high effi-
ciency, full range speaker whose response extends below
40Hz.
MAX. If the result violates the LM4856’s 150˚C, reduce the
maximum junction temperature by reducing the power sup-
ply voltage or increasing the load resistance. Further allow-
ance should be made for increased ambient temperatures.
The above examples assume that a device is a surface
mount part operating around the maximum power dissipation
point. Since internal power dissipation is a function of output
power, higher ambient temperatures are allowed as output
power or duty cycle decreases. If the result of Equation (5) is
greater than that of Equation (6), then decrease the supply
voltage, increase the load impedance, or reduce the ambient
temperature. If these measures are insufficient, a heat sink
can be added to reduce θJA. The heat sink can be created
using additional copper area around the package, with con-
nections to the ground pin(s), supply pin and amplifier output
pins. External, solder attached SMT heatsinks such as the
Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consid-
eration should be paid to value of CB, the capacitor con-
nected to the BYPASS pin. Since CB determines how fast
the LM4856 settles to quiescent operation, its value is critical
when minimizing turn-on pops. The slower the LM4856’s
outputs ramp to their quiescent DC voltage (nominally VDD
/
2), the smaller the turn-on pop. Choosing CB equal to 1.0µF
along with a small value of Ci (in the range of 0.1µF to
0.39µF), produces a click-less and pop-less shutdown func-
tion. As discussed above, choosing Ci no larger than neces-
sary for the desired bandwidth helps minimize clicks and
pops. CB’s value should be in the range of 5 times to 7 times
the value of Ci. This ensures that output transients are
eliminated when power is first applied or the LM4856 re-
sumes operation after shutdown.
θ
SA. (θJC is the junction-to-case thermal impedance, θCS is
the case-to-sink thermal impedance, and θSA is the sink-to-
ambient thermal impedance.) Refer to the Typical Perfor-
mance Characteristics curves for power dissipation informa-
tion at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 10µF in parallel with a 0.1µF filter capacitors to stabi-
lize the regulator’s output, reduce noise on the supply line,
and improve the supply’s transient response. However, their
presence does not eliminate the need for a local 1.0µF
tantalum bypass capacitance connected between the
LM4856’s supply pins and ground. Keep the length of leads
and traces that connect capacitors between the LM4856’s
power supply pin and ground as short as possible. Connect-
ing a 1µF capacitor, CB, between the BYPASS pin and
ground improves the internal bias voltage’s stability and
improves the amplifier’s PSRR. The PSRR improvements
increase as the bypass pin capacitor value increases. Too
large, however, increases turn-on time and can compromise
the amplifier’s click and pop performance. The selection of
bypass capacitor values, especially CB, depends on desired
PSRR requirements, click and pop performance (as ex-
plained in the section, Proper Selection of External Compo-
nents), system cost, and size constraints.
www.national.com
18
Demonstration ITL/LQ Board Layout
200607G0
Recommended ITL PC Board Layout:
Top Overlay Layer
200607F9
Recommended ITL PC Board Layout:
Top Layer
200607F7
Recommended ITL PC Board Layout:
Middle 1 Layer
200607F8
Recommended ITL PC Board Layout:
Middle 2 Layer
19
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Demonstration ITL/LQ Board Layout (Continued)
200607F6
Recommended ITL PC Board Layout:
Bottom Layer
200607G5
Recommended LQ PC Board Layout:
Top Overlay Layer
200607G4
Recommended LQ PC Board Layout:
Top Layer
200607G2
Recommended LQ PC Board Layout:
Middle 1 Layer
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20
Demonstration ITL/LQ Board Layout (Continued)
200607G3
Recommended LQ PC Board Layout:
Middle 2 Layer
200607G1
Recommended LQ PC Board Layout:
Bottom Layer
21
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead MOLDED PKG, Leadless Leadframe Package LLP
Order Number LM4856LQ
NS Package Number LQA24A
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22
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
18-Bump micro SMD
Order Number LM4856ITL
NS Package Number TLA18AAA
X1 = 1.996 X2 = 2.225 X3 = 0.600
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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