LM4875MX/NOPB [TI]
具有精密直流音量控制和耳机放大器的 750mW、立体声、模拟输入、AB 类音频放大器 | D | 8 | -40 to 85;
| 型号： | LM4875MX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有精密直流音量控制和耳机放大器的 750mW、立体声、模拟输入、AB 类音频放大器 | D | 8 | -40 to 85 放大器 光电二极管 商用集成电路 音频放大器 |
| 文件： | 总26页 (文件大小：1724K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM4875
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SNAS042C –JANUARY 2002–REVISED MAY 2013
LM4875
750 mW Audio Power Amplifier with DC Volume
Control and Headphone Switch
Check for Samples: LM4875
1
FEATURES
DESCRIPTION
The LM4875 is a mono bridged audio power amplifier
with DC voltage volume control. The LM4875 is
capable of delivering 750mW of continuous average
power into an 8Ω load with less than 1% THD when
powered by a 5V power supply. Switching between
bridged speaker mode and headphone (single ended)
mode is accomplished using the headphone sense
pin. To conserve power in portable applications, the
LM4875's micropower shutdown mode (IQ = 0.7µA,
typ) is activated when less than 300mV is applied to
the DC Vol/SD pin.
2
•
•
•
•
Precision DC Voltage Volume Control
Headphone Amplifier Mode
“Click and Pop” Suppression
Shutdown Control When Volume Control Pin Is
Low
•
Thermal Shutdown Protection
APPLICATIONS
•
GSM Phones and Accessories, DECT, Office
Phones
Boomer audio power amplifiers are designed
specifically to provide high power audio output while
maintaining high fidelity. They require few external
components and operate on low supply voltages.
•
•
Hand Held Radio
Other Portable Audio Devices
KEY SPECIFICATIONS
•
•
•
•
PO at 1.0% THD+N Into 8Ω; 750 mW (typ)
PO at 10% THD+N Into 8Ω; 1 W (typ)
Shutdown Current; 0.7µA(typ)
Supply Voltage Range; 2.7V to 5.5 V
TYPICAL APPLICATION
CONNECTION DIAGRAM
Small Outline Package (SOIC)
Mini Small Outline Package (VSSOP)
Top View
See Package Number D, DGK
Figure 1. Typical Audio Amplifier Application
Circuit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM4875
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage
6.0V
−65°C to +150°C
−0.3V to VDD +0.3V
Internally Limited
2000V
Storage Temperature
Input Voltage
Power Dissipation(3)
ESD Susceptibility(4)
ESD Susceptibility(5)
Junction Temperature
200V
150°C
Vapor Phase (60 sec.)
Infrared (15 sec.)
θJC (D)
215°C
Soldering Information
220°C
35°C/W
θJA (D)
150°C/W
Thermal Resistance
θJC (DGK)
56°C/W
θJA (DGK)
190°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions that ensure specific performance limits. This assumes that the device operates within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given. The typical value, however, is a good
indication of device performance.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings,
whichever is lower. For the LM4875M, TJMAX = 150°C.
(4) Human body model, 100pF discharged through a 1.5kΩ resistor.
(5) Machine Model, 220pF–240pF discharged through all pins.
OPERATING RATINGS
Temperature Range
TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +85°C
2.7V ≤ VDD ≤ 5.5V
Supply Voltage
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ELECTRICAL CHARACTERISTICS(1)(2)
The following specifications apply for VDD = 5V, unless otherwise specified. Limits apply for TA = 25°C.
LM4875
Typical(4)
Symbol
VDD
Parameter
Supply Voltage
Conditions
Min(3)
Max(3)
Units
V
2.7
5.5
7
VIN = 0V, IO = 0A, HP Sense = 0V
VIN = 0V, IO - 0A, HP Sense = 5V
4
mA
mA
µA
IDD
Quiescent Power Supply Current
3.5
0.7
5
6
ISD
Shutdown Current
VPIN4 ≤ 0.3V
VOS
Output Offset Voltage
VIN = 0V
50
mV
THD = 1% (max), HP Sense < 0.8V, f =
1kHz, RL = 8Ω
500
750
1.0
80
mW
W
THD = 10% (max), HP Sense < 0.8V, f =
1kHz, RL = 8Ω
PO
Output Power
THD + N = 1%, HP Sense > 4V,
f = 1kHz, RL = 32Ω
mW
mW
%
THD = 10%, HP Sense > 4V,
f = 1kHz, RL = 32Ω
110
0.6
50
PO = 300 mWrms, f = 20Hz–20kHz, RL =
8Ω
THD+N
PSRR
Total Harmonic Distortion + Noise
Power Supply Rejection Ratio
VRIPPLE = 200mVrms, RL = 8Ω, CB = 1.0
µF, f = 1kHz
dB
Gain with VPIN4 ≥ 4.0V, (80% of VDD
)
)
18.8
−70
4
20
dB
dB
V
GainRANGE Single-Ended Gain Range
Gain with VPIN4 ≤ 0.9V, (20% of VDD
−72
VIH
VIL
HP Sense High Input Voltage
HP Sense Low Input Voltage
0.8
V
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions that ensure specific performance limits. This assumes that the device operates within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given. The typical value, however, is a good
indication of device performance.
(3) Limits are ensured to AOQL (Average Outgoing Quality Level).
(4) Typicals are measured at 25°C and represent the parametric norm.
EXTERNAL COMPONENTS DESCRIPTION
(Figure 1)
Components
Functional Description
1.
Ci
Input coupling capacitor blocks DC voltage at the amplifier's input terminals. It also creates a highpass filter with the
internal Ri that produces an fc = 1/(2πRiCi) (10kΩ ≤ Ri ≤ 100kΩ). Refer to the APPLICATION INFORMATION section,
PROPERLY SELECTING EXTERNAL COMPONENTS, for an explanation of determining the value of Ci.
2.
3.
CS
CB
The supply bypass capacitor. Refer to the POWER SUPPLY BYPASSING section for information about properly placing,
and selecting the value of, this capacitor.
The capacitor, CB, filters the half-supply voltage present on the BYPASS pin. Refer to the APPLICATION INFORMATION
Section,PROPERLY SELECTING EXTERNAL COMPONENTS, for information concerning proper placement and selecting
CB's value.
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TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Frequency
THD+N vs Frequency
Figure 2.
Figure 3.
THD+N vs Output Power
THD+N vs Output Power
Figure 4.
Figure 5.
THD+N vs Output Power
THD+N vs Output Power
Figure 6.
Figure 7.
4
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Power Dissipation vs Load Resistance
Power Dissipation vs Output Power
Figure 8.
Figure 9.
Power Derating Curve
Clipping Voltage vs RL
Figure 10.
Figure 11.
Frequency Response vs
Input Capacitor Size
Noise Floor
Figure 12.
Figure 13.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Power Supply
Rejection Ratio
Attenuation Level vs
DC-Vol Amplitude
Figure 14.
Figure 15.
THD+N vs Frequency
THD+N vs Frequency
Figure 16.
Figure .
THD+N vs Frequency
THD+N vs Output Power
Figure 17.
Figure 18.
6
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power
THD+N vs Output Power
Figure 19.
Figure 20.
Output Power vs Load Resistance
Clipping Voltage vs Supply Voltage
Figure 21.
Figure 22.
Output Power vs Supply Voltage
Figure 23.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Power vs Supply Voltage
Supply Current vs Supply Voltage
Figure 24.
Figure 25.
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APPLICATION INFORMATION
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 1, the LM4875 consists of two operational amplifiers internally. An external DC voltage sets
the closed-loop gain of the first amplifier, whereas two internal 20kΩ resistors set the second amplifier's gain at -
1. The LM4875 can be used to drive a speaker connected between the two amplifier outputs or a monaural
headphone connected between VO1 and GND.
Figure 1 shows that the output of Amp1 serves as the input to Amp2. This results in both amplifiers producing
signals that are identical in magnitude, but 180° out of phase.
Taking advantage of this phase difference, a load placed between VO1 and VO2 is driven differentially (commonly
referred to as “bridge mode“ ). This mode is different from single-ended driven loads that are connected between
a single amplifier's output and ground.
Bridge mode has a distinct advantage over the single-ended configuration: its differential drive to the load
doubles the output swing for a specified supply voltage. This results in four times the output power when
compared to a single-ended amplifier under the same conditions. This increase in attainable output assumes that
the amplifier is not current limited or the output signal is not clipped.
Another advantage of the differential bridge output is no net DC voltage across load. This results from biasing
VO1 and VO2 at half-supply. This eliminates the coupling capacitor that single supply, single-ended amplifiers
require. Eliminating an output coupling capacitor in a single-ended configuration forces a single supply amplifier's
half-supply bias voltage across the load. The current flow created by the half-supply bias voltage increases
internal IC power dissipation and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful bridged or single-ended amplifier. Equation 1
states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and
driving a specified output load.
PDMAX = (VDD)2/(2π2RL) Single-Ended
(1)
However, a direct consequence of the increased power delivered to the load by a bridge amplifier is an increase
in internal power dissipation point for a bridge amplifier operating at the same given conditions.
PDMAX = 4*(VDD)2/(2π2RL) Bridge Mode
(2)
The LM4875 has two operational amplifiers in one package and the maximum internal power dissipation is 4
times that of a single-ended amplifier. However, even with this substantial increase in power dissipation, the
LM4875 does not require heatsinking. From Equation 2, assuming a 5V power supply and an 8Ω load, the
maximum power dissipation point is 633 mW. The maximum power dissipation point obtained from Equation 2
must not be greater than the power dissipation that results from Equation 3:
PDMAX = (TJMAX–TA)/θJA
(3)
For the SOIC package, θJA = 150°C/W. The VSSOP package has a 190°C/W θJA. TJMAX = 150°C for the
LM4875. For a given ambient temperature TA, Equation 3 can be used to find the maximum internal power
dissipation supported by the IC packaging. If the result of Equation 2 is greater than that of Equation 3, then
either decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. For a
typical application using the SOIC packaged LM4875, a 5V power supply, and an 8Ω load, the maximum ambient
temperature that does not violate the maximum junction temperature is approximately 55°C. The maximum
ambient temperature for the VSSOP package with the same conditions is approximately 30°C. These results
further assume that a device is a surface mount part operating around the maximum power dissipation point.
Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output
power decreases. Refer to the TYPICAL PERFORMANCE CHARACTERISTICS curves for power dissipation
information at lower output power levels.
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POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. The capacitors connected to the bypass and power supply pins should be placed as close to the
LM4875 as possible. The capacitor connected between the bypass pin and ground improves the internal bias
voltage's stability, producing improved PSRR. The improvements to PSRR increase as the bypass pin capacitor
value increases. Typical applications employ a 5V regulator with 10µF and a 0.1µF filter capacitors that aid in
supply stability. Their presence, however does not eliminate the need for bypassing the supply nodes of the
LM4875. The selection of bypass capacitor values, especially CB, depends on desired PSRR requirements, click
and pop performance (as explained in the section, PROPERLY SELECTING EXTERNAL COMPONENTS),
system cost, and size constraints.
DC VOLTAGE VOLUME CONTROL
The LM4875's internal volume control is controlled by the DC voltage applied its DC Vol/SD pin (pin 4). The
volume control's input range is from GND to VDD. A graph showing a typical volume response versus input
control voltage is shown in the TYPICAL PERFORMANCE CHARACTERISTICS section. The DC Vol/SD pin
also functions as the control pin for the LM4875's micropower shutdown feature. See the MUTE AND
SHUTDOWN FUNCTION section for more information.
Like all volume controls, the Lm4875's internal volume control is set while listening to an amplified signal that is
applied to an external speaker. The actual voltage applied to the DC Vol/SD pin is a result of the volume a
listener desires. As such, the volume control is designed for use in a feedback system that includes human ears
and preferences. This feedback system operates quite well without the need for accurate gain. The user simply
sets the volume to the desired level as determined by their ear, without regard to the actual DC voltage that
produces the volume. Therefore, the accuracy of the volume control is not critical, as long as volume changes
monotonically and step size is small enough to reach a desired volume that is not too loud or too soft. Since gain
accuracy is not critical, there may be a volume variation from part-to-part even with the same applied DC control
voltage. The gain of a given LM4875 can be set with a fixed external voltage, but another LM4875 may require a
different control voltage to achieve the same gain. Figure 26 is a curve showing the volume variation of seven
typical LM4875s as the voltage applied to the DC Vol/SD pin is varied. For gains between -20dB and +16dB, the
typical part-to-part variation is typically ±1dB for a given control voltage.
Figure 26. Typical Part-to-Part Gain Variation as a Function of DC-Vol Control Voltage
MUTE AND SHUTDOWN FUNCTION
The LM4875's mute and shutdown functions are controlled through the DC Vol/SD pin. Mute is activated by
applying a voltage in the range of 500mV to 1V. A typical attenuation of 75dB is achieved is while mute is active.
The LM4875's micropower shutdown mode turns off the amplifier's bias circuitry. The micropower shutdown
mode is activated by applying less than 300mVDC to the DC Vol/SD pin. When shutdown is active, they supply
current is reduced to 0.7µA (typ). A degree of uncertainty exists when the voltage applied to the DC Vol/SD pin is
in the range of 300mV to 500mV. The LM4875 can be in mute, still fully powered, or in micropower shutdown
and fully muted. In mute mode, the LM4875 draws the typical quiescent supply current. The DC Vol/SD pin
should be tied to GND for best shutdown mode performance. As the DC Vol/SD is increased above 0.5V the
amplifier will follow the attenuation curve in TYPICAL PERFORMANCE CHARACTERISTICS .
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HP-Sense FUNCTION
Applying a voltage between 4V and VCC to the LM4875's HP-Sense headphone control pin turns off Amp2 and
mutes a bridged-connected load. Quiescent current consumption is reduced when the IC is in this single-ended
mode.
Figure 27 shows the implementation of the LM4875's headphone control function. With no headphones
connected to the headphone jack, the R1-R2 voltage divider sets the voltage applied to the HP-Sense pin (pin 3)
at approximately 50mV. This 50mV enables the LM4875 and places it in bridged mode operation.
7
Figure 27. Headphone Circuit
While the LM4875 operates in bridged mode, the DC potential across the load is essentially 0V. Since the HP-
Sense threshold is set at 4V, even in an ideal situation, the output swing cannot cause a false single-ended
trigger. Connecting headphones to the headphone jack disconnects the headphone jack contact pin from VO1
and allows R1 to pull the HP Sense pin up to VCC. This enables the headphone function, turns off Amp2, and
mutes the bridged speaker. The amplifier then drives the headphones, whose impedance is in parallel with
resistor R2. Resistor R2 has negligible effect on output drive capability since the typical impedance of
headphones is 32Ω. The output coupling capacitor blocks the amplifier's half supply DC voltage, protecting the
headphones.
A microprocessor or a switch can replace the headphone jack contact pin. When a microprocessor or switch
applies a voltage greater than 4V to the HP Sense pin, a bridge-connected speaker is muted and Amp1 drives
the headphones.
PROPERLY SELECTING EXTERNAL COMPONENTS
Optimizing the LM4875's performance requires properly selecting external components. Though the LM4875
operates well when using external components having wide tolerances, the best performance is achieved by
optimizing component values.
Input Capacitor Value Selection
Amplification of the lowest audio frequencies requires high value input coupling capacitors. These high value
capacitors can be expensive and may compromise space efficiency in portable designs. In many cases,
however, the speakers used in portable systems, whether internal or external, have little ability to reproduce
signals below 150Hz. In application 5 using speakers with this limited frequency response, a large input capacitor
will offer little improvement in system performance.
Figure 1 shows that the nominal input impedance (RIN) is 10kΩ at maximum volume and 110kΩ at minimum
volume. Together, the input capacitor, Ci, and RIN, produce a -3dB high pass filter cutoff frequency that is found
using Equation 4.
(4)
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As the volume changes from minimum to maximum, RIN decrease from 110kΩ to 10kΩ. Equation 4 reveals that
the -3dB frequency will increase as the volume increases. The nominal value of Ci for lowest desired frequency
response should be calculated with RIN = 10kΩ . As an example when using a speaker with a low frequency limit
of 150Hz, Ci, using Equation 4 is 0.1µF. The 0.22µF Ci shown in Figure 1 is optimized for a speaker whose
response extends down to 75Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of the bypass capacitor
CB. Since CB determines how fast the LM4875 turns on, its value is the most critical when minimizing turn-on
pops. The slower the LM4875's outputs ramp to their quiescent DC voltage (nominally VDD/2), the smaller the
turn-on pop. Choosing CB equal to 1.0µF, along with a small value of Ci (in the range of 0.1µF to 0.39µF),
produces a clickless and popless shutdown function. Choosing Ci as small as possible helps minimize clicks and
pops.
CLICK AND POP CIRCUITRY
The LM4875 contains circuitry that minimizes turn-on and shutdown transients or "clicks and pops". For this
discussion, turn-on refers to either applying the power supply voltage or when the shutdown mode is deactivated.
While the power supply is ramping to its final value, the LM4875's internal amplifiers are configured as unity gain
buffers. An internal current source changes the voltage of the bypass pin in a controlled, linear manner. Ideally,
the input and outputs track the voltage applied to the bypass pin. The gain of the internal amplifiers remains unity
until the voltage on the bypass pin reaches 1/2 VDD. As soon as the voltage on the bypass pin is stable, the
device becomes fully operational and the gain is set by the external voltage applied to the DC Vol/SD pin.
Although the bypass pin current cannot be modified, changing the size of CB alters the device's turn-on time and
the magnitude of "clicks and pops". Increasing the value of CB reduces the magnitude of turn-on pops. However,
this presents a tradeoff: as the size of CB increases, the turn-on time increases. There is a linear relationship
between the size of CB and the turn-on time. Shown below are some typical turn-on times for various values of
CB:
CB
TON
0.01µF
0.1µF
3ms
30ms
0.22µF
0.47µF
1.0µF
65ms
135ms
280ms
In order eliminate "clicks and pops", all capacitors must be discharged before turn-on. Rapidly switching VDD may
not allow the capacitors to fully discharge, which may cause "clicks and pops". In a single-ended configuration,
the output coupling capacitor, COUT, is of particular concern. This capacitor discharges through an internal 20kΩ
resistor. Depending on the size of COUT, the time constant can be relatively large. To reduce transients in single-
ended mode, an external 1kΩ - 5kΩ resistor can be placed in parallel with the internal 20kΩ resistor. The tradeoff
for using this resistor is increased quiescent current.
RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT
Figure 28 through Figure 30 show the recommended two-layer PC board layout that is optimized for the SOIC-8
packaged LM4875 and associated external components. Figure 31 through Figure 33 show the recommended
two-layer PC board layout for the VSSOP packaged LM4875. Both layouts are designed for use with an external
5V supply, 8Ω speakers, and 8Ω - 32Ω headphones. The schematic for both recommended PC board layouts is
Figure 1.
Both circuit boards are easy to use. Apply a 5V supply voltage and ground to the board's VDD and GND pads,
respectively. Connect a speaker with an 8Ω minimum impedance between the board's -OUT and +OUT pads.
For headphone use, the layout has provisions for a headphone jack, J1. When a jack is connected as shown,
inserting a headphone plug automatically switches off the external speaker.
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Figure 28. Recommended SOIC PC Board Layout:
Component Side Silkscreen
Figure 29. Recommended SOIC PC Board Layout:
Component Side Layout
Figure 30. Recommended SOIC PC Board Layout:
Bottom Side Layout
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Figure 31. Recommended VSSOP PC Board Layout:
Component Side Silkscreen
Figure 32. Recommended VSSOP PC Board Layout:
Component Side Layout
Figure 33. Recommended VSSOP PC Board Layout:
Bottom Side Layout
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REVISION HISTORY
Changes from Revision B (May 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM4875M/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LM48
75M
LM4875MM/NOPB
LM4875MX/NOPB
ACTIVE
ACTIVE
VSSOP
SOIC
DGK
D
8
8
1000 RoHS & Green
2500 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
G75
LM48
75M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM4875MM/NOPB
LM4875MX/NOPB
VSSOP
SOIC
DGK
D
8
8
1000
2500
178.0
330.0
12.4
12.4
5.3
6.5
3.4
5.4
1.4
2.0
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM4875MM/NOPB
LM4875MX/NOPB
VSSOP
SOIC
DGK
D
8
8
1000
2500
208.0
367.0
191.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM4875M/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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