LM48901SQE [TI]
Audio Power Amplifier Series; 音频功率放大器系列
| 型号： | LM48901SQE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Audio Power Amplifier Series |
| 文件： | 总51页 (文件大小：805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 5, 2012
LM48901
Quad Class D Spatial Array
General Description
Features
The LM48901 is a quad Class D amplifier that utilizes Texas
Instruments’ proprietary spatial sound processor to create an
enhanced sound stage for portable multimedia devices. The
Class D output stages feature Texas Instruments’ edge rate
control (ERC) PWM architecture that significantly reduces RF
emissions while preserving audio quality and efficiency.
The LM48901’s flexible I2S interface is compatible with stan-
dard serial audio interfaces. A stereo differential-input ADC
gives the device the ability to process analog stereo audio
signals.
The LM48901 is configured through an I2C compatible inter-
face and is capable of delivering 2.8W/channel of continuous
output power into an 4Ω load with less than 10% THD+N. A
2.1 mode pairs two output drivers in parallel, increasing cur-
rent drive for 4Ω loads.
Output short circuit and thermal overload protection prevent
the device from being damaged during fault conditions. Su-
perior click and pop suppression eliminates audible transients
on power-up/down and during shutdown. The LM48901 is
available in space saving microSMD and LLP packages.
Spatial Sound Processing
■
■
■
I2S Compatible Input
Differential-Input Stereo ADC
Edge Rate Control Reduces EMI while Preserving Audio
Quality and Efficiency
■
Paralleled Output Mode
■
■
■
■
■
■
Short Circuit and Thermal Overload Protection
Minimum external components
Click and Pop suppression
Micro-power shutdown
Available in space-saving micro SMD and LLP packages
Applications
Laptops
■
■
■
■
■
■
■
Tablets
Desktop Computers
Sound Bars
Multimedia Devices
MP3 Player Accessories
Key Specifications
Docking Stations
■ꢀSNR (A-Weighted)
■ꢀOutput Power/channel, PVDD = 5V
RL = 8Ω, THD+N ≤10%
RL = 4Ω, THD+N ≤10%
■ꢀTHD+N
■ꢀEfficiency/Channel
■ꢀPSRR at 217Hz
■ꢀShutdown current
87dBA (typ)
1.7W (typ)
2.8W (typ)
0.06% (typ)
89% (typ)
71dB (typ)
1μA (typ)
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2012 Texas Instruments Incorporated
301692 SNAS520C
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Typical Application
30169203
FIGURE 1. Typical Audio Amplifier Application Circuit
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30169209
FIGURE 2. Channel Audio Amplifier Application Circuit
Only OUT2 and OUT3 can be configured in parallel. OUT1 and OUT4 cannot be configured in parallel.
3
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Connection Diagrams
micro SMD Package
36–Bump micro SMD Marking
301692a5
Top View
XY = Date code
TT = Die traceability
G = Boomer Family
02 = LM48901RL
30169202
Top View
Order Number LM48901RL
See NS Package Number RLA36JSA
SQ Package
30169201
Top View
Order Number LM48901SQ
See NS Package Number SQA32A
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Ordering Information
Ordering Information Table
Package
MSL
Level
Order Number
Package
Drawing
Number
Transport Media
Green Status n
LM48901RL
36–bump microSMD RLA36JSA
250 units on tape and reel
1000 units on tape and reel
1000 units on tape and reel
250 units on tape and reel
4500 units on tape and reel
1
1
1
1
1
RoHS & no Sb/Br
RoHS & no Sb/Br
RoHS & no Sb/Br
RoHS & no Sb/Br
RoHS & no Sb/Br
LM48901RLX 36–bump microSMD RLA36JSA
LM48901SQ
32–pin LLP
SQA32A
SQA32A
SQA32A
LM48901SQE 32–pin LLP
LM48901SQX 32–pin LLP
TABLE 1. Pin Descriptions
DESCRIPTION
BUMP
A1
PIN
1
NAME
OUT4+
PVDD
Channel 4 Non-Inverting Output
Class D Power Supply
A2, A5
A3
2, 7
4
OUT3+
OUT2+
OUT1+
OUT4-
PGND
OUT3-
OUT2-
OUT1-
IOVDD
DVDD
Channel 3 Non-Inverting Output. Connect to OUT2+ in Parallel Mode.
Channel 2 Non-Inverting Output. Connect to OUT3+ in Parallel Mode.
Channel 1 Non-Inverting Output
Channel 4 Inverting Output
A4
5
A6
8
B1
31
9, 32
3
B2, B5
B3
Power Ground
Channel 3 Inverting Output. Connect to OUT2- in Parallel Mode.
Channel 2 Inverting Output. Connect to OUT3- in Parallel Mode.
Channel 1 Inverting Output
B4
6
B6
10
29
28
30
11
—
12
27
26
30
—
—
13
25
23
20
18
15
14
24
22
21
19
17
16
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
Digital Interface Power Supply
Digital Power Supply
DGND
AGND1
AVDD3
AVDD1
SHDN
I2C_EN
IOGND
AGND2
PLLVDD
AVDD2
I2C_EX
Digital Ground
Modulator Analog Ground
ADC Reference Power Supply
Modulator Analog Power Supply. Set to same voltage as PVDD for maximum headroom.
Active Low Shutdown. Connect to VDD for normal operation.
I2C Enable Input
Digital Interface Ground
ADC Analog Ground
PLL Power Supply
ADC Analog Power Supply
I2C Enable Output
I2S Word Select Input
E2
WS
SDA
INR-
INL-
I2C Serial Data Input
E3
E4
Right Channel Inverting Analog Input
Left Channel Inverting Analog Input
ADC Reference Bypass
E5
E6
REF
F1
MCLK
SCLK
SDIO
SCL
Master Clock
F2
Serial Clock Input
I2S Serial Data Input/Output
F3
I2C Clock Input
F4
F5
INR+
INL+
Right Channel Non-Inverting Analog Input
Left Channel Non-Inverting Analog Input
F6
5
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Thermal Resistance
ꢁθJA (microSMD)
ꢁθJA (LLP)
Absolute Maximum Ratings (Note 1, Note
2)
26°C/W
26°C/W
2.6°C/W
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
ꢁθJC (LLP)
Operating Ratings
Supply Voltage
Temperature Range
TMIN ≤ TA ≤ TMAX
Supply Voltage
AVDD
ꢁ
AVDD, PVDD, PLVDD, IOVDD(Note 1)
−40°C ≤ TA ≤ +85°C
6.0V
Supply Voltage, DVDD (Note 1)
Storage Temperature
2.2V
−65°C to + 150°C
−0.3V to VDD + 0.3V
Internally limited
2000V
2.7V ≤ AVDD ≤ 5.5V
2.7V ≤ PVDD ≤ 5.5V
2.7V ≤ PLLVDD ≤ 5.5V
1.62V ≤ IOVDD ≤ 5.5V
1.62V ≤DVDD ≤1.98V
Input Voltage
PVDD
Power Dissipation (Note 3)
ESD Susceptibility (Note 4)
ESD Susceptibility (Note 5)
Junction Temperature
PLLVDD
IOVDD
DVDD
150V
150°C
Electrical Characteristics PVDD = AVDD = 5V, IOVDD = PLLVDD = 3.3V, DVDD
=
1.8 (Note 2, Note 8)
The following specifications apply for AV = 0dB, CREF = 4.7µF, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA
= 25°C.
LM48901
Units
Symbol
AVDD
Parameter
Conditions
Min
(Note 8)
Typ
Max
(Limits)
(Note 7)
(Note 8)
Analog Supply Voltage Range
(Note 9)
2.7
2.7
5.5
5.5
V
V
PVDD
Amplifier Supply Voltage Range (Note 9)
PLL Supply Voltage Range
PLLVDD
IOVDD
DVDD
2.7
5.5
V
Interface Supply Voltage Range
Digital Supply Voltage Range
1.62
1.62
5.5
V
1.98
21
V
LM48901RL
17.5
19.2
mA
mA
AIDD
Analog Quiescent Supply Current
LM48901SQ
22.3
Amplifier Quiescent Supply
Current
PIDD
RL = 8Ω
5.25
1.5
8.25
mA
mA
mA
PLLIDD
DIDD
PLL Quiescent Supply Current
LM48901RL
Quiescent Digital Power Supply
Current
5.5
6.2
5
Shutdown Current (Analog,
Amplifier and PLL Supplies)
ISD
Shutdown Enabled
Shutdown Enabled
1
μA
DISTBY
DISD
VOS
Digital Standby Current
Digital Shutdown Current
30
2
μA
μA
Differential Output Offset Voltage VIN = 0
–17
0
17
mV
ms
ms
kHz
Power Up (Device Initialization)
150
30
384
TWU
fSW
Wake-up Time
From Shutdown
fS = 48kHz
Switching Frequency
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LM48901
Units
(Limits)
Symbol
Parameter
Conditions
Min
Typ
(Note 7)
Max
(Note 8)
(Note 8)
RL = 4Ω, THD+N = 10%
f = 1kHz, 22kHz BW
VDD = 5V
2.8
1.4
W
W
VDD = 3.6V
RL = 4Ω, THD+N = 1%
f = 1kHz, 22kHz BW
VDD = 5V
2.2
1.2
W
W
VDD = 3.6V
PO
Output Power/Channel
RL = 8Ω, THD+N = 10%
f = 1kHz, 22kHz BW
VDD = 5V
1.7
W
VDD = 3.6V
825
mW
RL = 8Ω, THD+N = 1%
f = 1kHz, 22kHz BW
VDD = 5V
1.0
1.3
W
VDD = 3.6V
650
mW
RL = 4Ω, THD+N = 10%, f = 1kHz, 22kHz BW
VDD = 5V
3.2
1.6
W
W
VDD = 3.6V
Output Power (Parallel Mode)
(Note 10)
PO
RL = 4Ω, THD+N = 1%, f = 1kHz, 22kHz BW
VDD = 5V
2.5
1.2
W
W
%
VDD = 3.6V
THD+N
PSRR
Total Harmonic Distortion + Noise PO = 500mW, f = 1kHz, RL = 8Ω
0.06
VRIPPLE = 200mVP-P sine, Inputs AC GND, CIN = 1μF
fRIPPLE = 217Hz, Applied to PVDD
fRIPPLE = 217Hz, Applied to DVDD
fRIPPLE = 1kHz, Applied to PVDD
fRIPPLE = 1kHz, Applied to DVDD
fRIPPLE = 10kHz, Applied to PVDD
fRIPPLE = 10kHz, Applied to DVDD
VRIPPLE = 200mVP-P sine, Inputs –120dBFS
fRIPPLE = 217Hz, Applied to PVDD
fRIPPLE = 217Hz, Applied to DVDD
fRIPPLE = 1kHz, Applied to PVDD
fRIPPLE = 1kHz, Applied to DVDD
fRIPPLE = 10kHz, Applied to PVDD
fRIPPLE = 10kHz, Applied to DVDD
67
54
66
54
57
52
dB
dB
dB
dB
dB
dB
Power Supply Rejection Ratio
(ADC Path)
71
58
69
57
70
55
dB
dB
dB
dB
dB
dB
Power Supply Rejection Ratio
(I2S Path)
PSRR
VRIPPLE = 1VP-P, fRIPPLE = 217Hz,
AV = 0dB
CMRR
Common Mode Rejection Ratio
Efficiency/Channel
Efficiency
60
dB
VDD = 5V, PO = 1.1W
VDD = 3.6V, PO = 400mW
VDD = 5V, PO = 1.1W
VDD = 3.6V, PO = 400mW
ADC Input, PO = 1W
I2S Input, PO = 1W
89
87
87
86
85
87
%
%
η
%
η
%
dB
dB
SNR
Signal-to-Noise-Ratio
7
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LM48901
Units
(Limits)
Symbol
Parameter
Conditions
Min
Typ
(Note 7)
Max
(Note 8)
(Note 8)
Common Mode Input Voltage
Range
CMVR
5
V
Inputs AC GND, A-weighted,
AV = 0dB
130
μV
εOS
Output Noise
Crosstalk
I2S Input
72
75
μV
XTALK
dB
I2C Interface Characteristics (Note 1, Note 2)
The following specifications apply for RPU = 1kΩ to IOVDD, unless otherwise specified. Limits apply for TA = 25°C.
LM48901
Symbol
Parameter
Conditions
Units
Min
Typ
Max
(Note 7)
(Note 6)
(Note 7)
0.7*IOVDD
VIH
VIL
Logic Input High Threshold
Logic Input Low Threshold
Logic Output Low Threshold
Logic Output High Current
SCL Frequency
SDA, SCL
SDA, SCL
V
mV
V
300
VOL
IOH
SDA, ISDA = 3.6mA
SDA, SCL
0.35
2
uA
kHz
400
Hold Time
(repeated START Condition)
1
0.6
µs
2
3
Clock Low Time
Clock High Time
1.3
µs
ns
600
Setup Time for Repeated
START condition
4
600
ns
5
6
7
8
9
Data Hold Time
Output
300
100
900
ns
ns
ns
ns
ns
Data Setup Time
SDA Rise Time
300
300
SDA Fall Time
Setup Time for STOP Condition
600
1.3
Bus Free Time Between STOP
and START Condition
10
µs
I2S Timing Characteristics (Note 2, Note 8)
The following specifications apply for DVDD = 1.8V, unless otherwise specified. Limits apply for TA = 25°C.
LM48901
Units
(Limits)
Symbol
Parameter
Conditions
Min
Typ
(Note 6)
Max
(Note 7)
(Note 7)
tMCLKL
tMCLKH
tMCLKY
tBCLKR
tBCLKCF
tBCLKDS
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Period
16
16
27
ns
ns
ns
ns
ns
%
SCLK rise time
3
3
SCLK fall time
SCLK Duty Cycle
50
LRC Propagation Delay from
SCLK falling edge
TDL
TDST
TDHT
10
ns
ns
ns
DATA Setup Time to SCLK
Rising Edge
10
10
DATA Hold Time from SCLK
Rising Edge
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Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX − TA) / θJA or the given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 8: RL is a resistive load in series with two inductors to simulate an actual speaker load. For RL = 8Ω, the load is 15μH+8Ω+15μH. For RL = 4Ω, the load is
15μH+4Ω+15μH.
Note 9: Maintain PVDD and AVDD at the same voltage potential.
Note 10: Only OUT2 and OUT3 can be configured in Parallel Mode.
9
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Typical Performance Characteristics
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 500mW,
THD+N vs FREQUENCY
VDD = 5V, POUT = 925 mW,
RL = 8Ω, ADC Input
RL = 8Ω, ADC Input
30169220
30169221
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 7505 mW,
THD+N vs FREQUENCY
VDD = 5V, POUT = 1.3W,
RL = 4Ω, ADC Input
RL = 4Ω, ADC Input
30169223
30169222
THD+N vs FREQUENCY
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 900mW,
VDD = 3.6V, POUT = 450mW,
RL = 4Ω, ADC Input
RL = 8Ω, I2S Input
30169224
30169226
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THD+N vs FREQUENCY
VDD = 5V, POUT = 950mW,
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 750mW,
RL = 8Ω, I2S Input
RL = 4Ω, I2S Input
30169227
30169283
30169285
30169282
THD+N vs FREQUENCY
VDD = 5V, POUT = 1.65W,
THD+N vs FREQUENCY
VDD = 3.6V, POUT = 850mW,
RL = 4Ω, I2S Input
RL = 4Ω, I2S Input
30169284
THD+N vs FREQUENCY
VDD = 5V, POUT = 1.8W,
THD+N vs OUTPUT POWER
RL = 8Ω, f = 1kHz, ADC Input
RL = 4Ω, I2S Input
30169210
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THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, ADC Input, Single channel
THD+N vs OUTPUT POWER
RL = 8Ω, f = 1kHz, ADC Input
30169211
30169212
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, ADC Input, All channels
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, ADC Input, Parallel mode
30169213
30169214
THD+N vs OUTPUT POWER
RL = 8Ω, f = 1kHz, I2S Input, Single mode
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, I2S Input, Single channel
30169215
30169216
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THD+N vs OUTPUT POWER
RL = 8Ω, f = 1kHz, I2S Input, All channels
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, I2S Input, All channels
30169217
30169218
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, I2S Input, All channels
THD+N vs OUTPUT POWER
RL = 4Ω, f = 1kHz, I2S Input, Parallel mode
30169218
30169219
EFFICIENCY vs OUTPUT POWER
RL = 8Ω, f = 1kHz, ADC Input, All channels
EFFICIENCY vs OUTPUT POWER
RL = 4Ω, f = 1kHz, ADC Input, All channels
30169286
30169287
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POWER DISSIPATION vs OUTPUT POWER
POWER DISSIPATION vs OUTPUT POWER
RL = 8Ω, f = 1kHz, ADC Input
RL = 4Ω, f = 1kHz, ADC Input
30169288
30169289
OUTPUT POWER vs SUPPLY VOLTAGE
RL = 4Ω, f = 1kHz, ADC Input, Single mode
OUTPUT POWER vs SUPPLY VOLTAGE
RL = 4Ω, f = 1kHz, ADC Input, Parallel mode
30169290
30169291
OUTPUT POWER vs SUPPLY VOLTAGE
RL = 8Ω, f = 1kHz, ADC Input, Single channel
PSRR vs FREQUENCY
PVDD = 5V, VRIPPLE = 200mVP-P, RL = 8Ω,
ADC Mode, ADC input = AC GND
30169292
301692a8
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PSRR vs FREQUENCY
PSRR vs FREQUENCY
PVDD = 5V, VRIPPLE = 200mVP-P, RL = 8Ω,
I2S mode, I2S input = –120dBFS
DVDD = 1.8V, VRIPPLE = 200mVP-P, RL = 8Ω,
ADC Mode, ADC input = AC GND
301692a9
301692b0
PSRR vs FREQUENCY
DVDD = 1.8V, VRIPPLE = 200mVP-P, RL = 8Ω,
I2S mode, I2S input = –120dBFS
PSRR vs FREQUENCY
VRIPPLE = 200mVP-P, RL = 8Ω,
ADC mode
301692b1
30169297
SUPPLY CURRENT vs SUPPLY VOLTAGE (PVDD
RL = Open, ADC mode,
)
SUPPLY CURRENT vs SUPPLY VOLTAGE (AVDD
RL = Open
)
All channels enabled
30169299
30169298
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SUPPLY CURRENT vs SUPPLY VOLTAGE (PLVDD
ADC mode, All channels enabled
)
SUPPLY CURRENT vs SUPPLY VOLTAGE (DVDD
RL = Open
)
301692a0
301692a1
SHUTDOWN CURRENT vs SUPPLY VOLTAGE
SHUTDOWN CURRENT vs SUPPLY VOLTAGE (DVDD)
301692a2
301692a3
OUTPUT NOISE VS FREQUENCY
PVDD = 5V, RL = 8Ω,
ADC mode, ADC Input = AC GND
OUTPUT NOISE VS FREQUENCY
DVDD = 1.8V, RL = 8Ω,
I2S mode, I2S Input = –120dBFS
301692b7
301692b8
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as the I2C master, generating the SCL signal. Each transmis-
sion sequence is framed by a START condition and a STOP
condition Figure 4.
Application Information
I2C COMPATIBLE INTERFACE
Due to the number of data registers, the LM48901 employs a
page mode scheme. Each data write consists of 7, 8 bit data
bytes, device address (1 byte), 16 bit register address (2
bytes), and 32 bit register data (4 bytes). Each byte is followed
by an acknowledge pulse Figure 5. Single byte read and write
commands are ignored. The LM48901 device address is
0110000X.
The LM48901 is controlled through an I2C compatible serial
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock and data lines are bi-directional (open
drain). The LM48901 can communicate at clock rates up to
400kHz. Figure 3 shows the I2C interface timing diagram. Da-
ta on the SDA line must be stable during the HIGH period of
SCL. The LM48901 is a transmit/receive device, and can act
30169240
FIGURE 3. I2C Timing Diagram
30169241
FIGURE 4. Start and Stop Diagram
17
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WRITE SEQUENCE
Once the master device registers the ACK bit, the first 8-bit
register address word is sent, MSB first [15:8]. Each data bit
should be stable while SCL is HIGH. After the first 8-bit reg-
ister address is sent, the LM48901 sends another ACK bit.
Upon receipt of acknowledge, the second 8-bit register ad-
dress word is sent [7:0], followed by another ACK bit. The
register data is sent, 8-bits at a time, MSB first in the following
order [7:0], [15:8], [23:16], [31:24]. Each 8-bit word is followed
by an ACK, upon receipt of which the successive 8-bit word
is sent. Following the acknowledgement of the last register
data word [31:24], the master issues a STOP bit, allowing
SDA to go high while SDA is high.
The example write sequence is shown in Figure 5. The
START signal, the transition of SDA from HIGH to LOW while
SDA is HIGH, is generated, altering all devices on the bus that
a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant
bit (MSB) first, followed by the R/W bit (R/W = 0 indicating the
master is writing to the LM48901). The data is latched in on
the rising edge of the clock. Each address bit must be stable
while SDA is HIGH. After the R/W\ bit is transmitted, the mas-
ter device releases SDA, during which time, an acknowledge
clock pulse is generated by the slave device. If the LM48901
receives the correct address, the device pulls the SDA line
low, generating and acknowledge bit (ACK).
30169205
FIGURE 5. Example I2C Write Sequence
READ SEQUENCE
LM48901. Upon receipt of the acknowledge, the second 8-bit
register address word is sent [7:0], followed by another ACK
bit. Following the acknowledgement of the last register ad-
dress, the master initiates a REPEATED START, followed by
the 7-bit device address, followed by R/W = 1 (R/W = 1 indi-
cating the master wants to read data from the LM48901). The
LM48901 sends an ACK, followed by the selected register
data. The register data is sent, 8-bits at a time, MSB first in
the following order [7:0], [15:8], [23:16], [31:24]. Each 8-bit
word is followed by an ACK, upon receipt of which the suc-
cessive 8-bit word is sent. Following the acknowledgement of
the last register data word [31:24], the master issues a STOP
bit, allowing SDA to go high while SDA is high.
The example read sequence is shown in Figure 6. The
START signal, the transition of SDA from HIGH to LOW while
SDA is HIGH, is generated, altering all devices on the bus that
a device address is being written to the bus.
The 7-bit device address is written to the bus, followed by the
R/W = 0. After the R/W bit is transmitted, the master device
releases SDA, during which time, an acknowledge clock
pulse is generated by the slave device. If the LM48901 re-
ceives the correct address, the device pulls the SDA line low,
generating and acknowledge bit (ACK). Once the master de-
vice registers the ACK bit, the first 8-bit register address word
is sent, MSB first [15:8], followed by and ACK from the
30169206
FIGURE 6. Example I2C Read Sequence
www.ti.com
18
I2S DATA FORMAT
Mode, the audio data format is similar to the Normal Mode,
without the delay between the LSB and the change in
I2S_WS. In Right Justified Mode, the audio data MSB is trans-
mitted after a delay of a preset number of bits.
The LM48901 supports three I2S formats: Normal Mode Fig-
ure 7, Left Justified Mode Figure 8, and Right Justified Mode
Figure 9. In Normal Mode, the audio data is transmitted MSB
first, with the unused bits following the LSB. In Left Justified
301692b4
FIGURE 7. I2S Normal Input Format
301692b5
FIGURE 8. I2S Left Justified Input Format
301692b6
FIGURE 9. I2S Right Justified Input Format
19
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MEMORY ORGANIZATION
configuration settings, and a 48-bit wide Audio Sample Space
that holds the current audio data sampled from either the AD-
Cs or the I2S interface, organized as shown in Figure 10.
The LM48901 memory is organized into three main regions:
a 32-bit wide Coefficient Space that holds the spatial coeffi-
cients, a 32-bit wide Register Space that holds the device
30169207
FIGURE 10. LM48901 Memory Organization
COEFFICIENT MEMORY
Register 1 (0x504h) = 1 to enable Debug mode. The Coeffi-
cient Memory Space is organized as follows.
The device must be in Debug mode in order to write to the
Coefficient memory. Set Bit 7 (DBG_ENABLE) in Filter Debug
TABLE 2. Coefficient Memory Space
REGISTER ADDRESS
(31:16)
REGISTER CONTENTS
(15:0)
256x16 bit Array Taps
0x000h - 0x0FFh
256x16 bit Array Taps
(Left Input to OUT4)
256x16 bit Array Taps
(Left Input to OUT3)
256x16 bit Array Taps
(Left Input to OUT2)
256x16 bit Array Taps
(Left Input to OUT1)
C0 128x16 bit Prefilter FIR Taps
(Left to Left)
(Right Input to OUT4)
256x16 bit Array Taps
0x100h - 0x1FFh
(Right Input to OUT3)
256x16 bit Array Taps
0x200h - 0x2FFh
(Right Input to OUT2)
256x16 bit Array Taps
0x300h - 0x3FFh
(Right Input to OUT1)
C2 128x16 bit Prefilter Taps
0x400h - 0x47Eh (EVEN)
(Right to Right)
C3 128x16 bit Prefilter Taps
0x441h - 0x47Fh (ODD)
C1 128x16 bit Prefilter FIR Taps
(Left to Right)
(Right to Left)
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20
CONTROL REGISTERS
TABLE 3. Register Map
Register
Name
Register
Address
Default
Value
7
6
5
4
3
2
1
0
0x500h
[7:0]
0xFFh
ARRAY_TAP
PRE_TAP
CH2_SEL
0x500h
[15:8]
0xFFh UNUSED
FILTER
CONTROL
0x500h
[23:16]
0xE4h
0x31h
0x00h
CH4_SEL
CH3_SEL
ARRAY_ PRE_
CH1_SEL
ARRAY_
PRE_
0x500h
[31:24]
UNUSED
COMP_TH
UNUSED COMP_RATIO
ENABLE ENABLE BYPASS BYPASS
0x501h
[7:0]
G1_GAIN
0x501h
[15:8]
0x00h UNUSED
0x00h
POST_GAIN
FILTER
COMP1
0x501h
[23:16]
ARRAY_COMP_SELECT
UNUSED
0x501h
[31:24]
0x00h
0x502h
[7:0]
G1_GAIN
G1_GAIN
COMP_TH
COMP_RATIO
COMP_TH
COMP_RATIO
0x00h
0x502h
[15:8]
0x00h UNUSED
POST_GAIN
UNUSED
FILTER
COMP2
0x502h
[23:16]
0x00h
0x502h
[31:24]
0x00h UNUSED
0xFFh
POST_GAIN
UNUSED
DBG_DATA [7:0]
DBG_DATA [15:8]
DBG_DATA [23:16]
UNUSED
0x503h
[7:0]
0x503h
[15:8]
0xFFh
FILTER
DEBUG0
0x503h
[23:16]
0xFFh
DBG_
0xFFh
0x503h
[31:24]
STEP
DBG_
0xFFh
STEP_
FILTER_
SELECT
0x504h
[7:0]
UNUSE
D
ACC_ADDR
ENABLE ENABLE
0x504h
[15:8]
0xFFh
0xFFh
0xFFh
0x00h
0x80h
0x00h
0x80h
UNUSED
UNUSED
UNUSED
FILTER
DEBUG1
0x504h
[23:16]
0x504h
[31:24]
0x505h
[7:0]
COUNT1_MODE
UNUSED
CH_SEL
COUNT2_MODE
CH_SEL
0x505h
[15:8]
CLEAR
FILTER
STATS
0x505h
[23:16]
COUNT1_MODE
UNUSED
0x505h
[31:24]
CLEAR
COUNT2_MODE
21
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Register
Name
Register
Address
Default
Value
7
6
5
4
3
2
1
0
0x508h
[7:0]
0x7Fh
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
TAP_LENGTH
UNUSED
0x508h
[15:8]
FILTER TAP
(READ-
0x508h
[23:16]
ONLY)
UNUSED
0x508h
[31:24]
UNUSED
0x509h
[7:0]
DBG_ACCL [7:0]
DBG_ACCL [15:8]
DBG_ACCL [23:16]
DBG_ACCL [31:24]
DBG_ACCH
0x509h
[15:8]
ACCUML
DEBUG
(READ-
ONLY)
0x509h
[23:16]
0x509h
[31:24]
0x50Ah
[7:0]
0x50Ah
[15:8]
ACCUMH
DEBUG
(READ-
ONLY)
BDG_ACCH
0x50Ah
[23:16]
UNUSED
0x50Ah
[31:24]
UNUSED
0x50Bh
[7:0]
DBG_SAT [7:0]
DBG_SAT [15:8]
DBG_SAT [23:16]
UNUSED
0x50Bh
[15:8]
DBG SAT
(READ-
ONLY)
0x50Bh
[23:16]
0x50Bh
[31:24]
0x50Ch
[7:0]
COUNT [7:0]
COUNT [15:8]
COUNT [23:16]
COUNT [30:24]
COUNT [7:0]
COUNT [15:8]
COUNT [23:16]
COUNT [30:24]
0x50Ch
[15:8]
STAT
PCNT1
(READ-
ONLY)
0x50Ch
[23:16]
0x50Ch
[31:24]
OVF
0x50Dh
[7:0]
0x50Dh
[15:8]
STAT
PCNT2
(READ-
ONLY)
0x50Dh
[23:16]
0x50Dh
[31:24]
OVF
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22
Register
Name
Register
Address
Default
Value
7
6
5
4
3
2
1
0
0x50Eh
[7:0]
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
COUNT [7:0]
COUNT [15:8]
COUNT [23:16]
0x50Eh
[15:8]
STAT
ACNT1
(READ-
ONLY)
0x50Eh
[23:16]
0x50Eh
[31:24]
OVF
COUNT [30:24]
0x50Fh
[7:0]
COUNT [7:0]
COUNT [15:8]
COUNT [23:16]
0x50Fh
[15:8]
STAT
ACNT2
(READ-
ONLY)
0x50Fh
[23:16]
0x50Fh
[31:24]
OVF
COUNT [30:24]
CONFIG
_CLK_
0x530h
[7:0]
0x30h
DEVICE_ID
ENABLE
ALTID_
ENABLE
CL_
0x530h
[15:8]
SYS
CONFIG
0x00h
0x8Ch
0x00h
0x00h
0x10h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
ALT_DEVICE_ID
CL_PAGE
0x530h
[23:16]
UNUSED
CL_W
CL_REQ
ENABLE
MBIST1_ MBIST0_
ENABLE ENABLE
0x530h
[31:24]
UNUSED
0x531h
[7:0]
TRANS_LENGTH [7:0]
TRANS_LENGTH [15:8]
REG_START_ADDR [7:0]
REG_START_ADDR [16:8]
E2_START_ADDR [7:0]
E2_START_ADDR [15:8]
UNUSED
0x531h
[15:8]
CL REG0
0x531h
[23:16]
0x531h
[31:24]
0x532h
[7:0]
0x532h
[15:8]
CL REG1
0x532h
[23:16]
0x532h
[31:24]
UNUSED
0x533h
[7:0]
UNUSED
E2_OFFSET
0x533h
[15:8]
UNUSED
UNUSED
UNUSED
E2_
OFFSET
0x533h
[23:16]
0x533h
[31:24]
23
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Register
Name
Register
Address
Default
Value
7
6
5
4
3
2
1
0
I2C
0x534h
[7:0]
0x00h
0x00h
0x00h
0x00h
0x7Fh
0x80h
0x00h
0x80h
UNUSED
E2NXT_OFFSET
UNUSED
_EnXT
0x534h
[15:8]
I2C_EnXT
0x534h
[23:16]
UNUSED
UNUSED
0x534h
[31:24]
0x538h
[7:0]
UNUSED
MBIST_EN
MBIST_GO
MBIST_DONE
0x538h
[15:8]
MBIST
STAT
(READ-
ONLY)
UNUSED
UNUSED
UNUSED
0x538h
[23:16]
0x538h
[31:24]
0x520h
[7:0]
POWER_UP_DELAY [7:0]
POWER_UP_DELAY [15:8]
DEGLITCH_DELAY
0x06h
0x00h
0x20h
0x520h
[15:8]
DELAY
0x520h
[23:16]
0x520h
[31:24]
STATE_DELAY
0x09h
0x00h
VREF_
DELAY
0x521h
[7:0]
UNUSED
PULSE
FORCE ENABLE
QSA_
CLK_
STOP
PCM_
0x521h
[15:8]
0x00h UNUSED
HIFI
I2S_CLK
MCLK_RATE
ENABLE &
CLOCKS
CLK_SEL
ADC_
SYNC
0x521h
[23:16]
0x00h
0x00h
UNUSED
UNUSED
0x521h
[31:24]
ZERO_
0x33h
0x522h
[7:0]
MUTE
ADC_LVL
CROSS
0x522h
[15:8]
I2S_LVL
0x33h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
UNUSED
DIGITAL
MIXER
0x522h
[23:16]
ADC_DS
P
I2SB_ON I2SA_ON
OUT4_SEL
I2SB_TX_SEL
OUT3_SEL
I2SA_TX_SEL
OUT2_SEL
I2S_DSP
0x522h
[31:24]
OUT1_SEL
ANA_LVL
ZERO_
0x523h
[7:0]
BYPASS
_MOD
AUTO
_SD
ADC
TRIM
ZERO
_DIG
PARALLEL
TSD_DIS
ANA
PMC_
TEST
0x523h
[15:8]
SCKT
_DIS
UNUSED
SE_MOD
TST_SHT
ANALOG
0x523h
[23:16]
UNUSED
UNUSED
0x523h
[31:24]
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24
Register
Name
Register
Address
Default
Value
7
6
5
4
3
2
1
0
STEREO_
SYNC_
SYNC_
MODE
CLOCK_
PHASE
TX_
RX_
0x524h
[7:0]
SYNC
_MS
0x01h
CLK_MS
STEREO
PHASE
ENABLE ENABLE
0x524h
[15:8]
0x00h
0x00h
0x00h
0x00h
UNUSED
HALF_CYCLE_DIVIDER
SYNTH_
0x524h
[23:14]
UNUSED
SYNTH_NUM
DENOM
0x524h
[31:24]
UNUSED
TX_BIT
MONO_SYNC_WIDTH
TX_WIDTH
SYNC_RATE
RX_WIDTH
I2S PORT
0x525h
[7:0]
RX_
RX_
0x525h
[15:8]
RX
_MODE
0x02h
0x02h
RX_MSB_POSITION
A/µLAW COMPAN
D
TX_
TX_
0x525h
[23:16]
TX
_MODE
TX_MSB_POSITION
A/µLAW COMPAN
D
0x525h
[31:24]
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
UNUSED
0x526h
[7:0]
ADC_COMP_COEFF_C0 [7:0]
ADC_COMP_COEFF_C0 [15:8]
ADC_COMP_COEFF_C1 [7:0]
ADC_COMP_COEFF_C1 [15:8]
ADC_COMP_COEFF_C2 [7:0]
ADC_COMP_COEFF_C2 [15:8]
0x526h
[15:8]
0x526h
[23:14]
ADC TRIM
CO-EF
FICIENT
0x526h
[31:24]
0x527h
[7:0]
0x527h
[15:8]
I2SL
_LVL
CLIP
I2SR
_LVL
CLIP
ADCL
_LVL
CLIP
ADCR
_LVL
CLIP
ADCL_
CLIP
ADCR_
CLIP
0x528h
[7:0]
0x00h
UNUSED
UNUSED
0x528h
[15:8]
READBACK
(READ-
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
0x00h
THERMAL SHORT4 SHORT3 SHORT2 SHORT1
ONLY)
0x528h
[23:14]
SPARE
UNUSED
CE_STATE
SPARE
0x528h
[31:24]
0x529h
[7:0]
UNUSED
0x529h
[15:8]
READBACK
(READ-
0x529h
[23:14]
ONLY)
UNUSED
UNUSED
0x529h
[31:24]
FILTER CONTROL REGISTER (0x500h)
Configures the LM48901 Array and Pre-Array filters (Spatial Engine). The Filter Control Register sets the length of the Array and
Pre-Array filter taps, and selects the filter channel source for each audio output. Set PRE_BYPASS and ARRAY_BYPASS to 1 to
bypass the Spatial Engine, disabling the spatial effect without modifying the coefficients. Set PRE_ENABLE and ARRAY_ENABLE
25
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to 1 to enable the Spatial Engine. Set PRE_ENABLE and ARRAY_ENABLE to 0 to disable the spatial engine. Disabling the Spatial
Engine does not affect the register contents. Disable the Spatial Engine during coefficient programming.
TABLE 4. Filter Control Register
BIT
NAME
VALUE
DESCRIPTION
Array Filter Tap Length
7:0
ARRAY_TAP
Pre-filter Tap Length. Pre-filter tap length should be
less than or equal to the Array filter tap length
14:8
15
PRE_TAP
UNUSED
Channel 1 Output Routing Selection
Array Filter Channel 0 Output Select
Array Filter Channel 1 Output Select
Array Filter Channel 2 Output Select
Array Filter Channel 3 Output Select
Channel 2 Output Routing Selection
Array Filter Channel 0 Output Select
Array Filter Channel 1 Output Select
Array Filter Channel 2 Output Select
Array Filter Channel 3 Output Select
Channel 3 Output Routing Selection
Array Filter Channel 0 Output Select
Array Filter Channel 1 Output Select
Array Filter Channel 2 Output Select
Array Filter Channel 3 Output Select
Channel 4 Output Routing Selection
Array Filter Channel 0 Output Select
Array Filter Channel 1 Output Select
Array Filter Channel 2 Output Select
Array Filter Channel 3 Output Select
00
01
10
11
17:16
19:18
21:20
23:22
CH1_SEL
CH2_SEL
CH3_SEL
CH4_SEL
00
01
10
11
00
01
10
11
00
01
10
11
27:24
28
UNUSED
0
1
0
1
Pre-Array filter not bypassed
Pre-Array filter bypassed
Array filter not bypassed
Array filter bypassed
PRE_BYPASS
29
ARRAY_BYPASS
Pre-Array filter disabled. Disable the Pre-Array Filter
during filter and coefficient programming. Disabling
the Pre-Array Filter does not affect the device memory
contents.
0
30
PRE_ENABLE
1
0
1
Pre-Array filter enabled
Array filter disabled. Disable the Array Filter during
filter and coefficient programming. Disabling the Array
Filter does not affect the device memory contents.
31
ARRAY_ENABLE
Array filter enabled
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26
COMPRESSOR CONTROL REGISTER 1 (FILTER COMP1) (0x501h)
TABLE 5. Compressor Control Register
BIT
NAME
VALUE
DESCRIPTION
Pre-Filter Compressor Threshold
00000
00001
00010
-
0
0.3125
0.0625
-
4:0
COMP_TH
10000
-
0.5
-
11000
-
0.75
-
11111
0.96875
Pre-Compression Gain (V/V)
000
001
010
011
100
101
110
111
2
4
8
7:5
G1_GAIN
16
32
64
128
256
Compression Ratio
000
001
010
011
100
101
110
111
1:1
2:1
2.66:1
4:1
10:8
11
COMP_RATIO
UNUSED
5.33:1
8:1
10.66:1
16:1
Post Compression Gain (V/V)
000
001
010
011
100
101
110
111
1
1.25
1.5
2
14:12
POST_GAIN
UNUSED
2.5
3
4
8
15
27
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BIT
NAME
ARRAY_COMP_SELECT
UNUSED
VALUE
DESCRIPTION
Array Filter Compression Control Register Select. The
Array Filter has four channels, each channel can
choose one of two Array Filter Compression Threshold,
Pre-Compression Gain, Compression Ratio, and Post
Compression Gain settings from the FILTER_COMP2
register Table 4.
23:16
0000
-
Select Setting 0
-
1111
Select Setting 1
31:24
COMPRESSOR CONTROL REGISTER 2 (FILTER COMP2) (0x502h)
TABLE 6. Compressor Control Register 2
BIT
NAME
VALUE
DESCRIPTION
Array Filter Compressor Threshold (Setting 0)
00000
00001
00010
-
0
0.03125
0.0325
-
4:0
COMP_TH
10000
-
0.5
-
11000
-
0.75
-
11111
0.96875
Pre-Compression Gain (V/V) (Setting 0)
000
001
010
011
100
101
110
111
2
4
8
7:5
G1_GAIN
16
32
64
128
256
Compression Ratio (Setting 0)
000
001
010
011
100
101
110
111
1:1
2:1
2.66:1
4:1
10:8
11
COMP_RATIO
UNUSED
5.33:1
8:1
10.66:1
16:1
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28
BIT
14:12
15
NAME
POST_GAIN
UNUSED
VALUE
DESCRIPTION
Post Compression Gain (V/V) (Setting 0)
000
001
010
011
100
101
110
111
1
1.25
1.5
2
2.5
3
4
8
Pre-Filter Compressor Threshold (Setting 1)
00000
00001
00010
-
0
0.03125
0.0325
-
20:16
COMP_TH
10000
-
0.5
-
11000
-
0.75
-
11111
0.96875
Pre-Compression Gain (V/V) (Setting 1)
000
001
010
011
100
101
110
111
2
4
8
23:21
G1_GAIN
16
32
64
128
256
Compression Ratio (Setting 1)
000
001
010
011
100
101
110
111
1:1
2:1
2.66:1
4:1
24:26
COMP_RATIO
UNUSED
5.33:1
8:1
10.66:1
16:1
27
Post Compression Gain (V/V) (Setting 1)
000
001
010
011
100
101
110
111
1
1.25
1.5
2
30:28
POST_GAIN
UNUSED
2.5
3
4
8
31
29
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FILTER DEBUG REGISTER 1 (FILT_DBG1) (0x504h)
TABLE 7. Filter Debug Register 1
BIT
NAME
VALUE
DESCRIPTION
Accumulator Address. Selects which accumulator is
read during debug mode
3:0
ACC_ADDR
0
1
Selects Pre-Filter Accumulators
Selects Array Filter Accumulators
4
5
6
FILTER_SELECT
UNUSED
0
1
Single Step Disabled
Single Step Enabled
STEP_ENABLE
Debug Mode Disabled. Coefficient memory is
inaccessible with Debug mode is disabled.
0
1
7
DBG_ENABLE
UNUSED
Debug Mode Enabled. Coefficient memory is
accessible when Debug mode is enabled.
31:8
FILTER STATISTICS CONTROL REGISTER (FILT_STC) (0x505h)
TABLE 8. Filter Statistics Control Register
BIT
NAME
VALUE
DESCRIPTION
PRE-FILTER Counter
Channel Select
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
000
001
010
011
100
101
110
111
3:0
CH_SEL
Counter 1 Mode Select. Specifies input of Counter 1
Sample Count Mode. Every audio sample is counted
Overflow. Overflow events counted
0000
0001
Frequency Error. Indicates input frequency not
sufficient for given filter length
0010
1000
1001
1010
1011
1100
1101
1110
1111
MAGN[7}
MAGN[7:6]
MAGN[7:5}
MAGN[7:4}
MAGN[7:3}
MAGN[7:2]
MAGN[7:1}
MAGN[7:0]
7:4
COUNT1_MODE
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30
BIT
NAME
VALUE
DESCRIPTION
Counter 2 Mode Select. Specifies input of Counter 2
Sample Count Mode. Every audio sample is counted
Overflow. Overflow events counted
0000
0001
Frequency Error. Indicates input frequency not
sufficient for given filter length
0010
1000
1001
1010
1011
1100
1101
1110
1111
MAGN[7}
MAGN[7:6]
MAGN[7:5}
MAGN[7:4}
MAGN[7:3}
MAGN[7:2]
MAGN[7:1}
MAGN[7:0]
11:8
COUNT2_MODE
14:12
UNUSED
CLEAR
0
1
Counter Enabled
Counter Cleared
15
ARRAY-FILTER Counter
Channel Select
000
001
010
011
100
101
110
111
Channel 0
Channel 1
Channel 2
19:16
CH_SEL
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Counter 1 Mode Select. Specifies input of Counter 1
Sample Count Mode. Every audio sample is counted
Overflow. Overflow events counted
0000
0001
Frequency Error. Indicates input frequency not
sufficient for given filter length
0010
1000
1001
1010
1011
1100
1101
1110
1111
MAGN[7}
MAGN[7:6]
MAGN[7:5}
MAGN[7:4}
MAGN[7:3}
MAGN[7:2]
MAGN[7:1}
MAGN[7:0]
23:20
COUNT1_MODE
31
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BIT
NAME
VALUE
DESCRIPTION
Counter 2 Mode Select. Specifies input of Counter 2
Sample Count Mode. Every audio sample is counted
Overflow. Overflow events counted
0000
0001
Frequency Error. Indicates input frequency not
sufficient for given filter length
0010
1000
1001
1010
1011
1100
1101
1110
1111
MAGN[7}
MAGN[7:6]
MAGN[7:5}
MAGN[7:4}
MAGN[7:3}
MAGN[7:2]
MAGN[7:1}
MAGN[7:0]
27:24
COUNT2_MODE
30:28
31
UNUSED
CLEAR
0
1
Counter Enabled
Counter Cleared
DELAY REGISTER (DELAY) (0x520h)
TABLE 9. Delay Register
VALUE
BIT
15:0
NAME
DESCRIPTION
POWER_UP_DELAY
DEGLITCH_DELAY
STATE_DELAY
Sets I2C Delay Time. Default 10ms delay.
23:16
31:24
Sets ENABLE Bit Polling Timeout. Default 32ms delay
Sets Delay Between Power Up/Down States
ENABLE AND CLOCK CONFIGURATION REGISTER (ENABLE & CLOCKS) (0x521h)
TABLE 10. Enable and Clock Configuration Register
BIT
NAME
VALUE
DESCRIPTION
Device Disabled in I2C Mode
0
1
0
1
0
1
0
ENABLE
Device Enabled in I2C Mode
Device Enabled Via SHDN <<overbar>> Pin
Device Enabled Via I2C
1
2
FORCE
PULSE
SHDN<<overbar>> Requires a Stable Logic Level
SHDN<<overbar>> Accepts a Pulse Input
Device waits for delay time determined by
STATE_DELAY to enable.
0
1
3
RELY_ON_VREF
UNUSED
Device waits for stable VREF
7:4
Selects PLL Input Divider
32fs (1.536MHz)
64fs (3.072MHz)
128fs (6.114MHz)
256fs (12.288MHz)
512fs (24.576MHz)
UNUSED
000
001
010
011
100
101
110
111
0
10:8
MCLK_RATE
UNUSED
UNUSED
MCLK Input to PLL
I2S_CLK Input to PLL
11
I2S_CLK
1
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32
BIT
NAME
VALUE
DESCRIPTION
0
Oscillator Clock Input to Power Management Circuitry
External Clock to Power Management Circuitry. Power
management circuit uses MCLK or I2S_CLK. Clock
source depends on the state of I2S_CLK. External
Clock mode disables the internal oscillator.
12
PMC_CLK_SEL
1
0
1
HiFi Mode Disabled
13
HIFI
HiFi Mode Enabled. PLL always produces a 4096fs
clock.
0
1
QSA Clock Enabled
14
15
QSA_CLK_STOP
UNUSED
QSA Clock Disabled Following Device Configuration
0
1
Normal Operation
16
ADC_SYNC_SEL
UNUSED
Reverse ADC SYNC Signal for additional timing margin
at low supply voltages.
31:17
DIGITAL MIXER CONTROL REGISTER (DIGITAL MIXER) (0x522h)
TABLE 11. Digital Mixer Control Register
BIT
NAME
VALUE
DESCRIPTION
Sets the Gain of the ADC Path (dB)
000000
-76.5
000001
-75
-
1.5dB steps
5:0
ADC_LVL
110010
-1.5
110011
0
110100
1.5
-
1.5dB Steps
111111
18
0
1
0
1
Normal Operation
6
7
MUTE
Mute
Zero Crossing Detection Enabled
ZXD_DISABLE
Zero Crossing Detection Disabled
Sets the Gain of the I2S Path (dB)
000000
000001
-
-76.5
-75
1.5dB steps
I2S_LVL
13:8
110010
110011
110100
-
-1.5
0 (VOUT = 3.36VRMS with 0dBFS input)
1.5
1.5dB Steps
18
111111
15:14
16
UNUSED
I2S_DSP
I2S Data Not Passed to DSP
I2S Data Passed to DSP
0
1
0
1
ADC Output Not Passed to DSP
ADC Output Passed to DSP
17
ADC_DSP
33
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BIT
NAME
VALUE
DESCRIPTION
Selects Input of Primary I2S Transmitter
00
01
10
11
None
19:18
ISA_TX_SEL
ADC
DSP1/2
DSP3/4
Selects Input of Secondary I2S Transmitter
00
01
10
11
0
None
21:20
ISB_TX_SEL
ADC
DSP1/2
DSP3/4
I2SA Data NOT Output on SHDN
I2SA_ON
I2SB_ON
22
23
I2SA Data Output on SHDN
1
I2SB Data NOT Output on SHDN
0
I2SB Data Output on SHDN
1
Selects OUT1 Amplifier Input Source
00
01
10
11
OUT1 Disabled
25:24
27:26
29:28
31:30
OUT1_SEL
OUT2_SEL
OUT3_SEL
OUT4_SEL
DSP
I2S
ADC
Selects OUT2 Amplifier Input Source
00
01
10
11
OUT2 Disabled
DSP
I2S
ADC
Selects OUT3 Amplifier Input Source
00
01
10
11
OUT3 Disabled
DSP
I2S
ADC
Selects OUT4 Amplifier Input Source
00
01
10
11
OUT4 Disabled
DSP
I2S
ADC
ANALOG CONFIGURATION REGISTER (ANALOG) (0x523h)
TABLE 12. Analog Configuration Register
BIT
NAME
VALUE
DESCRIPTION
Sets ADC Preamplifier Gain (dB)
00
01
10
11
0
1:0
ANA_LVL
2.4
3.5
6
Normal Operation. OUT2 and OUT3 operate as
separate amplifiers.
0
1
2
PARALLEL
Parallel Operation. OUT2 and OUT3 operate in parallel
as a single amplifier.
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34
BIT
NAME
VALUE
DESCRIPTION
0
Normal Operation
3
ZERO_ANA
Auto-Shutdown Mode. Automatically disables the
amplifiers when no analog input is detected.
1
0
1
0
1
Normal Operation
4
ZERO_DIG
Auto-Shutdown Mode. Automatically disables the
amplifiers when there is no I2S input.
ADC Trim Disabled
5
6
ADCTRIM
AUTO_SD
ADC Trim Enabled. Use ADC_COMP_COEFF_C0-C2
to trim ADC.
0
1
0
Normal Operation
Fault Conditions Disable the Amplifiers
Normal Operation
Pulse Correction Bypass. Amplifier output stages act as
a buffer, passing PWM signal without correction to
output.
7
8
BYPASS_MOD
TST_SHT
1
0
1
Normal Operation
Short Amplifier Inputs. Sets amplifier outputs to 50%
duty cycle, minimizing click and pop during power up/
down.
0
1
0
1
0
1
0
1
Normal Operation
9
SCKT_DIS
TSD_DIS
Output Short Circuit Protection Disabled
Normal Operation
10
11
Thermal Shutdown Disabled
Normal Operation
PMC_TEST
PMC uses PLL Source Clock
Normal Operation
12
SE_MOD
UNUSED
Single Edge Modulation Mode
31:13
I2S PORT CONFIGURATION REGISTER (I2S PORT) (0x524h/0x525h)
TABLE 13.
BIT
NAME
VALUE
0x524h
DESCRIPTION
0
1
0
1
0
1
Mono Mode
0
1
2
STEREO
Stereo Mode
Receive Mode Disabled
Receive Mode Enabled
Transmit Mode Disabled
Transmit Mode Enabled
RX_ENABLE
TX_ENABLE
I2S Clock Slave. Device requires an external SCLK for
proper operation.
0
1
0
1
0
1
3
4
5
CLK_MS
SYNC_MS
I2S Clock Master. Device generates SCLK and transmits
when either RX or TX mode are enabled.
I2S WS Slave. Device requires an external WS for proper
operation.
I2S WS Master. Device generates WS and transmits
when either RX or TX mode are enabled.
I2S Clock Phase. Transmit on falling edge, receive on
rising edge.
CLOCK_PHASE
PCM Clock Phase. Transmit on rising edge, receive on
falling edge.
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BIT
NAME
VALUE
DESCRIPTION
I2S Data Format: Left, Right
0
STEREO_SYNC
_PHASE
6
1
Mono
0
I2S Data Format: Right, Left
Rising edge indicates start of data word.
SYNC low = Left, SYNC high = Right
SYNC low = Right, SYNC high = left
7
SYNC_MODE
1
Configures the I2S port master clock half-cycle divider.
Program the half-cycle divider by: (ReqDiv*2) 1
000000
000001
000010
000011
-
BYPASS
1
1.5
2
HALF_CYCLE
_DIVIDER
13:8
-
111101
111110
111111
31
31.5
32
15:14
18:16
UNUSED
Sets the Clock Generator Numberator
SYNTH_DENOM (1/)
000
001
010
011
100
101
110
111
0
100/SYNTH_DENOM
96/SYNTH_DENOM
SYNTH_NUM
80/SYNTH_DENOM
72/SYNTH_DENOM
64/SYNTH_DENOM
48/SYNTH_DENOM
0/SYNTH_DENOM
Clock Generator Denominator = 128
Clock Generator Denominator = 125
19
SYNTH_DENOM
UNUSED
1
23:20
Sets number of clock cycles before SYNC pattern
repeats.
MONO MODE
000
001
010
011
100
101
110
111
8
12
16
18
20
24
25
26:24
SYNC_RATE
32
STEREO MODE
000
01
16
24
32
36
40
48
50
64
010
011
100
101
110
111
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36
BIT
NAME
MONO_SYNC_WIDTH
UNUSED
VALUE
DESCRIPTION
Sets SYNC symbol width in Mono Mode
000
001
010
011
100
101
110
111
1
2
4
29:27
31:30
7
8
11
15
16
0x525h
Sets number of valid RECEIVE bits.
000
001
010
011
100
101
110
111
24
20
18
2:0
RX_WIDTH
16
14
13
12
8
Sets number of TRANSMIT bits.
000
001
010
011
100
101
110
111
24
20
18
5:3
TX_WIDTH
16
14
13
12
8
Sets number of pad bits after the valid Transmit bits.
00
01
10
11
0
0
7:6
8
TX_BIT
1
High-Z
High-Z
MSB Justified Receive Mode
LSB Justified Receive Mode
RX_MODE
1
37
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BIT
NAME
VALUE
DESCRIPTION
MSB location from the frame start (MSB Justified) or LSB
location from the frame end (LSB Justified)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0
0 (DSP/PCM LONG)
1 (I2S/PCM SHORT)
2
3
4
5
6
7
8
9
10
11
12
13
14
13:9
RX_MSB_POSITION
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Normal Operation
Audio Data Companded
µLaw Compand Mode
A-Law Compand Mode
MSB Justified Transmit Mode
LSB Justified Transmit Mode
14
15
16
RX_COMPAND
RX_A/µLAW
TX_MODE
1
0
1
0
1
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38
BIT
NAME
VALUE
DESCRIPTION
MSB location from the frame start (MSB Justified) or LSB
location from the frame end (LSB Justified)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0
0 (DSP/PCM LONG)
1 (I2S/PCM SHORT)
2
3
4
5
6
7
8
9
10
11
12
13
14
21:17
TX_MSB_POSITION
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Normal Operation
Audio Data Companded
µLaw Compand Mode
A-Law Compand Mode
22
TX_COMPAND
1
0
23
TX_A/µLAW
UNUSED
1
31:24
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ADC TRIM COEFFICIENT REGISTER (ADC_TRIM) (0x526h/0x527)
TABLE 14. ADC Trim Coefficient Register
VALUE
BIT
NAME
DESCRIPTION
0x526h
15:0
ADC_COMP_COEFF_C0
ADC_COMP_COEFF_C1
Sets ADC Trim Coefficient C0
Sets ADC Trim Coefficient C1
31:16
0x527h
15:0
ADC_COMP_COEFF_C2
Sets ADC Trim Coefficient C2
READBACK REGISTER (READBACK) (0x528h) READ-ONLY
TABLE 15. Readback Register
BIT
0
NAME
ADCR_CLIP
ADCL_CLIP
ADCR_LVLCLIP
ADCL_LVLCLIP
I2SR_LVLCLIP
I2SL_LVLCLIP
UNUSED
VALUE
DESCRIPTION
Right Channel ADC Input Clipped
Left Channel ADC Input Clipped
Right Channel ADC Output Clipped
Left Channel ADC Output Clipped
Right Channel I2S Output Clipped
Left Channel I2S Output Clipped
1
1
1
1
1
1
1
2
3
4
5
7:6
8
SHORT1
1
1
1
1
1
OUT1 Output Short Circuit
9
SHORT2
OUT2 Output Short Circuit
10
11
12
23:13
31:24
SHORT3
OUT3 Output Short Circuit
SHORT4
OUT4 Output Short Circuit
THERMAL
SPARE
Thermal Shutdown Threshold Exceeded
UNUSED
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40
SYSTEM CONFIGURATION REGISTER (SYS_CONFIG) (0x530h)
TABLE 16. System Configuration Register
BIT
NAME
VALUE
DESCRIPTION
6:0
DEVICE_ID
Sets LM48901 Device ID in slave mode
Configuration Loader Clock Disabled
Configuration Loader Clock Enabled
Sets Alternate Device ID in Slave Mode.
Selects DEVICE_ID
0
1
CONFIG_CLK
_ENABLE
7
14:8
15
ALT_DEVICE_ID
0
1
0
ALTID_ENABLE
Selects ALT_DEVICE_ID
Configuration Loader Access not Requested
16
17
CL_REQ
CL_W
Configuration Loader Access Requested. I2C Master
Transaction Enabled
1
0
1
Configuration Loader Set to READ-ONLY
Configuration Loader Set to WRITE
Sets I2C Page Mode Length
Single Byte
00
01
10
11
20:18
CL_PAGE
4 Bytes
8 Bytes
16 Bytes
22:21
23
UNUSED
CL_ENABLE
0
1
0
1
0
1
Device Configured as I2C Slave
Device Configured as I2C Master
Memory BIST Controller 0 Disabled
Memory BIST Control 0 Enabled.
Memory BIST Controller 1 Disabled
Memory BIST Control 1 Enabled.
24
MBIST0_ENABLE
25
MBIST1_ENABLE
UNUSED
31:26
I2C MASTER CONFIGURATION LOADER REGISTER 0 (CL_REG0) (0x531h)
TABLE 17. Filter Debug Register 0
BIT
15:0
NAME
VALUE
DESCRIPTION
Sets I2C Master Transaction Length
Starting Address of LM48901 Memory
TRANS_LENGTH
REG_START_ADDR
31:16
I2C MASTER CONFIGURATION LOADER REGISTER 1 (CL_REG1) (0x532h)
TABLE 18. Filter Debug Register 1
BIT
NAME
VALUE
DESCRIPTION
Sets EEPROM Address. Indicates EEPROM start
address where data is stored
15:0
E2_START_ADDR
UNUSED
31:16
EEPROM ADDRESS OFFSET REGISTER (E2_OFFSET) (0x533h)
TABLE 19. EEPROM Address Offset Register
VALUE
BIT
5:0
NAME
E2_OFFSET
UNUSED
DESCRIPTION
EEPROM Address Offset Value.
31:6
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I2C EnXT REGISTER (I2CEnXT) (0x534h)
TABLE 20. I2C EnXT Register
VALUE
BIT
5:0
6
NAME
E2NXT_OFFSET
UNUSED
DESCRIPTION
Sets EEPROM Address Offset for Following LM48901
when devices are Daisy Chained.
Next Device in Daisy Chain Disabled. I2C_EX driven
Low.
0
1
7
I2C_EnXT
UNUSED
Next Device in Daisy Chain Enabled. I2C_EX driven
HIGH.
31:8
READ-ONLY MBIST STATUS REGISTER (MBIST_STAT) (0x538h)
TABLE 21. MBIST Status Register
BIT
NAME
VALUE
DESCRIPTION
1:0
MBIST_DONE
Logic HIGH indicates memory test complete
Logic Low indicates memory fault when MBIST_DONE
is HIGH
3:2
BIST_GO
0
1
MBIST Read-back Disabled
MBIST Read-back Enabled
5:4
MBIST_EN
UNUSED
31:6
DAISY CHAINING
I2C_EN/I2C_EX
The LM48901 supports daisy chaining up to 127 devices from a single I2C bus utilizing I2C_EN and I2C_EX in a chain enable
scheme. I2C_EX is a push/pull logic output that drives the I2C_EN of the following device in the chain Figure 11. At power up,
I2C_EnXT (bit 8, I2C_EnXT Register [0x534h]) is set to 0, resulting in I2C_EN driven low, disabling the I2C interface of the following
device. Once device configuration is complete, and I2C_EnXT is set to 1, I2C_EN is driven high, enabling the I2C interface of the
following device. Driving I2C_EN high enables the device’s I2C interface, driving I2C_EN low disables the device’s I2C interface.
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42
30169208
FIGURE 11. I2C_EN/I2C_EX Daisy Chaining Example
Device Address
The 0110000X is the default LM48901 I2C address hard coded into the device. Two alternate device addresses can be pro-
grammed, via the SYS CONFIG (0x530h) Register. Use the default address during initial device configuration.
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GENERAL AMPLIFIER FUNCTION
Class D Amplifier
The LM48901 features four high-efficiency Class D audio power amplifiers that utilizes Texas Instruments’ filterless modulation
scheme external component count, conserving board space and reducing system cost. The Class D outputs transition from VDD
to GND with a 384kHz switching frequency. With no signal applied, the outputs switch with a 50% duty cycle, in phase, causing
the two outputs to cancel. This cancellation results in no net voltage across the speaker, thus there is no current to the load in the
idle state.
With the input signal applied, the duty cycle (pulse width) of the LM48901 outputs changes. For increasing output voltage, the duty
cycle of OUT_+ increases while the duty cycle of OUT_- decreases. For decreasing output voltages, the converse occurs. The
difference between the two pulse widths yield the differential output voltage.
Edge Rate Control (ERC)
The LM48901 features Texas Instruments’ advanced edge rate control (ERC) that reduces EMI, while maintaining high quality
audio reproduction and efficiency. The LM48901 ERC greatly reduces the high frequency components of the output square waves
by controlling the output rise and fall times, slowing the transitions to reduce RF emissions, while maximizing THD+N and efficiency
performance. The overall result of the E2S system is a filterless Class D amplifier that passes FCC Class B radiated emissions
standards with 24in of twisted pair cable, with excellent 0.06% THD+N and high 89% efficiency.
POWER DISSIPATION AND EFFICIENCY
The major benefit of a Class D amplifier is increased efficiency versus a Class AB. The efficiency of the LM48901 is attributed to
the region of operation of the transistors in the output stage. The Class D output stage acts as current steering switches, consuming
negligible amounts of power compared to their Class AB counterparts. Most of the power loss associated with the output stage is
due to the IR loss of the MOSFET on-resistance, along with switching losses due to gate charge.
ANALOG INPUT
The LM48901 features a differential input, stereo ADC for analog systems. A differential amplifier amplifies the difference between
the two input signals. Traditional audio power amplifiers have typically offered only single-ended inputs resulting in a 6dB reduction
of SNR relative to differential inputs. The LM48901 also offers the possibility of DC input coupling which eliminates the input coupling
capacitors. A major benefit of the fully differential amplifier is the improved common mode rejection ratio (CMRR) over single ended
input amplifiers. The increased CMRR of the differential amplifier reduces sensitivity to ground offset related noise injection, es-
pecially important in noisy systems.
PARALLEL MODE
In Parallel mode, channels OUT2 and OUT3 are driven from the same audio source, allowing the two channels to be connected
in parallel, increasing output power to 3.2W into 4Ω at 10% THD+N. Set bit 2 (PARALLEL) of the Analog Configuration Register
(0x532h) = 1 to configured the device in Parallel mode. After the device is set to Parallel mode, make an external connection
between OUT2+ and OUT3+, and a connection between OUT2- and OUT3- (Figure 2). In Parallel mode, the combined channels
are driven from the OUT2 source. OUT1 and OUT4 are unaffected. Signal routing, mixing, filtering, and equalization are done
through the Spatial Engine.
Make sure the device is configured in Parallel mode, before connecting OUT2 and OUT3 and enabling the outputs. Do not make
a connection between OUT2 and OUT3 together while the outputs are enabled. Disable the outputs first, then make the connections
between OUT2 and OUT3.
GAIN SETTING
The LM48901 has three gain stages, the ADC preamplifier, and two independent volume controls in the Digital Mixer, one for the
ADC path and one for the I2S path. The ADC preamplifier has four gain settings (0dB, 2.4dB, 3.5dB, and 6dB). The preamplifier
gain is set by bits 0 and 1 (ANA_LVL) of the Analog Configuration Register (0x523h). The Digital Mixer has two 64 step volume
controls. The ADC path volume control is set by bits 5:0 (ADC_LVL) in the Digital Mixer Control Register (0x522h). The I2S path
volume control is set by bits 13:8 (I2S_LVL) in the Digital Mixer Control Register (0x522h). Both volume controls have a range of
-76.5dB to 18dB in 1.5dB increments.
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44
MODULATOR POWER SUPPLY (AVDD1
)
The AVDD1 (RL package: bump C2, SQ package: pin 12) powers the class D modulators. For maximum output swing, set AVDD1
and PVDD to the same voltage. Table 22 shows the output voltage for different AVDD1 levels.
TABLE 22. Amplifier Output Voltage with Variable AVDD1 Voltage
AVDD1 (V)
VOUT (VRMS) @ PVDD = 5V, THD+N = 1%
VOUT (VRMS) @ PVDD = 3.6V, THD+N = 1%
5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
2
-
-
4.5
4.2
4
-
-
3.6
3.3
3
2.4
2.2
2.1
1.9
2.8
CLOCK REQUIREMENTS
The LM48901 requires an external clock source for proper operation, regardless of input source or device configuration. The device
derives the ADC, digital mixer, DSP, I2S port, and PWM clocks from the external clock. The clock can be derived from either MCLK
or SCLK inputs. Set bit 11 (I2S_CLK) of the Enable and Clock configuration register (0x521h) to 0 to select MCLK, set I2S_CLK to
1 to select SCLK. The LM48901 accepts five different clock frequencies, 1.536, 3.072, 6.114, 12.288, and 24.576MHz. Set bits
10:8 (MCLK_RATE) of the Enable and Clock Configuration Register to the appropriate clock frequency. In systems where both
MCLK and SCLK are available, choose the lower frequency clock for improved power consumption.
SHUTDOWN FUNCTION
There are two ways to shutdown the LM48901, hardware mode, and software mode. The default is hardware mode.
Set bit 1 (FORCE) of the Enable and Clock Configuration Register (0x521h) to 0 to enable hardware shutdown mode. In hardware
mode, the device is enabled and disabled through SHDN. Connect SHDN to VDD for normal operation. Connect SHDN to GND to
disable the device. Hardware shutdown mode supports a one shot, or momentary switch SHDN input. When bit 2 (PULSE) of the
Enable and Clock Configuration Register (0x521h) is set to 1, the LM48901 responds to a rising edge on SHDN to change the
device state. When PULSE = 0, the device requires a stable logic level on SHDN.
Set FORCE = 1 to enable software shutdown mode. In software shutdown mode, the device is enabled and disabled through bit
0 (ENABLE) of the Enable and Clock Configuration Register (0x512h). Set ENABLE = 0 to disable the LM48901. Set ENABLE =
1 to enable the LM48901.
In either hardware or software mode, the content of the LM48901 memory registers is retained after the device is disabled, as long
as power is still applied to the device. Minimize power consumption by disabling the PMC clock oscillator when the LM48901 is
shutdown. Set bit 12 (PMC_CLK_SEL) and bit 14 (QSA_CLK_STOP) of the Enable and Clock configuration Register (0x521h) =
1 to disable the PMC clock oscillator.
EXTERNAL CAPACITOR SELECTION
Power Supply Bypassing and Filtering
Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close
to the device as possible. Typical applications employ a voltage regulator with 10μF and 0.1μF bypass capacitors that increase
supply stability. These capacitors do not eliminate the need for bypassing of the LM48901 supply pins. A 1μF capacitor is recom-
mended for IOVDD, PLLVDD, DVDD, and AVDD. A 2.2μF capacitor is recommended for PVDD
.
REF and BYPASS Capacitor Selection
For best performance, bypass REF with a 4.7μF ceramic capacitor.
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INPUT CAPACITOR SELECTION
The LM48901 analog inputs require input coupling capacitors. Input capacitors block the DC component of the audio signal, elim-
inating any conflict between the DC component of the audio source and the bias voltage of the LM48901. The input capacitors
create a high-pass filter with the input resistors RIN. The -3dB point of the high pass filter is found using Equation (1) below.
f = 1 / 2πRINCIN
Where the value of RIN is 20kΩ.
The input capacitors can also be used to remove low frequency content from the audio signal. Small speakers cannot reproduce,
and may even be damaged by low frequencies. High pass filtering the audio signal helps protect the speakers. When the LM48901
is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above
the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and
heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR
and PSRR.
PCB LAYOUT GUIDELINES
As output power increases, interconnect resistance (PCB traces and wires) between the amplifier, load, and power supply create
a voltage drop. The voltage loss due to the traces between the LM48901 and the load results in lower output power and decreased
efficiency. Higher trace resistance between the supply and the LM48901 has the same effect as a poorly regulated supply, in-
creasing ripple on the supply line, and reducing peak output power. The effects of residual trace resistance increases as output
current increases due to higher output power, decreased load impedance or both. To maintain the highest output voltage swing
and corresponding peak output power, the PCB traces that connect the output pins to the load and the supply pins to the power
supply should be as wide as possible to minimize trace resistance.
The use of power and ground planes will give the best THD+N performance. In addition to reducing trace resistance, the use of
power planes creates parasitic capacitors that help to filter the power supply line.
The inductive nature of the transducer load can also result in overshoot on one of both edges, clamped by the parasitic diodes to
GND and VDD in each case. From an EMI standpoint, this is an aggressive waveform that can radiate or conduct to other compo-
nents in the system and cause interference. In is essential to keep the power and output traces short and well shielded if possible.
Use of ground planes beads and micros-strip layout techniques are all useful in preventing unwanted interference.
As the distance from the LM48901 and the speaker increases, the amount of EMI radiation increases due to the output wires or
traces acting as antennas become more efficient with length. Ferrite chip inductors places close to the LM48901 outputs may be
needed to reduce EMI radiation.
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46
Revision History
Rev
1.0
Date
Description
10/31/11
12/02/11
12/12/11
12/16/11
Initial Web released.
1.01
1.02
1.03
Fixed a typo (LM488901 to LM48901) on page 45.
Added two sections “Modulator Power Supply” and Clock Requirements.
Changed National to Texas Instruments.
47
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Physical Dimensions inches (millimeters) unless otherwise noted
36–pin micro SMD
Order Number LM48901RL
NS Package Number TLA36JSA
X1 = 3.204±0.03mmꢀX2 = 3.434±0.03mmꢀX3 = 0.65±0.075mm
LLP Package
Order Number LM48901SQ
NS Package Number SQA32A
X1 = 5mmꢀX2 = 5mmꢀX3 = 0.8mm
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48
Notes
49
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Notes
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