LM4890 [TI]
1W 音频功率放大器;
| 型号： | LM4890 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1W 音频功率放大器 放大器 功率放大器 |
| 文件： | 总39页 (文件大小：2168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM4890
www.ti.com
SNAS138L –SEPTEMBER 2001–REVISED MAY 2013
LM4890
1 Watt Audio Power Amplifier
Check for Samples: LM4890
1
FEATURES
DESCRIPTION
The LM4890 is an audio power amplifier primarily
designed for demanding applications in mobile
phones and other portable communication device
applications. It is capable of delivering 1 watt of
continuous average power to an 8Ω BTL load with
less than 1% distortion (THD+N) from a 5VDC power
supply.
2
•
Available in Space-Saving Packages: DSBGA,
VSSOP, SOIC, and WSON
•
•
•
Ultra Low Current Shutdown Mode
BTL Output Can Drive Capacitive Loads
Improved Pop & Click Circuitry Eliminates
Noises During Turn-On and Turn-Off
Transitions
Boomer audio power amplifiers were designed
specifically to provide high quality output power with a
minimal amount of external components. The
LM4890 does not require output coupling capacitors
or bootstrap capacitors, and therefore is ideally suited
for mobile phone and other low voltage applications
where minimal power consumption is a primary
requirement.
•
•
2.2 - 5.5V Operation
No Output Coupling Capacitors, Snubber
Networks or Bootstrap Capacitors Required
•
•
•
Thermal Shutdown Protection
Unity-Gain Stable
External Gain Configuration Capability
The LM4890 features a low-power consumption
shutdown mode, which is achieved by driving the
shutdown pin with logic low. Additionally, the LM4890
features an internal thermal shutdown protection
mechanism.
APPLICATIONS
•
•
•
Mobile Phones
PDAs
Portable Electronic Devices
The LM4890 contains advanced pop & click circuitry
which eliminates noises which would otherwise occur
during turn-on and turn-off transitions.
KEY SPECIFICATIONS
•
•
•
•
PSRR at 217Hz, VDD = 5V (Fig. 1): 62dB(typ.)
Power Output at 5.0V & 1% THD: 1W(typ.)
Power Output at 3.3V & 1% THD: 400mW(typ.)
Shutdown Current: 0.1μA(typ.)
The LM4890 is unity-gain stable and can be
configured by external gain-setting resistors.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
LM4890
SNAS138L –SEPTEMBER 2001–REVISED MAY 2013
www.ti.com
Connection Diagrams
Top View
Top View
Figure 1. 8 Bump DSBGA Package
See Package Number YPB0008
Figure 2. 9 Bump DSBGA Package
See Package Number YZR0009
Top View
Top View
Figure 3. WSON Package
See Package Number NGZ0010B
Figure 4. Mini Small Outline (VSSOP) Package
See Package Number DGK0008A
Top View
Top View
Figure 5. Small Outline (SOIC) Package
See Package Number D0008A
Figure 6. 9 Bump DSBGA Package
See Package Number YZR0009AAA
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SNAS138L –SEPTEMBER 2001–REVISED MAY 2013
Typical Application
Rf
20k
VDD
CS
1mF
RIN
Audio
Input
15pF
20k
VOUT
-
1
A1
CIN
0.39mF
10k
RL
8W
20k
20k
SW
250k
500k
CBYPASS
1mF
250k
A2
VOUT2
+
10k
Shutdown
Control
VIH
VIL
GND
Figure 7. Typical Audio Amplifier Application Circuit
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
Supply Voltage(3)
6.0V
−65°C to +150°C
−0.3V to VDD +0.3V
Internally Limited
2000V
Storage Temperature
Input Voltage
Power Dissipation(4)
ESD Susceptibility(5)
Junction Temperature
Thermal Resistance
150°C
θJC (SOIC)
35°C/W
θJA (SOIC)
150°C/W
θJA (8 Bump DSBGA,(6)
θJA (9 Bump DSBGA,(6)
θJC (VSSOP)
)
)
220°C/W
180°C/W
56°C/W
θJA (VSSOP)
190°C/W
θJA (WSON)
220°C/W
Soldering Information
See AN-1112 (SNVA009) "DSBGA Wafers Level Chip
Scale Package."
See AN-1187 (SNOA401) "Leadless Leadframe
Package (WSON)."
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) If the product is in shutdown mode and VDD exceeds 6V (to a max of 8V VDD), then most of the excess current will flow through the ESD
protection circuits. If the source impedance limits the current to a max of 10 ma, then the part will be protected. If the part is enabled
when VDD is greater than 5.5V and less than 6.5V, no damage will occur, although operational life will be reduced. Operation above
6.5V with no current limit will result in permanent damage.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever
is lower. For the LM4890, see power derating curves for additional information.
(5) Human body model, 100 pF discharged through a 1.5 kΩ resistor.
(6) All bumps have the same thermal resistance and contribute equally when used to lower thermal resistance. All bumps must be
connected to achieve specified thermal resistance.
Operating Ratings
Temperature Range TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ 85°C
2.2V ≤ VDD ≤ 5.5V
Supply Voltage
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Electrical Characteristics VDD = 5V(1)(2)(3)
The following specifications apply for the circuit shown in Figure 7 unless otherwise specified. Limits apply for TA = 25°C.
LM4890
Typical(4)
Units
(Limits)
Parameter
Test Conditions
Limit(5) (6)
8
IDD
Quiescent Power Supply Current
VIN = 0V, Io = 0A, No Load
VIN = 0V, Io = 0A, 8Ω Load
VSHUTDOWN = 0V
4
5
mA (max)
mA (max)
µA (max)
V (min)
V (max)
mV (max)
kΩ (max)
kΩ (min)
W
10
ISD
Shutdown Current
0.1
2.0
VSDIH
VSDIL
VOS
Shutdown Voltage Input High
Shutdown Voltage Input Low
Output Offset Voltage
1.2
0.4
7
50
ROUT-GND Resistor Output to GND(7)
9.7
8.5
7.0
Po
Output Power (8Ω)
THD = 2% (max); f = 1 kHz
Po = 0.4 Wrms; f = 1kHz
1.0
0.8
TWU
TSD
Wake-up time
170
220
150
190
ms (max)
°C (min)
°C (max)
%
Thermal Shutdown Temperature
170
THD+N
PSRR
Total Harmonic Distortion + Noise
Power Supply Rejection Ratio(8)
0.1
Vripple = 200mV sine p-p
Input Terminated with 10 ohms to
ground
62 (f = 217Hz)
66 (f = 1kHz)
55
dB (min)
TSDT
Shut Down Time
8 Ω load
1.0
ms (max)
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) For DSBGA only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a
maximum of 2µA.
(4) Typicals are measured at 25°C and represent the parametric norm.
(5) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(6) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(7) ROUT is measured from each of the output pins to ground. This value represents the parallel combination of the 10k ohm output
resistors and the two 20k ohm resistors.
(8) PSRR is a function of system gain. Specifications apply to the circuit in Figure 7 where AV = 2. Higher system gains will reduce PSRR
value by the amount of gain increase. A system gain of 10 represents a gain increase of 14dB. PSRR will be reduced by 14dB and
applies to all operating voltages.
Electrical Characteristics VDD = 3V(1)(2)(3)
The following specifications apply for the circuit shown in Figure 7 unless otherwise specified. Limits apply for TA = 25°C.
LM4890
Units
(Limits)
Parameter
Test Conditions
Typical(4)
Limit(5) (6)
IDD
Quiescent Power Supply Current
VIN = 0V, Io = 0A, No Load
VIN = 0V, Io = 0A, 8Ω Load
VSHUTDOWN = 0V
3.5
4.5
0.1
7
mA (max)
mA (max)
µA (max)
V(min)
9
ISD
Shutdown Current
2.0
1.2
0.4
VSDIH
VSDIL
Shutdown Voltage Input High
Shutdown Voltage Input Low
V(max)
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) For DSBGA only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a
maximum of 2µA.
(4) Typicals are measured at 25°C and represent the parametric norm.
(5) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(6) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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Electrical Characteristics VDD = 3V(1)(2)(3) (continued)
The following specifications apply for the circuit shown in Figure 7 unless otherwise specified. Limits apply for TA = 25°C.
LM4890
Typical(4)
Units
(Limits)
Parameter
Test Conditions
Limit(5) (6)
50
VOS
Output Offset Voltage
ROUT-GND Resistor Output to Gnd(7)
7
mV (max)
kΩ (max)
kΩ (min)
ms (max)
W
9.7
8.5
7.0
TWU
Po
Wake-up time
120
180
Output Power (8Ω)
THD = 1% (max); f = 1kHz
Po = 0.15Wrms; f = 1kHz
0.31
0.28
150
TSD
Thermal Shutdown Temperature
°C(min)
°C(max)
%
170
0.1
190
THD+N
PSRR
Total Harmonic Distortion + Noise
Power Supply Rejection Ratio(8)
Vripple = 200mV sine p-p
Input terminated with 10 ohms to
ground
56 (f = 217Hz)
62 (f = 1kHz)
45
dB(min)
(7) ROUT is measured from each of the output pins to ground. This value represents the parallel combination of the 10k ohm output
resistors and the two 20k ohm resistors.
(8) PSRR is a function of system gain. Specifications apply to the circuit in Figure 7 where AV = 2. Higher system gains will reduce PSRR
value by the amount of gain increase. A system gain of 10 represents a gain increase of 14dB. PSRR will be reduced by 14dB and
applies to all operating voltages.
Electrical Characteristics VDD = 2.6V(1)(2)(3)
The following specifications apply for for the circuit shown in Figure 7 unless otherwise specified. Limits apply for TA = 25°C.
LM4890
Typical(4) Limit(5) (6)
Units
(Limits)
Parameter
Test Conditions
IDD
ISD
P0
Quiescent Power Supply Current
Shutdown Current
VIN = 0V, Io = 0A, No Load
VSHUTDOWN = 0V
2.6
0.1
mA (max)
µA (max)
Output Power (8Ω)
Output Power (4Ω)
THD = 1% (max); f = 1 kHz
THD = 1% (max); f = 1 kHz
0.2
0.22
W
W
THD+N
PSRR
Total Harmonic Distortion + Noise
Power Supply Rejection Ratio(7)
Po = 0.1Wrms; f = 1kHz
0.08
%
Vripple = 200mV sine p-p
Input Terminated with 10 ohms to
ground
44 (f = 217Hz)
44 (f = 1kHz)
dB
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) For DSBGA only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a
maximum of 2µA.
(4) Typicals are measured at 25°C and represent the parametric norm.
(5) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(6) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(7) PSRR is a function of system gain. Specifications apply to the circuit in Figure 7 where AV = 2. Higher system gains will reduce PSRR
value by the amount of gain increase. A system gain of 10 represents a gain increase of 14dB. PSRR will be reduced by 14dB and
applies to all operating voltages.
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SNAS138L –SEPTEMBER 2001–REVISED MAY 2013
External Components Description
(See Figure 7)
Components
Functional Description
1.
RIN
Inverting input resistance which sets the closed-loop gain in conjunction with Rf. This resistor also forms a high pass
filter with CIN at fC= 1/(2π RINCIN).
2.
CIN
Input coupling capacitor which blocks the DC voltage at the amplifier's input terminals. Also creates a highpass filter
with RIN at fc = 1/(2π RINCIN). Refer to the section, Proper Selection of External Components, for an explanation of how
to determine the value of CIN
Feedback resistance which sets the closed-loop gain in conjunction with RIN
Supply bypass capacitor which provides power supply filtering. Refer to the section, Power Supply Bypassing, for
information concerning proper placement and selection of the supply bypass capacitor, CBYPASS
CBYPAS Bypass pin capacitor which provides half-supply filtering. Refer to the section, Proper Selection of External
.
3.
4.
Rf
.
CS
.
5.
Components, for information concerning proper placement and selection of CBYPASS
.
S
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Typical Performance Characteristics
THD+N vs Frequency
at VDD = 5V, 8Ω RL, and PWR = 250mW, AV = 2
THD+N vs Frequency
at VDD = 3.3V, 8Ω RL, and PWR = 150mW, AV = 2
Figure 8.
Figure 9.
THD+N vs Frequency
at VDD = 3V, RL = 8Ω, PWR = 250mW, AV = 2
THD+N vs Frequency
at VDD = 2.6V, RL = 8Ω, PWR = 100mW, AV = 2
Figure 10.
Figure 11.
THD+N vs Frequency
at VDD = 2.6V, RL = 4Ω, PWR = 100mW, AV = 2
THD+N vs Power Out
at VDD = 5V, RL = 8Ω, 1kHz, AV = 2
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
THD+N vs Power Out
at VDD = 3.3V, RL = 8Ω, 1kHz, AV = 2
THD+N vs Power Out
at VDD = 3V, RL = 8Ω, 1kHz, AV = 2
Figure 14.
Figure 15.
THD+N vs Power Out
at VDD = 2.6V, RL = 8Ω, 1kHz, AV = 2
THD+N vs Power Out
at VDD = 2.6V, RL = 4Ω, 1kHz, AV = 2
Figure 16.
Figure 17.
Power Supply Rejection Ratio (PSRR) at AV = 2
VDD = 5V, Vripple = 200mvp-p
Power Supply Rejection Ratio (PSRR) at AV = 2
VDD = 5V, Vripple = 200mvp-p
RL = 8Ω, RIN = 10Ω
RL = 8Ω, RIN = Float
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Power Supply Rejection Ratio (PSRR) at AV = 4
Power Supply Rejection Ratio (PSRR) at AV = 4
VDD = 5V, Vripple = 200mvp-p
VDD = 5V, Vripple = 200mvp-p
RL = 8Ω, RIN = 10Ω
RL = 8Ω, RIN = Float
Figure 20.
Figure 21.
Power Supply Rejection Ratio (PSRR) at AV = 2
VDD = 3V, Vripple = 200mvp-p,
Power Supply Rejection Ratio (PSRR) at AV = 2
VDD = 3V, Vripple = 200mvp-p,
RL = 8Ω, RIN = 10Ω
RL = 8Ω, RIN = Float
Figure 22.
Figure 23.
Power Supply Rejection Ratio (PSRR) at AV = 4
VDD = 3V, Vripple = 200mvp-p,
Power Supply Rejection Ratio (PSRR) at AV = 4
VDD = 3V, Vripple = 200mvp-p,
RL = 8Ω, RIN = 10Ω
RL = 8Ω, RIN = Float
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
Power Supply Rejection Ratio (PSRR) at AV = 2
VDD = 3.3V, Vripple = 200mvp-p,
RL = 8Ω, RIN = 10Ω
Power Supply Rejection Ratio (PSRR) at AV = 2
VDD = 2.6V, Vripple = 200mvp-p,
RL = 8Ω, RIN = 10Ω
Figure 26.
Figure 27.
PSRR vs DC Output Voltage
VDD = 5V, AV = 2
PSRR vs DC Output Voltage
VDD = 5V, AV = 4
10
10
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-10
-20
-30
-40
-50
-60
-70
-80
-6
6
-6
-4
-2
0
2
4
-4
-2
0
2
4
6
V
(V)
OUTDC
V
(V)
OUTDC
Figure 28.
Figure 29.
PSRR vs DC Output Voltage
VDD = 5V, AV = 10
PSRR vs DC Output Voltage
VDD = 3V, AV = 2
10
10
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-10
-20
-30
-40
-50
-60
-70
-80
-6
-3
-2
-1
0
1
2
3
-4
-2
0
2
4
6
V
(V)
V
(V)
OUTDC
OUTDC
Figure 30.
Figure 31.
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Typical Performance Characteristics (continued)
PSRR vs DC Output Voltage
VDD = 3V, AV = 4
PSRR vs DC Output Voltage
VDD = 3V, AV = 10
10
0
1
0
0
-10
-20
-30
-40
-50
-60
-10
-20
-30
-40
-50
-60
-3
-2
-1
0
1
2
3
-3
-2
-1
0
1
2
3
V
(V)
OUTDC
V
(V)
OUTDC
Figure 32.
Figure 33.
PSRR Distribution VDD = 5V
217Hz, 200mvp-p,
PSRR Distribution VDD = 3V
217Hz, 200mvp-p,
-30, +25, and +80°C
-30, +25, and +80°C
(dBr)
(dBr)
-80
-70
-60
-50
-40
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
Figure 34.
Figure 35.
Power Supply Rejection Ration vs
Bypass Capacitor Size
VDD = 5V, Input Grounded = 10Ω, Output Load = 8Ω
Power Supply Rejection Ration vs
Bypass Capacitor Size
VDD = 3V, Input Grounded = 10Ω, Output Load = 8Ω
Figure 36. Top Trace = No Cap, Next Trace Down = 1µf
Next Trace Down = 2µf, Bottom Trace = 4.7µf
Figure 37. Top Trace = No Cap, Next Trace Down = 1µf
Next Trace Down = 2µf, Bottom Trace = 4.7µf
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Typical Performance Characteristics (continued)
LM4890 vs LM4877 Power Supply Rejection Ratio
VDD = 5V, Input Grounded = 10Ω
LM4890 vs LM4877 Power Supply Rejection Ratio
VDD = 3V, Input Grounded = 10Ω
Output Load = 8Ω, 200mV Ripple
Output Load = 8Ω, 200mV Ripple
Figure 38. LM4890 = Bottom Trace
LM4877 = Top Trace
Figure 39. LM4890 = Bottom Trace
LM4877 = Top Trace
Power Derating Curves (PDMAX = 670mW)
Power Derating - 8 bump DSBGA (PDMAX = 670mW)
Note: (PDMAX = 670mW for 5V, 8Ω)
Figure 40. Ambient Temperature in Degrees C
Note: (PDMAX = 670mW for 5V, 8Ω)
Figure 41. Ambient Temperature in Degrees C
Power Derating - 9 bump DSBGA (PDMAX = 670mW)
Power Derating - 10 Pin LD Pkg (PDMAX = 670mW)
0.8
0.7
2
480mm
0.6
0.5
0.4
0.3
0.2
0.1
0
2
120mm
2
0mm
NOTE 13
0
20
100 120 140 160
80
40 60
AMBIENT TEMPERATURE (°C)
Note: (PDMAX = 670mW for 5V, 8Ω)
Figure 42. Ambient Temperature in Degrees C
Note: (PDMAX = 670mW for 5V, 8Ω)
Figure 43. Ambient Temperature in Degrees C
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Typical Performance Characteristics (continued)
Power Output vs Supply Voltage
Power Output vs Temperature
Figure 44.
Figure 45.
Power Dissipation vs Output Power
VDD = 5V, 1kHz, 8Ω, THD ≤ 1.0%
Power Dissipation vs Output Power
VDD = 3.3V, 1kHz, 8Ω, THD ≤ 1.0%
Figure 46.
Figure 47.
Power Dissipation vs Output Power
VDD = 2.6V, 1kHz
Output Power
vs Load Resistance
Figure 48.
Figure 49.
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Typical Performance Characteristics (continued)
Supply Current
vs Ambient Temperature
Clipping (Dropout) Voltage
vs Supply Voltage
Figure 50.
Figure 51.
Max Die Temp
at PDMAX (9 bump DSBGA)
Max Die Temp
at PDMAX (8 bump DSBGA)
Figure 52.
Figure 53.
Supply Current
vs Shutdown Voltage
Output Offset Voltage
Figure 54.
Figure 55.
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Typical Performance Characteristics (continued)
Shutdown Hysterisis Voltage
VDD = 5V
Shutdown Hysterisis Voltage
VDD = 3V
4
3
2
1
4
3
2
OFF
ON
OFF
ON
1
0
0
0
1
2
3
0
1
2
3
Shutdown Voltage (V)
SHUTDOWN VOLTAGE (V)
Figure 56.
Figure 57.
Open Loop Frequency Response
VDD = 5V, No Load
Open Loop Frequency Response
VDD = 3V, No Load
Figure 58.
Figure 59.
Gain / Phase Response, AV = 2
VDD = 5V, 8Ω Load, CLOAD = 500pF
Gain / Phase Response, AV = 4
VDD = 5V, 8Ω Load, CLOAD = 500pF
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-90
-90
-180
-180
0
0
-5
-5
-10
-15
-20
-10
-15
-20
100
1K
10K 100K 1M
FREQUENCY (Hz)
Figure 60.
10M
100M
100K
10M
100
10K
1M
100M
1K
FREQUENCY (Hz)
Figure 61.
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Typical Performance Characteristics (continued)
Phase Margin vs CLOAD, AV = 2
VDD = 5V, 8Ω Load
Capacitance to gnd on each output
Phase Margin vs CLOAD, AV = 4
VDD = 5V, 8Ω Load
Capacitance to gnd on each output
120
100
80
60
40
20
0
120
100
80
60
40
20
0
50 deg Stability Limit
50 deg Stability Limit
0
500
1000
1500
2000
0
500
1000
1500
2000
CAPACITANCE (pF)
CAPACITANCE (pF)
Figure 62.
Figure 63.
Phase Margin and Limits
vs Application Variables, RIN = 22KΩ
Figure 64.
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Typical Performance Characteristics (continued)
Frequency Response
vs Input Capacitor Size
Wake Up Time (TWU
)
Figure 65.
Figure 66.
Noise Floor
Figure 67.
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APPLICATION INFORMATION
BRIDGED CONFIGURATION EXPLANATION
As shown in Figure 7, the LM4890 has two operational amplifiers internally, allowing for a few different amplifier
configurations. The first amplifier's gain is externally configurable, while the second amplifier is internally fixed in
a unity-gain, inverting configuration. The closed-loop gain of the first amplifier is set by selecting the ratio of Rf to
RIN while the second amplifier's gain is fixed by the two internal 20kΩ resistors. Figure 7 shows that the output of
amplifier one serves as the input to amplifier two which results in both amplifiers producing signals identical in
magnitude, but out of phase by 180°. Consequently, the differential gain for the IC is
AVD= 2 *(Rf/RIN)
By driving the load differentially through outputs Vo1 and Vo2, an amplifier configuration commonly referred to as
“bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier
configuration where one side of the load is connected to ground.
A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides
differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output
power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable
output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closed-
loop gain without causing excessive clipping, please refer to the Audio Power Amplifier Design section.
A bridge configuration, such as the one used in the LM4890, also creates a second advantage over single-ended
amplifiers. Since the differential outputs, Vo1 and Vo2, are biased at half-supply, no net DC voltage exists across
the load. This eliminates the need for an output coupling capacitor which is required in a single supply, single-
ended amplifier configuration. Without an output coupling capacitor, the half-supply bias across the load would
result in both increased internal IC power dissipation and also possible loudspeaker damage.
EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATIONS FOR THE LM4890LD
The LM4890LD's exposed-DAP (die attach paddle) package (LD) provides a low thermal resistance between the
die and the PCB to which the part is mounted and soldered. The LM4890LD package should have its DAP
soldered to the grounded copper pad (heatsink) under the LM4890LD (the NC pins, no connect, and ground pins
should also be directly connected to this copper pad-heatsink area). The area of the copper pad (heatsink) can
be determined from the LD Power Derating graph. If the multiple layer copper heatsink areas are used, then
these inner layer or backside copper heatsink areas should be connected to each other with 4 (2 x 2) vias. The
diameter for these vias should be between 0.013 inches and 0.02 inches with a 0.050inch pitch-spacing. Ensure
efficient thermal conductivity by plating through and solder-filling the vias. Further detailed information concerning
PCB layout, fabrication, and mounting an WSON package is available from TI's Package Engineering Group
under application note AN1187.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or
single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an
increase in internal power dissipation. Since the LM4890 has two operational amplifiers in one package, the
maximum internal power dissipation is 4 times that of a single-ended amplifier. The maximum power dissipation
for a given application can be derived from the power dissipation graphs or from Equation 1.
PDMAX = 4*(VDD)2/(2π2RL)
(1)
It is critical that the maximum junction temperature TJMAX of 150°C is not exceeded. TJMAX can be determined
from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the
thermal resistance of the application can be reduced, resulting in higher PDMAX. Additional copper foil can be
added to any of the leads connected to the LM4890. Refer to the Application Information on the LM4890
reference design board for an example of good heat sinking. If TJMAX still exceeds 150°C, then additional
changes must be made. These changes can include reduced supply voltage, higher load impedance, or reduced
ambient temperature. Internal power dissipation is a function of output power. Refer to the Typical Performance
Characteristics curves for power dissipation information for different output powers and output loading.
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POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as
possible. Typical applications employ a 5V regulator with 10 µF tantalum or electrolytic capacitor and a ceramic
bypass capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of
the LM4890. The selection of a bypass capacitor, especially CBYPASS, is dependent upon PSRR requirements,
click and pop performance (as explained in the section, Proper Selection of External Components), system cost,
and size constraints.
SHUTDOWN FUNCTION
In order to reduce power consumption while not in use, the LM4890 contains a shutdown pin to externally turn off
the amplifier's bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the
shutdown pin. By switching the shutdown pin to ground, the LM4890 supply current draw will be minimized in idle
mode. While the device will be disabled with shutdown pin voltages less than 0.5VDC, the idle current may be
greater than the typical value of 0.1µA. (Idle current is measured with the shutdown pin grounded).
In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry to
provide a quick, smooth transition into shutdown. Another solution is to use a single-pole, single-throw switch in
conjunction with an external pull-up resistor. When the switch is closed, the shutdown pin is connected to ground
and disables the amplifier. If the switch is open, then the external pull-up resistor will enable the LM4890. This
scheme ensures that the shutdown pin will not float thus preventing unwanted state changes.
SHUTDOWN OUTPUT IMPEDANCE
For Rf = 20k ohms:
ZOUT1 (between Out1 and GND) = 10k||50k||Rf = 6kΩ
ZOUT2 (between Out2 and GND) = 10k||(40k+(10k||Rf)) = 8.3kΩ
ZOUT1-2 (between Out1 and Out2) = 40k||(10k+(10k||Rf)) = 11.7kΩ
The -3dB roll off for these measurements is 600kHz
PROPER SELECTION OF EXTERNAL COMPONENTS
Proper selection of external components in applications using integrated power amplifiers is critical to optimize
device and system performance. While the LM4890 is tolerant of external component combinations,
consideration to component values must be used to maximize overall system quality.
The LM4890 is unity-gain stable which gives the designer maximum system flexibility. The LM4890 should be
used in low gain configurations to minimize THD+N values, and maximize the signal to noise ratio. Low gain
configurations require large input signals to obtain a given output power. Input signals equal to or greater than
1Vrms are available from sources such as audio codecs. Please refer to the section, Audio Power Amplifier
Design, for a more complete explanation of proper gain selection.
Besides gain, one of the major considerations is the closed-loop bandwidth of the amplifier. To a large extent, the
bandwidth is dictated by the choice of external components shown in Figure 7. The input coupling capacitor, CIN,
forms a first order high pass filter which limits low frequency response. This value should be chosen based on
needed frequency response for a few distinct reasons.
Selection Of Input Capacitor Size
Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized
capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers
used in portable systems, whether internal or external, have little ability to reproduce signals below 100Hz to
150Hz. Thus, using a large input capacitor may not increase actual system performance.
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In addition to system cost and size, click and pop performance is effected by the size of the input coupling
capacitor, CIN. A larger input coupling capacitor requires more charge to reach its quiescent DC voltage
(nominally 1/2 VDD). This charge comes from the output via the feedback and is apt to create pops upon device
enable. Thus, by minimizing the capacitor size based on necessary low frequency response, turn-on pops can be
minimized.
Besides minimizing the input capacitor size, careful consideration should be paid to the bypass capacitor value.
Bypass capacitor, CBYPASS, is the most critical component to minimize turn-on pops since it determines how fast
the LM4890 turns on. The slower the LM4890's outputs ramp to their quiescent DC voltage (nominally 1/2VDD),
the smaller the turn-on pop. Choosing CBYPASS equal to 1.0µF along with a small value of CIN, (in the range of
0.1µF to 0.39µF), should produce a virtually clickless and popless shutdown function. While the device will
function properly, (no oscillations or motorboating), with CBYPASS equal to 0.1µF, the device will be much more
susceptible to turn-on clicks and pops. Thus, a value of CBYPASS equal to 1.0µF is recommended in all but the
most cost sensitive designs.
AUDIO POWER AMPLIFIER DESIGN
A 1W/8Ω Audio Amplifier
Given:
Power Output
Load Impedance
Input Level
1 Wrms
8Ω
1 Vrms
Input Impedance
Bandwidth
20 kΩ
100 Hz–20 kHz ± 0.25 dB
A designer must first determine the minimum supply rail to obtain the specified output power. By extrapolating
from the Output Power vs Supply Voltage graphs in the Typical Performance Characteristics section, the supply
rail can be easily found. A second way to determine the minimum supply rail is to calculate the required Vopeak
using Equation 2 and add the output voltage. Using this method, the minimum supply voltage would be (Vopeak
+
(VODTOP + VODBOT)), where VODBOT and VODTOP are extrapolated from the Dropout Voltage vs Supply Voltage curve in
theTypical Performance Characteristics.
(2)
5V is a standard voltage which in most applications is chosen for the supply rail. Extra supply voltage creates
headroom that allows the LM4890 to reproduce peaks in excess of 1W without producing audible distortion. At
this time, the designer must make sure that the power supply choice along with the output impedance does not
violate the conditions explained in the POWER DISSIPATION section.
Once the power dissipation equations have been addressed, the required differential gain can be determined
from Equation 3.
(3)
Rf/RIN = AVD/2
(4)
From Equation 3, the minimum AVD is 2.83; use AVD = 3.
Since the desired input impedance is 20 kΩ, and with an AVD gain of 3, a ratio of 1.5:1 of Rf to RIN results in an
allocation of RIN = 20 kΩ and Rf = 30 kΩ. The final design step is to address the bandwidth requirements which
must be stated as a pair of −3 dB frequency points. Five times away from a −3 dB point is 0.17 dB down from
passband response which is better than the required ±0.25 dB specified.
fL = 100Hz/5 = 20Hz
fH = 20kHz * 5 = 100kHz
As stated in the External Components Description section, RIN in conjunction with CIN create a highpass filter.
CIN ≥ 1/(2π*20 kΩ*20Hz) = 0.397µF; use 0.39µF
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The high frequency pole is determined by the product of the desired frequency pole, fH, and the differential gain,
AVD. With a AVD = 3 and fH = 100kHz, the resulting GBWP = 300kHz which is much smaller than the LM4890
GBWP of 2.5MHz. This calculation shows that if a designer has a need to design an amplifier with a higher
differential gain, the LM4890 can still be used without running into bandwidth limitations.
Figure 68. HIGHER GAIN AUDIO AMPLIFIER
The LM4890 is unity-gain stable and requires no external components besides gain-setting resistors, an input
coupling capacitor, and proper supply bypassing in the typical application. However, if a closed-loop differential
gain of greater than 10 is required, a feedback capacitor (C4) may be needed as shown in Figure 68 to
bandwidth limit the amplifier. This feedback capacitor creates a low pass filter that eliminates possible high
frequency oscillations. Care should be taken when calculating the -3dB frequency in that an incorrect
combination of R3 and C4 will cause rolloff before 20kHz. A typical combination of feedback resistor and
capacitor that will not produce audio band high frequency rolloff is R3 = 20kΩ and C4 = 25pf. These components
result in a -3dB point of approximately 320 kHz.
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Figure 69. DIFFERENTIAL AMPLIFIER CONFIGURATION FOR LM4890
Figure 70. REFERENCE DESIGN BOARD and LAYOUT - DSBGA
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LM4890 DSBGA BOARD ARTWORK
Silk Screen
Top Layer
Bottom Layer
Inner Layer VDD
Inner Layer Ground
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Figure 71. REFERENCE DESIGN BOARD and PCB LAYOUT GUIDELINES - VSSOP and SOIC Boards
LM4890 SOIC DEMO BOARD ARTWORK
Figure 72. Silk Screen
Figure 73. Top Layer
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Figure 74. Bottom Layer
LM4890 VSSOP DEMO BOARD ARTWORK
Figure 75. Silk Screen
Figure 76. Top Layer
Figure 77. Bottom Layer
Table 1. Mono LM4890 Reference Design Boards
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Table 1. Mono LM4890 Reference Design Boards
Bill of Material for all 3 Demo Boards (continued)
Bill of Material for all 3 Demo Boards
Item
Part Number
Part Description
LM4890 Mono Reference Design Board
LM4890 Audio AMP
Qty
1
Ref Designator
1
551011208-001
482911183-001
151911207-001
151911207-002
152911207-001
472911207-001
210007039-002
10
20
21
25
30
35
1
U1
C1
Tant Cap 1uF 16V 10
1
Cer Cap 0.39uF 50V Z5U 20% 1210
Tant Cap 1uF 16V 10
1
C2
1
C3
Res 20K Ohm 1/10W 5
3
R1, R2, R3
J1, J2
Jumper Header Vertical Mount 2X1 0.100
2
PCB LAYOUT GUIDELINES
This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power
and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual
results will depend heavily on the final layout.
GENERAL MIXED SIGNAL LAYOUT RECOMMENDATIONS
Power and Ground Circuits
For 2 layer mixed signal design, it is important to isolate the digital power and ground trace paths from the
analog power and ground trace paths. Star trace routing techniques (bringing individual traces back to a central
point rather than daisy chaining traces together in a serial manner) can have a major impact on low level signal
performance. Star trace routing refers to using individual traces to feed power and ground to each circuit or even
device. This technique will require a greater amount of design time but will not increase the final price of the
board. The only extra parts required will be some jumpers.
Single-Point Power / Ground Connections
The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can
be helpful in minimizing High Frequency noise coupling between the analog and digital sections. It is further
recommended to put digital and analog power traces over the corresponding digital and analog ground traces to
minimize noise coupling.
Placement of Digital and Analog Components
All digital components and high-speed digital signals traces should be located as far away as possible from
analog components and circuit traces.
Avoiding Typical Design / Layout Problems
Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB
layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90
degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise
coupling and cross talk.
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REVISION HISTORY
Changes from Revision K (May 2013) to Revision L
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 27
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM4890M/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LM48
90M
LM4890MM/NOPB
LM4890MMX/NOPB
LM4890MX/NOPB
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
1000 RoHS & Green
3500 RoHS & Green
2500 RoHS & Green
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
G90
G90
LM48
90M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM4890MM/NOPB
LM4890MMX/NOPB
LM4890MX/NOPB
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
1000
3500
2500
178.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
6.5
3.4
3.4
5.4
1.4
1.4
2.0
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM4890MM/NOPB
LM4890MMX/NOPB
LM4890MX/NOPB
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
1000
3500
2500
208.0
367.0
367.0
191.0
367.0
367.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM4890M/NOPB
D
8
95
495
8
4064
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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