LM49360RLX_技术文档

December 1, 2011

LM49360

Mono Class D Audio Codec PMU with Ground Referenced

Headphone Amplifiers, Earpiece Driver, Audio DSP, 2 Step-

Down DC-DC Converters, and 7 LDO Regulators

1.0 General Description

4.0 Features

The LM49360 combines a high performance mixed signal au-

dio subsystem and power management unit (PMU) into a tiny

4.169mm x 3.99mm micro SMD package. The LM49360 in-

cludes a high quality stereo DAC, a high quality stereo ADC,

a stereo headphone amplifier, which supports True Ground

operation, a low EMI Class D loudspeaker amplifier, an ear-

piece speaker amplifier, two high efficiency buck converters,

and seven LDO regulators. It combines advanced audio pro-

cessing, conversion, mixing, amplification, and power man-

agement in the smallest possible footprint while extending the

battery life of feature rich portable devices.

Ultra efficient, spread spectrum Class D loudspeaker

■

amplifier

Low voltage, true ground headphone amplifier operation

■

2 high efficiency 700mA step-down DC/DC converters

2 low noise 400mA LDOs and 4 low noise 200mA LDOs

1 low noise 20mA High Input Low Output (HILO) LDO

Programmable PMU startup sequence capability

High performance 103dB SNR stereo DAC

High performance 98dB SNR stereo ADC

Up to 96kHz stereo audio playback

The LM49360 features dual bi-directional I²S or PCM audio

interfaces and an I²C compatible interface for control. This

device can be configured as a sub-PMU for camera/multime-

dia modules or as a AP-PMU that powers the applications

processor.

Up to 48kHz stereo recording

Dual bidirectional I²S or PCM compatible audio interfaces

Read/write I²C compatible control interface

Flexible digital mixer with sample rate conversion

The LM49360 employs advanced techniques to extend bat-

tery life, to reduce controller overhead, to speed development

time, and to eliminate click and pop artifacts. Boomer audio

power amplifiers are designed specifically for mobile devices

and require minimal PCB area and external components.

Sigma-delta PLL clock network that supports system

clocks up to 50MHz including 13MHz, 19.2MHz, and

26MHz

■

Stereo 5 band parametric equalizer

■

Cascadable DSP effects that allow stereo 10 band

parametric equalization

2.0 Applications

ALC/Limiter/Compressor on both DAC and ADC paths

■

Smart Phones

■

Dedicated Earpiece Speaker Amplifier

Mobile Phones and VOIP Phones

Stereo auxiliary inputs and mono differential input

Portable GPS Navigator and Portable Gaming Devices

Differential microphone input with single-ended option

Portable Media Players

Automatic level control for digital audio inputs, mono

differential input, microphone input, and stereo auxiliary

inputs

■

Digital Cameras/Camcorders

■

3.0 Key Specifications

Flexible audio routing from input to output

■

P_EPat A_V_DD= 3.6V, 32Ω, 1% THD

P_HPat HP_V_DD= 2.8V, Stereo 32Ω,

60mW (typ)

70mW/ch (typ)

16 Step volume control for microphone with 2dB steps

32 Step volume control for auxiliary inputs in 1.5dB steps

4 Step volume control for class D loudspeaker amplifier

8 Step volume control for headphone amplifier

Micro-power shutdown mode

■

1% THD

P_LSat LS_V_DD= 5V, 8Ω, 1% THD

P_LSat LS_V_DD= 4.2V, 8Ω, 1% THD

P_LSat LS_V_DD= 3.6V, 8Ω, 1% THD

SNR (Stereo DAC at 48kHz)

PSRR at 217 Hz, A_V_DD= 3.6V,

1.3W (typ)

900mW (typ)

595mW (typ)

97dB (typ)

■

Available in the 4.169 x 3.99 mm 64 bump micro SMD

package

95dB (typ)

(HP from AUX)

Boomer® is a registered trademark of National Semiconductor Corporation.

301282

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5.0 LM49360 Overview

301282h8

FIGURE 1. LM49360 Block Diagram

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2

6.0 Typical Application

30128211

FIGURE 2. Sub PMU System Diagram

3

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30128216

FIGURE 3. AP PMU System Diagram

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LM49360 Default Voltage Options

CONFIG = VBATT (SUB_PMU Mode)

Max Output

Current (mA)

Outputs

Default

Start-up Sequence

Loads

Voltage (V)

Buck1

Buck2

700

400

200

400

200

20

1.0

1.5

1.8

2.9

3.3

1.8

2.6

2.8

1.0

CVDD _CORE

CAM_CORE

VDD_SDRAM

VDD_I/O

t4(t0+32μs)

I²C

LDO1

t0

LDO2

t0

t4(t0+32μs)

I²C

LDO3

VDD_PLL

LDO4

BT MODULE

MINT

I²C

LDO5

I²C

LDO6

CAM_I/O

LDO7(HILO)

PW_CVDD

t4(t0+32μs)

CONFIG = GND (AP-PMU Mode)

Max Output

Current (mA)

Outputs

Default

Voltage (V)

Start-up Sequence

Loads

Buck1

Buck2

700

400

200

400

200

20

1.2

1.8

2.6

2.8

3.3

2.8

1.5

t0

I²C

TCC Core

VT CAM I/O

TCC 1.8 I/O

MIC BIAS

LDO1

t4 (t0 + 256)

I²C

LDO2

LDO3

t4 (t0 + 256)

I²C

TCC 2.8 I/O

DC MOTOR

USB

LDO4

LDO5

t4 (t0 + 256)

LDO6

TFLASH

LDO7(HILO)

AP LDO ON(Memory)

CONFIG = NC (CAM Application Mode)

Max Output

Current (mA)

Outputs

Default

Voltage (V)

Start-up Sequence

Loads

Buck1

Buck2

700

400

200

400

200

20

1.2

1.8

2.8

1.8

2.8

1.2

t0

ISP_CORE

t0

SENSOR_CORE

CAM SQRAM

LDO1

t5(t0 + 320)

t4 (t0 + 256)

t3(t0 + 192)

t5(t0 + 320)

t4 (t0 + 256)

OVR

LDO2

CAM DIGITAL & PLL

CAM AF (PIEZO)

CAM DIGITAL

LDO3

LDO4

LDO5

CAM ANALOG

HOST I/F

LDO6

LDO7(HILO)

OTHERS (1.2V)

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Table of Contents

1.0 General Description ......................................................................................................................... 1

2.0 Applications .................................................................................................................................... 1

3.0 Key Specifications ........................................................................................................................... 1

4.0 Features ........................................................................................................................................ 1

5.0 LM49360 Overview .......................................................................................................................... 2

6.0 Typical Application ........................................................................................................................... 3

7.0 Connection Diagrams ..................................................................................................................... 10

7.1 PIN TYPE DEFINITIONS ........................................................................................................ 13

8.0 State Machine Description .............................................................................................................. 14

8.1 PMU STATE MACHINE DESCRIPTION .................................................................................... 14

8.2 AUDIO PMC STATE MACHINE DESCRIPTION ......................................................................... 16

8.2.1 State_0 (OFF) .............................................................................................................. 16

8.2.2 State_1 (BIAS) ............................................................................................................. 16

8.2.3 State_2 (AMPS ON) ..................................................................................................... 17

8.2.3.1 AMPLIFIER CONTROL FSM ............................................................................... 17

8.2.4 State_3 (UNMUTE) ...................................................................................................... 17

8.2.5 State_4 (ON) ............................................................................................................... 17

8.2.6 State_5 (MUTE) ........................................................................................................... 17

8.2.7 State_6 (AMPS_OFF) ................................................................................................... 17

8.2.8 State_7 (OFF) .............................................................................................................. 17

9.0 Absolute Maximum Ratings ............................................................................................................ 18

10.0 Operating Ratings ........................................................................................................................ 18

11.0 Total Shutdown Current Consumption ............................................................................................ 18

12.0 PMU Current Consumption ........................................................................................................... 18

13.0 Thermal Shutdown ....................................................................................................................... 19

14.0 Under Voltage Lock Out ............................................................................................................... 19

15.0 Logic and Control ........................................................................................................................ 19

16.0 Electrical Characteristics / Buck Converters ..................................................................................... 20

17.0 Electrical Characteristics / General LDOs 1 to 6 ............................................................................... 20

18.0 Electrical Characteristics / High Input Low Output LDO 7 .................................................................. 21

19.0 Electrical Characteristics / Audio CODEC: A_V_DD= LS_V_DD= 3.6V; HP_V_DD= D_V_DD= I/O_V_DD

=

1.8V .............................................................................................................................................. 22

20.0 Timing Characteristics: DV_DD= I/OV_DD= 1.8V ................................................................................ 27

21.0 Typical Performance Characteristics .............................................................................................. 29

22.0 System Control ............................................................................................................................ 38

22.1 INPUT POWER SEQUENCING .............................................................................................. 38

22.2 I²C SIGNALS ....................................................................................................................... 38

22.3 I²C DATA VALIDITY ............................................................................................................. 38

22.4 I²C START AND STOP CONDITIONS ..................................................................................... 38

22.5 TRANSFERRING DATA ........................................................................................................ 38

22.6 I²C TIMING PARAMETERS .................................................................................................. 40

22.7 POWER ON SEQUENCE ...................................................................................................... 40

23.0 Device Register Map .................................................................................................................... 46

24.0 Sleep Enables ............................................................................................................................ 51

25.0 LDO Flags and Bypass Pulse Control ............................................................................................. 52

26.0 Sequence and Voltage Programming (Banks 0 to 2) ........................................................................ 53

27.0 Basic PMC Setup Register ........................................................................................................... 64

28.0 PMC Clocks Register ................................................................................................................... 65

29.0 PMC Clock Divide Register ........................................................................................................... 65

30.0 LM49360 Clock Network .............................................................................................................. 66

31.0 PLL Setup Registers .................................................................................................................... 68

32.0 Analog Mixer Control Registers ..................................................................................................... 72

33.0 ADC Control Registers ................................................................................................................. 80

34.0 DAC Control Registers ................................................................................................................. 82

35.0 Digital Mixer Control Registers ...................................................................................................... 83

36.0 Audio Port Control Registers ......................................................................................................... 87

37.0 Digital Effects Engine ................................................................................................................... 94

38.0 DAC Effects Registers ................................................................................................................ 110

39.0 GPIO Registers ......................................................................................................................... 125

40.0 Schematic Diagram .................................................................................................................... 127

41.0 Demonstration Board Layout ....................................................................................................... 129

42.0 Revision History ........................................................................................................................ 133

43.0 Physical Dimensions .................................................................................................................. 134

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List of Figures

FIGURE 1. LM49360 Block Diagram ............................................................................................................. 2

FIGURE 2. Sub PMU System Diagram .......................................................................................................... 3

FIGURE 3. AP PMU System Diagram ........................................................................................................... 4

FIGURE 4. PMU State Machine .................................................................................................................. 15

FIGURE 5. LM49360 Audio PMC Sequencer Overview with Typical Timing. ............................................................ 16

FIGURE 6. Zero Cross Detect Comparator (ZXD) ............................................................................................ 17

FIGURE 7. I²C Signals: Data Validity ............................................................................................................ 38

FIGURE 8. I²C Start and Stop Conditions ...................................................................................................... 38

FIGURE 9. I2C Chip Address ..................................................................................................................... 38

FIGURE 10. Example I²C Write Cycle .......................................................................................................... 39

FIGURE 11. Example I²C Read Cycle .......................................................................................................... 39

FIGURE 12. I²C Timing Diagram ................................................................................................................ 39

FIGURE 13. Simplified Startup Sequence if CONFIG = H or Z (SUB_PMU) ............................................................. 40

FIGURE 14. Simplified Startup Sequence if CONFIG = L (PMU) .......................................................................... 41

FIGURE 15. LM493060A CONFIG = H Start-up Sequence ................................................................................. 42

FIGURE 16. LM49360A CONFIG = L Start-up Sequence ................................................................................... 43

FIGURE 17. LM49360A CONFIG = Z Start-up Sequence ................................................................................... 44

FIGURE 18. Typical PWM Operation ............................................................................................................ 54

FIGURE 19. Typical ECO Operation ............................................................................................................ 55

FIGURE 20. Internal Clock Network ............................................................................................................. 67

FIGURE 21. PLL Loop ............................................................................................................................ 68

FIGURE 22. Application Circuit for Headphone Detection ................................................................................... 78

FIGURE 23. Digital Mixer .......................................................................................................................... 83

FIGURE 24. I²S Serial Data Format (24 bit example) ........................................................................................ 87

FIGURE 25. Left Justified Data Format (24 bit example) .................................................................................... 87

FIGURE 26. Right Justified Data Format (24 bit example) .................................................................................. 87

FIGURE 27. PCM Serial Data Format (16 bit example) ...................................................................................... 87

FIGURE 28. Timing for I²S Master ............................................................................................................... 88

FIGURE 29. Timing for I²S Slave ................................................................................................................ 88

FIGURE 30. ADC DSP Effects Chain ........................................................................................................... 94

FIGURE 31. DAC DSP Effects Chain ........................................................................................................... 94

FIGURE 32. ALC Example ........................................................................................................................ 96

FIGURE 33. ALC Limiter ........................................................................................................................... 97

FIGURE 34. Audio Compressor Effect ........................................................................................................ 105

FIGURE 35. Soft Knee Example with Compression Ratio Setting of 1:3.4 ............................................................. 106

FIGURE 36. Demo Board Schematic .......................................................................................................... 127

FIGURE 37. Demo Board Schematic .......................................................................................................... 128

FIGURE 38. Top Silkscreen ..................................................................................................................... 129

FIGURE 39. Top Layer ........................................................................................................................... 129

FIGURE 40. Inner Layer 2 ....................................................................................................................... 130

FIGURE 41. Inner Layer 3 ....................................................................................................................... 130

FIGURE 42. Inner Layer 4 ....................................................................................................................... 131

FIGURE 43. Inner Layer 5 ....................................................................................................................... 131

FIGURE 44. Bottom Layer ...................................................................................................................... 132

FIGURE 45. Bottom Silkscreen ................................................................................................................. 132

List of Tables

TABLE 1. PMU Register Map .................................................................................................................... 46

TABLE 2. Audio Register Map .................................................................................................................... 47

TABLE 3. Nonzero I²C Default Registers ....................................................................................................... 50

TABLE 4. 0x00h PMU Setup ...................................................................................................................... 51

TABLE 5. NV BANK (0x01h) ...................................................................................................................... 51

TABLE 6. SLEEP 1 (0x02h) ....................................................................................................................... 51

TABLE 7. FLAGS 1 (0x03h) ....................................................................................................................... 52

TABLE 8. FLAGS 2 (0x04h) ....................................................................................................................... 52

TABLE 9. BYPASS (0x05h) ....................................................................................................................... 52

TABLE 10. SWOVR 1 (0x06h) .................................................................................................................... 52

TABLE 11. SWOVR 2 (0x07h) .................................................................................................................... 53

TABLE 12. ENB1Bank 0: CONFIG = Z (0x10h) Bank 1: CONFIG = H (0x20h)Bank 2: CONFIG = L (0x30h) ...................... 53

TABLE 13. Buck 1 and Buck 2 Operation ...................................................................................................... 55

TABLE 14. ENB2 Bank 0: CONFIG = Z (0x11h) Bank 1: CONFIG = H (0x21h)Bank 2: CONFIG = L (0x31h) ..................... 55

TABLE 15. BK1VBank 0: CONFIG = Z (0x12h)Bank 1: CONFIG = H (0x22h)Bank 2: CONFIG = L (0x32h) ....................... 56

TABLE 16. BK2V Bank 0: CONFIG = Z (0x13h)Bank 1: CONFIG = H (0x23h)Bank 2: CONFIG = L (0x33h) ...................... 56

TABLE 17. LDO1 — 6 Bank 0: CONFIG = Z (0x14h:LDO1) → (0x19h:LDO6)Bank 1: CONFIG = H (0x24h:LDO1) →

(0x29h:LDO6)Bank 2: CONFIG = L (0x34h:LDO1) → (0x39h:LDO6) ............................................................... 59

TABLE 18. LDO7 Bank 0: CONFIG = Z (0x1Ah) Bank 1: CONFIG = H (0x2Ah)Bank 2: CONFIG = L (0x3Ah) .................... 60

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TABLE 19. THRESBank 0: CONFIG = Z (0x1Bh)Bank 1: CONFIG = H (0x2Bh)Bank 2: CONFIG = L (0x3Bh) ................... 61

TABLE 20. PLDWNBank 0: CONFIG = Z (0x1Ch)Bank 1: CONFIG = H (0x2Ch)Bank 2: CONFIG = L (0x3Ch) .................. 61

TABLE 21. OVRBank 0: CONFIG = Z (0x1Dh)Bank 1: CONFIG = H (0x2Dh)Bank 2: CONFIG = L (0x3Dh) ...................... 61

TABLE 22. SUBOVRBank 0: CONFIG = Z (0x1Eh)Bank 1: CONFIG = H (0x2Eh) ..................................................... 62

TABLE 23. I²C1 (0x40h) ........................................................................................................................... 62

TABLE 24. I²C2 (0x41h) ........................................................................................................................... 63

TABLE 25. BK1_FPWM (0x5Ah) ................................................................................................................. 63

TABLE 26. BK2_FPWM (0x5Eh) ................................................................................................................. 64

TABLE 27. PMC_SETUP (0x00h) ............................................................................................................... 64

TABLE 28. PMC_SETUP (0x01h) ............................................................................................................... 65

TABLE 29. PMC_SETUP (0x02h) ............................................................................................................... 65

TABLE 30. DAC Clock Requirements ........................................................................................................... 66

TABLE 31. ADC Clock Requirements ........................................................................................................... 66

TABLE 32. PLL Settings for Common System Clock Frequencies ......................................................................... 69

TABLE 33. PLL_CLOCK_SOURCE (0x03h) ................................................................................................... 70

TABLE 34. PLL_M (0x04h) ........................................................................................................................ 70

TABLE 35. PLL_N (0x05h) ........................................................................................................................ 70

TABLE 36. PLL_N_MOD (0x06h) ................................................................................................................ 71

TABLE 37. PLL_P1 (0x07h) ....................................................................................................................... 71

TABLE 38. PLL_P2 (0x08h) ....................................................................................................................... 71

TABLE 39. CLASS_D_OUTPUT (0x10h) ....................................................................................................... 72

TABLE 40. LEFT HEADPHONE_OUTPUT (0x11h) .......................................................................................... 72

TABLE 41. RIGHT HEADPHONE_OUTPUT (0x12h) ........................................................................................ 73

TABLE 42. AUX_OUTPUT (0x13h) .............................................................................................................. 73

TABLE 43. OUTPUT_OPTIONS (0x14h) ....................................................................................................... 74

TABLE 44. ADC_INPUT (0x15h) ................................................................................................................. 74

TABLE 45. MIC_INPUT (0x16h) ................................................................................................................. 75

TABLE 46. AUX_LEVEL (0x18h) ................................................................................................................. 76

TABLE 47. MONO_LEVEL (0x19h) .............................................................................................................. 77

TABLE 48. HP_SENSE (0x1Bh) ................................................................................................................. 79

TABLE 49. ADC Basic (0x20h) ................................................................................................................... 80

TABLE 50. ADC_CLK_DIV (0x21h) ............................................................................................................. 80

TABLE 51. ADC_MIXER (0x23h) ................................................................................................................ 81

TABLE 52. DAC Basic (0x30h) .................................................................................................................. 82

TABLE 53. DAC_CLK_DIV (0x31h) ............................................................................................................. 82

TABLE 54. Input Levels 1 (0x40h) ............................................................................................................... 84

TABLE 55. Input Levels 2 (0x41h) ............................................................................................................... 84

TABLE 56. Audio Port 1 Input (0x42h) .......................................................................................................... 85

TABLE 57. Audio Port 2 Input (0x43h) .......................................................................................................... 85

TABLE 58. DAC Input Select (0x44h) ........................................................................................................... 86

TABLE 59. Decimator Input Select (0x45h) .................................................................................................... 86

TABLE 60. BASIC_SETUP (0x50h/0x60h) ..................................................................................................... 89

TABLE 61. CLK_GEN_1 (0x51h/0x61h) ........................................................................................................ 89

TABLE 62. CLK_GEN_1 (0x52h/62h) ........................................................................................................... 90

TABLE 63. CLK_GEN_1 (0x53h/63h) ........................................................................................................... 90

TABLE 64. DATA_WIDTHS (0x54h/64h) ....................................................................................................... 91

TABLE 65. RX_MODE (0x55h/x65h) ............................................................................................................ 92

TABLE 66. TX_MODE (0x56h/x66h) ............................................................................................................ 93

TABLE 67. ADC EFFECTS (0x70h) ............................................................................................................. 95

TABLE 68. DAC EFFECTS (0x71h) ............................................................................................................. 95

TABLE 69. HPF MODE (0x80h) .................................................................................................................. 95

TABLE 70. ADC_ALC_1 (0x81h) ................................................................................................................. 98

TABLE 71. ADC_ALC_2 (0x82h) ................................................................................................................. 98

TABLE 72. ADC_ALC_3 (0x83h) ................................................................................................................. 99

TABLE 73. ADC_ALC_4 (0x84h) ............................................................................................................... 100

TABLE 74. ADC_ALC_5 (0x85h) ............................................................................................................... 101

TABLE 75. ADC_ALC_6 (0x86h) .............................................................................................................. 102

TABLE 76. ADC_ALC_7 (0x87h) .............................................................................................................. 102

TABLE 77. ADC_ALC_8 (0x88h) ............................................................................................................... 102

TABLE 78. ADC_L_LEVEL (0x89h) .......................................................................................................... 103

TABLE 79. ADC_R_LEVEL (0x8Ah) ........................................................................................................... 104

TABLE 80. SOFTCLIP1 (0x90h) ............................................................................................................... 107

TABLE 81. SOFTCLIP2 (0x91h) ............................................................................................................... 108

TABLE 82. SOFTCLIP3 (0x92h) ............................................................................................................... 109

TABLE 83. DAC_ALC_1 (0xA0h) .............................................................................................................. 109

TABLE 84. DAC_ALC_2 (0xA1h) .............................................................................................................. 110

TABLE 85. DAC_ALC_3 (0xA2h) .............................................................................................................. 111

TABLE 86. DAC_ALC_4 (0xA3h) ............................................................................................................. 112

TABLE 87. DAC_ALC_5 (0xA4h) ............................................................................................................. 113

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TABLE 88. DAC_ALC_6 (0xA5h) ............................................................................................................. 114

TABLE 89. DAC_ALC_7 (0xA6h) ............................................................................................................. 114

TABLE 90. DAC_ALC_8 (0xA7h) .............................................................................................................. 114

TABLE 91. DAC_L_LEVEL (0xA8h) .......................................................................................................... 115

TABLE 92. DAC_R_LEVEL (0xA9h) .......................................................................................................... 116

TABLE 93. EQ_BAND_1 (0xABh) ............................................................................................................. 117

TABLE 94. EQ_BAND_2 (0xACh) ............................................................................................................. 118

TABLE 95. EQ_BAND_3 (0xADh) ............................................................................................................. 119

TABLE 96. EQ_BAND_4 (0xAEh) ............................................................................................................. 120

TABLE 97. EQ_BAND_5 (0xAFh) .............................................................................................................. 121

TABLE 98. SOFTCLIP1 (0xB0h) ............................................................................................................... 122

TABLE 99. SOFTCLIP2 (0xB1h) ............................................................................................................... 123

TABLE 100. SOFTCLIP3 (0xB2h) ............................................................................................................. 124

TABLE 101. GPIO1 (0xE0h) .................................................................................................................... 125

TABLE 102. GPIO2 (0xE1h) .................................................................................................................... 126

TABLE 103. RESET (0xF0h) .................................................................................................................... 126

TABLE 104. Spread Spectrum (0xF1h) ....................................................................................................... 126

TABLE 105. FORCE (0xFE) .................................................................................................................... 126

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7.0 Connection Diagrams

64 Bump micro SMD

64 Bump micro SMD Marking

301282q7

Top View

XY — Date Code

TT — Die Traceability

G — Boomer

30128250

Order Number LM49360RL

See NS Package Number RLA64JBA

N6 — LM49360RL

LM49360RL Pinout Diagram

30128251

Top View (Bump Side Down)

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Ordering Information

Order Number

Package

Package DWG #

Transport Media

MSL Level

Green Status

64 Bump micro

SMDxt

RoHS and

no Sb/Br

LM49360RL

RLA64JBA

250 units on tape and reel

1

64 Bump micro

SMDxt

RoHS and

no Sb/Br

LM49360RLX

1000 units on tape and reel

1

11

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Pin Descriptions

Pin Name

VINL1

Type

Direction

Input

Description

A1

A2

Supply

Input for LDO1 and LDO2

LDO3 Output

LDO3

Output

OVR allows hardware override of the enabling of LDO1 thru LDO7, Buck 1 and Buck

2. The OVR control is enabled in the OVR and ENB2 registers. When bits in these

registers are set, a high on OVR enables the corresponding voltage source. If

CONFIG pin is high, the Bank 1 OVR register has LDO4_OVR bit set, via the

EEPROM after power-up, allowing OVR enabling of LDO4. The functionality of OVR

override is available in all modes (ie CONFIG pin L, H or Z). The OVR pin has an

internal 500KΩ pull-down resistor.

A3

OVR

Digital

Input

A4

A5

A6

LDO5

VINL3

PGND

Supply

Output

Input

LDO5 Output

Inputs for LDO5, LDO6, LDO7(HILO)

PMU and LDO ground

Input

CONFIG = Low: In AP_PMU mode, PS_HOLD is a power control input from an

external processor. CONFIG = High or High Z: In sub-PMU mode, setting the

SUBOVR/(BUCK2_EN) pin high enables BUCK2 and any combination of LDO1, 4,

5, 7 or Buck 1 that has its SUBOVR I²C register bit set to 1. In this configuration the

A7 PS_HOLD/SUBOVR Digital

Input

SUBOVR(BUCK2_EN) pin has an internal 500kΩ pull-down resistor.

A8

B1

B2

B3

B4

B5

Supply

Input

Output

Input

μPWR

LDO1

LDO2

VINL2

LDO4

LDO6

Filter point for internal μPWR LDO

LDO1 Output

LDO2 Output

Input for LDO3 and LDO4

LDO4 Output

Output

LDO6 Output

LDO7 low current output used primarily for powering an external module's standby

power input.

B6

LDO7

Supply

Output

Input

CONFIG = Low: In AP-PMU mode, PWR_ON = low enables standby mode and

PWR_ON = high turns on the BUCK and LDO outputs. The PWR_ON pin expects

to be driven by Vbatt via an external switch. CONFIG = High or High Z: In sub-PMU

mode EN = low enables standby mode and EN = high turns on the BUCK and LDO

outputs. The EN pin expects to be driven by an external processor. PWR_ON/EN

has an internal 500kΩ pull-down resistor.

B7

PWR_ON / EN

Supply

RESET_N is an open drain output that indicates that the BUCK and LDO supplies

are stable. This pin can also be programmed as a general purpose output, GPO, in

sub-PMU mode when CONFIG = High or High Z.

B8

RESET_N / GPO

Digital

Output

C1

C2

HPR

Analog

Supply

Output

Input

Headphone right output

DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog mixer (AUX and

class D), and Earpiece amplifier power supply input

A_V_DD

DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog mixer (AUX and

class D), and Earpiece amplifier ground

C3

AGND

Supply

Input

C4

C5

C6

DAC REF

ADC REF

SDA

Analog Input/Output Filter point for the DAC reference

Filter point for the ADC reference. Connect this pin to A_V_DD

I²C interface data line

.

Analog

Input

Digital Input/Output

Hardwire to DGND for Bank 2 AP-PMU operation. Hardwire to Vbatt for Bank 1 sub-

PMU operation. Leave floating for Bank 0 sub-PMU operation.

C7

CONFIG

Supply

Input

C8

D1

D2

D3

D4

D5

DGND

HPL

Supply

Analog

Input

Output

Input

Reserved pin, connect to DGND

Headphone left output

AUX_R/AUX+

AUX_L/AUX-

PORT2_SYNC

PORT2_SDI

Right analog input or positive differential auxiliary input

Left analog input or negative differential auxiliary input

Input

Digital Input/Output Audio Port 2 sync signal (can be master or slave)

Digital

Input

Audio Port 2 serial data input

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12

D6

D7

D8

E1

E2

E3

Pin Name

SCL

Type

Digital

Supply

Analog

Supply

Analog

Direction

Input

Description

I²C interface clock line

PVDD

Input

PMU power supply input

Reserved pin, connect to DGND

DGND

Input

HP_V_SS

HP_V_DD

EP-/AUXOUT-

Output

Input

Negative power supply pin for the headphone amplifier

Headphone amplifier power supply pin

Output

Earpiece negative output or Auxiliary negative output

E4 PORT2_SDO / GPIO Digital Input / Output Audio port 2 serial data output or General Purpose Input Output

E5

E6

E7

E8

F1

F2

F3

F4

F5

F6

F7

F8

G1

G2

G3

G4

G5

PORT2_CLK

MCLK

Digital Input/Output Audio port 2 clock signal (can be master or slave)

Digital

Supply

Input

Output

Input

Input clock from 0.5MHz to 50 MHz

Buck2 feedback. Active pull-down when Buck2 is off.

Input for Buck2

FB2

VINB2

CP-

Analog Input/Output Fly capacitor negative input

Analog Input/Output Fly capacitor positive input

CP+

EP+/AUXOUT+

PORT1_SYNC

PORT1_SDO

DGND

Analog

Output

Earpiece positive output or Auxiliary positive output

Digital Input/Output Audio Port 1 sync signal (can be master or slave)

Digital

Supply

Analog

Digital

Output

Input

Output

Input

Audio Port 1 serial data output

Digital ground

B2_GND

SW2

Buck2 ground

Buck2 switch output

LSGND

LSV_DD

Loudspeaker ground

Loudspeaker amplifier supply input

MONO-

MIC-

Mono differential negative input

Microphone negative input

PORT1_SDI

Audio Port 1 serial data input

DAC (Digital), ADC (Digital), PLL (Digital), digital mixer, DSP core, and I²C register

power supply input

D_V_DD

G6

Supply

Input

G7

G8

H1

H2

H3

H4

H5

H6

H7

H8

FB1

VINB1

Supply

Analog

Output

Input

Buck1 feedback. Active pull-down when Buck1 is off.

Input for Buck1

LS -

Output

Input

Loudspeaker negative output

LS +

Loudspeaker positive output

MONO+

MIC +

Mono differential positive input

Input

Microphone positive input

PORT1_CLK

I/O_V_DD

B1_GND

SW1

Digital Input/Output Audio Port 1 clock signal (can be master or slave)

Digital I/O (MCLK, I²S/PCM, I²C) interface power supply input

Supply

Input

Buck1 ground

Output

Buck1 switch output

7.1 PIN TYPE DEFINITIONS

sive components can be connected

to these pins.

Analog Input —

A pin that is used by the analog and

is never driven by the device. Sup-

plies are part of this classification.

Digital Input —

A pin that is used by the digital but is

never driven by the device.

Analog Output —

A pin that is driven by the device and

should not be driven by external

sources.

Digital Output —

A pin that is driven by the device and

should not be driven by another de-

vice to avoid contention.

Analog Input/Output — A pin that is typically used for filtering

a DC signal within the device. Pas-

Digital Input/Output —

A pin that is either open drain (SDA)

or a bidirectional CMOS in/out. In

the latter case the direction is se-

lected by a control register within the

LM49360.

13

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is programmable, 8μs, 64μs, 128μs, and 256μs. The timing

for each output can be set individually and can be different for

each of the 3 modes. The output voltage is also pro-

grammable for each power output and can also be different

for each of the 3 modes. In addition, the device supports var-

ious override modes if the user wants to optionally control an

output or leave an output on when the rest of the device is

disabled:

8.0 State Machine Description

8.1 PMU STATE MACHINE DESCRIPTION

The device is based around a power sequencer with 8 se-

lectable stages for powering up and down outputs. There are

3 modes of operation that use this sequencer with different

settings, set by the config pin. Outputs are powered down in

the opposite order from power up. The time between stages

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14

301282h9

FIGURE 4. PMU State Machine

15

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8.2 AUDIO PMC STATE MACHINE DESCRIPTION

device to reach the ON state. A command to disable the de-

vice takes 0.75k clock cycles (2.2ms) to reach the OFF state.

The stated times are based on using the low power internal

oscillator, which is typically 350kHz but can vary by as much

as 30%.

The basic premise of the audio section is that it should be

configured in shutdown and enabled via the ENABLE register

in 0x00h bit[0]. Once it has been enabled the CHIP_ACTIVE

bit is set in 0x00h bit[7]. To disable the device the user should

clear the ENABLE bit (0x00h bit[0]) and wait for the CHIP_AC-

TIVE(0x00h bit [7]) bit to clear before re-enabling the device.

Sufficient time must be given for the state transitions to com-

plete before issuing another command via I²C. A device en-

able command takes 8.5k clock cycles (typically 25ms) for the

The ENABLE bit drives a sequencer that is responsible for

controlling bias circuits, clocking, click and pop and clean op-

eration of the volume controls without requiring manual I²C

commands, a simplified overview is shown below:

30128259

FIGURE 5. LM49360 Audio PMC Sequencer Overview with Typical Timing.

The Finite State Machine (FSM) can be clocked from a divid-

ed down MCLK, an I²S PORT or an internal 350kHz oscillator.

The device will automatically control the internal clock gating

of the MCLK and Oscillator clocks. The I²S clock inputs are

not automatically gated to allow to digital bypass modes when

the analog codec circuits are disabled. The FSM can be

clocked faster if required - the maximum clock speed to the

PMC is 14MHz.

8.2.1 State_0 (OFF)

In this state the internal clocks and oscillators are disabled

(unless an OVR bit in register 0x00 is set). The device is un-

biased and only leakage current is drawn from the supplies.

The I²C port is controllable and all control registers are free

to be changed.

When the ENABLE bit is set the device enables either the

MCLK pad or low power oscillator and waits 2 clock cycles

before rechecking the ENABLE bit. If it is still set the device

proceeds to STATE_1, otherwise the device remains in

STATE_0 and the deglitching digital flip-flops are disabled

and reset.

The user can use the internal oscillator for the PMC and it will

only enable the oscillator when required (the low power os-

cillator is reused by many circuits in the device that require

delays, the PMC controls when it should be enabled). If the

PMC is not using the oscillator (i.e. PMC_CLK_SEL is set to

MCLK) it will remain off unless another circuit requires it. The

PMC will also automatically control the MCLK input buffer to

reduce power on chip but the power spent driving the PCB

trace to the MCLK pin makes the oscillator the preferred so-

lution. The only advantage to using an external pin is where

precise timing of the sequencer is needed. When an external

clock is required it should not be removed until the device has

reached the OFF condition. The function and timing of each

stage is detailed below:

8.2.2 State_1 (BIAS)

In state 1 the device enables its internal references and com-

mon mode points. The preamplifiers to analog inputs are

enabled and the PMC starts to inject current into decoupling

caps. The PMC clock is started and the clocking circuits are

readied. The mixer and amplifiers remain muted.

The device waits 8192 clock cycles (typically 23 to 24ms using

the internal oscillator, enough time for the common mode

points to reach vcm and start to settle without any audible click

and pop or coupling back to driving circuits) before moving to

the next stage.

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16

8.2.3 State_2 (AMPS ON)

ondary state machine notes a change in the requested state

for each amplifier and requests a clock and a 10ms count-

down from the PMC clock domain so it can proceed to safely

change the gain of the amplifier.

Once the common mode points have settled, the amplifiers

power up with their inputs muted. Any calibration takes place

at this stage. Protection circuits enable and the I/O amplifiers

(not the analog mixer yet) are allowed to unmute once vcm

has settled, ensuring better settling of the common mode

throughout the muted mixer.

The amp control FSM checks the current gain and signal

routing and if required (if zipper or click and pop is a risk) en-

ables a small differential comparator on the output of the amp.

8.2.3.1 AMPLIFIER CONTROL FSM

The muting, unmuting and volume control is always handled

by a separate state machine for each amplifier. This sec-

301282i0

FIGURE 6. Zero Cross Detect Comparator (ZXD)

The controller waits 1ms for this comparator to stabilize then

monitors the output of the comparator for a Zero Crossing

Event. At this exact moment the new gain or mute/unmute

condition is applied to the amplifier (in conjunction with any

changes required to the rest of the analog mixer to ensure

click and pop free operation). The comparator is then pow-

ered down. If no zero crossing occurs after 11ms (assume

audio content at frequencies above 36Hz) the changes are

applied regardless and the controller returns to a zero power

state.

monitored for a falling edge. Once a deglitched falling edge is

seen the FSM moves to state 5.

8.2.6 State_5 (MUTE)

The output stages are muted first using the amplifier control

FSM for each channel. The digital logic circuits are also muted

and cleared at this stage. Once the amplifiers are muted and

1ms has passed (256 clock cycles) the PMU moves to state

6. CHIP_ACTIVE is cleared at this stage.

8.2.7 State_6 (AMPS_OFF)

The PMC leaves STATE_2 after 256 clock cycles (about

1ms).

With the output stages muted the I/O amplifiers can be dis-

abled, only the ADCs and DACs remain enabled, flushing out

any residual data from their filters. The device waits another

256 clock cycles.

8.2.4 State_3 (UNMUTE)

In state 3 the audio DACs and ADCs have been cleared and

are unmuted then the digital and analog mixers are unmuted.

8.2.8 State_7 (OFF)

The PMC leaves STATE_3 after 256 clock cycles (about

1ms).

The Bias circuits are disabled and the common mode and

reference bypass points are allowed to discharge. The MCLK

and oscillator are disabled and power is leakage only.

8.2.5 State_4 (ON)

The PMC now sets the CHIP_ACTIVE flag (0x00h bit[7]). The

internal timers are all powered down. The ENABLE pin is

17

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Human Body Model (Note 4)

Machine Model (Note 5)

Charged Device Model

Junction Temperature

Thermal Resistance

2kV

150V

500V

150°C

9.0 Absolute Maximum Ratings (Note

1, Note 2)

If Military/Aerospace specified devices are required,

please contact the Texas Instruments Sales Office/

Distributors for availability and specifications.

ꢀθ_JA– RLA64 (soldered down

to PCB with 2in²1oz. copper plane)

Analog Supply Voltage

60°C/W

(A_V_DDand LS_V_DD

)

6.0V

2.2V

5.5V

3.0V

6.0V

Soldering Information

See Applications Note AN-1112.

Digital Supply Voltage

D_V_DD

I/O Supply Voltage

I/O_V_DD

10.0 Operating Ratings

Ambient Temperature Range

T_A

Headphone Supply Voltage

HP_V_DD

−40°C to +85°C

Supply Voltage

A_V_DD, ADCREF

D_V_DD

I/O_V_DD

HP_V_DD

Buck Input Supply Voltage

V_INB1, V_INB2

2.8V to 5.5V

1.6V to 2.0V

1.6V to 4.5V

1.7V to 2.8V

LDO Input Supply Voltage

V_INL1, V_INL2, V_INL3

6.0V

−65°C to +150°C

Storage Temperature

Maximum Continuous Power

PV_DD, LSV_DD, V_INB1

V_INB2,V_INL1,V_INL2,V_INL3

3.0V to 5.5V

Dissipation (Note 3)

2.0W

ESD Ratings

11.0 Total Shutdown Current Consumption

Unless otherwise noted, PV_DD= V_IN1= V_IN2= V_IN3= V_INB1= V_INB2= 3.6V, C_VINB1= C_VINB2= 4.7µF, C_VIN1= C_VIN2= C_VIN3= 10µF,

A_V_DD= LS_V_DD= 3.6V, HP_V_DD= D_V_DD= IO_V_DD= 1.8V. Typical values and limits appearing in boldface type apply over the

entire ambient temperature range for operation, T_A= –40 to +85°C. (Note 7).

Symbol

Parameter

Condition

Min

Typ

Max

Units

PMU Standby Conditions: All outputs

disabled, (Note 12)

Total

I_{Q (SHUTDOWN)}

Total Shutdown Current

9.1

20

Audio CODEC Conditions:

Shutdown Mode, f_MCLK= 13MHz,

PLL Off

μA

12.0 PMU Current Consumption

Unless otherwise noted, PV_DD= V_IN1= V_IN2= V_IN3= V_INB1= V_INB2= 3.6V, C_VINB1= C_VINB2= 4.7µF, C_VIN1= C_VIN2= C_VIN3= 10µF.

Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing in boldface type apply over the ambient

junction temperature range for operation, T_A= –40 to +85°C. (Note 7).

Symbol

Parameter

Standby Current

Condition

Min

Typ

Max

Units

I_{Q (STANDBY)}

All outputs disabled, (Note 12)

4.5

10.2

µA

Current in SLEEP Mode

at no load

I

All outputs enabled

105

150

µA

Q_(SLEEP)

I_{Q (IDLE)}

Current at no load

All outputs enabled

Only Buck 1 enabled

365

145

450

170

µA

I_{Q (IDLE 1)}

μA

Only Buck 1, LDO1, LDO2, LDO3,

and LDO6 enabled

I_{Q (IDLE 2)}

Current at no load

250

300

μA

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18

13.0 Thermal Shutdown

The Thermal Shutdown (TSD) function monitors the chip temperature to protect the chip from temperature damage caused by

excessive power dissipation. There are a total of three thermal monitors on the LM49360, with one monitoring the upper limit audio

section, another acting as an early warning flag for the PMU section, and a third monitoring the upper limit of the PMU section.

(Note 7).

Symbol

Parameter

Condition

Min

Typ

Max

Units

Upper Limit (Automatic)

160

°C

TSD_PMU

PMU Thermal Shutdown

Lower Limit

(Acts as an early warning flag)

120

°C

TSD_AUDIO

TSD_HYST

Audio Codec Thermal Shutdown (Automatic)

TSD Hysteresis

155

20

°C

14.0 Under Voltage Lock Out

This device has Under Voltage Lock Out (UVLO) that checks the PV_DDpin voltage before enabling any of the PMU outputs (LDO’s

1 thru 7, Buck 1 and Buck 2), this occurs during the PMU state machine DELAY (state 6). If the PV_DDis below the UVLO threshold

the PMU state machine returns to the STANDBY (state 3) and the PMU outputs remain disabled. If PV_DDis greater than the UVLO

threshold than the selected PMU outputs are enabled. Upon enabling the PMU outputs the PV_DDpin voltage is continuously

monitored to determine if it is above the UVLO threshold. If the PV_DDdrops below the UVLO threshold an UVLO_EVENT occurs

and the PMU state machine returns to the STANDBY state and the PMU outputs are disabled.

Symbol

Parameter

UVLO threshold

Hysteresis

Condition

Min

Typ

2.8

80

Max

Units

V

UVLO_VSEL = 1010b

mV

15.0 Logic and Control

Unless otherwise noted, PVDD = V_IN1= V_IN2= V_IN3= V_INB1= V_INB2= 3.6V, C_VINB1= C_VINB2= 4.7µF, C_VIN1= C_VIN2= C_VIN3= 10µF.

Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing in boldface type apply over the entire

ambient temperature range for operation, T_A= –40 to +85°C. (Note 7).

Symbol

Parameter

Condition

Min

Typ

Max

Units

Logic and Control Inputs

MCLK, PORT1_CLK, PORT1_WS,

PORT1 _SDI, PORT2_CLK,

PORT2_WS, PORT2_SDI,

PORT2_SDO/GPIO

0.3 x I/

O_V_DD

V

V_IL

Input Low Level

Input High Level

0.3 x

V_BATT

SCL, SDA CONFIG

SCL, SDA, MCLK, PORT1_CLK,

PORT1_WS, PORT1 _SDI,

PORT2_CLK, PORT2_WS,

0.7x I/

O_V_DD

V_IH

V

PORT2_SDI, PORT2_SDO/GPIO

0.7 x

V_BATT

CONFIG

V

SCL, SDA, PS_HOLD / SUBOVR

(BUCK2_EN), PWR_ON / EN, OVR

(LDO4_EN), CONFIG

I_IL

Input Low Level Current

0.1

0.5

6.0

µA

V_IL= 0V

PS_HOLD / SUBOVR (BUCK2_EN),

PWR_ON

I_IH

Input High Level Current

Pull Down Resistance

4.7

µA

V_IH= V_IN1

From PWR_ON / EN, PS_HOLD /

SUBOVR (BUCK2_EN), OVR

(LDO4_EN)

R_PD

800

kΩ

Logic and Control Outputs

19

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Symbol

V_OL

Parameter

Output Low Level

Condition

Min

Typ

Max

Units

SDA, RESET_N, I_OUT= 2mA

0.4

V

0.3 x I/

O_V_DD

PORT1_SDO, PORT2_SDO/GPIO

SDA, RESET_N

V

Open

Drain

V_OH

Output High Level

0.7 x

I/O_V_DD

PORT1_SDO, PORT2_SDO/GPIO

V

16.0 Electrical Characteristics / Buck Converters

Unless otherwise noted, PV_DD= V_INB1= V_INB2= 3.6V, C_VINB1= C_VINB2= 4.7µF. Typical values and limits appearing in normal type

apply for T_J= 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, T_A= –40 to

+85°C. (Note 7, Note 8)

Symbol

Parameter

Condition

PWM Mode, No load

Min

Typ

Max

Units

-3

3

%

V_OUT= 1.1V to 1.8V

PWM Mode, No load

V_OUT= 0.6V to 1.0V

V_FB

Feedback Voltage

-3.7

3.7

229

630

200

%

ECO Mode, FB = V_IN,

No Switching

I_{Q_ECO}

ECO Mode IQ

60

µA

PWM Mode, FB = V_IN,

No Switching

I_{Q_PWM}

R_DSON(P)

PWM Mode IQ

465

170

V_IN= VGS = 3.6V

I_OUT= 200mA

Pin-Pin resistance for NMOS

mΩ

V_IN= V_GS= 3.6V

I_OUT= -200mA

R_DSON(N)

Pin-Pin resistance for NMOS

100

120

I_LIM

Switch Peak Current Limit

Start Up Time

Open-loop, programmable

I_OUT= 0mA to 100mA

PWM Mode

1020

3.8

1200

50

1360

mA

µs

t_STARTUP

f_SW

Switching frequency

4

4.2

MHz

17.0 Electrical Characteristics / General LDOs 1 to 6

Unless otherwise noted, PV_DD= V_IN1= V_IN2= V_IN3= 3.6V, GND = 0V, C_VIN1= C_VIN2= C_VIN3= 10µF. Typical values and limits

appearing in normal type apply for T_J= 25°C. Limits appearing in boldface type apply over the entire ambient temperature range

for operation, T_A= –40 to +85°C. (Note 7)

Symbol

Parameter

Condition

Min

-2

Typ

Max

2

Units

%

V_OUT

I_OUT= 1mA, V_OUT= 2.85V

Output Voltage Accuracy

-3

3

%

V_OUT= 0V

780

mA

LDO1, LDO3

I_SC

Output Current Limit

V_OUT= 0V

400

140

mA

mV

LDO2, LDO4, LDO5, LDO6

I_OUT= I_MAX(Note 9)

V_DO

Dropout Voltage

Line Regulation

250

V_OUT+ 0.5V ≤ V_IN≤ 4.5V

I_OUT= I_MAX

1.0

mV

ΔV_OUT

(Note 10)

1mA < I_OUT< I_MAX

Load Regulation

4

mV

mA

LDO1, LDO3

400

200

440

250

20

I_MAX

Max Output Current

LDO2, LDO4, LDO5, LDO6

I_SLEEP

Max Output Current in sleep Mode

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20

Symbol

e_N

Parameter

Condition

10Hz < f < 100kHz

Min

Typ

Max

Units

I_OUT= I_MAX

µV_RMS

Output Voltage Noise

13

C_OUT= 1µF

f = 10KHz, C_OUT= 1µF

I_OUT= 20mA

PSRR

Power Supply Rejection Ratio

36

dB

t_STARTUP

I_OUT= I_MAX, C_OUT= 1µF

I_OUT= I_MAX(Note 11)

Start-up Time from Shutdown

Start-up Transient Overshoot

25

20

µs

V_TRANSIENT

mV

External Output Capacitance for

Stability

C_OUT

(Note 11)

0.6

1

20

µF

18.0 Electrical Characteristics / High Input Low Output LDO 7

Unless otherwise noted, PV_DD= V_IN3= 3.6V, GND = 0V, C_VIN3= 10µF. Typical values and limits appearing in normal type apply

for T_J= 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, T_A= –40 to +85°

C. (Note 7)

Symbol

Parameter

Condition

I_OUT= 1mA, V_OUT= 1.2V

I_OUT= 1mA, V_OUT= 1.2V,

over temperature

Min

Typ

Max

Units

-2

2

%

V_OUT

Output Voltage Accuracy

-3

3

%

I_OUT

I_SC

V_OUT+ 0.5V < V_IN3< 5.5V

Max Output Current

Output Current Limit

20

40

mA

V_OUT= 0V

I_OUT= 20mA

(Note 9)

110

V_DO

Dropout Voltage

54

65

mV

V_OUT+ 0.5V ≤ V_IN3≤ 5.5V,

I_OUT= 20mA (Note 10)

Line Regulation

Load Regulation

0.5

53

mV

ΔV_OUT

1mA < I_OUT< 20mA

10Hz = f = 100kHz

I_OUT= 20mA; No C_OUT

10Hz = f = 100kHz

I_OUT= 20mA; C_OUT= 10µF

f = 10kHz, C_OUT= 1µF

I_OUT= 2mA

µV_RMS

e_N

Output Voltage Noise

µV_RMS

dB

90

35

PSRR

Power Supply Rejection Ratio

f = 10kHz, C_OUT= 1µF

I_OUT= 20mA

dB

t_STARTUP

I_OUT= 20mA ; C_OUT= 1µF

I_OUT= 0mA to 2mA

I_OUT= 2mA to 0mA

Start-up Time from Shutdown

Load Transient Overshoot

Start-up Transient Overshoot

60

–55

55

µs

mV

V_LOADTRANS

V_TRANSIENT

C_OUT

I_OUT= 20mA; C_OUT= 1μF(Note 11)

(Note 11)

20

External Output Capacitance for

Stability

0.6

1

20

µF

21

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19.0 Electrical Characteristics / Audio CODEC: A_V_DD= LS_V_DD= 3.6V;

HP_V_DD= D_V_DD= I/O_V_DD= 1.8V (Note 1, Note 2) The following specifications apply for R_L(LS)= 8Ω,

R_L(HP)= 32Ω, f = 1kHz, unless otherwise specified. Limits apply for T_A= 25°C.

LM49360

Units

(Limit)

Symbol

Parameter

Conditions

Typical

Limit

(Note 6) (Note 7)

DC CHARACTERISTICS (Digital current combines D_V_DDand I/O_V_DD. Analog current combines A_V_DD, HP_V_DD

,

and LS_V_DD

)

Shutdown Mode,

f_MCLK= 13MHz, PLL Off

DI_SD

Digital Shutdown Current

4

10

1.4

0.5

1.5

µA

f_MCLK= 11.2896MHz, f_S= 44.1kHz,

Stereo DAC On, OSR_DAC= 64,

PLL Off, HP On

Digital Active Current (MP3 Mode)

Digital Active Current (FM Mode)

1.2

0.2

1.3

mA (max)

f_MCLK= 13MHz

Analog Audio modes

f_MCLK= 12.288MHz, f_S= 48kHz,

Stereo ADC On, OSR_ADC= 128,

PLL Off, Stereo Analog Inputs On

DI_DD

Digital Active Current

(FM Record Mode)

f_MCLK= 12.288MHz, f_S= 8kHz,

Mono ADC On, Mono DAC On,

OSR_DAC= 64

Digital Active Current

(CODEC Mode)

0.7

0.1

0.8

9

mA (max)

OSR_ADC= 128, PLL Off, MIC On

AI_SD

Analog Shutdown Current

Shutdown Mode

μA (max)

f_MCLK= 11.2896MHz, f_S= 44.1kHz, Stereo DAC On,

OSR_DAC= 64, PLL Off, Stereo HP On

Analog Supply Current (MP3 Mode)

From A_V_DD

4.6

1.7

6

mA (max)

From HP_V_DD

2.7

f_MCLK= 13MHz, PLL Off

Stereo Auxiliary Inputs On,

PLL Off, Stereo HP On

Analog Supply Current (FM Mode)

From A_V_DD

1.8

1.6

2.6

2.7

mA (max)

AI_DD

From HP_V_DD

f_MCLK= 12.288MHz, f_S= 48kHz,

Stereo ADC On, OSR_ADC= 128,

PLL Off, Stereo Analog Inputs On

Analog Supply Current

(FM Record Mode)

7.3

9.3

mA (max)

f_MCLK= 12.288MHz, f_S= 8kHz,

Mono ADC On, Mono DAC On,

OSR_DAC= 64

Analog Supply Current

(CODEC Mode)

7.0

8.7

mA (max)

OSR_ADC= 128, PLL Off, MIC On,

EP On

f_MCLK= 13MHz, f_PLLOUT= 12MHz, PLL On only

PLLI_DD

From A_V_DD

PLL Total Active Current

1.9

1.4

1.6

2.4

0.4

2.7

2

mA (max)

mA

From D_V_DD

Stereo HP On only

LS On only

HPI_DD

LSI_DD

Headphone Quiescent Current

Loudspeaker Quiescent Current

Microphone Quiescent Current

mA

MICI_DD

Mono MIC

mA

f_s= 48kHz, Stereo

From A_V_DD

ADCI_DD

DACI_DD

ADC Total Active Current

DAC Total Active Current

6.5

1.4

mA

From D_V_DD

f_S= 48kHz, Stereo

From A_V_DD

3.5

1.0

mA

From D_V_DD

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22

LM49360

Typical Limit

(Note 6) (Note 7)

Units

(Limit)

Symbol

Parameter

Conditions

Mono/Auxiliary Input Amplifier

Quiescent Current

Mono and AUX Input Amplifiers

enabled

AUXINI_DD

0.6

mA

AUXOUT enabled

Earpiece Mode

0.5

1.2

mA

Auxiliary Output Amplifier Quiescent

Current

AUXOUTI_DD

LOUDSPEAKER AMPLIFIER

P_O= 940mW, R_L= 8Ω,

LS_VDD = 4.2V

LS_EFF

Loudspeaker Efficiency

87

%

P_O= 300mW, f = 1kHz,

R_L= 8Ω, Mono Input Signal

THD+N

Total Harmonic Distortion + Noise

0.06

R_L= 8Ω, f = 1kHz, THD+N = 1%, Mono Input Signal

LS_V_DD= 5V

LS_V_DD= 4.2V

LS_V_DD= 3.6V

1.3

900

595

W

mW

555

mW (min)

P_O

Output Power

R_L= 4Ω, f = 1kHz, THD+N = 1%, Mono Input Signal

LS_V_DD= 5V

LS_V_DD= 4.2V

LS_V_DD= 3.6V

2.2

1.6

W

950

mW

V_RIPPLE= 200mV_P-P

f_RIPPLE= 217Hz

Mono Input Terminated

V_REF= 1.0μF, Input Referred

LS Gain = 12dB

82

65

dB (min)

dB

PSRR

Power Supply Rejection Ratio

V_RIPPLE= 200mV_P-P

f_RIPPLE= 217Hz

80

From DAC, DAC gain = 0dB

Reference = V_OUT(1% THD+N ), Mono gain = 0dB

A-weighted, Mono Input Terminated, LS Gain = 8dB

LS_V_DD= 4.2V

LS_V_DD= 3.6V

92

91

dB

85

dB (min)

SNR

Signal-to-Noise Ratio

Reference = V_OUT(1% THD+N ), DAC Gain = 0dB, A-weighted

f_S= 48kHz, OSR = 128 LS Gain = 8dB

LS_V_DD= 4.2V

LS_V_DD= 3.6V

84

83

dB

e_OS

V_OS

Mono gain = 0dB, A-weighted,

Mono Input Terminated, Input Referred

Output Noise

Offset Voltage

90

10

µV

Mono gain = 0dB, from Mono Input

50

mV (max)

HEADPHONE AMPLIFIERS

P_O= 15mW, f = 1kHz,

R_L= 32Ω

THD+N Total Harmonic Distortion + Noise

0.03

0.1

% (max)

Stereo Analog Input Signal

R_L= 32Ω, f = 1kHz, THD+N = 1%,

Stereo Analog Input Signal, In phase

HP_V_DD= 2.8V

70

23

mW

HP_V_DD= 1.8V

18.5

mW (min)

P_O

Headphone Output Power

R_L= 16Ω, f = 1kHz, THD+N = 1%,

Stereo Analog Input Signal, In phase

HP_V_DD= 2.8V

70

25

mW

HP_V_DD= 1.8V

23

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LM49360

Typical Limit

(Note 6) (Note 7)

Units

(Limit)

Symbol

Parameter

Conditions

V_RIPPLE= 200mV_P-P, f_RIPPLE= 217Hz, Mono Input Terminated

Mono gain = 0dB V_REF= 1.0μF, Mono Differential Input Mode,

Ripple applied to AV_DDonly

100

92

82

dB (min)

dB

Ripple applied to AV_DDand HPV_DD

PSRR

Power Supply Rejection Ratio

V_RIPPLE= 200mV_P-P, f_RIPPLE= 217Hz

From DAC, DAC gain = 0dB

Ripple applied to AV_DD

90

95

dB

HPV_DD, and DV_DD

Reference = V_OUT(1% THD+N )

Gain = 0dB, A-weighted

Stereo Inputs Terminated

90

92

dB (min)

SNR

Signal to Noise Ratio

Output Noise

Reference = V_OUT(1% THD+N),

Gain = 0dB,

97

dB (min)

A-weighted, I²S Input = Digital Zero

Gain = 0dB, A-weighted,

Stereo Inputs Terminated

12

13

µV

e_OS

Gain = 0dB, A-weighted,

I²S Input = Digital Zero

P_O= 7.5mW, f = 1kHz, R_L= 32Ω

Stereo Analog Input Signal

X_TALK

Crosstalk

85

dB

ΔA_CH-CH

Channel-to-Channel Gain Matching

0.03

0.25

AUX Gain = 0dB

From mono Input

1

mV (max)

V_OS

Output Offset Voltage (Note 13)

DAC Gain = 0dB

From DAC Input, f_MCLK= 12.288MHz

0.25

mV (max)

%

AUXILIARY OUTPUT/EARPIECE AMPLIFIER

AUX_LINE_OUT, f = 1kHz

From Mono In

0.006

R_L= 5kΩ, V_OUT= 1V_RMS

THD+N

Total Harmonic Distortion

Output Power

Earpiece mode, f = 1kHz,

From Mono In

0.03

60

%

mW (min)

dB

R_L= 32Ω BTL, P_OUT= 20mW

Earpiece mode, f = 1kHz

P_OUT

50

85

R_L= 32Ω BTL, THD+N = 1%

V_RIPPLE= 200mV_P-P, f_RIPPLE= 217Hz

Mono Input terminated, C_REF= 1.0μF

AUX_LINE_OUT

80

PSRR

SNR

Power Supply Rejection Ratio

V_RIPPLE= 200mV_P-P, f_RIPPLE= 217Hz

Mono Input terminated, C_REF= 1.0μF

Earpiece mode,

–6dB cut enabled

100

dB

Gain = 0dB, V_REF= V_OUT(1% THD+N)

A-weighted, Mono Input Terminated

Gain = 0dB, V_REF= V_OUT(1% THD+N)

A-weighted, Mono Input Terminated

Signal to Noise Ratio

Output Noise

101

11.4

4.2

∈

μV

OUT

MONO gain = 0dB, From Mono Input

AUX_LINE_OUT

mV

V_OS

Output Offset Voltage

Turn-On time

Gain = 0dB, From Mono Input

Earpiece mode

3

10

mV (max)

ms

T_WU

PMC Clock = 300kHz

29

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24

LM49360

Typical Limit

(Note 6) (Note 7)

Units

(Limit)

Symbol

Parameter

Conditions

STEREO ADC

THD+N_ADC

Mono Differential Input

V_IN= 1V_RMS, f = 1kHz

Gain = 0dB, f_S= 48kHz

ADC Total Harmonic Distortion

+ Noise

0.008

220

%

HPF On, f_S= 48kHz

Lower -3dB Point

Hz

PB_ADC

ADC Passband

ADC Ripple

0.41*f_S

0.1

HPF On, Upper -3dB Point

OSR_DAC= 128

kHz

dB

R_ADC

Reference = V_OUT(0dBFS )

Gain = 6dB

96

dB

A-weighted From MIC, f_S= 8kHz

SNR_ADC

ADC Signal to Noise Ratio

ADC Full Scale Input Level

Reference = V_OUT(0dBFS )

Gain = 0dB

A-weighted From Stereo Input,

f_S= 48kHz

98

dB

ADC_LEVEL

V_RMS

1.65

STEREO DAC

I²S Input, AUXOUT, OSR_DAC= 64

V_IN= 500mFFS_RMS, f = 1kHz

Gain = 0dB

DAC Total Harmonic Distortion

+ Noise

THD+N_DAC

0.015

%

DAC_LEVEL

R_DAC

V_RMS

dB

DAC Full Scale Output Level

DAC Ripple

1.1

0.1

PB_DAC

0.45*f_S

96

DAC Passband

Upper –3dB Point

kHz

dB

SNR_DAC

f_S= 48kHz, A-weighted, AUXOUT

DAC Signal to Noise Ratio

VOLUME CONTROL

Minimum Gain

Maximum Gain

Minimum Gain

Maximum Gain

Minimum Gain

Maximum Gain

Minimum Gain

Maximum Gain

Minimum Gain

Maximum Gain

Minimum Gain

Maximum Gain

Minimum Gain

Maximum Gain

–46.5

18

dB

VCR_AUX

VCR_MONO

VCR_DAC

VCR_ADC

VCR_MIC

VCR_LS

Stereo Input Volume Control Range

MONO Input Volume Control Range

DAC Volume Control Range

–46.5

18

–76.5

18

–76.5

18

ADC Volume Control Range

6

MIC Volume Control Range

36

0

Loudspeaker Amplifier Volume

Control Range

12

–18

0

Headphone Amplifier Volume

Control Range

VCR_HP

SS_LS

Loudspeaker Amplifier Volume

Control Stepsize

4

dB

Headphone Amplifier Volume

Control Stepsize

Refer to

Table 45

SS_HP

dB

SS_AUX

SS_MONO

AUX Input Volume Control Stepsize

1.5

MONO Input Volume Control

Stepsize

1.5

SS_DAC

SS_ADC

SS_MIC

DAC Volume Control Stepsize

ADC Volume Control Stepsize

MIC Volume Control Stepsize

1.5

2

dB

25

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LM49360

Typical Limit

(Note 6) (Note 7)

Units

(Limit)

Symbol

SV_AUX

Parameter

Conditions

AUX Volume Setting Variation

MONO Volume Setting Variation

MIC Volume Setting Variation

±1

dB (max)

dB (min)

dB (max)

SV_MONO

SV_MIC

ANALOG INPUTS

AUX Gain = 18dB

10

38

64

10

38

64

50

kΩ

AUX_R_IN

Auxiliary Input Impedance

AUX Gain = 0dB

AUX Gain = –46.5dB

MONO Gain = 18dB

MONO Gain = 0dB

MONO Gain = –46.5dB

All MIC gain settings

MONO_R_IN

MIC_R_IN

Mono Input Impedance

Microphone Input Impedance

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. LSV_DDmust always

be the highest input power supply, LSV_DD≥ PV_DD, AV_DD, IOV_DD, Vin and must be supplied first during initial power-up.

Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T_JMAX, θ_JA, and the ambient temperature, T_A. The maximum

allowable power dissipation is P_DMAX= (T_JMAX- T_A) / θ_JAor the number given in Absolute Maximum Ratings, whichever is lower.

Note 4: Human body model, applicable std. JESD22-A114C.

Note 5: Machine model, applicable std. JESD22-A115-A.

Note 6: Typical values represent most likely parametric norms at T_A= +25ºC, and at the Recommended Operation Conditions at the time of product

characterization and are not guaranteed.

Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.

Note 8: The parameters in the electrical characteristic table are tested under open loop conditions at V_IN= 3.6V unless otherwise specified. For performance

over the input voltage range and closed loop condition, refer to the datasheet curves.

Note 9: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value.

Note 10: The minimum input voltage equals Vout (nom) + 0.5V or 3.0V, which ever is greater.

Note 11: This specification is guaranteed by design.

Note 12: If CONFIG = L, the device can be placed in the standby state by de-asserting the PS_HOLD and PWR_ON pins as shown in Figure 14. If CONFIG =

H or Z, the device can be placed in the standby state by de-asserting the EN pin as shown in Figure 13. None of the software Override (SWOVR) bits can be set

or the device will not be in the standby state.

Note 13: V_OSis reduced through auto-calibration. The procedure to start auto-calibration is to make sure the audio section is disabled by setting chip enable = 0

in audio register 0x00. Select the audio path. Enable audio with chip enable = 1. Wait 500 microseconds for the calibration to complete.

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26

20.0 Timing Characteristics: DV_DD= I/OV_DD= 1.8V (Note 1, Note 2) The following specifications

apply for R_L(SP)= 8Ω, R_L(HP)= 32Ω, f = 1kHz, unless otherwise specified. Limits apply for T_A= 25°C.

LM49360

Units

Symbol

PLL

f_IN

Parameter

Conditions

Typical

Limit

(Limit)

(Note 6)

(Note 7)

Minimum MCLK Frequency

Maximum MCLK Frequency

0.5

50

MHz (min)

MHz (max)

PLL Input Frequency Range

I²S MASTER TIMING

I2S_CLK_PER

tCLK_L

I²S Master

I2S_CLK Period

81.38

37

ns

I2S_CLK Low Time

I2S_CLK High Time

tCLK_H

37

WS Propagation Delay from I2S_CLK

falling edge

t_{WS_DLY}

t_{SDO_DLY}

t_DST

I²S Master

21

20

ns

SDO Propagation Delay from I2S_CLK

falling edge

SDI Setup Time to I2S_CLK Rising

Edge

SDI Hold Time to I2S_CLK Rising

Edge

t_DHT

I²S SLAVE TIMING

I2S_CLK_PER

tCLK_L

I²S Slave

I2S_CLK Period

81.38

37

ns (min)

I2S_CLK Low Time

I2S_CLK High Time

tCLK_H

37

SDO Propagation Delay from I2S_CLK

falling edge

t_{SDO_DLY}

t_DST

I²S Slave

21

ns

SDI Setup Time to I2S_CLK Rising

Edge

20

ns (min)

SDI Hold Time to I2S_CLK Rising

Edge

t_DHT

WS Setup Time to I2S_CLK Rising

Edge

t_{WS_ST}

t_{WS_HT}

WS Hold Time to I2S_CLK Rising

Edge

CONTROL INTERFACE TIMING

SCL Frequency

400

0.6

kHz (max)

Hold Time (repeated START

Condition)

1

μs (min)

2

3

Clock Low Time

Clock High Time

1.3

μs (min)

ns (min)

600

Setup Time for a Repeated START

Condition

4

600

50

ns (min)

Output

(LM49360 generated)

5

Data Hold Time

Input

(Master generated)

50

6

7

8

9

Data Setup Time

100

300

600

ns (min)

ns (max)

ns (min)

Rise Time of SDA and SCL

Fall Time SDA and SCL

Setup Time for STOP Condition

27

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LM49360

Units

(Limit)

Symbol

Parameter

Conditions

Typical

(Note 6)

Limit

(Note 7)

Bus Free Time Between a STOP and

START Condition

10

C_B

1.3

μs (min)

Bus Capacitance

200

pF (max)

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28

21.0 Typical Performance Characteristics

Class D Loudspeaker Amplifier Efficiency

vs Output Power

DAC Frequency Response

f_S= 48kHz

Blue >> OSR = 64

THD+N < 10%, R_L= 8Ω

Green >> LSV_DD= 3.6V

Gray >> LSV_DD= 4.2V

Light Blue >> OSR = 128

Blue >> LSV_DD= 5V

100

90

80

70

60

50

40

30

20

10

0

301282b3

0

400

800

1200 1600

2000

OUTPUT POWER (mW)

301282b2

DAC Frequency Response

f_S= 8kHz

DAC THD+N vs Frequency

f_S= 48kHz, OSR = 128

I²S Input = 500mFFS

Blue >> OSR = 64

Light Blue >> OSR = 128

30128277

301282b4

29

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DAC THD+N vs Frequency

f_S= 48kHz, OSR = 64

I²S Input = 500mFFS

DAC THD+N vs Input Level

f_S= 48kHz, OSR = 64

I²S Input = 1kHz

30128285

301282b8

Stereo Audio ADC Frequency Response

f_S= 48kHz, OSR = 64

From MIC, MIC Gain = 6dB, C_IN= 1µF

Stereo Audio ADC Frequency Response

f_S= 8kHz, OSR = 128

From MIC, MIC Gain = 6dB, C_IN= 1µF

301282b9

301282c0

Mono Voice ADC Frequency Response

f_S= 48kHz, OSR = 128

From MIC, MIC Gain = 6dB, C_IN= 1µF

Mono Voice ADC Frequency Response

f_S= 8kHz, OSR = 128

From MIC, MIC Gain = 6dB, C_IN= 1µF

301282a0

30128222

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30

Stereo Audio HPF ADC Frequency Response

f_S= 48kHz, OSR = 128

From MONO/AUX, MONO>AUX Gain = 0dB, C_IN= 1µF

Gray >> No HPF

Mono Voice HPF ADC Frequency Response

f_S= 48kHz, OSR = 128

From MIC, MIC Gain = 6dB, C_IN= 1µF

Gray >> No HPF

Yellow >> HPF Mode = '000'

Light Green >> HPF Mode = '001'

Green >> HPF Mode = '010'

Light Blue >> HPF Mode = '011'

Blue >> HPF Mode = '100'

Green >> HPF Mode = '101'

Light Blue >> HPF Mode = '110'

Blue >> HPF Mode = '111'

301282a4

301282a5

Mono Voice HPF ADC Frequency Response

f_S= 8kHz, OSR = 128

ADC THD+N vs Frequency

f_S= 48kHz, OSR = 128

From MONO/AUX, MONO/AUX Gain = 0dB, V_IN= 1V_RMS

From MIC, MIC Gain = 6dB, C_IN= 1µF

Gray >> No HPF

Yellow >> HPF Mode = '000'

Light Green >> HPF Mode = '001'

Green >> HPF Mode = '010'

Light Blue >> HPF Mode = '011'

Blue >> HPF Mode = '100'

301282c5

301282a6

31

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ADC THD+N vs Frequency

f_S= 48kHz, OSR = 128

From MIC, MIC Gain = 6dB, V_IN= 500mV_RMS

ADC THD+N vs Input Voltage

f_S= 48kHz, OSR = 128

From MONO/AUX, MONO/AUX Gain = 0dB, f_IN= 1kHz

301282h6

301282a2

ADC THD+N vs Input Voltage

f_S= 48kHz, OSR = 128

From MIC, MIC Gain = 6dB, f_IN= 1kHz

Loudspeaker THD+N vs Frequency

From MONO/AUX Input, MONO/AUX Gain = 0dB

LS Gain = 8dB, P_OUT= 400mW, R_L= 8Ω

Blue >> LSV_DD= 3.6V

Light Blue >> LSV_DD= 4.2V

Green >> LSV_DD= 5V

301282a3

301282h0

Loudspeaker THD+N vs Frequency

From MONO/AUX Input, MONO/AUX Gain = 0dB

LS Gain = 8dB, P_OUT= 400mW, R_L= 4Ω

Blue >> LSV_DD= 3.6V

Loudspeaker THD+N vs Output Power

From MONO/AUX Input, MONO/AUX Gain = 0dB

LS Gain = 8dB, f_IN= 1kHz, R_L= 8Ω

Blue >> LSV_DD= 3.6V

Light Blue >> LSV_DD= 4.2V

Green >> LSV_DD= 5V

301282h1

301282h2

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32

Loudspeaker THD+N vs Output Power

From MONO/AUX Input, MONO/AUX Gain = 0dB

LS Gain = 8dB, f_IN= 1kHz, R_L= 4Ω

Blue >> LSV_DD= 3.6V

Loudspeaker PSRR vs Frequency

MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB

LSV_DD= 3.6V, V_RIPPLE= 200mV_PP, Input Referred

Light Blue >> LSV_DD= 4.2V

Green >> LSV_DD= 5V

30128274

301282h3

Loudspeaker PSRR vs Frequency

f_S= 48kHz, OSR = 128

Loudspeaker PSRR vs Frequency

MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB

LSV_DD= 5V, V_RIPPLE= 200mV_PP, Input Referred

MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB

LSV_DD= 4.2V, V_RIPPLE= 200mV_PP, Input Referred

30128276

30128275

Headphone PSRR vs Frequency

DAC Input, DAC Gain = 0dB, LS Gain = 12dB

LSVDD = 3.6V, AVDD = 3.6V,

HeadphoneTHD+N vs Frequency

MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB

HPV_DD= 3.3V, P_OUT= 15mW, R_L= 32Ω

Stereo In Phase

DV_DD= 1.8V, V_RIPPLE= 200mV_PP

Ripple on LSV_DD, AV_DD, DV_DD, Input Referred

30128267

30128261

33

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Headphone THD+N vs Frequency

MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB

HPV_DD= 2.8V, P_OUT= 15mW, R_L= 32Ω

Stereo In Phase

Headphone THD+N vs Frequency

MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB

HPV_DD= 1.8V, P_OUT= 15mW, R_L= 16Ω

Stereo In Phase

30128262

30128263

Headphone THD+N vs Frequency

MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB

HPV_DD= 2.8V, P_OUT= 15mW, R_L= 16Ω

Stereo in Phase

Headphone PSRR vs Frequency

MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB

HPV_DD= 1.8V, AV_DD= 3.6V, V_RIPPLE= 200mV_PP

Ripple on HPV_DD, AV_DD

30128268

30128264

Headphone PSRR vs Frequency

MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB

HPV_DD= 1.8V, AV_DD= 3.6V, V_RIPPLE= 200mV_PP

Ripple on AV_DDonly

Headphone PSRR vs Frequency

DAC Input, DAC Gain = 0dB, HP Gain = 0dB

HPV_DD= 1.8V, AV_DD= 3.6V,

DV_DD= 1.8V, V_RIPPLE= 200mV_PP

Ripple on HPV_DD, AV_DD, DV_DD

30128269

30128273

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34

Headphone Crosstalk vs Frequency

Earpiece THD+N vs Frequency

MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB

HPV_DD= 1.8V, AV_DD= 3.6V, P_OUT= 15mW, R_L= 32Ω

AV_DD= 3.6V, P_OUT= 20mW, R_L= 32Ω

Earpiece Mode

301282e4

30128265

Earpiece PSRR vs Frequency

Auxiliary Output THD+N vs Frequency

MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = –6dB MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB

AV_DD= 3.6V, V_RIPPLE= 200mV_PP, Earpiece Mode

AV_DD= 3.6V, V_OUT= 1V_RMS, R_L= 5kΩ

AUXOUT Mode

301282e6

301282e7

Auxiliary Output THD+N vs Output Voltage

Auxiliary Output PSRR vs Frequency

MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB

AV_DD= 3.6V, V_RIPPLE= 200mV_PP, AUXOUT Mode

AV_DD= 3.6V, f_IN= 1kHz, R_L= 5kΩ

AUXOUT Mode

301282e8

30128266

35

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Buck Load Transient

V_IN= 3.6V, V_OUT= 2.0V, 1–400mA Load

LDO Load Transient

V_IN= 3.6V, V_OUT= 2.0V, 1–400mA Load

C_OUT= 1μF LDO1, LDO3

301282g0

301282g1

LDO Load Transient

V_IN= 3.6V, V_OUT= 2.0V, 1–400mA Load

LDO Load Transient

V_IN= 3.6V, V_OUT= 2.0V, 1–200mA Load

C_OUT= 10μF LDO1, LDO3

C_OUT= 1μF LDO2, LDO4, LDO5, LDO6

301282g2

301282g3

LDO Load Transient

V_IN= 3.6V, V_OUT= 2.0V, 1–200mA Load

Buck Turn On Time

V_IN= 3.6V, Config = V_BATT

C_OUT= 10μF LDO2, LDO4, LDO5, LDO6

301282g5

301282g4

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36

Reset Timing

V_IN= 3.6V

LDO Turn On Time

V_IN= 3.6V, Config = V_BATT

301282g6

301282g7

LDO Output Ripple

V_IN= 3.6V, Buck 1 and 2 On

LDO Output Ripple

V_IN= 3.6V, Buck 1 and 2 Off

301282g9

301282g8

37

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22.4 I²C START AND STOP CONDITIONS

22.0 System Control

START and STOP conditions classify the beginning and the

end of the I²C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is

HIGH. STOP condition is defined as the SDA transitioning

from LOW to HIGH while SCL is HIGH. The I²C master always

generates START and STOP bits. The I²C bus is considered

to be busy after START condition and free after STOP con-

dition. During data transmission, I²C master can generate

repeated START conditions. First START and repeated

START conditions are equivalent, function-wise.

22.1 INPUT POWER SEQUENCING

The following input power supplies are normally connected to

the battery voltage VBAT: LS_VDD, P_VDD, VIN_B1,

VIN_B2, VIN_L1, VIN_L2, VIN_L3. The power to these sup-

plies should always be the highest voltage and applied first.

The remaining supplies: A_VDD, HP_VDD, D_VDD, and I/

O_VDD must be powered after the VBAT supplies or exces-

sive current may be consumed.

22.2 I²C SIGNALS

For I²C control the LM49360's SCL pin is used for the I²C

clock and the SDA pin is used for the I²C data signal. Both of

these signals require a pull-up resistor according to the I²C

specification. The LM49360 requires two unique I²C slave

addresses, with one address accessing the PMU related I²C

registers and the other address accessing the audio related

I²C registers. Since the LM49360 has three modes of PMU

operation depending on the status of the CONFIG pin, the

I²C address that accesses the PMU related I²C registers also

depends on the status of the CONFIG pin.

30128224

FIGURE 8. I²C Start and Stop Conditions

If CONFIG is tied to ground, the LM49360 operates in AP-

PMU mode and the PMU related registers are accessed via

the I²C chip address that is defined by 'PMU_L_I²C_ADDR'

of I²C register 0x41h with a default address of 1111101₂.

If CONFIG is tied to V_BATTERY, the LM49360 operates in sub-

PMU mode and the PMU related registers are accessed via

the I²C address that is defined by 'PMU_H_I²C_ADDR' of

I²C register 0x40h with a default address of 1111111₂.

If CONFIG is left floating, the LM49360 operates in CAM

mode and the PMU related registers are accessed via the

I²C chip address that is defined by 'PMU_Z_I²C_ADDR' of

I²C register 0x40h with a default address of 1111100₂.

The audio related I²C registers are accessed via the I²C chip

address that is defined by 'AUD_I²C_ADDR' of I²C register

0x41h with a default address of 0011010₂, independent of the

status of the CONFIG pin.

22.5 TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with

the most significant bit (MSB) being transferred first. Each

byte of data has to be followed by an acknowledge bit. The

acknowledge related clock pulse is generated by the master.

The transmitter releases the SDA line (HIGH) during the ac-

knowledge clock pulse. The receiver pulls down the SDA line

during the 9^thclock pulse, signifying an acknowledge. A re-

ceiver which has been addressed must generate an acknowl-

edge after each byte has been received.

After the START condition, the I²C master sends a chip ad-

dress. This address is seven bits long followed by an eighth

bit which is a data direction bit (R/W). For the eighth bit, a “0”

indicates a WRITE and a “1” indicates a READ. The second

byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

All of the LM49360's I²C chip addresses are selectable via

I²C registers 0x40h and 0x41h in the PMU register space.

22.3 I²C DATA VALIDITY

The data on SDA line must be stable during the HIGH period

of the clock signal (SCL). In other words, state of the data line

can only be changed when SCL is LOW.

30128225

FIGURE 9. I2C Chip Address

30128223

FIGURE 7. I²C Signals: Data Validity

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38

Register changes take effect at the SCL rising edge during the last ACK from slave.

30128226

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by slave)

rs = repeated start

FIGURE 10. Example I²C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle

waveform.

30128227

FIGURE 11. Example I²C Read Cycle

30128228

FIGURE 12. I²C Timing Diagram

39

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22.6 I²C TIMING PARAMETERS

Symbol

Parameter

Limit

Units

Min

0.6

1.3

600

300

0

Max

1

2

Hold Time (repeated) START Condition

µs

ns

µs

pF

Clock Low Time

Clock High Time

3

4

Setup Time for a Repeated START Condition

Data Hold Time (Output direction, delay generated by LM49360)

Data Hold Time (Input direction, delay generated by the Master)

Data Setup Time

5

900

5

6

100

20+0.1C_B

15+0.1C_B

600

7

Rise Time of SDA and SCL

300

8

Fall Time of SDA and SCL

9

Set-up Time for STOP condition

10

C_B

Bus Free Time between a STOP and a START Condition

Capacitive Load for Each Bus Line

1.3

10

200

NOTE: Data guaranteed by design

22.7 POWER ON SEQUENCE

30128206

FIGURE 13. Simplified Startup Sequence if CONFIG = H or Z (SUB_PMU)

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40

30128207

FIGURE 14. Simplified Startup Sequence if CONFIG = L (PMU)

•

Note 1 : See detailed on/off sequence diagrams for the CONFIG options.

Note 2 : To initiate the shutdown sequence PS_HOLD needs to be held low greater than 30ms before RESET_N is asserted

low. The PMU then starts the shutdown sequence in the opposite order of the startup sequence.

•

Note 3 : If PS_HOLD is not asserted within 1.5 seconds of the assertion of PWR_ON, the PMU will start the shutdown sequence

and assert RESET_N.

41

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30128253

FIGURE 15. LM493060A CONFIG = H Start-up Sequence

•

t_ON: 256μs – Reference and bias turn ON.

t_S: Programmable time steps. (Typically 8μs.) time step accuracy is defined by OSC frequency accuracy.

Note 1: START UP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers

are not rewritten via I²C.

•

Note 2: The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling / disabling process

duration depends on voltages and loading conditions. Buck startup duration is typically 40μs, LDO startup duration is typically

50μs, and LDO7(HILO) startup duration is typically 70μs. For details please see LDOs and BUCK electrical specifications.

•

Note 3: LDO4, LDO5 and LDO6 are enabled via I²C. These outputs will be disabled at ts = 0, when EN goes from High to Low.

Note 4: Buck 2 is enabled by SUBOVR or I²C. If this input is high when EN goes to high then this output turns on after t_S7.

Note 5: Upon initial power-up the PMU registers are loaded with default values. Changes to the default values will be retained

until device power is removed. Register values are retained when PMU outputs are disabled via EN going low.

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42

30128256

FIGURE 16. LM49360A CONFIG = L Start-up Sequence

•

t_BON: 256μs – Reference and bias turn ON.

t_S: Programmable time steps. (Typically 64μs) time step accuracy is defined by OSC frequency accuracy.

Note 1: START UP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers

are not rewritten via I²C.

•

Note 2: The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling / disabling process

duration depends on voltages and loading conditions. Buck startup duration is typically 40μs, LDO startup duration is typically

50μs, and LDO7(HILO) startup duration is typically 70μs. For details please see LDOs and BUCK electrical specifications.

•

Note 3: Buck 2, LDO2, and LDO4 are enabled via I2C.

Note 4: Upon initial power-up the PMU registers are loaded with default values. Changes to the default values will be retained

until device power is removed. Register values are retained when PMU outputs are disabled via PS_HOLD going low.

43

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30128255

FIGURE 17. LM49360A CONFIG = Z Start-up Sequence

•

t_BON: 256μs – Reference and bias turn ON

t_S: Programmable time steps. (Typically 64μs.) time step accuracy is defined by OSC frequency accuracy.

Note 1: START UP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers

are not rewritten via I²C.

•

Note 2: The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling / disabling process

duration depends on voltages and loading conditions. Buck startup duration is typically 40μs, LDO startup duration is typically

50μs, and LDO7(HILO) startup duration is typically 70μs. For details please see LDOs and BUCK electrical specifications.

Note 3: LDO7 is enabled via I²C.

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44

•

Note 4: Buck 2 is enabled by SUBOVR or I²C. If this input is high when EN goes to high then this output turn on after t_S= 7.

Note 5: Upon initial power-up the PMU registers are loaded with default values. Changes to the default values will be retained

until device power is removed. Register values are retained when PMU outputs are disabled via EN going low.

45

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23.0 Device Register Map

TABLE 1. PMU Register Map

De-

Address Register

fault

7

6

5

4

3

2

1

0

Value

Basic Setup

PMU

0x00h

SWOVR

FORCE_ENABLE

RESERVED

SETUP

NV

0x01h

RESERVED

BANKS

0x02h

0x03h

SLEEP1

FLAGS1

LDO6SLP LDO5SLP LDO4SLP LDO3SLP LDO2SLP

LDO1SLP BK2SLP

BK1SLP

LDO1

LDO6

LDO5

LDO4

LDO3

LDO2

UVLO

_EVENT

BK2

WAKE

BK1

WAKE

0x04h

FLAGS2

BK2_RDY BK1_RDY

UVLO

TSDL

TSDH

UVLO

RSVD

0x05h BYPASS

0x06h SWOVR1

0x07h SWOVR2

LDO6_BY LDO5_BY LDO4_BY

LDO3_BY LDO2_BY

LDO1_BY

_MASK

SW

LDO7

LDO6

LDO5

LDO4

LDO3

LDO2

LDO1

SWOVR

PSHOLD SWOVR

SWOVR

BK2

_SWOVR

BK1

_SWOVR

RSVD

BANK 0 CONFIG = Z (subPMU)

0xFFh LDO6_EN LDO5_EN LDO4_EN LDO3_EN LDO2_EN

0x10h

0x11h

0x12h

0x13h

0x14h

0x15h

0x16h

0x17h

0x18h

0x19h

0x1Ah

0x1Bh

0x1Ch

ENB1

ENB2

BK1V

BK2V

LDO1

LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

THRES

LDO1_EN BK2_EN

BK1_DLY

BK1_EN

0x00h BK2OVR LDO7_EN

BK2_DLY

BK1_VSEL

BK2_VSEL

0x67h

0xACh

0x99h

0x79h

0xACh

0x99h

0x07h

LDO1_DLY

LDO2_DLY

LDO3_DLY

LDO4_DLY

LDO5_DLY

LDO6_DLY

LDO7_DLY

LDO1_VSEL

LDO2_VSEL

LDO3_VSEL

LDO4_VSEL

LDO5_VSEL

LDO6_VSEL

LDO7_VSEL

UVLO_VSEL

LDO1_PD BK2_PD

RSVD

TIMESTEP

0x9Ah LDO7_PD RSVD

PLDWN 0xFFh LDO6_PD LDO5_PD LDO4_PD LDO3_PD LDO2_PD

LDO7OV

BK1_PD

0x1Dh

OVR

0x80h

LDO6OVR LDO5OVR LDO4OVR LDO3OVR LDO2OVR LDO1OVR BK1OVR

R

LDO7

LDO5

LDO4

LDO1

BK1

0x1Eh SubOVR 0x00h

RESET_MODE

SubOVR SubOVR

SubOVR

BANK 1 CONFIG = H (subPMU)

0x1Dh LDO6_EN LDO5_EN LDO4_EN LDO3_EN LDO2_EN

0x20h

0x21h

0x22h

0x23h

0x24h

0x25h

0x26h

0x27h

0x28h

0x29h

0x2Ah

0x2Bh

ENB1

ENB2

BK1V

BK2V

LDO1

LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

THRES

LDO1_EN BK2_EN

BK1_DLY

BK1_EN

0x41h BK2OVR LDO7_EN

BK2_DLY

BK1_VSEL

BK2_VSEL

0x45h

0x9Ah

0x0Ch

0x1Bh

0x3Fh

0x0Ch

0x15h

0x19h

0x2Bh

LDO1_DLY

LDO2_DLY

LDO3_DLY

LDO4_DLY

LDO5_DLY

LDO6_DLY

LDO7_DLY

LDO1_VSEL

LDO2_VSEL

LDO3_VSEL

LDO4_VSEL

LDO5_VSEL

LDO6_VSEL

RSVD

TIMESTEP

LDO7_VSEL

UVLO_VSEL

0x8Ah LDO7_PD RSVD

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46

De-

fault

Value

Address Register

7

6

5

4

3

2

1

0

0x2Ch

0x2Dh

PLDWN 0xFFh LDO6_PD LDO5_PD LDO4_PD LDO3_PD LDO2_PD

LDO7

LDO1_PD BK2PD

BK1PD

OVR

0x00h

LDO6OVR LDO5OVR LDO4OVR LDO3OVR LDO2OVR LDO1OVR BK1OVR

OVR

LDO7

LDO5

LDO4

LDO1

BK1

SubOVR

/RESET

0x2Eh

0x00h

RESET_MODE

SubOVR SubOVR

SubOVR

BANK 2 CONFIG = L (PMU Mode)

0xD5h LDO6_EN LDO5_EN LDO4_EN LDO3_EN LDO2_EN

0x30h

0x31h

0x32h

0x33h

0x34h

0x35h

0x36h

0x37h

0x38h

0x39h

0x3Ah

0x3Bh

0x3Ch

ENB1

ENB2

BK1V

BK2V

LDO1

LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

THRES

LDO1_EN BK2_EN

BK1_DLY

BK1_EN

0x40h BK2OVR LDO7_EN

BK2_DLY

BK1_VSEL

BK2_VSEL

0x67h

0xCDh

0x8Ch

0x15h

0x99h

0x1Fh

0x9Fh

0x99h

0x81h

LDO1_DLY

LDO2_DLY

LDO3_DLY

LDO4_DLY

LDO5_DLY

LDO6_DLY

LDO7_DLY

LDO1_VSEL

LDO2_VSEL

LDO3_VSEL

LDO4_VSEL

LDO5_VSEL

LDO6_VSEL

RSVD

TIMESTEP

LDO7_VSEL

0x9Ah LDO7_PD RSVD

UVLO_VSEL

PLDWN 0xFFh LDO6_PD LDO5_PD LDO4_PD LDO3_PD LDO2_PD

LDO7OV

LDO1_PD BK2PD

BK1PD

0x3Dh

OVR

0x00h

LDO6OVR LDO5OVR LDO4OVR LDO3OVR LDO2OVR LDO1OVR BK1OVR

R

I²C DEVICE ADDRESSES

0x40h

0x41h

I2C1

I2C2

RSVD

PMU_Z_I2C_ADDR

AUD_I2C_ADDR

PMU_H_I2C_ADDR

PMU_L_I2C_ADDR

BUCK MODE SELECTION

BK1_

FPWM

FORCE_

PWM

RE-

SERVED

RE-

SERVED

RE-

SERVED

RE-

SERVED

RE-

SERVED

RE-

SERVED

RE-

SERVED

0x5Ah

0x5Eh

BK2_

FPWM

FORCE_

PWM

RE-

SERVED

RE-

SERVED

RE-

SERVED

RE-

SERVED

RE-

SERVED

RE-

SERVED

RE-

SERVED

TABLE 2. Audio Register Map

Address

Register

7

6

5

4

3

2

1

0

BASIC SETUP

PMC

CHIP

PORT2

PORT1

CLK OVR

MCLK

OVR

OSC

ENB

PLL

CHIP

PLL_P2

ENB

0x00h

0x01h

0x02h

SETUP

ACTIVE

CLK OVR

ENB

ENABLE

PMC

CLOCKS

PMC_CLK_SEL

PMC

CLK_DIV

PMC_CLK_DIV(R)

PLL

0x03h

0x04h

0x05h

PLL_CLK_SEL

PLL M

PLL N

PLL M

PLL N

PLL

N_MOD

0x06h

PLL P2[8]

PLL P1[8]

PLL N_MOD

0x07h

0x08h

PLL P

PLL P1 [7:0]

PLL P2[7:0]

PLL P2

ANALOG MIXER

AUX_LS MONO_LS

0x10h

CLASSD

DACL_LS DACR_LS

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47

Address

Register

HEAD

7

6

5

4

3

2

1

0

MONO

_HPL

0x11h

AUX_HPL

DACL_HPL DACR_HPL

PHONESL

HEAD

MONO

_HPR

DACL

_HPR

DACR

_HPR

0x12h

0x13h

0x14h

0x15h

AUX_HPR

AUX_AUX

PHONESR

MONO

_AUX

DACR

_AUX

AUX_OUT

MIC_AUX DACL_AUX

OUTPUT

OPTIONS

AUX_LINE AUX_NEG

_OUT

LS_LEVEL

LR_HP_LEVEL

DACL

RSVD

_6dB

MONO

_ADCL

AUX

_ADCR

DACR

_ADCR

ADC

MIC_ADCL MIC_ADCR

_ADCL

0x16h

0x18h

MIC_LVL

MUTE

SE/DIFF

MIC_LEVEL

AUXL_LVL

SE/DIFF

AUX_LEVEL

AUXL_MON

O_IN

0x19h

0x1Bh

MONO_LV

MONO_LEVEL

HP

_SENSE

HP SENSE HP SENSE

HP

HP SENSE

MONO

_AUX_D

_AUX

SENSE_D

ADC

ADC_CLK_SEL

0x20h

0x21h

ADC BASIC DSPONLY

MUTE_R

MUTE_L

ADC_OSR

ADC

CLOCK

ADC_CLK_DIV (T)

ADC

_MIXER

STEREO

_LINK

0x23h

ADC_MIX_LEVEL_R

ADC_MIX_LEVEL_L

DAC_OSR

DAC

DAC_CLK_SEL

DAC

0x30h

0x31h

DSPONLY

_BASIC

MUTE_R

DAC_CLK_DIV (S)

DIGITAL MIXER

MUTE_L

DAC

_CLOCK

0x40h

0x41h

0x42h

0x43h

0x44h

0x45h

IPLVL1

IPLVL2

PORT2_RX_R_LVL

INTERP_L_LVL

PORT2_RX_L_LVL

INTERP_R_LVL

PORT1_RX_R_LVL

ADC_R_LVL

R_SEL

PORT1_RX_L_LVL

ADC_L_LVL

L_SEL

OPPORT1

OPPORT2

OPDAC

MONO

ADCR

SWAP

R_SEL

L_SEL

SWAP

PORT2R

PORT1R

R_SEL

ADCL

PORT2L

PORT1L

OPDECI

MXRCLK_SEL

AUDIO PORT 1

L_SEL

STEREO

_SYNC

_MODE

STEREO

_SYNC

_PHASE

0x50h

BASIC

CLK_PH

SYNC_MS CLK_MS

TX_ENB

RX_ENB

STEREO

0x51h

0x52h

CLK_GEN1

CLK_GEN2

CLK_SEL

HALF_CYCLE_DIVIDER

SYNTH

_DENOM

SYNTH_NUM

SYNC_RATE

RX_WIDTH

SYNC

_GEN

0x53h

0x54h

SYNC_WIDTH(MONO MODE)

TX_WIDTH

DATA

_WIDTH

TX_EXTRA_BITS

0x55h

0x56h

RX_MODE

TX_MODE

A/ULAW

COMPAND

MSB_POSITION

RX_MODE

TX_MODE

AUDIO PORT 2

CLK_PH SYNC_MS CLK_MS

HALF_CYCLE_DIVDER

STEREO

_SYNC

_MODE

STEREO

_SYNC

_PHASE

0x60h

0x61h

BASIC

TX_ENB

RX_ENB

STEREO

CLK_GEN1

CLK_SEL

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48

Address

Register

7

6

5

4

3

2

1

0

SYNTH_

DENOM

0x62h

CLK_GEN2

SYNTH_NUM

SYNC

_GEN

0x63h

0x64h

SYNC_WIDTH(MONO MODE)

TX_WIDTH

SYNC_RATE

RX_WIDTH

DATA

_WIDTH

TX_EXTRA_BITS

0x65h

0x66h

RX_MODE

TX_MODE

A/ULAW

COMPAND

MSB_POSITION

RX_MODE

TX_MODE

COMPAND

MSB_POSITION

EFFECTS ENGINE

ADC

PK ENB

DAC

ADC

0x70h

0x71h

ADC FX

DAC FX

RSVD

SCLP ENB

DAC

ALC ENB HPF_ENB

DAC

SCLP ENB

ADC EFFECTS

EQ ENB

PK ENB

ALC ENB

0x80h

0x81h

HPF

ADC

HPF MODE

SOURCE

OVR

SOURCE

RSEL

SOURCE

LSEL

STEREO

LINK

LIMITER

ADC_SAMPLE

ALC 1

ADC

0x82h

0x83h

0x84h

0x85h

0x86h

0x87h

0x88h

0x89h

0x8Ah

0x90h

0x91h

0x92h

NG_ENB

NOISE_FLOOR

ALC 2

ADC

ALC_TARGET_LEVEL

ATTACK_RATE

DECAY_RATE/RELEASE_RATE

HOLDTIME

ALC 3

ADC

ALC 4

ADC

PK_DECAY_RATE

ALC 5

ADC

ALC 6

ADC

MAX_LEVEL

ALC 7

ADC

MIN_LEVEL

ALC 8

ADC L

LEVEL

ADC R

LEVEL

STEREO

LINK

ADC_L_LEVEL

ADC_R_LEVEL

THRESHOLD

SOFTCLIP

1

SOFT

KNEE

SOFTCLIP

2

RATIO

SOFTCLIP

3

LEVEL

ADC EFFECT MONITORS

ADC LEFT LEVEL MONITOR

0x98h

0x99h

LVLMONL

LVLMONR

ADC RIGHT LEVEL MONITOR

SCLP_R

CLIP

SCLP_L

CLIP

GAIN

_R CLIP

GAIN

_L CLIP

ADC_R

CLIP

ADC_L

CLIP

0x9Ah

0x9Bh

0x9Ch

FXCLIP

SCLP_R

DISTORT

SCLP_L

DISTORT

SCLP_R

DISTORT

ALCMONL

ALCMONR

ADC LEFT ALC MONITOR

ADC RIGHT ALC MONITOR

DISTORT

DAC EFFECTS

49

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Address

Register

DAC

7

6

5

4

3

2

1

0

STEREO

LINK

0xA0h

LIMITER

DAC_SAMPLE

ALC 1

DAC

0xA1h

0xA2h

0xA3h

0xA4h

0xA5h

0xA6h

0xA7h

0xA8h

0xA9h

NG_ENB

NOISE_FLOOR

ALC 2

DAC

AGC_TARGET_LEVEL

ATTACK_RATE

ALC 3

DAC

ALC 4

DAC

PK_DECAY_RATE

DECAY_RATE/RELEASE_RATE

HOLDTIME

ALC 5

DAC

ALC 6

DAC

MAX_LEVEL

ALC 7

DAC

MIN_LEVEL

ALC 8

DAC L

LEVEL

DAC R

LEVEL

EQ BAND 1

EQ BAND 2

EQ BAND 3

EQ BAND 4

EQ BAND 5

STEREO

LINK

DAC_L_LEVEL

DAC_R_LEVEL

0xABh

0xACh

0xADh

0xAEh

0xAFh

LEVEL

FREQ

Q

SOFTCLIP

1

SOFT

KNEE

0xB0h

0xB1h

0xB2h

THRESHOLD

RATIO

SOFTCLIP

2

SOFTCLIP

3

LEVEL

DAC EFFECT MONITORS

DAC LEFT LEVEL MONITOR

0xB8h

0xB9h

LVLMONL

LVLMONR

DAC RIGHT LEVEL MONITOR

SCLP_R

CLIP

SCLP_L

CLIP

EQ_R

CLIP

EQ_L

RSVD

CLIP

GAIN

_R CLIP

GAIN

_L CLIP

0xBAh

0xBBh

0xBCh

FXCLIP

RSVD

SCLP_R

DISTORT

SCLP_L

DISTORT

SCLP_R

DISTORT

ALCMONL

ALCMONR

DAC LEFT ALC MONITOR

DAC RIGHT ALC MONITOR

DISTORT

GPIO

0xE0h

0xE1h

GPIO1

GPIO2

GPIO_RX

GPIO_TX

GPIO_MODE

TEMP

RSVD

SHORT

RSVD

SPREAD SPECTRUM

SOFT

RSVD

0xF0h

RESET

RSVD

_RESET

SS

_DISABLE

0xF1h

0xFEh

SS

RSVD

FORCE

CPFORCE

DACREF

Unless otherwise specified, the default values of the I²C registers is 0x00H.

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TABLE 3. Nonzero I²C Default Registers

Address

0x02h

0x30h

0x31h

0x84h

0x85h

0x86h

0x87h

0x89h

0x8Ah

0xA3h

0xA4h

0xA5h

0xA6h

0xA8h

0xA9h

0xF0h

Register

PMC_CLK_DIV

DAC_BASIC

DAC_CLOCK

ADC_ALC_4

ADC_ALC_5

ADC_ALC_6

ADC_ALC_7

ADC_L_LEVEL

ADC_R_LEVEL

DAC_ALC_4

DAC_ALC_5

DAC_ALC_6

DAC_ALC_7

DAC_L_LEVEL

DAC_R_LEVEL

RESET

Default Data Value

0x50h

0x02h

0x03h

0x0Ah

0x1Fh

0x33h

0x0Ah

0x33h

0x02h

TABLE 4. 0x00h PMU Setup

Description

Bits

Field

4:0

6:5

RSVD

Reserved

FORCE

_ENABLE

This determines the startup mode of the LM49360.

FORCE_ENABLE

MODE

00

01

10

11

Selected by the CONFIG pin

Force Bank 0 (CAM)

Force Bank 1 (SUB_PMU)

Force Bank 2 (AP_PMU)

7

SWOVR

If SWOVR (Software Override) is set, it allows PMU outputs to be enabled under I²C control of the

SWOVR (Software Override) bits in I²C registers SWOVR 1 (0x06h) and SWOVR 2 (0x07h)

TABLE 5. NV BANK (0x01h)

Bits

Field

Description

7:0

RSVD

Reserved

24.0 Sleep Enables

TABLE 6. SLEEP 1 (0x02h)

Description

Bits

0

Field

BK1_SLEEP If set, Buck 1 is set to sleep state.

BK2_SLEEP If set, Buck 2 is set to sleep state.

LDO1_SLEEP If set, LDO 1 is set to sleep state.

LDO2_SLEEP If set, LDO 2 is set to sleep state.

LDO3_SLEEP If set, LDO 3 is set to sleep state.

LDO4_SLEEP If set, LDO 4 is set to sleep state.

LDO5_SLEEP If set, LDO 5 is set to sleep state.

LDO6_SLEEP If set, LDO 6 is set to sleep state.

1

2

3

4

5

6

7

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25.0 LDO Flags and Bypass Pulse Control

TABLE 7. FLAGS 1 (0x03h)

Bits

0

Field

Description

LDO1_ERROR

LDO2_ERROR

LDO3_ERROR

LDO4_ERROR

LDO5_ERROR

LDO6_ERROR

If 1 an error is present on this LDO.

1

2

3

4

5

TABLE 8. FLAGS 2 (0x04h)

Bits

0

Field

TSDH

TSDL

Description

Set if TSDH is reported from the analog. >160 degrees

Set if TSDL is reported from the analog. >120 degrees

1

Output from BK1 - should toggle in sleep mode when the BUCK wakes up

momentarily to step back above the threshold.

2

3

BK1_WAKEUP

BK2_WAKEUP

Output from BK2 - should toggle in sleep mode when the BUCK wakes up

momentarily to step back above the threshold.

4

5

6

7

RESERVED

UVLO_EVENT

BK1_RDY

Reserved bit

1 = debounced UVLO event detected, 0 = UVLO not currently triggered.

Reports if BK1 is above 90% of it's programmed output voltage.

Reports if BK2 is above 90% of it's programmed output voltage.

BK2_RDY

TABLE 9. BYPASS (0x05h)

Description

Bits

0

Field

LDO1_BY

LDO2_BY

LDO3_BY

LDO4_BY

LDO5_BY

LDO6_BY

RSVD

If set, the internal reference filter is bypassed. Set this bit high for 1ms after

changing VSEL if the output voltage needs to be adjusted while the LDO is

enabled. Otherwise the internal filter will slow the transition time to over a second.

This is performed automatically every time the LDO is enabled, only use the filter

bypass when adjusting VSEL when the LDO is enabled."

1

2

3

4

5

6

Reserved

If set, the effects of the UVLO trigger are Ignored by the state machine. This can

be useful if the user wishes to determine the current battery voltage without

powering up an ADC. The UVLO trigger level can be increased until the I²C

reports a UVLO event, the level can then be changed back and the mask cleared

to return to normal operation.

7

UVLO_MASK

TABLE 10. SWOVR 1 (0x06h)

Description

Bits

Field

If set, LDO1 will enable when SWOVR is set and the device is in Standby state or

above.

0

LDO1_SWOVR

If set, LDO2 will enable when SWOVR is set and the device is in Standby state or

above.

1

2

3

4

LDO2_SWOVR

LDO3_SWOVR

LDO4_SWOVR

LDO5_SWOVR

If set, LDO3 will enable when SWOVR is set and the device is in Standby state or

above.

If set, LDO4 will enable when SWOVR is set and the device is in Standby state or

above.

If set, LDO5 will enable when SWOVR is set and the device is in Standby state or

above.

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Bits

Field

Description

If set, LDO6 will enable when SWOVR is set and the device is in Standby state or

above.

5

LDO6_SWOVR

If set, the LDO7 will enable when SWOVR is set and the device is in Standby state

or above.

6

7

LDO7_SWOVR

SW_PSHOLD

Can be used in AP_PMU mode as an alternative to raising the PS_HOLD pin.

TABLE 11. SWOVR 2 (0x07h)

Description

Bits

Field

If set, Buck 1 will enable when SWOVR is set and the device is in Standby state

or above.

0

BK1_SWOVR

If set, Buck 2 will enable when SWOVR is set and the device is in Standby state

or above.

1

BK2_SWOVR

RSVD

5:2

Reserved

26.0 Sequence and Voltage Programming (Banks 0 to 2)

TABLE 12. ENB1

Bank 0: CONFIG = Z (0x10h)

Bank 1: CONFIG = H (0x20h)

Bank 2: CONFIG = L (0x30h)

Bits

0

Field

Description

If set, Buck 1 is enabled at timestep BUCK1_DLY.

If set, Buck 2 is enabled at timestep BUCK2_DLY.

If set, LDO 1 is enabled at timestep LDO1_DLY.

If set, LDO 2 is enabled at timestep LDO2_DLY.

If set, LDO 3 is enabled at timestep LDO3_DLY.

If set, LDO 4 is enabled at timestep LDO4_DLY.

If set, LDO 5 is enabled at timestep LDO5_DLY.

If set, LDO 6 is enabled at timestep LDO6_DLY.

BK1_ENABLE

BK2_ENABLE

LDO1_ENABLE

LDO2_ENABLE

LDO3_ENABLE

LDO4_ENABLE

LDO5_ENABLE

LDO6_ENABLE

1

2

3

4

5

6

7

Note: Do not set these registers to 0x00. At least one regulator must remain enabled for proper operation.

BUCK INFORMATION

The LM49360 has two integrated high efficiency step-down DC-DC switching buck converters that deliver a constant voltage from

a single cell battery to portable devices. Using voltage mode architecture with synchronous rectification, the buck has the ability

to deliver up to 800mA depending on the input voltage and output voltage, ambient temperature, and the inductor chosen.

There are two modes of operation depending on the current required - PWM (Pulse Width Modulation), ECO (ECOnomy) mode.

The device operates in PWM mode at load currents of approximately 50mA (typ.) or higher. Lighter output current loads cause the

device to automatically switch into ECO mode for reduced current consumption and a longer battery life. Additional features include

soft-start, under voltage protection, current overload protection, and thermal shutdown protection. Only three external power com-

ponents are required for implementation.

Buck Circuit Operation

The switching buck converter operates as follows. During the first portion of each switching cycle, the control block in the LM49360

turns on the internal PMOS switch. This allows current to flow from the input through the inductor to the output filter capacitor and

load. The inductor limits the current to a ramp with a slope of (V_IN–V_OUT)/L, by storing energy in a magnetic field. During the second

portion of each cycle, the controller turns the PMOS switch off, blocking current flow from the input, and then turns the NMOS

synchronous rectifier on. The inductor draws current from ground through the NMOS to the output filter capacitor and load, which

ramps the inductor current down with a slope of –V_OUT/L.

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load.

The output voltage is regulated by modulating the PMOS switch on time to control the average current sent to the load. The effect

is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to

a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW

pin.

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ENABLING AND DISABLING V_OUT

Do not power down all voltage outputs via the I²C register ENB1 (LDO1, 2, 3, 4, 5, 6, Buck 1 and Buck 2) and I²C register ENB2

(LDO 7). It is recommended to place the LM49360 in the standby mode to disable all the V_OUToutputs. If CONFIG = L the device

can be placed in the standby state by de-asserting the PS_HOLD and PWR_ON pins as shown in Figure 14. If CONFIG = H or Z

the device can be placed in the standby state by de-asserting the EN pin as shown in Figure 13. Each individual V_OUTcan be

disabled and enabled via the I²C registers ENB1 and ENB2, however one VOUT must remained enabled for the proper device

operation. Prior to change a V_OUTvoltage selection (ie. VSEL) it is recommended to disable the V_OUTvoltage prior to the V_OUT

voltage selection change, then re-enable after making the VOUT voltage selection.

PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the con-

verter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate

this dependence, feed forward inversely proportional to the input voltage is introduced. While in PWM mode, the output voltage is

regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the

beginning of each clock cycle the PMOS switch is turned on and the inductor current ramps up until the comparator trips and the

control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PMOS is

exceeded. Then the NMOS switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning

off the NMOS and turning on the PMOS.

30128232

FIGURE 18. Typical PWM Operation

Internal Synchronous Operation

While in PWM mode, the buck uses an internal NMOS as a synchronous rectifier to reduce rectifier forward voltage drop and

associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is

relatively low compared to the voltage drop across an ordinary rectifier diode.

Current Limiting

A current limit feature allows the device to protect itself and external components during overload conditions. PWM mode imple-

ments current limit using an internal comparator that trips at 1200mA (typ.). If the output is shorted to ground and output voltage

becomes lower than 0.3V (typ.), the device enters a timed current limit mode where the switching frequency will be one fourth, and

NMOS synchronous rectifier is disabled, thereby preventing excess current and thermal runaway.

ECO Mode Operation

The buck switches from ECO state to PWM state based on output load current. At light loads (less than 50mA), the converter

enters ECO mode. In this mode the part operates with low Iq. During ECO operation, the converter positions the output voltage

slightly higher (+30mV typ.) than the nominal output voltage in PWM operation. Because the reference is set higher, the output

voltage increases to reach the target voltage when the part goes from idle state to switching state. Once this voltage is reached

the converter stops switching, thereby reducing switching losses and improving light load efficiency. The output voltage ripple is

slightly higher in ECO mode (30mV peak–peak ripple typ.).

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30128233

FIGURE 19. Typical ECO Operation

Inductor Selection for Buck 1 and Buck 2 Operation

A 1.0μH inductor should be selected. The inductor should be able to handle the maximum current without significant degradation

on inductance and it’s saturation current should not be significantly lower than 1.2A. Additionally the inductors DC Resistance

should not be greater than 100mΩ. The table below shows the possible selection of inductor types and suppliers.

TABLE 13. Buck 1 and Buck 2 Operation

Model

Vendor

FDK

Dimensions LxWXH (mm)

2.0 x 1.25 x 1

DCR (mΩ)

MIPSZ2012D1R0

CBC2016T1R0M

EPL2010-102ML

90

100

99

Taiyo Yuden

Coilcraft

2.0 x 1.6 x 1.6

2.0 x 2.0 x 1.05

Buck Output Voltage Selection

The selection of the bucks’ output voltages can be done by writing a specific code into the control registers (addr. 0x12, 0x22, 0x32

for Buck1… addr. 0x13, 0x23, 0x33 for Buck2). The required voltage can be calculated from the following equation.

V_OUT(V) = 0.6V + code(dec) x 0.00588V

TABLE 14. ENB2

Bank 0: CONFIG = Z (0x11h)

Bank 1: CONFIG = H (0x21h)

Bank 2: CONFIG = L (0x31h)

Bits

Field

Description

2:0

BK1_DELAY

This sets the time slot when Buck1 enables and disables.

000

001

010

011

100

101

110

111

Power up in slot 0, Power down in slot 0

Power up in slot 1, Power down in slot 1

Power up in slot 2, Power down in slot 2

Power up in slot 3, Power down in slot 3

Power up in slot 4, Power down in slot 4

Power up in slot 5, Power down in slot 5

Power up in slot 6, Power down in slot 6

Power up in slot 7, Power down in slot 7

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Bits

Field

Description

5:3

BK2_DELAY

This sets the time slot when Buck2 enables and disables.

000

001

010

011

100

101

110

111

Power up in slot 0, Power down in slot 0

Power up in slot 1, Power down in slot 1

Power up in slot 2, Power down in slot 2

Power up in slot 3, Power down in slot 3

Power up in slot 4, Power down in slot 4

Power up in slot 5, Power down in slot 5

Power up in slot 6, Power down in slot 6

Power up in slot 7, Power down in slot 7

6

7

LDO7_ENABLE

BK2_OVR

If set, LDO 7 is enabled and disabled at time slot LDO7_DLY.

If set, BUCK2 will enable when the OVR pin is asserted.

TABLE 15. BK1V

Bank 0: CONFIG = Z (0x12h)

Bank 1: CONFIG = H (0x22h)

Bank 2: CONFIG = L (0x32h)

Bits

Field

Description

Sets the Buck 1 output voltage.

Vout(V) = 0.6 + (BK1_VSEL*0.00588)

7:0

BK1_VSEL

TABLE 16. BK2V

Bank 0: CONFIG = Z (0x13h)

Bank 1: CONFIG = H (0x23h)

Bank 2: CONFIG = L (0x33h)

Bits

Field

Description

Sets the Buck 2 output voltage.

Vout(V) = 0.6 + (BK2_VSEL*0.00588)

7:0

BK2_VSEL

LDO INFORMATION

There are 8 LDOs in LM49360 grouped as:

6 General type “PERFECT” LDOs

1 HILO LDO

1 µPWR LDO

All LDOs can be programmed through serial interface for different output voltage values, which are summarized in the LDO output

voltage selection register tables.

For stability all LDOs need to have an external capacitor Cout connected to the output with the recommended value of 1μF. It is

important that the capacitance is within the specified value across voltage and temperature.

PMU Enabled

The PMU allows four major methods of enabling and disabling the PMU outputs.

The first method is to use the I²C registers ENB1 and ENB2. Then set the Timestep and Delay for the required power sequence.

The second method is via the OVR pin and the OVR register bits to enable any of the PMU outputs under hardware control. This

mode is available in AP_PMU, SUB-PMU and CAM modes.

The third method is via the SUBOVR pin and the SUBOVR register bits to enable any of the SUB-PMU outputs Buck 1, LDO1,

LDO4, LDO5 and LDO7 under hardware control. This mode is available in SUB-PMU and CAM modes. A subset of this mode is

that the SUBOVR pin can be used to enable Buck 2 without setting a SUBOVR register bit. This means that Buck 2 will always be

enabled when the SUBOVR pin is high.

The fourth method is software control via I²C access to the ENB2, SWOVR 1 and SWOVR 2 registers. This mode is available in

AP_PMU, SUB-PMU and CAM modes.

The PMU outputs are enabled on an “OR” condition of the 4 methods. If the enable bits in the I²C registers ENB1 and ENB2 are

cleared, one of the other three methods can be used to enable and disable the PMU outputs. If the Timestep and Delays are

programmed but the Enables (ENB1, ENB2) are cleared, then the initial enabling of the PMU output via hardware and software

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occurs immediately upon the hardware or software override. Subsequently if the PMU is disabled via PWR_ON and PS_HOLD

the (and the enable condition still exist, hardware or software) the subsequent powering of the PMU output will be based upon the

programmed Timestep and Delays.

OVR

Hardware

Override

SUBOVR

Hardware

Override

SWOVR

Software

Override

ENB1 & ENB2

Default

CONFIG

Pin Sate

PMU

Enabled

Mode

Buck1, Buck2,

LDO1, LDO2,

LDO3, LDO4,

LDO5, LDO6,

LDO7

OVR Pin = H &&

OVR Reg bit = 1b

L, H, Z

Buck1, LDO1,

LDO4, LDO5,

LDO7

SUBOVR Pin = H

&& SUBOVR Reg

bit = 1b

H, Z

Buck2 Only

SUBOVR Pin = H

Buck 1, Buck 2,

LDO1, LDO2,

LDO3, LDO4,

LDO5, LDO6,

LDO7

PMU Setup Reg

SWOVR = 1b &&

{SWOVR 1 Reg bit

= 1b || SWOVR 2

Reg bit = 1b}

L, H, Z

Buck 1, Buck 2,

LDO1, LDO2,

LDO3, LDO4,

LDO5, LDO6,

LDO7

ENABLE = 1b,

PMU enabled at

the specified

timestep.

The OVR register bits for Buck 1 and LDO1 thru LDO7 are located in the following I²C OVR registers:

- Bank 0: CONFIG = Z (0x1Dh), bits 0 – 7.

- Bank 1: CONFIG = H (0x2Dh), bits 0 – 7.

- Bank 2: CONFIG = L (0x3Dh), bits 0 – 7.

The OVR register bit for Buck 2 is located in the following ENB2 registers:

- Bank 0: CONFIG = Z (0x11h), bit 7.

- Bank 1: CONFIG = H (0x21h), bit 7.

- Bank 2: CONFIG = L (0x31h), bit 7.

The SUBOVR register bits for Buck 1, LDO1, LDO4, LDO5 and LDO7 are located in the following I²C SUBOVR registers

- Bank 0: CONFIG = Z (0x1Eh), bits 3 – 7.

The SWOVR register bits for LDO1, LDO2, LDO3, LDO4, LDO5 and LDO7 (HILO) are located in the I²C SWOVR 1(0x06h). The

SWOVR register bits for Buck 1 and Buck 2 are located I²C SWOVR 2(0x07h). The SWOVR register bit in the I²C PMU Setup

(0x00h) must be set for the register bits in SWOVR 1 and SWOVR 2 to be enabled.

The I²C SWOVR 1(0x06h) register also supports a software PS_HOLD, bit 7.

The enable register bits for Buck 1, Buck 2, LDO1, LDO2, LDO3, LDO4, LDO5 and LDO6 are located in the following I²C ENB1

registers:

- Bank 0: CONFIG = Z (0x10h), bits 0 – 7.

- Bank 1: CONFIG = H (0x20h), bits 0 – 7.

- Bank 2: CONFIG = L (0x30h), bits 0 – 7.

The enable register bit for LDO7 is located in the following I²C ENB2 registers:

- Bank 0: CONFIG = Z (0x11h), bit 6.

- Bank 1: CONFIG = H (0x21h), bits 6.

- Bank 2: CONFIG = L (0x31h), bits 6.

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PMU Sleep

The SLEEP state(s) can be enabled and disabled for each of the voltage outputs independently in the I²C register SLEEP (0x02h).

PMU Under Voltage Lock Out (UVLO)

The PMU registers that support the UVLO are listed in the table below. See individual register descriptions for the details.

I²C Register

Name

I²C Register

Address

0x04h

Bit #

Bit Name

FLAGS 2

BYPASS

5

7

UVLO_EVENT

UVLO_MASK

0x05h

CONFIG = Z

(0x1Bh)

CONFIG = H

(0x2Bh)

UVLO voltage

selection

THRES

[3:0]

[2:0]

CONFIG = L

(0x3Bh)

CONFIG = Z

(0x1Eh)

RESET_MODE.

Allows UVLO or

UVLO to be output

onto RESET_N

SUBOVR

CONFIG = H

(0x2Eh)

PMU Thermal Shutdown (TSD)

The PMU registers that support the TSD are listed in the table below. See individual register descriptions for the details.

I²C Register

Name

I²C Register

Address

Bit #

Bit Name

0

1

TSDH

TSDL

FLAGS 2

0x04h

CONFIG = Z

(0x1Eh)

RESET_MODE.

Allows TSDL,

SUBOVR

[2:0]

TSDH, TSDL or

TSDH to be output

onto RESET_N

CONFIG = H

(0x2Eh)

Power Savings

The PMU registers that support the power savings are listed in the table below. See individual register descriptions for the details.

The power saving features are under software control, the setting and clearing of these bits are not control by hardware.

I²C Register

Name

I²C Register

Address

0x5Ah

Bit #

Bit Name

BK1_FPWM

BK2_FPWM

7

FORCE_PWM

0x5Eh

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General Type LDOS

The general “PERFECT” LDOs are optimized for supplying both analog and digital loads having ULTRA LOW NOISE (10µV_RMS

for I_OUT>5mA) and excellent PSRR (75dB at 10kHz) performance. They can be programmed through the serial interface for different

output voltage values.

For fast discharging of output capacitors in shut down, the LDOs can connect a 300Ω pull-down resistor to the output. This resistor

is only connected when the LDO is disabled. See Table 20 for the register description.

In sleep mode, quiescent current is reduced to 30µA for energy saving. In this mode these LDOs should not be loaded with more

than 3-5mA of output current.

HILO LDO

LDO7 (HILO) has lowered output voltage range from 0.8V to 1.55V (step 50mV) controlled by 4 bit control signal as shown in LDO7

(HILO) output voltage selection table below. Typical output current is 2mA but maximum current can reach 20mA. For proper

operation, an input voltage of more than 2V is necessary. Hence, voltage drop on the pass transistor (dropout voltage) always

exceeds 0.45V and is not dependent on output current (in specified current range).

For fast discharging of output capacitors in shut down, the LDO7 (HILO) can connect a 300Ω pull-down resistor to the output. This

resistor is only connected when the LDO is disabled. See Table 20 for the register description.

Since the LDO7 (HILO) is based on the micro power LDO, no extra output capacitor is needed. However, for better dynamic

performance it is recommended that a capacitor in the 100nF to 1μF range be used.

µPWR LDO

This LDO is primarily used for internal supply purposes and fixed to 1.8V, but may deliver up to 30mA of current also externally.

This LDO is ON even in Standby mode (with total PMU current consumption about 2uA) and the user may use it to supply some

backup/always on system(s).

TABLE 17. LDO1 — 6

Bank 0: CONFIG = Z (0x14h:LDO1) → (0x19h:LDO6)

Bank 1: CONFIG = H (0x24h:LDO1) → (0x29h:LDO6)

Bank 2: CONFIG = L (0x34h:LDO1) → (0x39h:LDO6)

Bits

Field

Description

4:0

LDO(1-6)*_VSEL

This sets the output voltage of the corresponding LDO.

LDO*_VSEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

Vout (V)

1.2

LDO*_VSEL

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Vout (V)

2.1

1.25

1.3

2.2

2.3

1.35

1.4

2.4

2.5

1.45

1.5

2.6

2.65

2.7

1.55

1.6

2.75

2.8

1.65

1.7

2.85

2.9

1.75

1.8

2.95

3

1.85

1.9

3.1

2

3.3

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Bits

Field

Description

7:5

LDO(1-6)_DLY

This sets the time slot when the LDO enables and disables.

LDO(1–6)_DLY

Power Up/Down Time Slot

000

001

010

011

100

101

110

111

Power up in slot 0, Power down in slot 0

Power up in slot 1, Power down in slot 1

Power up in slot 2, Power down in slot 2

Power up in slot 3, Power down in slot 3

Power up in slot 4, Power down in slot 4

Power up in slot 5, Power down in slot 5

Power up in slot 6, Power down in slot 6

Power up in slot 7, Power down in slot 7

TABLE 18. LDO7

Bank 0: CONFIG = Z (0x1Ah)

Bank 1: CONFIG = H (0x2Ah)

Bank 2: CONFIG = L (0x3Ah)

Bits

Field

Description

3:0

LDO7_VSEL

Selects the output voltage.

LDO*_VSEL

0000

Vout (V)

1.55

1.5

LDO*_VSEL

Vout (V)

1.15

1.1

1000

1001

1010

1011

1100

1101

1110

1111

0001

0010

1.45

1.4

1.05

1

0011

0100

1.35

1.3

0.95

0.9

0101

0110

1.25

1.2

0.85

0.8

0111

4

RESERVED

LDO7_DLY

Reserved bit, this bit must remain cleared.

Sets the time slot when the LDO enables and disables.

7:5

LDO7_DLY

000

Power Up/Down Time Slot

Power up in slot 0, Power down in slot 0

001

Power up in slot 1, Power down in slot 1

Power up in slot 2, Power down in slot 2

Power up in slot 3, Power down in slot 3

Power up in slot 4, Power down in slot 4

Power up in slot 5, Power down in slot 5

Power up in slot 6, Power down in slot 6

Power up in slot 7, Power down in slot 7

010

011

100

101

110

111

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TABLE 19. THRES

Bank 0: CONFIG = Z (0x1Bh)

Bank 1: CONFIG = H (0x2Bh)

Bank 2: CONFIG = L (0x3Bh)

Bits

Field

Description

3:0

UVLO_VSEL

Input on PV_DD.

The PVDD voltage level is monitored and if it falls below this value, the PMU will enter

into the STANDBY state.

UVLO_VSEL

0000

PVDD (V)

2.3

UVLO_VSEL

1000

PVDD (V)

2.7

0001

2.35

2.4

1001

2.75

2.8

0010

1010

0011

2.45

2.5

1011

2.85

2.9

0100

1100

0101

2.55

2.6

1101

2.95

3

0110

1110

0111

2.65

1111

3.05

5:4

TIMESTEP

Time per Step

(microseconds)

TIMESTEP

00

01

10

11

8

64

128

256

6

7

RESERVED

LDO7_PD

Reserved bit, this bit must remain cleared.

If set, the LDO7 output will be pulled down by a 300Ω resistor when the LDO is disabled,

speeding the discharge of attached decoupling capacitors.

TABLE 20. PLDWN

Bank 0: CONFIG = Z (0x1Ch)

Bank 1: CONFIG = H (0x2Ch)

Bank 2: CONFIG = L (0x3Ch)

Bits

0

Field

Description

BK1_PD

If set, the Buck1 output will be pulled down by a 300Ω resistor when disabled.

If set, the Buck2 output will be pulled down by a 300Ω resistor when disabled.

If set, the LDO1 output will be pulled down by a 300Ω resistor when disabled.

If set, the LDO2 output will be pulled down by a 300Ω resistor when disabled.

If set, the LDO3 output will be pulled down by a 300Ω resistor when disabled.

If set, the LDO4 output will be pulled down by a 300Ω resistor when disabled.

If set, the LDO5 output will be pulled down by a 300Ω resistor when disabled.

If set, the LDO6 output will be pulled down by a 300Ω resistor when disabled.

1

BK2_PD

2

LDO1_PD

LDO2_PD

LDO3_PD

LDO4_PD

LDO5_PD

LDO6_PD

3

4

5

6

7

TABLE 21. OVR

Bank 0: CONFIG = Z (0x1Dh)

Bank 1: CONFIG = H (0x2Dh)

Bank 2: CONFIG = L (0x3Dh)

This sets the Function of OVR pin mode. If all are zero only Buck2 is enabled by the pin (this pin always forces Buck2 on). Other

outputs can be set by setting the relevant bit here.

Bits

0

Field

Description

If set, the Buck 1 output is enabled when OVR is set.

If set, the LDO 1 output is enabled when OVR is set.

If set, the LDO 2 output is enabled when OVR is set.

If set, the LDO 3 output is enabled when OVR is set.

BK1_OVR

LDO1_OVR

LDO2_OVR

LDO3_OVR

1

2

3

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Bits

4

Field

Description

If set, the LDO 4 output is enabled when OVR is set.

If set, the LDO 5 output is enabled when OVR is set.

If set, the LDO 6 output is enabled when OVR is set.

If set, the LDO 7 output is enabled when OVR is set.

LDO4_OVR

LDO5_OVR

LDO6_OVR

LDO7_OVR

5

6

7

TABLE 22. SUBOVR

Bank 0: CONFIG = Z (0x1Eh)

Bank 1: CONFIG = H (0x2Eh)

Bits

Field

Description

2:0

RESERVED

Reserved bits, this bit field must remain at 000b.

RESERVED

000

Function of RESET_N Pin

RESET_N (Default)

RESET

001

010

TSDL or UVLO

TSDH or TSDL

0

011

100

101

110

111

1

If set, the Buck1 output enables when SUBOVR is set

(i.e. PS_HOLD in a subPMU mode).

3

4

5

6

7

BK1_SUBOVR

LDO1_SUBOVR

LDO4_SUBOVR

LDO5_SUBOVR

LDO7_SUBOVR

If set, the LDO1 output enables when SUBOVR is set

(i.e. PS_HOLD in a subPMU mode).

If set, the LDO4 output enables when SUBOVR is set

(i.e. PS_HOLD in a subPMU mode).

If set, the LDO5 output enables when SUBOVR is set

(i.e. PS_HOLD in a subPMU mode).

If set, the LDO7 output enables when SUBOVR is set

(i.e. PS_HOLD in a subPMU mode).

TABLE 23. I²C1 (0x40h)

Bits

Field

Description

2:0

PMU_H_I²C_ADDR

The I²C Address for the Power Management CONFIG “H”

PMU_H_I²C

_ADDR

000

I²C_ADDR

1111111

1111110

1111101

1111100

1111011

1111010

1111001

1111000

001

010

011

100

101

110

111

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62

Bits

Field

Description

5:3

PMU_Z_I²C_ADDR

The I²C Address for the Power Management CONFIG “Z”

PMU_Z_I²C_ADDR

I²C_ADDR

1111100

1111101

1111110

1111111

1111000

1111001

1111010

1111011

000

001

010

011

100

101

110

111

6

7

RESEREVED

Reserved bit, this bit must remain cleared.

TABLE 24. I²C2 (0x41h)

Bits

Field

Description

2:0

PMU_L_I²C_ADDR

The I²C Address for the Power Management CONFIG “L”

PMU_L_I²C

I²C_ADDR

_ADDR

000

1111101

1111100

1111111

1111110

1111001

1111000

1111011

1111010

001

010

011

100

101

110

111

5:3

AUD_I²C_ADDR

The I²C Address for the Audio Subsystem

AUD_I²C_ADDR

I²C_ADDR

0011010

0011011

0011000

0011001

0011110

0011111

0011100

0011101

000

001

010

011

100

101

110

111

6

7

RESERVED

Reserved bit, this bit must remain cleared.

TABLE 25. BK1_FPWM (0x5Ah)

Description

Bits

Field

6:0

Reserved

Do not change the value of these bits, read the value of these bits and write back when

updating bit 7, FORCE_PWM.

7

FORCE_PWM

If set, forces the Buck 1 converter into PWM mode. If cleared, the Buck 1 converter will

switch between ECO and PWM mode depending on the load current.

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TABLE 26. BK2_FPWM (0x5Eh)

Bits

Field

Reserved

Description

6:0

Do not change the value of these bits, read the value of these bits and write back when

updating bit 7, FORCE_PWM.

7

FORCE_PWM

If set, forces the Buck 2 converter into PWM mode. If cleared, the Buck 2 converter will

switch between ECO and PWM mode depending on the load current.

27.0 Basic PMC Setup Register

The LM49360's Power Management Circuit (PMC) controls the basic power management setup for the audio section of the device.

TABLE 27. PMC_SETUP (0x00h)

Bits

Field

Description

When this bit is set, the power management will enable the MCLK I/O or internal

oscillator¹. It will then use this clock to sequence the enabling of the analog references and

bias points. When this bit is cleared, the PMC will bring the analog down gently and disable

the MCLK or oscillator.

0

CHIP_ENABLE

CHIP _ENABLE

Chip Status

Turn Chip Off

Turn Chip On

0

1

This enables the PLL.

PLL_ENABLE

PLL Status

PLL Off

1

2

PLL_ENB

0

1

PLL On

This enables the P2 output of the PLL.

PLL_P2ENB

PLL P2 Status

PLL P2 Off

PLL_P2ENB

0

1

PLL P2 On

This enables the internal 300kHz Oscillator. For analog only chip modes, the oscillator can

be used instead of an external system clock to drive the chip's power management (PMC).

OSC_ENABLE

Oscillator Status

Oscillator Off

Oscillator On

3

OSC_ENB

0

1

This forces the MCLK input to enable, regardless of requirement. If set, the audio ports and

digital mixer can be activated even if the chip is in shutdown mode. This assumes that MCLK

is selected as the PMC clock source (reg 0x01h) and that there is an active clock signal

driving the MCLK pin. Setting this bit reduces power consumption by allowing audio ports

and digital mixer to operate while the analog sections of the chip are powered down.

4

5

MCLK_OVR

Comment

0

1

I/O control is automatic

MCLK input forced on.

This forces the clock input of Audio Port 1 input to enable, regardless of other port settings.

PORT1_CLK_OVR

Comment

PORT1_CLK_OVR

0

1

I/O control is automatic

PORT_CLK input forced on

This forces the clock input of Audio Port 2 input to enable regardless of other port settings.

PORT2_CLK_OVR

Comment

6

7

PORT2_CLK_OVR

CHIP_ACTIVE

0

1

I/O control is automatic

PORT_CLK input forced on

This bit is used to read back the enable status of the chip.

1. If the PMC is set to operate from one of the audio ports, then it will wait for the port to be enabled or the relevant override bit to

be set, forcing the port clock input to enable.

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64

28.0 PMC Clocks Register

This register is used to control the LM49360's Basic Power Management Clock.

TABLE 28. PMC_SETUP (0x01h)

Bits

Field

Description

This selects the source of the PMC input clock.

1:0

PMC_CLK_SEL

PMC Input Clock Source

MCLK (Default divide is 40.5)

Internal 300kHz Oscillator

DAC SOURCE CLOCK

00

01

10

11

ADC SOURCE CLOCK

29.0 PMC Clock Divide Register

This register is used to control the LM49360's Power Management Circuit Clock Divider.

TABLE 29. PMC_SETUP (0x02h)

Bits

Field

Description

7:0

PMC_CLK_DIV

This programs the half cycle divider that precedes the PMC. The PMC should run from a

300kHz clock. The default of this divider is 0x50h (divide by 40.5) to get a ≈300kHz PMC

clock from a 12MHz or 12.288MHz MCLK.

Program this divider with the required division, multiplied by 2, and subtract 1.

PMC_CLK_DIV

00000000

00000001

00000010

00000011

00000100

00000101

—

Divide by

1

1.5

2

2.5

3

—

11111101

11111110

11111111

126

127.5

128

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30.0 LM49360 Clock Network

(Refer to Figure 20)

The audio DAC and ADC operate at a clock frequency of 2*OSR*f_Swhere OSR is the oversampling ratio and f_Sis the sampling

frequency of the DAC or ADC. The DAC can operate at three different OSR settings (128, 125, 64). The ADC can operate at two

different OSR settings (128, 125). For example, if the stereo DAC or ADC is set at OSR = 128, a 12.288MHz clock is required for

48kHz data. If a 12.288MHz clock is not available, then the internal PLL can be used to generate the desired clock frequency.

Otherwise, if a 12.288MHz is available, the PLL can be bypassed to reduce power consumption. The DAC clock divider or ADC

clock divider can also be used to generate the correct clock. If an 18.432 MHz clock is available, the DAC or ADC clock divider

could be set to 1.5 in order to generate a 12.288MHz clock from 18.432MHz without using a PLL.

The DAC path clock (DAC_SOURCE_CLK) and ADC path clock (ADC_SOURCE_CLK) can be driven directly by the MCLK input,

the PORT1_CLK input, the PORT2_CLK input, or PLL output.

For instances where a PLL must be used, the PLL input clock can come from three sources. The clock input to the PLL can come

from the MCLK input, the PORT1_CLK input, or the PORT2_CLK input.

The LM49360's Power Management Circuit (PMC) requires a clock of ≈300kHz that is independent from the DAC or ADC. The

PMC clock divider is available to generate the correct clock to the PMC block. The PMC clock path can be driven directly by the

MCLK input, the internal 300kHz oscillator, the DAC_SOURCE_CLK, or the ADC_SOURCE_CLK.

TABLE 30. DAC Clock Requirements

DAC Sample Rate

(kHz)

Clock Required at A

(OSR = 128)

Clock Required at A

(OSR = 125)

Clock Required at A

(OSR = 64)

8

11.025

12

2.048 MHz

2.8224 MHz

3.072 MHz

4.096 MHz

5.6448 MHz

6.144 MHz

8.192 MHz

11.2896 MHz

12.288 MHz

24.576 MHz

2 MHz

2.75625 MHz

3 MHz

1.024 MHz

1.4112 MHz

1.536 MHz

2.048 MHz

2.8224 MHz

3.072 MHz

4.096 MHz

5.6448 MHz

6.144 MHz

12.288 MHz

16

4 MHz

22.05

24

5.5125 MHz

6 MHz

32

8 MHz

44.1

48

11.025 MHz

12 MHz

96

24 MHz

TABLE 31. ADC Clock Requirements

ADC Sample Rate

Clock Required at B

(OSR = 128)

Clock Required at B

(kHz)

(OSR = 125)

8

2.048 MHz

2.8224 MHz

3.072 MHz

4.096 MHz

5.6448 MHz

6.144 MHz

8.192 MHz

11.2896 MHz

12.288 MHz

2 MHz

11.025

12

2.75625 MHz

3 MHz

16

4 MHz

22.05

24

5.5125 MHz

6 MHz

32

8 MHz

44.1

48

11.025 MHz

12 MHz

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66

30128213

FIGURE 20. Internal Clock Network

67

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31.0 PLL Setup Registers

30128230

FIGURE 21. PLL Loop

The LM49360 contains a PLL for flexible operation of its dual audio ports. The PLL has a P1 and P2 output divider thereby allowing

the PLL to generate two distinct clock outputs. The equations for the PLL's generated output clocks are as follows:

f_OUT1= (f_IN. N / M . P₁)

f_OUT2= (f_IN. N / M . P₂)

where:

N = PLL_N + PLL_N_MOD

M = (PLL_M + 1) / 2

P₁= (PLL_P1 + 1) / 2

P₂= (PLL_P2 + 1) / 2

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TABLE 32. PLL Settings for Common System Clock Frequencies

f_IN(MHz)

12

f_OUT(Hz)

12288000

12287970

12288000

11289600

11289603

11289600

11289602.1

12289600

12000000

11025000

M

2.5

15.5

12.5

13.5

3.5

12.5

20.5

16.5

32.5

22.5

12.5

10

N

N_MOD

P

12.5

12

Error (Hz)

32

0

26

0

–30

0

13

175

128

32

14.4

16.2

16.8

19.2

19.68

19.8

26

12

0

12.5

12

0

96

0

160

128

192

128

147

144

147

196

126

147

196

144

196

195

125

102

68

0

12.5

16

0

27

0

12

0

12.288

13

0

9

19

0

18.5

15

+3

0

14.4

16.2

16.8

19.2

19.68

19.8

26

12.5

22.5

12.5

20

0

12.5

15

0

12.5

18

0

20.5

27.5

18.5

37.5

10.5

8

0

19

0

2.1

0

27

12.5

17.5

16

11.2896

12.288

13

0

6.5

4.5

6

0

17

0

13.5

14.4

16.2

16.8

19.2

19.68

19.8

26

0

17

0

85

0

17

0

13.5

7

170

85

0

17

0

17

0

8

85

0

17

0

20.5

16.5

6.5

8

200

170

36

0

16

0

17

0

12

0

11.2896

12

125

147

114

96

0

16

0

10

0

16

0

12.288

13

8

27

15

0

16

0

6.5

10

17.5

18

0

13.5

14.4

16.2

16.8

19.2

19.68

19.8

26

147

49

0

4

0

16

0

4

49

0

18

0

16

189

147

189

147

27

0

18

0

16

0

16

0

16

0

18

0

16

0

16.5

13

0

5

18

0

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TABLE 33. PLL_CLOCK_SOURCE (0x03h)

Description

Bits

Field

1:0

PLL_CLK_SEL

This selects the source of the input clock to the PLL.

PLL_CLK_SEL

PLL Input Clock Source

MCLK

00

01

10

11

PORT1_CLK

PORT2_CLK

RESERVED

TABLE 34. PLL_M (0x04h)

Bits

Field

Description

6:0

PLL_M

This programs the PLL's M divider to divide from 1 to 64.

PLL_M

000000

000001

000010

000011

000100

000101

—

PLL Input Divider Value

1

1.5

2

2.5

3

—

63

63.5

64

1111101

1111110

1111111

TABLE 35. PLL_N (0x05h)

Bits

Field

Description

7:0

PLL_N

This programs the PLL N divider to divide from 1 to 250.

PLL_N

00000000 to 00001010

00001011

Feedback Divider Value

10

11

00001100

12

00001101

13

00001110

14

00001111

15

—

11111000

248

249

250

11111001

11111010 to 11111111

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TABLE 36. PLL_N_MOD (0x06h)

Description

Bits

Field

4:0

PLL_N_MOD

This programs the sigma-delta modulator in the PLL.

PLL_N_MOD

00000

00001

00010

00011

00100

00101

—

Fractional Part of N

0

1/32

2/32

3/32

4/32

5/32

—

11101

11110

11111

20/32

30/32

31/32

5

6

PLL_P1[8]

PLL_P2[8]

This sets the MSB of the 1st P Divider on the PLL which is part of a standard half-cycle divider

control.

This sets the MSB of the 2nd P Divider on PLL which is part of a standard half-cycle divider

control.

TABLE 37. PLL_P1 (0x07h)

Description

Bits

Field

7:0

PLL_P1[7:0]

This programs the 8 LSBs of the PLL's P1 Divider. These LSBs combine with PL1_P1[8] which

allows the P1 divider to divide by up to 256.

PLL_P1 [8:0]

000000000

000000001

000000010

000000011

000000100

000000101

—

P1 Divider Value

1

1.5

2

2.5

3

—

111111101

111111110

111111111

255

255.5

256

TABLE 38. PLL_P2 (0x08h)

Bits

Field

Description

7:0

PLL_P2[7:0]

This programs 8 LSBs of the PLL's P2 Divider. These LSBs combine with PLL_P2[8] which

allows the P2 divider to divide by up to 256.

PLL_P2 [8:0]

000000000

000000001

000000010

000000011

000000100

000000101

—

P2 Divider Value

1

1.5

2

2.5

3

—

111111101

111111110

111111111

255

255.5

256

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32.0 Analog Mixer Control Registers

This register is used to control the LM49360's Analog Mixer:

TABLE 39. CLASS_D_OUTPUT (0x10h)

Description

Bits

0

Field

DACR_LS

DACL_LS

RSVD

The right DAC output is added to the loudspeaker output.

The left DAC output is added to the loudspeaker output.

Reserved

1

2

3

RSVD

Reserved

4

MONO_LS

AUX_LS

The MONO input is added to the loudspeaker output.

The AUX input is added to the loudspeaker output.

5

Class D Loudspeaker Amplifier

The LM49360 features a filterless modulation scheme. The differential outputs of the device switch at 300kHz from V_DDto GND.

When there is no input signal applied, the two outputs (LS+ and LS-) switch with a 50% duty cycle, with both outputs in phase.

Because the outputs of the LM49360 are differential, the two signals cancel each other. This results in no net voltage across the

speaker, thus there is no load current during an idle state, conserving power.

With an input signal applied, the duty cycle (pulse width) of the LM49360 outputs changes. For increasing output voltages, the duty

cycle of LS+ increases, while the duty cycle of LS- decreases. For decreasing output voltages, the converse occurs, the duty cycle

of LS- increases while the duty cycle of LS+ decreases. The difference between the two pulse widths yields the differential output

voltage.

Spread Spectrum Modulation

The LM49360 features a fitlerless spread spectrum modulation scheme that eliminates the need for output filters, ferrite beads or

chokes. The switching frequency varies by ±30% about a 300kHz center frequency, reducing the wideband spectral content,

improving EMI emissions radiated by the speaker and associated cables and traces. Where a fixed frequency class D exhibits

large amounts of spectral energy at multiples of the switching frequency, the spread spectrum architecture of the LM49360 spreads

that energy over a larger bandwidth. The cycle-to-cycle variation of the switching period does not affect the audio reproduction or

efficiency.

Class D Power Dissipation and Efficiency

In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required to produce it

with the difference being the power dissipated, typically, in the IC. The key here is “useful” work. For audio systems, the energy

delivered in the audible bands is considered useful including the distortion products of the input signal. Sub-sonic (DC) and super-

sonic components (>22kHz) are not useful. The difference between the power flowing from the power supply and the audio band

power being transduced is dissipated in the LM49360 and in the transducer load. The amount of power dissipation in the LM49360's

class D amplifier is very low. This is because the ON resistance of the switches used to form the output waveforms is typically less

than 0.25Ω. This leaves only the transducer load as a potential "sink" for the small excess of input power over audio band output

power. The LM49360 dissipates only a fraction of the excess power requiring no additional PCB area or copper plane to act as a

heat sink.

TABLE 40. LEFT HEADPHONE_OUTPUT (0x11h)

Bits

0

Field

DACR_HPL

DACL_HPL

RSVD

Description

The right DAC output is added to the left headphone output.

The left DAC output is added to the left headphone output.

Reserved

1

2

3

RSVD

Reserved

4

MONO_HPL

AUX_HPL

The MONO input is added to the left headphone output.

The AUX input is added to the left headphone output.

5

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TABLE 41. RIGHT HEADPHONE_OUTPUT (0x12h)

Bits

0

Field

DACR_HPR

DACL_HPR

RSVD

Description

The right DAC output is added to the right headphone output.

The left DAC output is added to the right headphone output.

Reserved

1

2

3

RSVD

Reserved

4

MONO_HPR

AUX _HPR

The MONO input is added to the right headphone output.

The AUX input is added to the right headphone output.

5

Headphone Amplifier Function

The LM49360 headphone amplifier features National’s ground referenced architecture that eliminates the large DC-blocking ca-

pacitors required at the outputs of traditional headphone amplifiers. A low-noise inverting charge pump creates a negative supply

(HP_V_SS) from the positive supply voltage (LS_V_DD). The headphone amplifiers operate from these bipolar supplies, with the

amplifier outputs biased about GND, instead of a nominal DC voltage (typically V_DD/2), like traditional amplifiers. Because there is

no DC component to the headphone output signals, the large DC-blocking capacitors (typically 220μF) are not necessary, con-

serving board space and system cost, while improving frequency response.

Charge Pump Capacitor Selection

Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.

Charge Pump Flying Capacitor (C38)

The flying capacitor (C38) affects the load regulation and output impedance of the charge pump. A C38 value that is too low results

in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C38 improves load regulation and lowers charge

pump output impedance to an extent. Above 2.2μF, the R_DS(ON)of the charge pump switches and the ESR of C38 and C61 dominate

the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Please refer

to the demonstration board schematic shown in Figure 36.

Charge Pump Flying Capacitor (C61)

The value and ESR of the hold capacitor (C61) directly affects the ripple on CPV_SS. Increasing the value of C61 reduces output

ripple. Decreasing the ESR of C61 reduces both output ripple and charge pump output impedance. A lower value capacitor can

be used in systems with low maximum output power requirements. Please refer to the demonstration board schematic shown in

Figure 36.

TABLE 42. AUX_OUTPUT (0x13h)

Bits

0

Field

Description

The right DAC output is added to the AUX output.

The left DAC output is added to the AUX output.

The MIC input is added to the AUX output.

Reserved

DACR_AUX

DACL_AUX

MIC_AUX

RSVD

1

2

3

4

MONO_AUX

AUX_AUX

The MONO input is added to the AUX output.

The AUX input is added to the AUX output.

5

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Auxiliary Output Amplifier

The LM49360’s auxiliary output (AUXOUT) amplifier provides differential drive capability to loads that are connected across its

outputs. This results in output signals at the AUX_OUT+ and AUX_OUT- pins that are 180 degrees out of phase with respect to

each other. This effectively doubles the maximum possible output swing for a specific supply voltage when compared to single-

ended output configurations. The differential output configuration also allows the load to be isolated from ground since both the

AUX_OUT+ and AUX_OUT- pins are biased at the same DC potential. This eliminates the need for any large and expensive DC

blocking capacitors at the AUXOUT amplifier outputs. The load can then be directly connected to the positive and negative outputs

of the AUXOUT amplifier which then isolates it from any ground noise, thereby improving signal-to-noise-ratio (SNR) and power

supply rejection ratio (PSRR).

The AUXOUT amplifier has two modes of operation. The primary mode of operation is high current drive mode (Earpiece Mode)

where the AUXOUT amplifier can be used to differentially drive a mono earpiece speaker. The secondary mode of operation is

low current drive mode where the AUXOUT amplifier operates in a power saving mode (AUX_LINE_OUT Mode) to provide a

differential output that is used as a mono differential line level input to a standalone mono differential input class D amplifier

(LM4675) for stereo loudspeaker applications.

TABLE 43. OUTPUT_OPTIONS (0x14h)

Bits

0

Field

RSVD

Description

Reserved

3:1

LR_HP_LEVEL

This sets the gain of the left and right headphone amplifiers. The gain of the left and right headphone

amplifiers are always set to the same level.

LR_HP_LEVEL

Gain (dB)

0

000

001

–1.5

–3

010

011

–6

100

–9

101

–12

–15

–18

110

111

4

5

AUX_NEG_6dB

AUX_LINE_OUT

LS_LEVEL

This sets the gain of the Auxiliary output amplifier.

AUX_NEG_6dB

Gain (dB)

0

1

–6

This sets the Auxiliary output amplifier mode of operation.

AUX_LINE_OUT

Auxiliary Output Mode

Earpiece Amplifier

AUX_LINE_OUT

0

1

7:6

This sets the gain of the Class D loudspeaker amplifier.

LS_LEVEL

Gain (dB)

00

01

10

11

0

4

8

12

TABLE 44. ADC_INPUT (0x15h)

Bits

0

Field

Description

The right DAC output is added to the ADC right input.

The left DAC output is added to the ADC left input.

The MIC input is added to the ADC right input.

The MIC input is added to the ADC left input.

The AUX input is added to the ADC right input.

The MONO input is added to the ADC left input.

DACR_ADCR

DACL_ADCL

MIC_ADCR

MIC_ADCL

AUX_ADCR

MONO_ADCL

1

2

3

4

5

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TABLE 45. MIC_INPUT (0x16h)

Description

Bits

Field

3:0

MIC_LEVEL

This sets the gain of the microphone preamp.

MIC_LEVEL

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Gain

6dB

8dB

10dB

12dB

14dB

16dB

18dB

20dB

22dB

24dB

26dB

28dB

30dB

32dB

34dB

36dB

4

5

SE_DIFF

MUTE

If set, the MIC negative input is ignored. In single-ended mode, the MIC negative input pin should

be left floating.

If set, the microphone preamp is muted.

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TABLE 46. AUX_LEVEL (0x18h)

Description

Bits

Field

5:0

AUX_LEVEL This programs the AUX input level. All gain changes are performed at zero crossings.

AUX_LEVEL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011100

011101

011110

011111

Level

–46.5dB

–45dB

–43.5dB

–42dB

–40.5dB

–39dB

–37.5dB

–36dB

–34.5dB

–33dB

–31.5dB

–30dB

–28.5dB

–27dB

–25.5dB

–24dB

–22.5dB

–21dB

–19.5dB

–18dB

–16.5dB

–15dB

–13.5dB

–12dB

–10.5dB

–9dB

AUX_LEVEL

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

Level

1.5dB

3dB

4.5dB

6dB

7.5dB

9dB

10.5dB

12dB

13.5dB

15dB

16.5dB

18dB

–7.5dB

–6dB

–4.5dB

–3dB

–1.5dB

0dB

6

SE/DIFF

If set, the AUXL input is ignored. In single-ended mode, the AUXL input pin should be left

floating.

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TABLE 47. MONO_LEVEL (0x19h)

Description

Bits

Field

5:0

MONO_LEVEL This programs the MONO input level. All gain changes are performed at zero crossings.

MONO_LEVEL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011100

011101

011110

011111

Level

–46.5dB

–45dB

–43.5dB

–42dB

–40.5dB

–39dB

–37.5dB

–36dB

–34.5dB

–33dB

–31.5dB

–30dB

–28.5dB

–27dB

–25.5dB

–24dB

–22.5dB

–21dB

–19.5dB

–18dB

–16.5dB

–15dB

–13.5dB

–12dB

–10.5dB

–9dB

MONO_LEVEL

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

Level

1.5dB

3dB

4.5dB

6dB

7.5dB

9dB

10.5dB

12dB

13.5dB

15dB

16.5dB

18dB

–7.5dB

–6dB

–4.5dB

–3dB

–1.5dB

0dB

6

7

SE/DIFF

If set, the MONO– input is ignored. In single-ended mode, the MONO- input pin should

be left floating.

AUXL_MONO If set, AUXL is routed to the MONO Input Amplifier.

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Headphone Detection Circuit

The LM49360 features a headphone detection circuit (HDC) that automatically enables the headphone amplifier whenever the

insertion of a headphone plug is detected and disables the headphone amplifier during the removal of a headphone plug. The HDC

optimizes power management by automatically disabling any output amplifier that is not in use. The HDC eliminates the necessity

of polling the I²C bus for status changes. However, since the HDC requires the use of the GPIO pin, the PORT2_SDO functionality

sensing is required.

The HDC requires a headphone jack with a normally closed mechanical switch and a pull-up resistor, R_PU, tied between the

mechanical switch and I/O_V_DD(refer to Figure 22). Choosing a R_PUvalue of at least 500kΩ ensures minimal current draw through

the pull-up resistor. When the headphone amplifier is disabled, an internal 50kΩ pull-down, R_PD, is connected to each headphone

amplifier output. Without the presence of a headphone plug, the headphone jack’s mechanical switch is closed thereby connecting

the right headphone amplifier output to R_PU. The GPIO pin detects a logic low level due to the voltage division between R_PUand

R_PD. When the GPIO pin is set to HPSENSE mode, a logic low voltage reading causes the HDC to disable the headphone amplifier.

When a headphone plug is inserted, the mechanical connection between R_PUand R_PDis broken, resulting in a logic high level

detected by the GPIO pin. A logic high voltage reading causes the HDC to enable the headphone amplifier.

The HDC has four modes of operation that automatically enable/disable different combinations of the audio output amplifiers

contained within the LM49360. Having the choice of four different HDC settings maximizes power management flexibility to suit a

particular application. Please refer to the HP_SENSE (reg 0x1Bh) register table for a detailed discussion on the different HDC

modes of operation.

30128293

FIGURE 22. Application Circuit for Headphone Detection

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TABLE 48. HP_SENSE (0x1Bh)

Description

Bits

Field

0

HP SENSE

This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically

turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone

sense input. If the presence of a headphone insertion is detected, the headphone amplifier will

automatically turn on. If a headphone removal is detected, the headphone amplifier will

automatically turn off.

HPSENSE

Headphone Sense Status

0

1

Off

On

1

2

3

HPSENSE_D

This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically

turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone

sense input. If the presence of a headphone insertion is detected, the headphone amplifier will

automatically turn on and the Class D loudspeaker amplifier will turn off. If a headphone removal is

detected, the headphone amplifier will automatically turn off and the Class D loudspeaker amplifier

will turn on. This bit overrides bit 0 of this register.

HPSENSE_D

Headphone Sense Status

0

1

Off

On

HPSENSE_AUX

This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically

turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone

sense input. If the presence of a headphone insertion is detected, the headphone amplifier will

automatically turn on and the Earpiece / Auxout amplifier will turn off. If a headphone removal is

detected, the headphone amplifier will automatically turn off and the Earpiece / Auxout amplifier will

turn on. This bit overrides bit 0 and bit 1 of this register.

HPSENSE_AUX

Headphone Sense Status

0

1

Off

On

HPSENSE_AUX_D This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically

turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone

sense input. If the presence of a headphone insertion is detected, the headphone amplifier will

automatically turn on and the Class D loudspeaker amplifier along with the Earpiece / Auxout

amplifier will turn off. If a headphone removal is detected, the headphone amplifier will automatically

turn off and the Class D loudspeaker amplifier along with the Earpiece / Auxout amplifier will turn

on. This bit overrides bit 0, bit 1, and bit 2 of this register.

HPSENSE_AUX_D

Headphone Sense Status

0

1

Off

On

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33.0 ADC Control Registers

This register is used to control the LM49360's ADC:

TABLE 49. ADC Basic (0x20h)

Description

Bits

Field

0

MONO

This sets mono or stereo operation of the ADC.

MONO

0

ADC Operation

Stereo Audio

1

Mono Voice (Right ADC channel disabled, Left ADC channel active)

1

OSR

This sets the oversampling ratio of the ADC.

Stereo Audio ADC

OSR

Mono Voice ADC Oversampling Ratio

Oversampling Ratio

0

1

128

125

128

2

3

MUTE_L

MUTE_R

If set, a digital mute is applied to the Left (or mono) ADC output.

If set, a digital mute is applied to the Right ADC output.

6:4

ADC_CLK_SEL

This selects the source of the ADC clock domain, ADC_SOURCE_CLK.

ADC_CLK_SEL

Source

000

001

010

011

100

MCLK

PORT1_RX_CLK

PORT2_RX_CLK

PLL_OUTPUT1

PLL_OUTPUT2

7

ADC_DSP_ONLY

If set, the ADC's analog circuitry is disabled to reduce power consumption, however, ADC DSP

functionality is maintained. This can be used to perform asynchronous re-sampling between audio

rates of a common family. Setting this bit is also useful whenever applying Automatic Level Control

(ALC) to an analog only audio path.

TABLE 50. ADC_CLK_DIV (0x21h)

Description

Bits

Field

7:0

ADC_CLK_DIV

This programs the half cycle divider that precedes the ADC. The input of this divider should be

around 12MHz. The default of this divider is 0x00.

Program this divider with the division you want, multiplied by 2, and subtract 1.

ADC_CLK_DIV

00000000

00000001

00000010

00000011

—

Divides by

1

1.5

2

—

11111101

11111110

11111111

127

127.5

128

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TABLE 51. ADC_MIXER (0x23h)

Description

Bits

Field

1:0

ADC_MIX_LEVEL_L This sets the input level to the left ADC channel.

ADC_MIX_LEVEL_L

Level

0dB

00

01

1.35dB

3.5dB

6dB

10

11

3.2

ADC_MIX_LEVEL_R This sets the input level to the right ADC channel.

ADC_MIX_LEVEL_R

Level

0dB

00

01

10

11

1.35dB

3.5dB

6dB

4

STEREO_LINK

If set, this links ADC_MIX_LEVEL_R with ADC_MIX_LEVEL_L.

STEREO_LINK

Status

Off

0

1

On

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34.0 DAC Control Registers

This register is used to control the LM49360's DAC.

TABLE 52. DAC Basic (0x30h)

Description

Bits

Field

1:0

MODE

This programs the over sampling ratio of the stereo DAC.

MODE

DAC Oversampling Ratio

00

125

128

01

10

11

64 (Default)

RSVD

2

3

MUTE_L

MUTE_R

This digitally mutes the Left DAC output.

This digitally mutes the Right DAC output.

6:4

DAC_CLK_SEL

This selects the source of the DAC clock domain, DAC_SOURCE_CLK.

DAC_CLK_SEL

Source

000

001

010

011

100

MCLK

PORT1_RX_CLK

PORT2_RX_CLK

PLL_OUTPUT1

PLL_OUTPUT2

7

DSP_ONLY

If set, the DAC's analog circuitry is disabled to reduce power consumption, however DAC DSP

functionality is maintained. This can be used to perform asynchronous re-sampling between audio

rates of a common family.

TABLE 53. DAC_CLK_DIV (0x31h)

Description

Bits

Field

7:0

DAC_CLK_DIV

This programs the half cycle divider that precedes the DAC. The input of this divider should be

around 12MHz. The default of this divider is 0x03 which gives a division by 2.

Program this divider with the division you want, multiplied by 2, and subtract 1.

DAC_CLK_DIV

00000000

00000001

00000010

00000011

—

Divides by

1

1.5

2 (Default)

—

11111101

11111110

11111111

127

127.5

128

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82

35.0 Digital Mixer Control Registers

Digital Mixer

The LM49360’s digital mixer allows for flexible routing of digital audio signals between both audio ports, DAC, and ADC. This mixer

handles which digital data path (Port1 RX data, Port2 RX data, or ADC output) is routed to the DAC input. The digital mixer also

selects the appropriate digital data path (Port1 RX data, Port2 RX data, ADC output, DAC DSP output, or ADC DSP output) that

is used for data transmission on Audio Port 1 and 2. Audio inputs to the digital mixer can be attenuated down to -18dB to avoid

clipping conditions.

Another key feature of the digital mixer is sample rate conversion (SRC) between audio ports. This allows simultaneous operation

of the dual audio ports even if each port is operating at a different sample rate. The LM49360 can be used as an audio port bridge

with SRC capability. The digital mixer allows either straight pass through between audio ports or, if desired, DSP effects can be

added to the digital audio signal during audio port bridge operation. The digital mixer automatically handles stereo I²S to mono

PCM conversion between audio ports and vice versa.

30128237

FIGURE 23. Digital Mixer

The LM49360 includes two separate and independent DSP blocks, one for the DAC and the other for the ADC. The digital mixer

also allows both DSP blocks to be cascaded together in either order so that the DSP effects from both blocks can be combined

into the same signal path.

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This register is used to control the LM49360's digital mixer.

TABLE 54. Input Levels 1 (0x40h)

Bits

Field

Description

1:0

PORT1_RX_L

_LVL

This programs the input level of the data arriving from the left receive channel of Audio Port 1.

PORT1_RX_L_LVL

Level

0dB

00

01

10

11

–6dB

–12dB

–18dB

3:2

5:4

7:6

PORT1_RX_R

_LVL

This programs the input level of the data arriving from the right receive channel of Audio Port 1.

PORT1_RX_R_LVL

Level

0dB

00

01

10

11

–6dB

–12dB

–18dB

PORT2_RX_L

_LVL

This programs the input level of the data arriving from the left receive channel of Audio Port 2.

PORT2_RX_L_LVL

Level

0dB

00

01

10

11

–6dB

–12dB

–18dB

PORT2_RX_R

_LVL

This programs the input level of the data arriving from the right receive channel of Audio Port 2.

PORT2_RX_R_LVL

Level

0dB

00

01

10

11

–6dB

–12dB

–18dB

TABLE 55. Input Levels 2 (0x41h)

Bits

Field

Description

1:0

3:2

5:4

ADC_L_LVL

This programs the input level of the data arriving from the left ADC channel.

ADC_L_LVL

Level

0dB

00

01

–6dB

–12dB

–18dB

10

11

ADC_R_LVL

This programs the input level of the data arriving from the right ADC channel.

ADC_R_LVL

Level

0dB

00

01

10

11

–6dB

–12dB

–18dB

INTERP_L_LVL This programs the input level of the data arriving from the left DAC's interpolator output.

INTERP_L_LVL

Level

0dB

00

01

10

11

–6dB

–12dB

–18dB

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84

Bits

Field

Description

7:6

INTERP_R_LVL This programs the input level of the data arriving from the right DAC's interpolator output.

INTERP_R_LVL

Level

0dB

00

01

10

11

–6dB

–12dB

–18dB

TABLE 56. Audio Port 1 Input (0x42h)

Bits

Field

Description

1:0

L_SEL

This selects which input is fed to the Left TX Channel of Audio Port 1.

L_SEL

Selected Input

None

00

01

ADC_L

10

PORT2_RX_L

DAC_INTERP_L

11

3:2

R_SEL

This selects which input is fed to the Right TX Channel of Audio Port 1.

R_SEL

Selected Input

None

00

01

ADC_R

10

PORT2_RX_R

DAC_INTERP_R

11

4

5

SWAP

MONO

If set, this swaps the Left and Right outputs to Audio Port 1.

If set, the right channel is ignored and the left channel becomes (left+right) / 2.

TABLE 57. Audio Port 2 Input (0x43h)

Bits

Field

Description

1:0

L_SEL

This selects which input is fed to Audio Port 2's Left TX Channel.

L_SEL

Selected Input

00

None

01

ADC_L

10

PORT1_RX_L

DAC_INTERP_L

11

3:2

R_SEL

This selects which input is fed to Audio Port 2's Right TX Channel.

R_SEL

Selected Input

None

00

01

ADC_R

10

PORT1_RX_R

DAC_INTERP_R

11

4

5

SWAP

MONO

If set, this swaps the Left and Right outputs to Audio Port 2.

If set, the right channel is ignored and the left channel becomes (left+right) / 2.

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TABLE 58. DAC Input Select (0x44h)

Bits

0

Field

Description

This adds Audio Port 1's left RX channel to the DAC's left input.

This adds Audio Port 2's left RX channel to the DAC's left input.

This adds the ADC's left output to the DAC's left input

PORT1_L

PORT2_L

ADC_L

1

2

3

PORT1_R

PORT2_R

ADC_R

This adds Audio Port 1's right RX channel to the DAC's right input.

This adds Audio Port 2's right RX channel to the DAC's right input.

This adds the ADC's right output to the DAC's right input.

If set, this swaps the Left and Right inputs to the DAC.

4

5

6

SWAP

TABLE 59. Decimator Input Select (0x45h)

Bits

Field

Description

1:0

L_SEL

This selects which input is fed to the left ADC's decimator input.

L_SEL

Selected Input

None

00

01

PORT1_RX_L

PORT2_RX_L

DAC_INTERP_L

10

11

3:2

5:4

R_SEL

This selects which input is fed to the right ADC's decimator input.

R_SEL

00

Selected Input

None

01

PORT1_RX_R

PORT2_RX_R

DAC_INTERP_R

10

11

MXR_CLK_SEL This selects the source of the Digital Mixer Clock. The 'Auto' setting will automatically select the source

with the highest clock frequency. If the DAC interpolator output (DAC_OSR_L or DAC_OSR_R) is

selected, then MXR_CLK_SEL should be set to '10'.

MXR_CLK_SEL

Selected Input

Auto

00

01

10

11

MCLK

DAC

ADC

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36.0 Audio Port Control Registers

30128271

FIGURE 24. I²S Serial Data Format (24 bit example)

30128272

FIGURE 25. Left Justified Data Format (24 bit example)

30128270

FIGURE 26. Right Justified Data Format (24 bit example)

30128234

FIGURE 27. PCM Serial Data Format (16 bit example)

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301282i1

FIGURE 28. Timing for I²S Master

301282i2

FIGURE 29. Timing for I²S Slave

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The following registers are used to control the LM49360's audio ports. Audio Port 1 and Audio Port 2 are identical. Port 1 is

programmed through the (0x5Xh) registers. Port 2 is programmed through the (0x6Xh) registers.

TABLE 60. BASIC_SETUP (0x50h/0x60h)

Bits

0

Field

Description

STEREO

If set, the audio port will receive and transmit stereo data.

1

RX_ENABLE

If set, the input is enabled (enables the SDI port and input shift register and any clock

generation required).

2

TX_ENABLE

If set, the output is enabled (enables the SDO port and output shift register and any clock

generation required).

3

4

5

CLOCK_MS

SYNC_MS

If set, the audio port will transmit the clock when either the RX or TX is enabled.

If set, the audio port will transmit the sync signal when either the RX or TX is enabled.

This sets how data is clocked by the Audio Port.

CLOCK_PHASE

Audio Data Mode

0

1

I²S (TX on falling edge, RX on rising edge)

PCM (TX on rising edge, RX on falling edge)

6

7

STEREO_SYNC_PHASE

If set, this reverses the left and right channel data of the Audio Port.

STEREO_SYNC_PHASE

0

Audio Port Data Orientation

Left channel data goes to left channel output.

Right channel data goes to right channel output.

1

Right channel data goes to left channel output.

Left channel data goes to right channel output.

SYNC_INVERT

If this bit is set, the SYNC is inverted before the receiver and transmitter.

SYNC_INVERT

SYNC ORIENTATION

0

1

SYNC Low = Left, SYNC High = Right

SYNC Low = Right, SYNC High = Left

TABLE 61. CLK_GEN_1 (0x51h/0x61h)

Bits

Field

Description

5:0

HALF_CYCLE_CLK_ This programs the half-cycle divider that generates the master clocks in the audio port. The default

DIV

of this divider is 0x00, i.e. bypassed.

Program this divider with the required division multiplied by 2, and subtract 1.

HALF_CYCLE_CLK_DIV

Divides By

000000

000001

000010

000011

—

BYPASS

1

1.5

2

—

111101

111110

11111

31

31.5

32

6

CLOCK_SEL

This selects the clock source of the master mode Audio Port Clock generator's half-cycle divider.

0 = DAC_SOURCE_CLK

1 = ADC_SOURCE_CLK

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TABLE 62. CLK_GEN_1 (0x52h/62h)

Description

Bits

Field

2:0

SYNTH_NUM

Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in

master mode.

SYNTH_NUM

Numerator

000

001

010

011

100

101

110

111

SYNTH_DENOM (1/1)

100/SYNTH_DENOM

96/SYNTH_DENOM

80/SYNTH_DENOM

72/SYNTH_DENOM

64/SYNTH_DENOM

48/SYNTH_DENOM

0/SYNTH_DENOM

3

SYNTH_DENOM

Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or Port 2 clock in master

mode.

SYNTH_DENOM

Denominator

128

0

1

125

TABLE 63. CLK_GEN_1 (0x53h/63h)

Description

Bits

Field

2:0

SYNC_RATE

This sets the number of clock cycles before the sync pattern repeats. This depends if the audio port

data is mono or stereo.

In MONO mode:

SYNC_RATE

Number of Clock Cycles

000

8

001

12

16

18

20

24

25

32

010

011

100

101

110

111

In STEREO mode:

SYNC_RATE

000

Number of Clock Cycles

16

24

32

36

40

48

50

64

001

010

011

100

101

110

111

www.ti.com

90

Bits

Field

Description

5:3

SYNC_WIDTH

In MONO mode, this programs the width (in number of bits) of the SYNC signal.

SYNC_WIDTH

Width of SYNC (in bits)

000

001

010

011

100

101

110

111

1

2

4

7

8

11

15

16

TABLE 64. DATA_WIDTHS (0x54h/64h)

Bits

Field

Description

2:0

RX_WIDTH

This programs the expected bits per word of the serial data input SDI.

RX_WIDTH

Bits

24

20

18

16

14

13

12

8

000

001

010

011

100

101

110

111

5:3

TX_WIDTH

This programs the bits per word of the serial data output SDO.

TX_WIDTH

000

Description

24

20

18

16

14

13

12

8

001

010

011

100

101

110

111

7:6

TX_EXTRA_BITS This programs the TX data output padding.

TX_EXTRA_BITS

Description

00

01

10

11

0

1

High-Z

91

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TABLE 65. RX_MODE (0x55h/x65h)

Bits

Field

Description

0

RX_MODE

This sets the RX data input justification with respect to the SYNC signal.

RX_MODE

Description

MSB Justified

LSB Justified

0

1

5:1

MSB_POSITION This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of

the frame (LSB Justified).

MSB_POSITION

Description

00000

0(Left Justified/PCM Long)

00001

1(I²S/PCM Short)

00010

2

00011

3

00100

4

00101

5

00110

6

00111

7

01000

8

01001

9

01010

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

6

7

COMPAND

If set, received audio data will be companded.

This sets the audio companding mode.

μLaw/A-Law

Compand Mode

μLaw/A-Law

0

μLaw

1

A-Law

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92

TABLE 66. TX_MODE (0x56h/x66h)

Bits

Field

Description

0

TX_MODE

This sets the TX data input justification with respect to the SYNC signal.

TX_MODE

Description

MSB Justified

LSB Justified

0

1

5:1

MSB_POSITION This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of

the frame (LSB Justified).

MSB_POSITION

Description

00000

0(Left Justified/PCM Long)

1(I²S/PCM Short)

00001

00010

2

00011

3

00100

4

00101

5

00110

6

00111

7

01000

8

01001

9

01010

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

6

7

COMPAND

If set, transmitted audio data will be companded.

This sets the audio companding mode.

μLaw/A-Law

Compand Mode

μLaw/A-Law

0

μLaw

1

A-Law

93

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37.0 Digital Effects Engine

Digital Signal Processor (DSP)

The LM49360 is designed to handle the entire audio signal conditioning and processing within the audio system, thereby freeing

up the workload of any other applications processor contained within the system. The LM49360 features two independent DSPs,

one for the DAC and the other for the ADC. The DAC DSP features digital volume control, automatic level control (ALC), digital

soft clip compression and a 5-band parametric EQ. The ADC DSP features digital volume control, automatic level control (ALC)

and digital soft clip compression. The effects chain of each DSP engine is shown by the diagrams below.

30128257

FIGURE 30. ADC DSP Effects Chain

30128236

FIGURE 31. DAC DSP Effects Chain

The ADC and DAC DSP engines can be cascaded together in any order via the digital mixer to combine different audio effects to

the same signal path. For example, a signal can be processed with high-pass filtering from the ADC effects engine with ALC from

the DAC effects engine.

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94

TABLE 67. ADC EFFECTS (0x70h)

Description

Bits

0

Field

ADC_HPF_ENB

ADC_ALC_ENB

ADC_PK_ENB

RSVD

This enables the ADC's High Pass Filter.

This enables the ADC's Automatic Level Control.

This enables the ADC's Peak Detector.

Reserved

1

2

3

4

ADC_SCLP_ENB

This enables the ADC's Soft Clip Feature.

TABLE 68. DAC EFFECTS (0x71h)

Bits

0

Field

Description

DAC_ALC_ENB

DAC_PK_ENB

DAC_EQ_ENB

RSVD

This enables the DAC's Automatic Level Control.

This enables the DAC's Peak Detector.

This enables the DAC's 5-band Parametric EQ.

Reserved

1

2

3

4

ADC_SCLP_ENB

This enables the DAC's Soft Clip Feature.

TABLE 69. HPF MODE (0x80h)

Bits

Field

Description

2:0

HPF_MODE

This configures the ADC's High Pass Filter.

HPF_MODE

000

FILTER CHARACTERISTICS

8kHz Voice

001

12kHz Voice

010

16kHz Voice

011

24kHz Voice

100

32kHz Voice

101

32kHz Audio

110

48kHz Audio

111

96kHz Audio

95

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ALC Overview

The Automatic Level Control (ALC) system can be used to regulate the audio output level to a user defined target level. The ALC

feature is especially useful whenever the level of the audio input is unknown, unpredictable, or has a large dynamic range. The

main purpose of the ALC is to optimize the dynamic range of the audio input to audio output path.

There are two separate and independent ALC circuits in the LM49360. One of the ALC circuits is located within the DAC DSP

effects block. The other ALC circuit is integrated into the ADC DSP effects block. The DAC ALC controls the DAC digital gain. The

ADC ALC controls the mono/auxiliary input amplifier gain or microphone preamplifier gain. The dual ALCs can be used to regulate

the level of the analog (AUX, MONO, MIC) and digital (Port1 Data In, Port2 Data In) audio inputs. The ALC regulated output can

be routed to any of the LM49360’s amplifier outputs for playback. The ALC regulated output can also be routed to Audio Port1 or

Audio Port2 for digital data transmission via I²S or PCM.

Only audio inputs that are considered signals (rather than noise) are sent to the ALC’s peak detector block. The peak detector

compares the level of the audio input versus the ALC target level (TARGET_LEVEL). Signals lower than the target level will be

amplified and signals higher than the target level will be attenuated. Any audio input that is lower than the level specified by the

noise floor level (NOISE_FLOOR) will be considered as noise and will be gated from the ALC’s peak detector in order to avoid

noise pumping. So it is important to set NOISE_FLOOR to correlate with the signal to noise ratio of the corresponding audio path.

In some instances (ie. Conference calls), it may be desirable to mute audio input signals that consist solely of background noise

from the audio output. This is accomplished by enabling the ALC’s noise gate (NG_ENB). When the noise gate is enabled, signals

lower than the noise floor level will be muted from the audio output.

If the audio input signal is below the target level, the ALC will increase the gain of the corresponding volume control until the signal

reaches the target level. The rate at which the ALC performs gain increases is known as decay rate (DECAY RATE). But before

each ALC gain increase the ALC must wait a predetermined amount of time (HOLD TIME). If the audio input signal is above the

target level, the ALC will decrease the gain of the corresponding volume control until the signal reaches the target level. The rate

at which the ALC performs attenuation is known as attack rate (ATTACK RATE). The ALC’s peak detector tracks increases in

audio input signal amplitude instantaneously, but tracks decreases in audio input signal amplitude at programmable rate (PEAK

DECAY TIME). ATTACK RATE, DECAY RATE, HOLD TIME, and PEAK DECAY TIME are fully adjustable which allows flexible

operation of the ALC circuit. The ALC’s timers are based on the sample rate of the DAC or ADC, so the closest corresponding

sample rate must be programmed into the DAC SAMPLE setting (for DAC ALC) or the ADC SAMPLE (for ADC ALC).

30128291

FIGURE 32. ALC Example

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96

Limiter

The LM49360’s ALC features a limiter function. The purpose of the limiter is to limit the maximum level of the audio signal to the

specified ALC target level. When the limiter is enabled, the ALC will decrease the gain of the volume control whenever the audio

signal is higher than the specified target level. The programmed I²C gain setting when the limiter is first enabled is the maximum

gain setting that the ALC limiter will apply to the audio signal. Gain increases beyond the original I²C gain setting are disabled.

This is in contrast to ALC operation with the limiter disabled, where the ALC may increase gain of audio signals below target level

using gain settings beyond the original I²C gain setting. Therefore, it is important to set the gain of the audio path to the desired

setting before enabling the ALC limiter function.

The limiter’s target level can be set just below the clipping level of the output amplifier or ADC in order to prevent harsh distortions

delivered to the loudspeaker or headphone on the receiving end. This method of ALC limiter operation is also known as “no clip”

mode. Operating the ALC limiter in “no clip” mode maximizes the dynamic range of the audio amplifier or ADC while ensuring that

the audio signal will never clip. Utilizing the ALC limiter in “no clip” mode also protects the loudspeaker from damage due to harmful

overdriven conditions.

The ALC limiter’s target level can also be set for a predetermined maximum output power or voltage level. This method of ALC

limiter operation is known as “power limit” mode. Operating the ALC limiter in “power limit” mode prevents the speaker or headphone

from playing at unsafe hearing levels that can permanently damage the end user’s ears. “Power limit” operation is especially useful

for applications such as listening to music through a set of headphones. Another benefit of using the ALC limit in “power limit” mode

is to extend battery life by reducing power consumption of the output amplifiers during audio playback.

30128292

FIGURE 33. ALC Limiter

97

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TABLE 70. ADC_ALC_1 (0x81h)

Description

This programs the timers on the ALC with the closest sample rate of the ADC.

Bits

Field

2:0

ADC_SAMPLE

Expected ADC f_S

000

001

010

011

100

101

110

111

8kHz

12kHz

16kHz

24kHz

32kHz

48kHz

96kHz

192kHz

3

4

LIMITER

If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate the

signal as soon as it reaches target and release it at the decay rate, once signal level reduces below

target. The I²C gain setting (at the time the LIMITER is enabled) is the maximum gain that the ALC

will apply. Care should be taken when choosing the optimum I²C gain setting whenever enabling

the Limiter.

STEREO LINK

If set, the ALC circuit uses the stereo average of the input signals to control the gain of the stereo

output. This maintains stereo imaging. If this bit is cleared, then both channels operate as dual

mono.

5

6

7

SOURCE_RSEL

SOURCE_LSEL

SOURCE_OVR

If both SOURCE_OVR and this bit is set, the right ADC ALC channel will be active.

If both SOURCE_OVR and this bit is set, the left ADC ALC channel will be active.

If set, the active channel of the ADC ALC is determined by SOURCE_RSEL and SOURCE_LSEL.

If cleared, the active channel of the ADC ALC is determined by the selected input to the ADC.

MONO enables left ALC, AUX enables right ALC, MIC enables left and / or right ALC depending

on which ADC channel MIC is selected to.

TABLE 71. ADC_ALC_2 (0x82h)

Description

Bits

Field

3:0

NOISE_FLOOR

This sets the anticipated noise floor. Signals lower than the noise floor specified will be gated from

the ALC to avoid noise pumping.

NOISE_FLOOR

0000

Noise Floor (dB)

–39

–42

–45

–48

–51

–54

–57

–60

–63

–66

–69

–72

–75

–78

–81

–84

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

4

NG_ENB

This enables the Noise Gate.

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98

TABLE 72. ADC_ALC_3 (0x83h)

Description

Bits

Field

4:0

TARGET_LEVEL

This sets the desired target output level. Signals lower than this will be amplified and signals larger

than this will be attenuated.

TARGET_LEVEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Target Level (dB)

–1.5

–3

–4.5

–6

–7.5

–9

–10.5

–12

–13.5

–15

–16.5

–18

–19.5

–21

–22.5

–24

–25.5

–27

–28.5

–30

–31.5

–33

–34.5

–36

–37.5

–39

–40.5

–42

–43.5

–45

–46.5

–48

99

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TABLE 73. ADC_ALC_4 (0x84h)

Description

This sets the rate at which the ALC will reduce gain if it detects the input signal is large.

Bits

Field

4:0

ATTACK_RATE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Time between gain steps (μs)

21

42

83

167

250

333

417

542

729

958

1250 (Default)

1604

1896

2208

2792

3708

4792

5688

6563

8396

11000

14167

17083

20000

25000

32000

45000

60000

75000

87500

100000

114583

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100

TABLE 74. ADC_ALC_5 (0x85h)

Description

Bits

Field

4:0

DECAY_RATE

This sets the rate at which the ALC will increase gain if it detects the input signal is too

small.

DECAY_RATE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

PK_DECAY_RATE

000

Time between gain steps (μs)

104

125

167

250

292

396

500

708

896

1250

1396 (Default)

2000

2708

3500

4750

6250

8000

11000

14000

18500

25000

32000

42000

55000

72500

100000

125000

160000

225000

300000

375000

500000 (0.5s)

Max Time to track decay

1.3ms (Default)

2.6ms

7:5

PK_DECAY_RATE

001

010

5.3ms

011

10.6ms

21.3ms

42.6.3ms

85.5ms

2.73 secs

100

101

110

111

101

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TABLE 75. ADC_ALC_6 (0x86h)

Description

This sets how long the ALC circuit waits before increasing the gain.

Bits

Field

4:0

HOLD_TIME

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Time (ms)

1

1.25

1.6

2

2.5

3.2

4

5

6.25

8

10 (Default)

12.5

16

20

25

32

40

50

64

80

100

125

160

200

250

320

400

500

640

800

1000

1250

TABLE 76. ADC_ALC_7 (0x87h)

Bits

Field

Description

5:0

MAX_LEVEL

This sets the maximum allowed gain of the volume control to the output amplifier

whenever the ALC is use. If the volume control is less than 6 bits, the relevant LSBs are

used as the limit and the MSBs are ignored.

TABLE 77. ADC_ALC_8 (0x88h)

Description

Bits

Field

5:0

MIN_LEVEL

This sets the minimum allowed gain of the volume control to the output amplifier whenever

the ALC is use. If the volume control is less than 6 bits, the relevant LSBs are used as

the limit and the MSBs are ignored.

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102

TABLE 78. ADC_L_LEVEL (0x89h)

Description

This sets the post ADC digital gain of the left channel.

Bits

Field

5:0

ADC_L_LEVEL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

Level

-76.5dB

-75dB

ADC_L_LEVEL

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

Level

-28.5dB

-27dB

-25.5dB

-24dB

-22.5dB

-21dB

-20.5dB

-18dB

-16.5dB

-15dB

-13.5dB

-12dB

-10.5dB

-9dB

-73.5dB

-72dB

-70.5dB

-69dB

-67.5dB

-66dB

-64.5dB

-63dB

-61.5dB

-60dB

-58.5dB

-57dB

-55.5dB

-54dB

-7.5dB

-6dB

-52.5dB

-51dB

-4.5dB

-3dB

-49.5dB

-48dB

-1.5dB

0dB

-46.5dB

-45dB

1.5dB

3dB

-43.5dB

-42dB

4.5dB

6dB

-40.5dB

-39dB

7.5dB

9dB

-37.5dB

-36dB

10.5dB

12dB

-34.5dB

-33dB

13.5dB

15dB

-31.5dB

-30dB

16.5dB

18dB

6

STEREO_LINK

If set, this links the ADC_R_LEVEL with ADC_L_LEVEL.

103

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TABLE 79. ADC_R_LEVEL (0x8Ah)

Description

This sets the post ADC digital gain of the right channel.

Bits

Field

5:0

ADC_R_LEVEL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

Level

-76.5dB

-75dB

ADC_R_LEVEL

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

Level

-28.5dB

-27dB

-25.5dB

-24dB

-22.5dB

-21dB

-20.5dB

-18dB

-16.5dB

-15dB

-13.5dB

-12dB

-10.5dB

-9dB

-73.5dB

-72dB

-70.5dB

-69dB

-67.5dB

-66dB

-64.5dB

-63dB

-61.5dB

-60dB

-58.5dB

-57dB

-55.5dB

-54dB

-7.5dB

-6dB

-52.5dB

-51dB

-4.5dB

-3dB

-49.5dB

-48dB

-1.5dB

0dB

-46.5dB

-45dB

1.5dB

3dB

-43.5dB

-42dB

4.5dB

6dB

-40.5dB

-39dB

7.5dB

9dB

-37.5dB

-36dB

10.5dB

12dB

-34.5dB

-33dB

13.5dB

15dB

-31.5dB

-30dB

16.5dB

18dB

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104

Digital Audio Compressor

The LM49360 features a digital audio compressor on both the DAC and ADC paths. The compressor works by reducing the level

of the audio signal that is higher than the level set by the audio compressor threshold level (THRESHOLD) by a fixed ratio (com-

pressor output / compressor input) that is set by a predetermined audio compression ratio (RATIO). Higher compression ratios

result in more compression as shown in Figure 34. The audio compressor can be used in conjunction with the ALC to limit audio

peaks that the ALC may not be fast enough to react to.

30128289

FIGURE 34. Audio Compressor Effect

105

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Soft Knee Function

The LM49360’s audio compressor also features a soft knee function that smooths the harsh edges found during clipping of an

audio signal. For audio signals higher than the compressor threshold level, the soft knee function gradually increases the com-

pression ratio for increasing levels of audio signal beyond the compressor threshold. To achieve the smoothing effect to prevent

hard clipping, the soft knee function initially compresses the audio signal at the smallest ratio and then incrementally increases the

compression ratio if required. The highest level of compression applied by the soft knee function is set by the compressor ratio.

The effect of the soft knee function is shown in Figure 35.

30128290

FIGURE 35. Soft Knee Example with Compression Ratio Setting of 1:3.4

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106

TABLE 80. SOFTCLIP1 (0x90h)

Field

THRESHOLD

Bits

Description

3:0

This sets the threshold level of the audio compressor. Audio signals

above the threshold will be compressed.

THRESHOLD

0000

Threshold Level (dB)

-36dB

0001

-30dB

0010

-24dB

0011

-20dB

0100

-18dB

0101

-17dB

0110

-16dB

0111

-15dB

1000

-14dB

1001

-12dB

1010

-10dB

1011

-8dB

1100

-6dB

1101

-4dB

1110

-2.5dB

-1dB

1111

4

SOFT_KNEE

If set, the audio compressor will automatically apply higher

compression ratios to audio signals higher than the threshold level.

As the audio signal approaches levels higher than the threshold,

SOFT_KNEE will increase the compression RATIO. The highest

compression that the SOFT_KNEE algorithm will apply is the

compression that is set by RATIO.

107

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TABLE 81. SOFTCLIP2 (0x91h)

Field

RATIO

Bits

Description

4:0

This sets the ratio at which the audio is compressed to when it

passes beyond the threshold. In SOFT_KNEE mode this is the final

level of compression.

RATIO

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Ratio

1:1 (Bypass)

1:1.2

1:1.4

1:1.7

1:2.0

1:2.4

1:2.8

1:3.4

1:4.0

1:4.7

1:5.7

1:6.7

1:8.0

1:9.5

1:11.3

1:13.5

1:16.0

1:19.0

1:22.8

1:27.0

1:32.0

1:37.9

1:45.5

1:53.9

1:64.0

1:75.0

1:91.0

1:108

1:128

1:152

1:182

1:215

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108

TABLE 82. SOFTCLIP3 (0x92h)

Field

LEVEL

Bits

Description

3:0

This sets the post compressor gain level.

LEVEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Level (dB)

-22.5dB

-21dB

-19.5dB

-18dB

-16.5dB

-15dB

-13.5dB

-12dB

-10.5dB

-9dB

-7.5dB

-6dB

-4.5dB

-3dB

-1.5dB

0dB

1.5dB

3dB

4.5dB

6dB

7.5dB

9dB

10.5dB

12dB

13.5dB

15dB

16.5dB

18dB

19.5dB

21dB

22.5dB

24dB

109

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38.0 DAC Effects Registers

TABLE 83. DAC_ALC_1 (0xA0h)

Bits

Field

Description

2:0

DAC_SAMPLE

This programs the timers on the ALC with the closest DAC sample

rate.

DAC_SAMPLE

Expected DAC f_S

8kHz

000

001

010

011

100

101

110

111

12kHz

16kHz

24kHz

32kHz

48kHz

96kHz

192kHz

3

4

LIMITER

If set, the circuit will never apply gain to the signal, no matter how

small, but it will attenuate the signal as soon as it reaches target

and release it at the decay rate, once signal level reduces below

target. The I²C gain setting (at the time the LIMITER is enabled) is

the maximum gain that the ALC will apply. Care should be taken

when choosing the optimum I²C gain setting whenever enabling the

Limiter.

STEREO LINK

If set, the ALC circuit uses the stereo average of the input signals

to control the gain of the stereo output. This maintains stereo

imaging. If this bit is cleared, then both channels operate as dual

mono.

TABLE 84. DAC_ALC_2 (0xA1h)

Bits

Field

Description

3:0

NOISE_FLOOR

This sets the anticipated noise floor. Signals lower than the

specified noise floor will be gated from the ALC to avoid noise

pumping.

NOISE_FLOOR

Noise Floor (dB)

0000

-39

-42

-45

-48

-51

-54

-57

-60

-63

-66

-69

-72

-75

-78

-81

-84

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

4

NG_ENB

This enables the Noise Gate.

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110

TABLE 85. DAC_ALC_3 (0xA2h)

Field

TARGET_LEVEL

Bits

Description

4:0

This sets the desired output level. Signals lower than this will be

amplified and signals larger than this will be attenuated.

TARGET_LEVEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Target Level (dB)

-1.5

-3

-4.5

-6

-7.5

-9

-10.5

-12

-13.5

-15

-16.5

-18

-19.5

-21

-22.5

-24

-25.5

-27

-28.5

-30

-31.5

-33

-34.5

-36

-37.5

-39

-40.5

-42

-43.5

-45

-46.5

-48

111

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TABLE 86. DAC_ALC_4 (0xA3h)

Field

ATTACK_RATE

Bits

Description

4:0

This sets the rate at which the ALC will reduce gain if it detects the

input signal is too large.

ATTACK_RATE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Time between gain steps(us)

21

42

83

167

250

333

417

542

729

958

1250 (Default)

1604

1896

2208

2792

3708

4792

5688

6563

8396

11000

14167

17083

20000

25000

32000

45000

60000

75000

87500

100000

114583

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112

TABLE 87. DAC_ALC_5 (0xA4h)

Bits

Field

Description

4:0

DECAY_RATE

This sets the rate at which the ALC will increase gain if it detects the

input signal is too small.

DECAY_RATE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Time between gain steps(us)

104

125

167

250

292

396

500

708

896

1250

1396 (Default)

2000

2708

3500

4750

6250

8000

11000

14000

18500

25000

32000

42000

55000

72500

100000

125000

160000

225000

300000

375000

500000 (0.5s)

7:5

PK_DECAY_RATE

This sets how precise the ALC will track amplitude reductions of the

audio input. The shorter the length of time for PK_DECAY_RATE, the

more responsive the ALC will be when applying gain increases

whenever the audio falls below target level.

PK_DECAY_RATE

Time

1.3ms (Default)

2.6ms

000

001

010

011

100

101

110

111

5.3ms

10.6ms

21.3ms

42.6ms

85.5ms

2.73secs

113

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TABLE 88. DAC_ALC_6 (0xA5h)

Field

HOLD_TIME

Bits

Description

4:0

This sets how long the ALC circuit waits before increasing the gain.

HOLDTIME

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Time (ms)

1

1.25

1.6

2

2.5

3.2

4

5

6.25

8

10 (Default)

12.5

16

20

25

32

40

50

64

80

100

125

160

200

250

320

400

500

640

800

1000

1250

TABLE 89. DAC_ALC_7 (0xA6h)

Bits

Field

Description

5:0

MAX_LEVEL

This sets the maximum allowed gain to the digital level control

when the ALC is used.

TABLE 90. DAC_ALC_8 (0xA7h)

Bits

Field

Description

5:0

MIN_LEVEL

This sets the minimum allowed gain to the digital level control

when the ALC is used.

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114

TABLE 91. DAC_L_LEVEL (0xA8h)

Description

Bits

Field

5:0

DAC_L_LEVEL

This sets the pre DAC digital gain.

DAC_L_LEVEL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

Level

-76.5dB

-75dB

DAC_L_LEVEL

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

Level

-28.5dB

-27dB

-25.5dB

-24dB

-22.5dB

-21dB

-20.5dB

-18dB

-16.5dB

-15dB

-13.5dB

-12dB

-10.5dB

-9dB

-73.5dB

-72dB

-70.5dB

-69dB

-67.5dB

-66dB

-64.5dB

-63dB

-61.5dB

-60dB

-58.5dB

-57dB

-55.5dB

-54dB

-7.5dB

-6dB

-52.5dB

-51dB

-4.5dB

-3dB

-49.5dB

-48dB

-1.5dB

0dB

-46.5dB

-45dB

1.5dB

3dB

-43.5dB

-42dB

4.5dB

6dB

-40.5dB

-39dB

7.5dB

9dB

-37.5dB

-36dB

10.5dB

12dB

-34.5dB

-33dB

13.5dB

15dB

-31.5dB

-30dB

16.5dB

18dB

6

STEREO_LINK

If set, this links DAC_R_LEVEL with DAC_L_LEVEL.

115

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TABLE 92. DAC_R_LEVEL (0xA9h)

Description

Bits

Field

5:0

DAC_R_LEVEL

This sets the pre DAC digital gain.

DAC_R_LEVEL

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

Level

-76.5dB

-75dB

DAC_R_LEVEL

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

Level

-28.5dB

-27dB

-25.5dB

-24dB

-22.5dB

-21dB

-20.5dB

-18dB

-16.5dB

-15dB

-13.5dB

-12dB

-10.5dB

-9dB

-73.5dB

-72dB

-70.5dB

-69dB

-67.5dB

-66dB

-64.5dB

-63dB

-61.5dB

-60dB

-58.5dB

-57dB

-55.5dB

-54dB

-7.5dB

-6dB

-52.5dB

-51dB

-4.5dB

-3dB

-49.5dB

-48dB

-1.5dB

0dB

-46.5dB

-45dB

1.5dB

3dB

-43.5dB

-42dB

4.5dB

6dB

-40.5dB

-39dB

7.5dB

9dB

-37.5dB

-36dB

10.5dB

12dB

-34.5dB

-33dB

13.5dB

15dB

-31.5dB

-30dB

16.5dB

18dB

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116

TABLE 93. EQ_BAND_1 (0xABh)

Field

Bits

Description

1:0

FREQ

This sets the Sub-bass shelving filter's cut-off frequency.

FREQ

00

Frequency (Hz)

60

80

01

10

100

120

11

6:2

LEVEL

This sets the gain at f_C.

LEVEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Effect

Off (0dB)

-15dB

-14dB

-13dB

-12dB

-11dB

-10dB

-9dB

-8dB

-7dB

-6dB

-5dB

-4dB

-3dB

-2dB

-1dB

0dB

1dB

2dB

3dB

4dB

5dB

6dB

7dB

8dB

9dB

10dB

11dB

12dB

13dB

14dB

15dB

117

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TABLE 94. EQ_BAND_2 (0xACh)

Field

Bits

Description

1:0

FREQ

This sets the Bass peak filter's center frequency.

FREQ

Frequency (Hz)

00

150

200

250

300

01

10

11

6:2

LEVEL

This sets the gain at f_C.

LEVEL

Effect

Off (0dB)

-15dB

-14dB

-13dB

-12dB

-11dB

-10dB

-9dB

-8dB

-7dB

-6dB

-5dB

-4dB

-3dB

-2dB

-1dB

0dB

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

1dB

10010

2dB

10011

3dB

10100

4dB

10101

5dB

10110

6dB

10111

7dB

11000

8dB

11001

9dB

11010

10dB

11dB

12dB

13dB

14dB

15dB

11011

11100

11101

11110

11111

7

Q

This programs the width of the peak filter.

Q

0

Bandwidth

2/3 Octave

4/3 Octave

1

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118

TABLE 95. EQ_BAND_3 (0xADh)

Field

Bits

Description

1:0

FREQ

This sets the Mid peak filter's center frequency.

FREQ

Frequency (Hz)

00

600

800

1k

01

10

11

1.2k

6:2

LEVEL

This sets the gain at f_C.

LEVEL

Effect

Off (0dB)

-15dB

-14dB

-13dB

-12dB

-11dB

-10dB

-9dB

-8dB

-7dB

-6dB

-5dB

-4dB

-3dB

-2dB

-1dB

0dB

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

1dB

10010

2dB

10011

3dB

10100

4dB

10101

5dB

10110

6dB

10111

7dB

11000

8dB

11001

9dB

11010

10dB

11dB

12dB

13dB

14dB

15dB

11011

11100

11101

11110

11111

7

Q

This programs the width of the peak filter.

Q

0

Bandwidth

2/3 Octave

4/3 Octave

1

119

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TABLE 96. EQ_BAND_4 (0xAEh)

Field

Bits

Description

1:0

FREQ

This sets the Treble peak filter's center frequency.

FREQ

Frequency (Hz)

00

2k

01

2.7k

3.4k

4.1k

10

11

6:2

LEVEL

This sets the gain at f_C.

LEVEL

Effect

Off (0dB)

-15dB

-14dB

-13dB

-12dB

-11dB

-10dB

-9dB

-8dB

-7dB

-6dB

-5dB

-4dB

-3dB

-2dB

-1dB

0dB

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

1dB

10010

2dB

10011

3dB

10100

4dB

10101

5dB

10110

6dB

10111

7dB

11000

8dB

11001

9dB

11010

10dB

11dB

12dB

13dB

14dB

15dB

11011

11100

11101

11110

11111

7

Q

This programs the width of the peak filter.

Q

0

Bandwidth

2/3 Octave

4/3 Octave

1

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120

TABLE 97. EQ_BAND_5 (0xAFh)

Field

Bits

Description

1:0

FREQ

This sets the presence shelving filter's cut-off frequency.

FREQ

00

Frequency (Hz)

7k

9k

01

10

11k

20k

11

6:2

LEVEL

This sets the gain at f_C.

LEVEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Effect

Off (0dB)

-15dB

-14dB

-13dB

-12dB

-11dB

-10dB

-9dB

-8dB

-7dB

-6dB

-5dB

-4dB

-3dB

-2dB

-1dB

0dB

1dB

2dB

3dB

4dB

5dB

6dB

7dB

8dB

9dB

10dB

11dB

12dB

13dB

14dB

15dB

121

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TABLE 98. SOFTCLIP1 (0xB0h)

Field

TRESHOLD

Bits

Description

3:0

This sets the threshold level of the audio compressor. Audio signals

above the threshold will be compressed.

THRESHOLD

0000

Threshold Level (dB)

-36dB

0001

-30dB

0010

-24dB

0011

-20dB

0100

-18dB

0101

-17dB

0110

-16dB

0111

-15dB

1000

-14dB

1001

-12dB

1010

-10dB

1011

-8dB

1100

-6dB

1101

-4dB

1110

-2.5dB

-1dB

1111

4

SOFT_KNEE

If set, the audio compressor will automatically apply higher

compression ratios to audio signals higher than the threshold level.

As the audio signal approaches levels higher than the threshold,

SOFT_KNEE will increase the compression RATIO. The highest

compression that the SOFT_KNEE algorithm will apply is the

compression that is set by RATIO.

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122

TABLE 99. SOFTCLIP2 (0xB1h)

Field

RATIO

Bits

Description

4:0

This sets the ratio at which the audio is compressed to when it

passes beyond the threshold. In soft clip mode, this is the final level

of compression.

RATIO

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Ratio

1:1 (Bypass)

1:1.2

1:1.4

1:1.7

1:2.0

1:2.4

1:2.8

1:3.4

1:4.0

1:4.7

1:5.7

1:6.7

1:8.0

1:9.5

1:11.3

1:13.5

1:16.0

1:19.0

1:22.8

1:27.0

1:32.0

1:37.9

1:45.5

1:53.9

1:64

1:75.9

1:91.0

1:108

1:128

1:152

1:182

1:215

123

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TABLE 100. SOFTCLIP3 (0xB2h)

Field

LEVEL

Bits

Description

4:0

This sets the post compressor gain level.

LEVEL

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Level (dB)

-22.5dB

-21dB

-19.5dB

-18dB

-16.5dB

-15dB

-13.5dB

-12dB

-10.5dB

-9dB

-7.5dB

-6dB

-4.5dB

-3dB

-1.5dB

0dB

1.5dB

3dB

4.5dB

6dB

7.5dB

9dB

10.5dB

12dB

13.5dB

15dB

16.5dB

18dB

19.5dB

21dB

22.5dB

24dB

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124

39.0 GPIO Registers

TABLE 101. GPIO1 (0xE0h)

Bits

Field

Description

5:0

GPIO_MODE

This sets the mode of the GPIO pin.

GPIO_MODE

GPIO STATUS

If GPIO Mode is disabled, PORT2_SDO is controlled by

the Port2 serial interface configuration. In all the other

modes, PORT2_SDO is configured as the GPIO pin.

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

GPIO_RX (in)

CHIP ENABLE (in)

ADC MUTE (in)

HP SENSE (in)

SPARE (in)

GPIO TX (out)

CHIP ACTIVE (out)

HP ENABLE (out)

LS ENABLE (out)

EP ENABLE (out)

ADC CLIPPED (out)

DAC CLIPPED (out)

SOMETHING CLIPPED (out)

ADC NG ACTIVE (out)

DAC NG ACTIVE (out)

THERMAL (out)

LS SHORT CCT (out)

ANALOG ERROR

Thermal or LS CCT condition (out)

100001

100010

ANALOG ERROR (out)

ERROR (out)

Thermal or LS CCT

or Clipping

100011

100100

ERROR (out)

RESERVED

100101 – 111111

6

7

Whenever GPIO_MODE is set to '001010', the GPIO pin will output a logic level based on

this bit setting. Setting this bit high will result in a logic high GPIO output.

GPIO_TX

GPIO_RX

This bit reports the logic level is present on the GPIO pin.

125

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TABLE 102. GPIO2 (0xE1h)

Bits

Field

Description

0

SHORT

This bit will go high whenever a short circuit condition occurs on the Class

D loudspeaker amplifier outputs. Once triggered by a short circuit event,

an I²C write of 1 to this bit clear this bit.

1

TEMP

This bit will go high whenever the temperature of the LM49360 reaches

a critical temperature. Once triggered by a thermal event, an I²C write of

1 to this bit clear this bit.

TABLE 103. RESET (0xF0h)

Bits

4:0

5

Field

RSVD

Description

Reserved.

SOFT_RESET

Setting this bit resets the digital core of LM49360. SOFT_RESET does

not affect the current I²C register settings.

TABLE 104. Spread Spectrum (0xF1h)

Bits

1:0

2

Field

RSVD

Description

Reserved

SS_DISABLE

If this bit is set, Spread Spectrum mode will be disabled from the Class

D amplifier.

TABLE 105. FORCE (0xFE)

Bits

0

Field

RSVD

Description

Reserved

1

DACREF

This bit determines whether the DAC reference voltage is internally

generated or externally driven.

DACREF

STATUS

DACREF uses an internal bandgap

reference.

0

DACREF is driven by an external

voltage reference.

1

2

CP_FORCE

If set, a -LS_VDD rail will be generated on HP_VSS, even if the

headphone output stage is not required.

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126

40.0 Schematic Diagram

127

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128

41.0 Demonstration Board Layout

30128243

FIGURE 38. Top Silkscreen

30128244

FIGURE 39. Top Layer

129

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30128238

FIGURE 40. Inner Layer 2

30128239

FIGURE 41. Inner Layer 3

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130

30128240

FIGURE 42. Inner Layer 4

30128241

FIGURE 43. Inner Layer 5

131

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30128231

FIGURE 44. Bottom Layer

30128242

FIGURE 45. Bottom Silkscreen

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132

42.0 Revision History

Rev

1.0

Date

Description

11/14/11

12/01/11

Initial WEB released.

1.01

Changed the Vdo Max limit in the “EC LDOs 1 to 6” table from (200 to 250).

133

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43.0 Physical Dimensions inches (millimeters) unless otherwise noted

micro SMD–64 Package

Order Number LM49360RL

NS Package Number RLA64JBA

X₁= 4.169±.03mm, X₂= 3.99±.03mm, X₃= 0.65±.075mm

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134

Notes

135

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型号：	LM49360RLX
厂家：	TEXAS INSTRUMENTS
描述：	Mono Class D Audio Codec PMU with Ground Referenced Headphone Amplifiers, Earpiece Driver, Audio DSP, 2 Step-Down DC-DC Converters, and 7 LDO Regulators 单声道D类音频编解码器PMU与接地参考耳机放大器，耳机驱动器，音频DSP ， 2降压型DC - DC转换器，以及7 LDO稳压器解码器驱动器转换器稳压器编解码器放大器
文件：	总137页 (文件大小：2402K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM49360RLX [TI]

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