LM5000-3MTCX [TI]

High Voltage Switch Mode Regulator;
LM5000-3MTCX
型号: LM5000-3MTCX
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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High Voltage Switch Mode Regulator

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LM5000  
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SNVS176D MAY 2004REVISED MARCH 2007  
LM5000 High Voltage Switch Mode Regulator  
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1
FEATURES  
DESCRIPTION  
The LM5000 is  
a monolithic integrated circuit  
2
80V Internal Switch  
specifically designed and optimized for flyback, boost  
or forward power converter applications. The internal  
power switch is rated for a maximum of 80V, with a  
current limit set to 2A. Protecting the power switch  
are current limit and thermal shutdown circuits. The  
current mode control scheme provides excellent  
rejection of line transients and cycle-by-cycle current  
limiting. An external compensation pin and the built-in  
slope compensation allow the user to optimize the  
frequency compensation. Other distinctive features  
include softstart to reduce stresses during start-up  
and an external shutdown pin for remote ON/OFF  
control. There are two operating frequency ranges  
available. The LM5000-3 is pin selectable for either  
300kHz (FS Grounded) or 700kHz (FS Open). The  
LM5000-6 is pin selectable for either 600kHz (FS  
Grounded) or 1.3MHz (FS Open). The device is  
available in a low profile 16-lead TSSOP package or  
a thermally enhanced 16-lead WSON package.  
Operating Input Voltage Range of 3.1V to 40V  
Pin Selectable Operating Frequency  
300kHz/700kHz (-3)  
600kHz/1.3MHz (-6)  
Adjustable Output Voltage  
External Compensation  
Input Undervoltage Lockout  
Softstart  
Current Limit  
Over Temperature Protection  
External Shutdown  
Small 16-Lead TSSOP or 16-Lead WSON  
Package  
APPLICATIONS  
Flyback Regulator  
Forward Regulator  
Boost Regulator  
DSL Modems  
Distributed Power Converters  
Typical Application Circuit  
Figure 1. LM5000 Flyback Converter  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2007, Texas Instruments Incorporated  
LM5000  
SNVS176D MAY 2004REVISED MARCH 2007  
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Connection Diagram  
Figure 2. Top View  
PIN DESCRIPTIONS  
Pin  
Name  
Function  
1
COMP  
Compensation network connection. Connected to the output of the voltage error amplifier. The RC  
compenstion network should be connected from this pin to AGND. An additional 100pF high frequency  
capacitor to AGND is recommended.  
2
3
FB  
Output voltage feedback input.  
SHDN  
AGND  
PGND  
PGND  
PGND  
PGND  
SW  
Shutdown control input, Open = enable, Ground = disable.  
Analog ground, connect directly to PGND.  
Power ground.  
4
5
6
Power ground.  
7
Power ground.  
8
Power ground.  
9
Power switch input. Switch connected between SW pins and PGND pins  
Power switch input. Switch connected between SW pins and PGND pins  
Power switch input. Switch connected between SW pins and PGND pins  
Bypass-Decouple Capacitor Connection, 0.1µF ceramic capacitor recommended.  
10  
11  
12  
13  
SW  
SW  
BYP  
VIN  
Analog power input. A small RC filter is recommended, to suppress line glitches. Typical values of 10  
and 0.1µF are recommended.  
14  
15  
16  
-
SS  
FS  
Softstart Input. External capacitor and internal current source sets the softstart time.  
Switching frequency select input. Open = Fhigh. Ground = Flow  
Factory test pin, connect to ground.  
TEST  
Exposed Pad  
underside of WSON  
package  
Connect to system ground plane for reduced thermal resistance.  
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Absolute Maximum Ratings(1)(2)  
VIN  
-0.3V to 40V  
-0.3V to 80V  
-0.3V to 5V  
-0.3V to 3V  
-0.3V to 7V  
150°C  
SW Voltage  
FB Voltage  
COMP Voltage  
All Other Pins  
Maximum Junction Temperature  
Power Dissipation(3)  
Lead Temperature  
Infrared (15 sec.)  
ESD Susceptibility(4)  
Internally Limited  
216°C  
235°C  
Human Body Model  
Machine Model  
2kV  
200V  
Storage Temperature  
65°C to +150°C  
(1) Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the  
device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test  
conditions, see the Electrical Characteristics.  
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and  
specifications.  
(3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal  
resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance of various layouts.  
The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) TA)/θJA. Exceeding  
the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.  
(4) The human body model is a 100 pF capacitor discharged through a 1.5kresistor into each pin. The machine model is a 200pF  
capacitor discharged directly into each pin.  
Operating Conditions  
Operating Junction Temperature Range(1)  
Supply Voltage(1)  
40°C to +125°C  
3.1V to 40V  
(1) Supply voltage, bias current product will result in aditional device power dissipation. This power may be significant. The thermal  
dissipation design should take this into account.  
Electrical Characteristics  
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating  
Temperature Range (TJ = 40°C to +125°C) Unless otherwise specified. VIN = 12V and IL = 0A, unless otherwise specified.  
Symbol  
Parameter  
Quiescent Current  
Conditions  
Min(1)  
Typ(2)  
Max(1)  
Units  
IQ  
FB = 2V (Not Switching)  
FS = 0V  
2.0  
2.5  
mA  
FB = 2V (Not Switching)  
FS = Open  
2.1  
2.5  
mA  
VSHDN = 0V  
18  
30  
1.2840  
2.7  
µA  
V
VFB  
Feedback Voltage  
1.2330  
1.35  
1.259  
2.0  
ICL  
Switch Current Limit  
A
%VFB/ΔVIN  
Feedback Voltage Line  
Regulation  
3.1V VIN 40V  
0.001  
0.04  
%/V  
IB  
FB Pin Bias Current(3)  
55  
200  
nA  
(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are  
100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)  
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).  
(2) Typical numbers are at 25°C and represent the most likely norm.  
(3) Bias current flows into FB pin.  
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Electrical Characteristics (continued)  
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating  
Temperature Range (TJ = 40°C to +125°C) Unless otherwise specified. VIN = 12V and IL = 0A, unless otherwise specified.  
Symbol  
BV  
Parameter  
Conditions  
Min(1)  
Typ(2)  
Max(1)  
Units  
Output Switch Breakdown  
Voltage  
TJ = 25°C, ISW = 0.1µA  
80  
V
TJ = -40°C to + 125°C, ISW  
0.5µA  
=
76  
VIN  
gm  
Input Voltage Range  
3.1  
40  
V
µmho  
V/V  
%
Error Amp Transconductance  
Error Amp Voltage Gain  
ΔI = 5µA  
150  
410  
280  
90  
750  
AV  
DMAX  
Maximum Duty Cycle  
LM5000-3  
FS = 0V  
FS = 0V  
85  
85  
Maximum Duty Cycle  
LM5000-6  
90  
%
TMIN  
fS  
Minimum On Time  
165  
300  
700  
600  
1.3  
ns  
Switching Frequency LM5000- FS = 0V  
3
240  
550  
360  
840  
715  
1.545  
-2  
FS = Open  
kHz  
Switching Frequency LM5000- FS = 0V  
6
485  
FS = Open  
1.055  
MHz  
µA  
µA  
mΩ  
V
ISHDN  
IL  
Shutdown Pin Current  
Switch Leakage Current  
Switch RDSON  
VSHDN = 0V  
VSW = 80V  
ISW = 1A  
1  
0.008  
160  
0.6  
5
RDSON  
ThSHDN  
445  
SHDN Threshold  
Output High  
Output Low  
0.9  
0.6  
0.3  
V
UVLO  
On Threshold  
Off Threshold  
VCOMP Trip  
2.74  
2.60  
2.92  
2. 77  
0.67  
11  
3.10  
2.96  
V
V
OVP  
ISS  
V
Softstart Current  
Thermal Resistance  
8
14  
µA  
°C/W  
θJA  
TSSOP, Package only  
WSON, Package only  
150  
45  
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Typical Performance Characteristics  
Iq (non-switching) vs VIN @ fSW = 300kHz  
3.000  
Iq (non-switching) vs VIN @ fSW = 700kHz  
3.000  
2.800  
2.600  
2.400  
2.200  
2.000  
1.800  
1.600  
1.400  
2.800  
2.600  
2.400  
2.200  
2.000  
1.800  
1.600  
1.400  
-40oC  
-40oC  
25oC  
25oC  
125oC  
125oC  
1.200  
1.000  
1.200  
1.000  
10 15  
0
5
20 25  
VIN (V)  
35 40  
30  
10 15  
0
5
20 25  
VIN (V)  
35 40  
30  
Figure 3.  
Figure 4.  
Iq (switching) vs VIN @ fSW = 300kHz  
Iq (switching) vs VIN @ fSW = 700kHz  
10  
9
10  
9
-40oC  
8
8
25oC  
125oC  
7
7
6
6
-40oC  
5
5
4
4
125oC  
25oC  
3
3
2
2
0
5
10 15 20 25 30 35 40  
0
5
10 15 20 25 30 35 40  
VIN (V)  
VIN (V)  
Figure 5.  
Figure 6.  
Vfb vs Temperature  
RDS(ON) vs VIN @ ISW =1A  
1.2800  
1.2700  
1.2600  
1.2500  
1.2400  
1.2300  
400  
350  
300  
250  
200  
150  
100  
50  
125oC  
25oC  
-40oC  
0
-40 -20  
0
20 40 60 80 100 120  
0
5
10 15 20 25 30 35 40  
TEMPERATURE (oC)  
VIN (V)  
Figure 7.  
Figure 8.  
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Typical Performance Characteristics (continued)  
Current Limit vs Temperature  
Current Limit vs VIN  
2
1.95  
1.9  
2
1.95  
1.9  
1.85  
1.8  
1.85  
1.8  
1.75  
1.7  
1.75  
1.7  
1.65  
1.6  
1.65  
1.6  
1.55  
1.5  
1.55  
1.5  
120  
100  
40 60  
-40  
0
20  
80  
-20  
10 15  
0
5
20 25  
VIN (V)  
35 40  
30  
TEMPERATURE (oC)  
Figure 9.  
Figure 10.  
fSW vs. VIN @ FS = Low (-3)  
fSW vs. VIN @ FS = OPEN (-3)  
770  
750  
730  
710  
690  
670  
650  
630  
315  
310  
305  
300  
295  
290  
285  
10 15  
10 15  
0
5
20 25  
VIN (V)  
35 40  
0
5
20 25  
VIN (V)  
35 40  
30  
30  
Figure 11.  
Figure 12.  
fSW vs. Temperature @ FS = Low (-3)  
fSW vs. Temperature @ FS = OPEN (-3)  
770  
330  
320  
310  
300  
290  
280  
270  
750  
730  
710  
690  
670  
650  
630  
-40 -20  
0
20 40  
80  
60  
100  
120  
-40 -20  
0
20 40 60 80 100 120  
TEMPERATURE (oC)  
TEMPERATURE (oC)  
Figure 13.  
Figure 14.  
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Typical Performance Characteristics (continued)  
fSW vs. Temperature @ FS = Low (-6)  
fSW vs. Temperature @ FS = OPEN (-6)  
1.38  
640  
620  
600  
580  
560  
540  
520  
1.34  
1.30  
1.26  
1.22  
1.18  
1.14  
-40 -20  
0
20 40 60 80 100 120  
-40 -20  
0
20 40 60 80 100 120  
TEMPERATURE (oC)  
TEMPERATURE (oC)  
Figure 15.  
Figure 16.  
Error Amp. Transconductance vs Temp.  
600  
BYP Pin Voltage vs VIN  
8
7
6
5
4
3
2
1
0
125oC  
550  
500  
450  
400  
350  
300  
250  
-40oC  
25oC  
-40 -20  
0
20 40  
80  
60  
100  
120  
10 15  
0
5
20 25  
VIN (V)  
35 40  
30  
TEMPERATURE (oC)  
Figure 17.  
Figure 18.  
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Typical Application Diagrams  
Figure 19. 300 kHz operation, 48V output  
Figure 20. 700 kHz operation, 48V output  
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Block Diagram  
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BOOST REGULATOR OPERATION  
The LM5000 utilizes a PWM control scheme to regulate the output voltage over all load conditions. The operation  
can best be understood referring to the block diagram and Figure 21. At the start of each cycle, the oscillator  
sets the driver logic and turns on the NMOS power device conducting current through the inductor, cycle 1 of  
Figure 21 (a). During this cycle, the voltage at the COMP pin controls the peak inductor current. The COMP  
voltage will increase with larger loads and decrease with smaller. This voltage is compared with the summation  
of the SW volatge and the ramp compensation.The ramp compensation is used in PWM architectures to  
eliminate the sub-harmonic oscillations that occur during duty cycles greater than 50%. Once the summation of  
the ramp compensation and switch voltage equals the COMP voltage, the PWM comparator resets the driver  
logic turning off the NMOS power device. The inductor current then flows through the output diode to the load  
and output capacitor, cycle 2 of Figure 21 (b). The NMOS power device is then set by the oscillator at the end of  
the period and current flows through the inductor once again.  
The LM5000 has dedicated protection circuitry running during the normal operation to protect the IC. The  
Thermal Shutdown circuitry turns off the NMOS power device when the die temperature reaches excessive  
levels. The UVP comparator protects the NMOS power device during supply power startup and shutdown to  
prevent operation at voltages less than the minimum input voltage. The OVP comparator is used to prevent the  
output voltage from rising at no loads allowing full PWM operation over all load conditions. The LM5000 also  
features a shutdown mode. An external capacitor sets the softstart time by limiting the error amp output range,  
as the capacitor charges up via an internal 10µA current source.  
The LM5000 is available in two operating frequency ranges. The LM5000-3 is pin selectable for either 300kHz  
(FS Grounded) or 700kHz (FS Open). The LM5000-6 is pin selectable for either 600kHz (FS Grounded) or  
1.3MHz (FS Open)  
Operation  
Figure 21. Simplified Boost Converter Diagram  
(a) First Cycle of Operation (b) Second Cycle Of Operation  
CONTINUOUS CONDUCTION MODE  
The LM5000 is a current-mode, PWM regulator. When used as a boost regulator the input voltage is stepped up  
to a higher output voltage. In continuous conduction mode (when the inductor current never reaches zero at  
steady state), the boost regulator operates in two cycles.  
In the first cycle of operation, shown in Figure 21 (a), the transistor is closed and the diode is reverse biased.  
Energy is collected in the inductor and the load current is supplied by COUT  
.
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The second cycle is shown in Figure 21 (b). During this cycle, the transistor is open and the diode is forward  
biased. The energy stored in the inductor is transferred to the load and output capacitor.  
The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as:  
VIN  
VIN  
VOUT  
=
, D' = (1-D) =  
VOUT  
1-D  
where  
D is the duty cycle of the switch  
D and Dwill be required for design calculations  
(1)  
SETTING THE OUTPUT VOLTAGE  
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in  
Figure 19. The feedback pin is always at 1.259V, so the ratio of the feedback resistors sets the output voltage.  
VOUT - 1.259  
W
RFB1 = RFB2  
x
1.259  
(2)  
INTRODUCTION TO COMPENSATION  
Figure 22. (a) Inductor current. (b) Diode current.  
The LM5000 is a current mode PWM regulator. The signal flow of this control scheme has two feedback loops,  
one that senses switch current and one that senses output voltage.  
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To keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet  
certain criteria. The inductor, along with input and output voltage, will determine the slope of the current through  
the inductor (see Figure 22 (a)). If the slope of the inductor current is too great, the circuit will be unstable above  
duty cycles of 50%.  
The LM5000 provides a compensation pin (COMP) to customize the voltage loop feedback. It is recommended  
that a series combination of RC and CC be used for the compensation network, as shown in Figure 19. The  
series combination of RC and CC introduces pole-zero pair according to the following equations:  
1
fZC  
=
Hz  
2pRCCC  
(3)  
1
fPC  
=
Hz  
2p(RC + RO)CC  
where  
RO is the output impedance of the error amplifier, 850kΩ  
(4)  
For most applications, performance can be optimized by choosing values within the range 5kΩ ≤ RC 20kand  
680pF CC 4.7nF.  
COMPENSATION  
This section will present a general design procedure to help insure a stable and operational circuit. The designs  
in this datasheet are optimized for particular requirements. If different conversions are required, some of the  
components may need to be changed to ensure stability. Below is a set of general guidelines in designing a  
stable circuit for continuous conduction operation (loads greater than 100mA), in most all cases this will provide  
for stability during discontinuous operation as well. The power components and their effects will be determined  
first, then the compensation components will be chosen to produce stability.  
INDUCTOR SELECTION  
To ensure stability at duty cycles above 50%, the inductor must have some minimum value determined by the  
minimum input voltage and the maximum output voltage. This equation is:  
2
D
-1  
( D')  
VINRDSON  
(in H)  
L >  
D
0.144 fs  
+1  
( D')  
where  
fs is the switching frequency  
D is the duty cycle  
RDSON is the ON resistance of the internal switch  
(5)  
(6)  
This equation is only good for duty cycles greater than 50% (D>0.5).  
VIND  
(in Amps)  
DiL =  
2Lfs  
The inductor ripple current is important for a few reasons. One reason is because the peak switch current will be  
the average inductor current (input current) plus ΔiL. Care must be taken to make sure that the switch will not  
reach its current limit during normal operation. The inductor must also be sized accordingly. It should have a  
saturation current rating higher than the peak inductor current expected. The output voltage ripple is also affected  
by the total ripple current.  
DC GAIN AND OPEN-LOOP GAIN  
Since the control stage of the converter forms a complete feedback loop with the power components, it forms a  
closed-loop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC  
gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover  
frequency and the phase margin. A high phase margin (greater than 45°) is desired for the best stability and  
transient response. For the purpose of stabilizing the LM5000, choosing a crossover point well below where the  
right half plane zero is located will ensure sufficient phase margin. A discussion of the right half plane zero and  
checking the crossover using the DC gain will follow.  
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OUTPUT CAPACITOR SELECTION  
The choice of output capacitors is somewhat more arbitrary. It is recommended that low ESR (Equivalent Series  
Resistance, denoted RESR) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum.  
Higher ESR capacitors may be used but will require more compensation which will be explained later on in the  
section. The ESR is also important because it determines the output voltage ripple according to the approximate  
equation:  
ΔVOUT 2ΔiLRESR (in Volts)  
(7)  
After choosing the output capacitor you can determine a pole-zero pair introduced into the control loop by the  
following equations:  
1
(in Hz)  
fP1  
=
2p(RESR + RL)COUT  
(8)  
1
(in Hz)  
fZ1  
=
2pRESRCOUT  
where  
RL is the minimum load resistance corresponding to the maximum load current  
(9)  
The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low  
ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the HIGH OUTPUT  
CAPACITOR ESR COMPENSATION section.  
RIGHT HALF PLANE ZERO  
A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect  
of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the  
phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is  
influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be  
designed to have a bandwidth of ½ the frequency of the RHP zero or less. This zero occurs at a frequency of:  
VOUT(D')2  
(in Hz)  
RHPzero =  
2pILOADL  
where  
ILOAD is the maximum load current  
(10)  
SELECTING THE COMPENSATION COMPONENTS  
The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in  
the control loop. Simply choose values for RC and CC within the ranges given in the INTRODUCTION TO  
COMPENSATION section to set this pole in the area of 10Hz to 100Hz. The frequency of the pole created is  
determined by the equation:  
1
(in Hz)  
fPC  
=
2p(RC + RO)CC  
where  
RO is the output impedance of the error amplifier, 850kΩ  
(11)  
Since RC is generally much less than RO, it does not have much effect on the above equation and can be  
neglected until a value is chosen to set the zero fZC. fZC is created to cancel out the pole created by the output  
capacitor, fP1. The output capacitor pole will shift with different load currents as shown by the equation, so setting  
the zero is not exact. Determine the range of fP1 over the expected loads and then set the zero fZC to a point  
approximately in the middle. The frequency of this zero is determined by:  
1
(in Hz)  
fZC  
=
2pCCRC  
(12)  
Copyright © 2004–2007, Texas Instruments Incorporated  
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SNVS176D MAY 2004REVISED MARCH 2007  
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Now RC can be chosen with the selected value for CC. Check to make sure that the pole fPC is still in the 10Hz to  
100Hz range, change each value slightly if needed to ensure both component values are in the recommended  
range. After checking the design at the end of this section, these values can be changed a little more to optimize  
performance if desired. This is best done in the lab on a bench, checking the load step response with different  
values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should  
produce a stable, high performance circuit. For improved transient response, higher values of RC (within the  
range of values) should be chosen. This will improve the overall bandwidth which makes the regulator respond  
more quickly to transients. If more detail is required, or the most optimal performance is desired, refer to a more  
in depth discussion of compensating current mode DC/DC switching regulators.  
HIGH OUTPUT CAPACITOR ESR COMPENSATION  
When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control  
loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding  
another capacitor, CC2, directly from the compensation pin VC to ground, in parallel with the series combination of  
RC and CC. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole  
follows:  
1
(in Hz)  
fPC2  
=
2pCC2(RC //RO)  
(13)  
To ensure this equation is valid, and that CC2 can be used without negatively impacting the effects of RC and CC,  
fPC2 must be greater than 10fPC  
.
CHECKING THE DESIGN  
The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP  
zero. This is done by calculating the open-loop DC gain, ADC. After this value is known, you can calculate the  
crossover visually by placing a 20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The  
point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is  
at less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also  
be improved some by adding CC2 as discussed earlier in the section. The equation for ADC is given below with  
additional equations required for the calculation:  
RFB2  
gmROD'  
{[(wcLeff)// RL]//RL} (in dB)  
ADC(DB) = 20log10  
(
)
RDSON  
RFB1 + RFB2  
(14)  
(15)  
2fs  
(in rad/s)  
@
wc  
nD'  
L
Leff =  
(D')2  
(16)  
2mc  
m1  
(no unit)  
n = 1+  
(17)  
(18)  
mc 0.072fs (in A/s)  
VINRDSON  
(in V/s)  
@
m1  
L
where  
RL is the minimum load resistance  
VIN is the maximum input voltage  
RDSON is the value chosen from the graph "RDSON vs. VIN " in the Typical Performance Characteristics  
section  
(19)  
SWITCH VOLTAGE LIMITS  
In a flyback regulator, the maximum steady-state voltage appearing at the switch, when it is off, is set by the  
transformer turns ratio, N, the output voltage, VOUT, and the maximum input voltage, VIN (Max):  
VSW(OFF) = VIN (Max) + (VOUT +VF)/N  
where  
VF is the forward biased voltage of the output diode, and is typically 0.5V for Schottky diodes and 0.8V for  
ultra-fast recovery diodes  
(20)  
14  
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Copyright © 2004–2007, Texas Instruments Incorporated  
Product Folder Links: LM5000  
LM5000  
www.ti.com  
SNVS176D MAY 2004REVISED MARCH 2007  
In certain circuits, there exists a voltage spike, VLL, superimposed on top of the steady-state voltage . Usually,  
this voltage spike is caused by the transformer leakage inductance and/or the output rectifier recovery time. To  
“clamp” the voltage at the switch from exceeding its maximum value, a transient suppressor in series with a  
diode is inserted across the transformer primary.  
If poor circuit layout techniques are used, negative voltage transients may appear on the Switch pin. Applying a  
negative voltage (with respect to the IC's ground) to any monolithic IC pin causes erratic and unpredictable  
operation of that IC. This holds true for the LM5000 IC as well. When used in a flyback regulator, the voltage at  
the Switch pin can go negative when the switch turns on. The “ringing” voltage at the switch pin is caused by the  
output diode capacitance and the transformer leakage inductance forming a resonant circuit at the  
secondary(ies). The resonant circuit generates the “ringing” voltage, which gets reflected back through the  
transformer to the switch pin. There are two common methods to avoid this problem. One is to add an RC  
snubber around the output rectifier(s). The values of the resistor and the capacitor must be chosen so that the  
voltage at the Switch pin does not drop below 0.4V. The resistor may range in value between 10and 1 k,  
and the capacitor will vary from 0.001 μF to 0.1 μF. Adding a snubber will (slightly) reduce the efficiency of the  
overall circuit.  
The other method to reduce or eliminate the “ringing” is to insert a Schottky diode clamp between the SW pin  
and the PGND pin. The reverse voltage rating of the diode must be greater than the switch off voltage.  
OUTPUT VOLTAGE LIMITATIONS  
The maximum output voltage of a boost regulator is the maximum switch voltage minus a diode drop. In a  
flyback regulator, the maximum output voltage is determined by the turns ratio, N, and the duty cycle, D, by the  
equation:  
VOUT N × VIN × D/(1 D)  
(21)  
The duty cycle of a flyback regulator is determined by the following equation:  
(22)  
Theoretically, the maximum output voltage can be as large as desired—just keep increasing the turns ratio of the  
transformer. However, there exists some physical limitations that prevent the turns ratio, and thus the output  
voltage, from increasing to infinity. The physical limitations are capacitances and inductances in the LM5000  
switch, the output diode(s), and the transformer—such as reverse recovery time of the output diode (mentioned  
above).  
INPUT LINE CONDITIONING  
A small, low-pass RC filter should be used at the input pin of the LM5000 if the input voltage has an unusually  
large amount of transient noise. Additionally, the RC filter can reduce the dissipation within the device when the  
input voltage is high.  
Flyback Regulator Operation  
The LM5000 is ideally suited for use in the flyback regulator topology. The flyback regulator can produce a single  
output voltage, or multiple output voltages.  
The operation of a flyback regulator is as follows: When the switch is on, current flows through the primary  
winding of the transformer, T1, storing energy in the magnetic field of the transformer. Note that the primary and  
secondary windings are out of phase, so no current flows through the secondary when current flows through the  
primary. When the switch turns off, the magnetic field collapses, reversing the voltage polarity of the primary and  
secondary windings. Now rectifier D5 is forward biased and current flows through it, releasing the energy stored  
in the transformer. This produces voltage at the output.  
The output voltage is controlled by modulating the peak switch current. This is done by feeding back a portion of  
the output voltage to the error amp, which amplifies the difference between the feedback voltage and a 1.259V  
reference. The error amp output voltage is compared to a ramp voltage proportional to the switch current (i.e.,  
inductor current during the switch on time). The comparator terminates the switch on time when the two voltages  
are equal, thereby controlling the peak switch current to maintain a constant output voltage.  
Copyright © 2004–2007, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Links: LM5000  
LM5000  
SNVS176D MAY 2004REVISED MARCH 2007  
www.ti.com  
Figure 23. LM5000 Flyback Converter  
16  
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Copyright © 2004–2007, Texas Instruments Incorporated  
Product Folder Links: LM5000  
LM5000  
www.ti.com  
ITEM  
SNVS176D MAY 2004REVISED MARCH 2007  
PART NUMBER  
C4532X7R2A105MT  
DESCRIPTION  
Capacitor, CER, TDK  
VALUE  
1µ, 100V  
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
T
1
2
3
4
5
6
7
8
9
10  
11  
1
2
3
4
5
1
1
2
3
4
5
6
7
1
1
C4532X7R2A105MT  
C1206C224K5RAC  
C1206C104K5RAC  
C1206C104K5RAC  
C1206C101K1GAC  
C1206C104K5RAC  
C4532X7S0G686M  
C4532X7S0G686M  
C1206C221K1GAC  
C1206C102K5RAC  
BZX84C10-NSA  
CMZ5930B-NSA  
CMPD914-NSA  
Capacitor, CER, TDK  
Capacitor, CER, KEMET  
Capacitor, CER, KEMET  
Capacitor, CER, KEMET  
Capacitor, CER, KEMET  
Capacitor, CER, KEMET  
Capacitor, CER, TDK  
Capacitor, CER, TDK  
Capacitor, CER, KEMET  
Capacitor, CER, KEMET  
Central, 10V Zener, SOT-23  
Central, 16V Zener, SMA  
Central, Switching, SOT-23  
Central, Switching, SOT-23  
Central, Schottky, SMC  
Coilcraft, Transformer  
Resistor  
1µ, 100V  
0.22µ, 50V  
0.1µ, 50V  
0.1µ, 50V  
100p, 100V  
0.1µ, 50V  
68µ, 4V  
68µ, 4V  
220p, 100V  
1000p, 500V  
CMPD914-NSA  
CMSH3-40L-NSA  
A0009-A  
R
R
R
R
R
R
R
Q
U
CRCW12064992F  
CRCW12061001F  
CRCW12061002F  
CRCW12066191F  
CRCW120610R0F  
CRCW12062003F  
CRCW12061002F  
CXT5551-NSA  
49.9K  
1K  
Resistor  
Resistor  
10K  
6.19K  
10  
Resistor  
Resistor  
Resistor  
200K  
10K  
Resistor  
Central, NPN, 180V  
Regulator, TI  
LM5000-3  
Copyright © 2004–2007, Texas Instruments Incorporated  
Submit Documentation Feedback  
17  
Product Folder Links: LM5000  
PACKAGE OPTION ADDENDUM  
www.ti.com  
1-Nov-2013  
PACKAGING INFORMATION  
Orderable Device  
LM5000-3MTC  
Status Package Type Package Pins Package  
Eco Plan  
Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(6)  
(3)  
(4/5)  
NRND  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
WSON  
WSON  
WSON  
WSON  
PW  
16  
16  
16  
16  
16  
16  
16  
16  
92  
TBD  
Call TI  
CU SN  
Call TI  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
Call TI  
LM5000  
3MTC  
LM5000-3MTC/NOPB  
LM5000-3MTCX  
ACTIVE  
NRND  
PW  
PW  
92  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
Call TI  
LM5000  
3MTC  
2500  
2500  
1000  
1000  
4500  
4500  
TBD  
LM5000  
3MTC  
LM5000-3MTCX/NOPB  
LM5000SD-3/NOPB  
LM5000SD-6/NOPB  
LM5000SDX-3/NOPB  
LM5000SDX-6/NOPB  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PW  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
LM5000  
3MTC  
NHQ  
NHQ  
NHQ  
NHQ  
Green (RoHS  
& no Sb/Br)  
5000-3  
5000-6  
5000-3  
5000-6  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
1-Nov-2013  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish  
value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Nov-2015  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LM5000-3MTCX  
TSSOP  
PW  
PW  
16  
16  
16  
16  
16  
16  
2500  
2500  
1000  
1000  
4500  
4500  
330.0  
330.0  
178.0  
178.0  
330.0  
330.0  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
6.95  
6.95  
5.3  
5.6  
5.6  
5.3  
5.3  
5.3  
5.3  
1.6  
1.6  
1.3  
1.3  
1.3  
1.3  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
LM5000-3MTCX/NOPB TSSOP  
LM5000SD-3/NOPB  
LM5000SD-6/NOPB  
LM5000SDX-3/NOPB  
LM5000SDX-6/NOPB  
WSON  
WSON  
WSON  
WSON  
NHQ  
NHQ  
NHQ  
NHQ  
5.3  
5.3  
5.3  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Nov-2015  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LM5000-3MTCX  
LM5000-3MTCX/NOPB  
LM5000SD-3/NOPB  
LM5000SD-6/NOPB  
LM5000SDX-3/NOPB  
LM5000SDX-6/NOPB  
TSSOP  
TSSOP  
WSON  
WSON  
WSON  
WSON  
PW  
PW  
16  
16  
16  
16  
16  
16  
2500  
2500  
1000  
1000  
4500  
4500  
367.0  
367.0  
210.0  
210.0  
367.0  
367.0  
367.0  
367.0  
185.0  
185.0  
367.0  
367.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
NHQ  
NHQ  
NHQ  
NHQ  
Pack Materials-Page 2  
MECHANICAL DATA  
NHQ0016A  
SDA16A (Rev A)  
www.ti.com  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
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performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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