LM5018_13 [TI]

100 V, 300 mA Constant On-Time Synchronous Buck Regulator;
LM5018_13
型号: LM5018_13
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

100 V, 300 mA Constant On-Time Synchronous Buck Regulator

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February 9, 2012  
LM5018  
100V, 300mA Constant On-Time Synchronous Buck  
Regulator  
General Description  
Features  
The LM5018 is a 100V, 300mA synchronous step-down reg-  
ulator with integrated high side and low side MOSFETs. The  
constant-on-time (COT) control scheme employed in the  
LM5018 requires no loop compensation, provides excellent  
transient response, and enables very low step-down ratios.  
The on-time varies inversely with the input voltage resulting  
in nearly constant frequency over the input voltage range. A  
high voltage startup regulator provides bias power for internal  
operation of the IC and for integrated gate drivers.  
Wide 9V to 100V Input Range  
Integrated 100V, High and Low Side Switches  
No Schottky Required  
Constant On-time Control  
No Loop Compensation Required  
Ultra-Fast Transient Response  
Nearly Constant Operating Frequency  
Intelligent Peak Current Limit  
A peak current limit circuit protects against overload condi-  
tions. The undervoltage lockout (UVLO) circuit allows the  
input undervoltage threshold and hysteresis to be indepen-  
dently programmed. Other protection features include ther-  
mal shutdown and bias supply undervoltage lockout.  
Adjustable Output Voltage from 1.225V  
Precision 2% Feedback Reference  
Frequency Adjustable to 1MHz  
Adjustable Undervoltage Lockout  
The LM5018 is available in LLP-8 and PSOP-8 plastic pack-  
ages.  
Remote Shutdown  
Thermal Shutdown  
Packages  
LLP-8  
PSOP-8  
Applications  
Smart Power Meters  
Telecommunication Systems  
Automotive Electronics  
Isolated Bias Supply  
Typical Application  
30181601  
FIGURE 1.  
© 2012 Texas Instruments Incorporated  
301816 SNVS787B  
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Connection Diagram  
30181603  
Top View (Connect Exposed Pad to RTN)  
30181602  
Top View (Connect Exposed Pad to RTN)  
Ordering Information  
Order Number  
Package Type  
PSOP-8  
Package Drawing  
MRA08A  
Supplied As  
LM5018MR  
LM5018SD  
1000 Units on Tape and Reel  
1000 Units on Tape and Reel  
LLP-8  
SDC08B  
Pin Descriptions  
Pin  
1
Name  
RTN  
VIN  
Description  
Application Information  
Ground  
Ground connection of the integrated circuit.  
Operating input range is 9V to 100V.  
2
Input Voltage  
3
UVLO  
Input Pin of Undervoltage Comparator  
Resistor divider from VIN to UVLO to GND programs  
the undervoltage detection threshold. An internal  
current source is enabled when UVLO is above  
1.225V to provide hysteresis. When UVLO pin is  
pulled below 0.66V externally, the parts goes in  
shutdown mode.  
4
RON  
On-Time Control  
Feedback  
A resistor between this pin and VIN sets the switch on-  
time as a function of VIN. Minimum recommended on-  
time is 100ns at max input voltage.  
5
6
FB  
This pin is connected to the inverting input of the  
internal regulation comparator. The regulation level is  
1.225V.  
VCC  
Output From the Internal High Voltage Series Pass The internal VCC regulator provides bias supply for the  
Regulator. Regulated at 7.6V  
gate drivers and other internal circuitry. A 1.0μF  
decoupling capacitor is recommended.  
7
8
BST  
Bootstrap Capacitor  
An external capacitor is required between the BST  
and SW pins (0.01μF ceramic). The BST pin capacitor  
is charged by the VCC regulator through an internal  
diode when the SW pin is low.  
SW  
EP  
Switching Node  
Exposed Pad  
Power switching node. Connect to the output inductor  
and bootstrap capacitor.  
Exposed pad must be connected to RTN pin. Connect  
to system ground plane on application board for  
reduced thermal resistance.  
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2
FB to RTN  
-0.3V to 5V  
Absolute Maximum Ratings (Note 1)  
ESD Rating (Human Body Model(Note 2kV  
5)  
Lead Temperature (Note 2)  
If Military/Aerospace specified devices are required,  
please contact the Texas Instruments Sales Office/  
Distributors for availability and specifications.  
200°C  
-55°C to +150°C  
Storage Temperature Range  
VIN, UVLO to RTN  
SW to RTN  
-0.3V to 100V  
-1.5V to VIN +0.3V  
100V  
Operating Ratings (Note 1)  
VIN Voltage  
BST to VCC  
9V to 100V  
−40°C to +125°C  
BST to SW  
13V  
Operating Junction Temperature  
RON to RTN  
VCC to RTN  
-0.3V to 100V  
-0.3V to 13V  
Electrical Characteristics  
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temper-  
ature range. VIN = 48V, unless otherwise stated. See (Note 3).  
Symbol  
VCC Supply  
VCC Reg  
Parameter  
Conditions  
Min  
Typ  
7.6  
4.5  
Max  
8.55  
4.9  
Units  
VCC Regulator Output  
VCC Current Limit  
VIN = 48V, ICC = 20mA  
6.25  
26  
V
mA  
V
VIN = 48V(Note 4)  
VCC Undervoltage Lockout  
Voltage (VCC Increasing)  
4.15  
VCC Undervoltage Hysteresis  
VCC Drop Out Voltage  
IIN Operating Current  
300  
2.3  
mV  
V
VIN = 9V, ICC = 20mA  
Non-Switching, FB = 3V  
UVLO = 0V  
1.75  
50  
mA  
µA  
IIN Shutdown Current  
225  
1.8  
Switch Characteristics  
Buck Switch RDS(ON)  
ITEST = 200mA, BST-SW =  
0.8  
7V  
Synchronous RDS(ON)  
Gate Drive UVLO  
ITEST = 200mA  
0.45  
3
1
V
VBST − VSW Rising  
2.4  
3.6  
Gate Drive UVLO Hysteresis  
260  
mV  
Current Limit  
Current Limit Threshold  
350  
575  
150  
12  
700  
mA  
ns  
Current Limit Response Time  
Off-Time Generator (Test 1)  
Off-Time Generator (Test 2)  
Time to Switch Off  
FB = 0.1V, VIN = 48V  
FB = 1V, VIN = 48V  
µs  
2.5  
µs  
On-Time Generator  
TON Test 1  
VIN = 32V, RON = 100k  
VIN = 48V, RON = 100k  
VIN = 75V, RON = 250k  
VIN = 10V, RON = 250k  
270  
188  
350  
250  
460  
336  
ns  
ns  
ns  
ns  
TON Test 2  
TON Test 3  
TON Test 4  
250  
370  
500  
1880  
3200  
4425  
3
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Symbol  
Parameter  
Conditions  
FB = 0V  
Min  
1.2  
Typ  
144  
Max  
1.25  
Units  
ns  
Minimum Off-Time  
Minimum Off-Timer  
Regulation and Overvoltage Comparators  
FB Regulation Level  
Internal reference trip point  
for switch ON  
1.225  
V
FB Overvoltage Threshold  
FB Bias Current  
Trip point for switch OFF  
1.62  
60  
V
nA  
Undervoltage Sensing Function  
UV Threshold  
UV Rising  
1.19  
-10  
1.225  
-20  
1.26  
–29  
V
µA  
V
UV Hysteresis Input Current  
Remote Shutdown Threshold  
Remote Shutdown Hysteresis  
Thermal Shutdown  
UV = 2.5V  
Voltage at UVLO Falling  
0.32  
0.66  
110  
mV  
Tsd  
Thermal Shutdown Temp.  
165  
20  
°C  
°C  
Thermal Shutdown Hysteresis  
Thermal Resistance  
Junction to Ambient  
PSOP-8  
LLP-8  
40  
40  
°C/W  
°C/W  
θJA  
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the  
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. The RTN pin is the GND reference  
electrically connected to the substrate.  
Note 2: For detailed information on soldering plastic PSOP package, refer to the Packaging Data Book available from National Semiconductor Corporation. Max  
solder time not to exceed 4 seconds.  
Note 3: All limits are guaranteed by design. All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and  
cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.  
Note 4: VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.  
Note 5: The human body model is a 100pF capacitor discharged through a 1.5kresistor into each pin.  
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4
 
 
 
 
 
Typical Performance Characteristics  
Efficiency at 240kHz, 10V  
VCC vs VIN  
30181604  
30181605  
VCC vs ICC  
ICC vs External VCC  
30181607  
30181606  
TON vs VIN and RON  
TOFF (ILIM) vs VFB and VIN  
30181608  
30181609  
5
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IIN vs VIN (Operating, Non Switching)  
IIN vs VIN (Shutdown)  
30181611  
30181610  
Switching Frequency vs VIN  
30181612  
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Block Diagram  
30181613  
FIGURE 2. Functional Block Diagram  
7
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Functional Description  
The LM5018 step-down switching regulator features all the  
functions needed to implement a low cost, efficient, buck con-  
verter capable of supplying up to 300mA to the load. This high  
voltage regulator contains 100V, N-channel buck and syn-  
chronous switches, is easy to implement, and is provided in  
thermally enhanced PSOP-8 and LLP-8 packages. The reg-  
ulator operation is based on a constant on-time control  
scheme using an on-time inversely proportional to VIN. This  
control scheme does not require loop compensation. The cur-  
rent limit is implemented with a forced off-time inversely pro-  
portional to VOUT. This scheme ensures short circuit protec-  
tion while providing minimum foldback. The simplified block  
diagram of the LM5018 is shown in Figure 2, Functional Block  
Diagram.  
The output voltage (VOUT) is set by two external resistors  
(RFB1, RFB2). The regulated output voltage is calculated as  
follows:  
This regulator regulates the output voltage based on ripple  
voltage at the feedback input, requiring a minimum amount of  
ESR for the output capacitor (COUT). A minimum of 25mV of  
ripple voltage at the feedback pin (FB) is required for the  
LM5018. In cases where the capacitor ESR is too small, ad-  
ditional series resistance may be required (RC in Figure 3 Low  
Ripple Output Configuration).  
The LM5018 can be applied in numerous applications to ef-  
ficiently regulate down higher voltages. This regulator is well  
suited for 48V telecom and 42V automotive power bus  
ranges. Protection features include: thermal shutdown, un-  
dervoltage lockout, minimum forced off-time, and an intelli-  
gent current limit.  
For applications where lower output voltage ripple is required  
the output can be taken directly from a low ESR output ca-  
pacitor, as shown in Figure 3 Low Ripple Output Configura-  
tion. However, RC slightly degrades the load regulation.  
Control Overview  
The LM5018 buck regulator employs a control principle based  
on a comparator and a one-shot on-timer, with the output  
voltage feedback (FB) compared to an internal reference  
(1.225V). If the FB voltage is below the reference the internal  
buck switch is turned on for the one-shot timer period, which  
is a function of the input voltage and the programming resistor  
(RON). Following the on-time the switch remains off until the  
FB voltage falls below the reference, but never before the  
minimum off-time forced by the minimum off-time one-shot  
timer. When the FB pin voltage falls below the reference and  
the minimum off-time one-shot period expires, the buck  
switch is turned on for another on-time one-shot period. This  
will continue until regulation is achieved and the FB voltage  
is approximately equal to 1.225V (typ).  
VCC Regulator  
The LM5018 contains an internal high voltage linear regulator  
with a nominal output of 7.6V. The input pin (VIN) can be con-  
nected directly to the line voltages up to 100V. The VCC  
regulator is internally current limited to 30mA. The regulator  
sources current into the external capacitor at VCC. This regu-  
lator supplies current to internal circuit blocks including the  
synchronous MOSFET driver and the logic circuits. When the  
voltage on the VCC pin reaches the undervoltage lockout  
threshold of 4.5V, the IC is enabled.  
In a synchronous buck converter, the low side (sync) FET is  
'on' when the high side (buck) FET is 'off.' The inductor current  
ramps up when the high side switch is ‘on’ and ramps down  
when the high side switch is ‘off’. There is no diode emulation  
feature in this IC, and therefore, the inductor current may  
ramp in the negative direction at light load. This causes the  
converter to operate in continuous conduction mode (CCM)  
regardless of the output loading. The operating frequency re-  
mains relatively constant with load and line variations. The  
operating frequency can be calculated as follows:  
The VCC regulator contains an internal diode connection to  
the BST pin to replenish the charge in the gate drive boot  
capacitor when SW pin is low.  
At high input voltages, the power dissipated in the high volt-  
age regulator is significant and can limit the overall achievable  
output power. As an example, with the input at 48V and  
switching at high frequency, the VCC regulator may supply up  
to 7mA of current resulting in 48V x 7mA = 336mW of power  
dissipation. If the VCC voltage is driven externally by an alter-  
nate voltage source, between 8V and 13V, the internal regu-  
lator is disabled. This reduces the power dissipation in the IC.  
30181617  
FIGURE 3. Low Ripple Output Configuration  
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8
 
Regulation Comparator  
N-Channel Buck Switch and Driver  
The feedback voltage at FB is compared to an internal 1.225V  
reference. In normal operation, when the output voltage is in  
regulation, an on-time period is initiated when the voltage at  
FB falls below 1.225V. The high side switch will stay on for  
the on-time, causing the FB voltage to rise above 1.225V. Af-  
ter the on-time period, the high side switch will stay off until  
the FB voltage again falls below 1.225V. During start-up, the  
FB voltage will be below 1.225V at the end of each on-time,  
causing the high side switch to turn on immediately after the  
minimum forced off-time of 144ns. The high side switch can  
be turned off before the on-time is over, if the peak current in  
the inductor reaches the current limit threshold.  
The LM5018 integrates an N-Channel Buck switch and as-  
sociated floating high voltage gate driver. The gate driver  
circuit works in conjunction with an external bootstrap capac-  
itor and an internal high voltage diode. A 0.01uF ceramic  
capacitor connected between the BST pin and the SW pin  
provides the voltage to the driver during the on-time. During  
each off-time, the SW pin is at approximately 0V, and the  
bootstrap capacitor charges from VCC through the internal  
diode. The minimum off-timer, set to 144ns, ensures a mini-  
mum time each cycle to recharge the bootstrap capacitor.  
Synchronous Rectifier  
The LM5018 provides an internal synchronous N-Channel  
MOSFET rectifier. This MOSFET provides a path for the in-  
ductor current to flow when the high-side MOSFET is turned  
off.  
Overvoltage Comparator  
The feedback voltage at FB is compared to an internal 1.62V  
reference. If the voltage at FB rises above 1.62V the on-time  
pulse is immediately terminated. This condition can occur if  
the input voltage and/or the output load changes suddenly.  
The high side switch will not turn on again until the voltage at  
FB falls below 1.225V.  
The synchronous rectifier has no diode emulation mode, and  
is designed to keep the regulator in continuous conduction  
mode even during light loads which would otherwise result in  
discontinuous operation.  
On-Time Generator  
Undervoltage Detector  
The on-time for the LM5018 is determined by the RON resistor,  
and is inversely proportional to the input voltage (VIN), result-  
ing in a nearly constant frequency as VIN is varied over its  
range. The on-time equation for the LM5018 is:  
The LM5018 contains a dual level undervoltage lockout (UV-  
LO) circuit. When the UVLO pin voltage is below 0.66V, the  
controller is in a low current shutdown mode. When the UVLO  
pin voltage is greater than 0.66V but less than 1.225V, the  
controller is in standby mode. In standby mode the VCC bias  
regulator is active while the regulator output is disabled. When  
the VCC pin exceeds the VCC undervoltage threshold and the  
UVLO pin voltage is greater than 1.225V, normal operation  
begins. An external set-point voltage divider from VIN to GND  
can be used to set the minimum operating voltage of the reg-  
ulator.  
See figure “TON vs VIN and RON” in the section “Performance  
Curves.” RON should be selected for a minimum on-time (at  
maximum VIN) greater than 100ns, for proper operation. This  
requirement limits the maximum switching frequency for high  
VIN.  
UVLO hysteresis is accomplished with an internal 20μA cur-  
rent source that is switched on or off into the impedance of  
the set-point divider. When the UVLO threshold is exceeded,  
the current source is activated to quickly raise the voltage at  
the UVLO pin. The hysteresis is equal to the value of this cur-  
Current Limit  
rent times the resistance RUV2  
.
The LM5018 contains an intelligent current limit off-timer. If  
the current in the buck switch exceeds 575mA the present  
cycle is immediately terminated, and a non-resetable off-timer  
is initiated. The length of off-time is controlled by the FB volt-  
age and the input voltage VIN. As an example, when FB = 0V  
and VIN = 48V, the maximum off-time is set to 16μs. This con-  
dition occurs when the output is shorted, and during the initial  
part of start-up. This amount of time ensures safe short circuit  
operation up to the maximum input voltage of 100V.  
UVLO  
VCC  
Mode  
Description  
<0.66V  
Shutdown VCC Regulator  
Disabled.  
Switcher Disabled.  
0.66V – 1.225V  
>1.225V  
Standby VCC Regulator  
Enabled  
Switcher Disabled.  
In cases of overload where the FB voltage is above zero volts  
(not a short circuit) the current limit off-time is reduced. Re-  
ducing the off-time during less severe overloads reduces the  
amount of foldback, recovery time, and start-up time. The off-  
time is calculated from the following equation:  
VCC <4.5V Standby VCC Regulator  
Enabled.  
Switcher Disabled.  
VCC >4.5V Operating VCC Enabled.  
Switcher Enabled.  
If the UVLO pin is wired directly to the VIN pin, the regulator  
will begin operation once the VCC undervoltage is satisfied.  
The current limit protection feature is peak limited. The max-  
imum average output will be less than the peak.  
9
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30181621  
FIGURE 4. UVLO Resistor Setting  
When activated, typically at 165°C, the controller is forced into  
a low power reset state, disabling the buck switch and the  
VCC regulator. This feature prevents catastrophic failures from  
accidental device overheating. When the junction tempera-  
ture reduces below 145°C (typical hysteresis = 20°C), the  
VCC regulator is enabled, and normal operation is resumed.  
Thermal Protection  
The LM5018 should be operated so the junction temperature  
does not exceed 150°C during normal operation. An internal  
Thermal Shutdown circuit is provided to protect the LM5018  
in the event of a higher than normal junction temperature.  
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10  
Resistor RON sets the nominal switching frequency based on  
the following equations:  
Application Information  
SELECTION OF EXTERNAL COMPONENTS  
Selection of external components is illustrated through a de-  
sign example. The design example specifications are as fol-  
lows:  
where K = 1 x 10–10. Operation at high switching frequency  
results in lower efficiency while providing the smallest solu-  
tion. For this example a conservative 400kHz was selected,  
resulting in RON = 246k. Selecting a standard value for  
RON = 237kresults in a nominal frequency of 416kHz.  
Buck Converter Design Specifications  
Input Voltage Range  
Output Voltage  
12.5V to 95V  
10V  
Maximum Load Current  
Switching Frequency  
300mA  
400kHz  
Inductor Selection:  
The inductance selection is a compromise between solution  
size, output ripple, and efficiency. The peak inductor current  
at maximum load current should be smaller than the minimum  
current limit of 350mA. The maximum permissible peak to  
peak inductor ripple is:  
RFB1, RFB2  
:
VOUT = VFB x (RFB2/RFB1 + 1), and since VFB = 1.225V, the  
ratio of RFB2 to RFB1 calculates as 7:1. Standard values of  
6.98kand 1.00kare chosen. Other values could be used  
as long as the 7:1 ratio is maintained.  
ΔIL = 2*(ILIM(min) — IOUT(max)) = 2*50 = 100mA  
The minimum inductance is given by:  
Frequency Selection:  
At the minimum input voltage, the maximum switching fre-  
quency of LM5018 is restricted by the forced minimum off-  
time (TOFF(MIN)) as given by:  
Resulting in L=215µH. A standard value of 220µH is selected.  
For proper operation the inductor saturation current should be  
higher than the peak encountered in the application. For ro-  
bust short circuit protection, the inductor saturation current  
should be higher than the maximum current limit of 700mA.  
Similarly, at maximum input voltage, the maximum switching  
frequency of LM5018 is restricted by the minimum TON as  
given by:  
30181622  
FIGURE 5. Reference Schematic for Selection of External Components  
11  
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Output Capacitor:  
Input Capacitor:  
The output capacitor is selected to minimize the capacitive  
ripple across it. The maximum ripple is observed at maximum  
input voltage and is given by:  
Input capacitor should be large enough to limit the input volt-  
age ripple:  
choosing a ΔVIN = 0.5V gives a minimum CIN = 0.36μF. A  
standard value of 1μF is selected. The input capacitor should  
be rated for the maximum input voltage under all conditions.  
A 100V, X7R dielectric should be selected for this design.  
where ΔVripple is the voltage ripple across the capacitor. Sub-  
stituting ΔVripple = 10mV gives COUT = 2.9μF. A 4.7μF standard  
value is selected. An X5R or X7R type capacitor with a voltage  
rating 16V or higher should be selected.  
Input capacitor should be placed directly across VIN and RTN  
(pin 2 and 1) of the IC. If it is not possible to place all of the  
input capacitor close to the IC, a 0.1μF capacitor should be  
placed near the IC to provide a bypass path for the high fre-  
quency component of the switching current. This helps limit  
the switching noise.  
Series Ripple Resistor RC:  
The series resistor should be selected to produce sufficient  
ripple at the feedback node. The ripple produced by RC is  
proportional to the inductor current ripple, and therefore RC  
should be chosen for minimum inductor current ripple which  
occurs at minimum input voltage. The RC is calculated by the  
equation:  
UVLO Resistors:  
The UVLO resistors RFB1 and RFB2 set the UVLO threshold  
and hysteresis according to the following relationship:  
and  
This gives an RC of greater than or equal to 10.8. Selecting  
RC = 11Ω results in ~1V of maximum output voltage ripple.  
For application requiring lower output voltage ripple, Type II  
or Type III ripple injection circuits should be used as described  
in the section “Ripple Configuration”.  
VCC and Bootstrap Capacitor:  
where IHYS = 20μA. Setting UVLO hysteresis of 2.5V and UV-  
LO rising threshold of 12V results in RUV1 = 14.53kand  
RUV2 = 125k. Selecting standard value of RUV1 = 14kand  
RUV2 = 125kresults in UVLO thresholds and hysteresis of  
12.4V and 2.5V respectively.  
The VCC capacitor provides charge to bootstrap capacitor as  
well as internal circuitry and low side gate driver. The Boot-  
strap capacitor provides charge to high side gate driver. A  
good value for CVCC is 1μF. A good value for CBST is 0.01μF.  
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12  
APPLICATION CIRCUIT: 12V TO 95V INPUT AND 10V,  
300mA OUTPUT BUCK CONVERTER  
1. Capacitive ripple caused by the inductor current ripple  
charging/discharging the output capacitor.  
The application schematic of a buck supply is shown in Figure  
6 below. For output voltage (VOUT) above the maximum reg-  
ulation threshold of VCC (8.3V, see electrical characteristics),  
the VCC pin can be connected to VOUT through a diode (D2),  
as shown below, for higher efficiency and lower power dissi-  
pation in the IC.  
2. Resistive ripple caused by the inductor current ripple  
flowing through the ESR of the output capacitor.  
The capacitive ripple is not in phase with the inductor current.  
As a result, the capacitive ripple does not decrease mono-  
tonically during the off-time. The resistive ripple is in phase  
with the inductor current and decreases monotonically during  
the off-time. The resistive ripple must exceed the capacitive  
ripple at the output node (VOUT) for stable operation. If this  
condition is not satisfied unstable switching behavior is ob-  
served in COT converters, with multiple on-time bursts in  
close succession followed by a long off-time.  
RIPPLE CONFIGURATION  
LM5018 uses Constant-On-Time (COT) control scheme, in  
which the on-time is terminated by an on-timer, and the off-  
time is terminated by the feedback voltage (VFB) falling below  
the reference voltage (VREF). Therefore, for stable operation,  
the feedback voltage must decrease monotonically, in phase  
with the inductor current during the off-time. Furthermore, this  
change in feedback voltage (VFB) during off-time must be  
large enough to suppress any noise component present at the  
feedback node.  
Type 3 ripple method uses Rr and Cr and the switch node  
(SW) voltage to generate a triangular ramp. This triangular  
ramp is ac coupled using Cac to the feedback node (FB). Since  
this circuit does not use the output voltage ripple, it is ideally  
suited for applications where low output voltage ripple is re-  
quired. See application note AN-1481 for more details for  
each ripple generation method.  
Table 1 shows three different methods for generating appro-  
priate voltage ripple at the feedback node. Type 1 and Type  
2 ripple circuits couple the ripple at the output of the converter  
to the feedback node (FB). The output voltage ripple has two  
components:  
30181633  
FIGURE 6. Final Schematic for 12V to 95V Input, and 10V, 300mA Output Buck Converter  
13  
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Type 1  
Type 2  
Type 3  
Lowest Cost Configuration  
Reduced Ripple Configuration  
Minimum Ripple Configuration  
LAYOUT RECOMMENDATION  
side gate drivers. These two capacitors should also be  
placed as close to the IC as possible, and the connecting  
trace length and loop area should be minimized (See  
Figure 7 Placement of Bypass Capacitors).  
A proper layout is essential for optimum performance of the  
circuit. In particular, the following guidelines should be ob-  
served:  
3. The Feedback trace carries the output voltage  
information and a small ripple component that is  
necessary for proper operation of LM5018. Therefore,  
care should be taken while routing the feedback trace to  
avoid coupling any noise to this pin. In particular,  
feedback trace should not run close to magnetic  
components, or parallel to any other switching trace.  
1. CIN: The loop consisting of input capacitor (CIN), VIN pin,  
and RTN pin carries switching currents. Therefore, the  
input capacitor should be placed close to the IC, directly  
across VIN and RTN pins and the connections to these  
two pins should be direct to minimize the loop area. In  
general it is not possible to accommodate all of input  
capacitance near the IC. A good practice is to use a  
0.1μF or 0.47μF capacitor directly across the VIN and  
RTN pins close to the IC, and the remaining bulk  
capacitor as close as possible (Refer to Figure 7  
Placement of Bypass Capacitors).  
4. SW trace: The SW node switches rapidly between VIN  
and GND every cycle and is therefore a possible source  
of noise. The SW node area should be minimized. In  
particular, the SW node should not be inadvertently  
connected to a copper plane or pour.  
2. CVCC and CBST: The VCC and bootstrap (BST) bypass  
capacitors supply switching currents to the high and low  
30181640  
FIGURE 7. Placement of Bypass Capacitors  
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14  
 
Physical Dimensions inches (millimeters) unless otherwise noted  
PSOP–8 Outline Drawing  
NS Package Number MRA08A  
8-Lead LLP Package  
NS Package Number SDC08B  
15  
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