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LM5022-Q1

ZHCSES8 –MARCH 2016

LM5022-Q1 适用于升压和 SEPIC 的 2.2MHz、60V 低侧控制器

1 特性

3 说明

1

•

具有符合 AEC-Q100 1 级标准的下列结果：

LM5022-Q1 是一款高压、低侧 N 沟道 MOSFET 控制

器，非常适合升压稳压器和 SEPIC 稳压器。该器件包

含实现单端一次侧拓扑所需的全部功能。输出稳压基

于电流模式控制，这不仅简化了环路补偿的设计，同时

还能够提供固有输入电压前馈。LM5022-Q1 包含一个

启动稳压器，该稳压器在 6V 至 60V 的宽输入电压范

围内工作。PWM 控制器专为高速性能而设计，振荡器

频率范围高达 2.2MHz，总传播延迟不到 100ns。其他

功能包括误差放大器、精密基准、线路欠压锁定、逐

周期电流限制、斜率补偿、软启动、外部同步功能以及

热关断。LM5022-Q1 采用 10 引脚 VSSOP 封装。

–

器件温度等级 1：-40°C 至 125°C 的环境运行

温度范围

器件人体放电模式 (HBM) 静电放电 (ESD) 分类

等级 2

器件组件充电模式 (CDM) ESD 分类等级 C5

•

内部 60V 启动稳压器

峰值电流为 1A 的金属氧化物半导体场效应晶体管

(MOSFET) 栅极驱动器

•

V_IN范围：6V 至 60V（启动后，最低可以在 3V 下

工作）

•

占空比限值为 90%

器件信息⁽¹⁾

可编程欠压锁定 (UVLO) 与滞后

逐周期电流限制

器件型号

LM5022-Q1

封装

封装尺寸（标称值）

VSSOP (10)

3.00mm x 3.00mm

可通过单个电阻设置振荡器频率

可调节开关频率范围达 2.2MHz

外部时钟同步

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

斜率补偿

可调节软启动

10 引脚超薄小外形尺寸 (VSSOP) 封装

2 应用

•

升压转换器

SEPIC 转换器

典型应用

V

IN

L1

V

D1

O

Q1

R

C

O

IN

R

S1

VIN

RT

OUT

R

T

R

UV2

UV1

SNS

CS

C

CS

UVLO

SS

GND

C

SS

C

F

VCC

R

FB2

COMP

R1

FB

C2

R

FB1

C1

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSAG9

LM5022-Q1

ZHCSES8 –MARCH 2016

www.ti.com.cn

7.4 Device Functional Modes........................................ 12

Application and Implementation ........................ 14

8.1 Application Information............................................ 14

8.2 Typical Application ................................................. 14

Power Supply Recommendations...................... 28

1

2

3

4

5

6

特性.......................................................................... 1

8

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings: LM5022-Q1 ........................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics .......................................... 5

6.6 Typical Characteristics.............................................. 7

Detailed Description .............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................. 10

10 Layout................................................................... 28

10.1 Layout Guidelines ................................................. 28

10.2 Layout Example .................................................... 30

11 器件和文档支持 ..................................................... 31

11.1 器件支持................................................................ 31

11.2 社区资源................................................................ 31

11.3 商标....................................................................... 31

11.4 静电放电警告......................................................... 31

11.5 Glossary................................................................ 31

12 机械、封装和可订购信息....................................... 31

7

4 修订历史记录

日期

修订版本

注释

2016 年 3 月

*

首次发布。

2

LM5022-Q1

www.ti.com.cn

ZHCSES8 –MARCH 2016

5 Pin Configuration and Functions

DGS Package

10-Pin VSSOP

Top View

1

10

9

VIN

SS

RT

2

3

4

FB

8

COMP

VCC

OUT

CS

7

6

UVLO

GND

5

Pin Functions

NAME

TYPE

DESCRIPTION

APPLICATION INFORMATION

NO.

1

VIN

Input to the start-up regulator. Operates from 6 V to 60

V.

I

Source input voltage

Inverting input to the internal voltage error amplifier.

The non-inverting input of the error amplifier connects

to a 1.25-V reference.

2

3

FB

I

Feedback pin

Error amplifier output and PWM

comparator input

The control loop compensation components connect

between this pin and the FB pin.

COMP

I/O

O

Output of the internal, high voltage linear

regulator.

This pin should be bypassed to the GND pin with a

ceramic capacitor.

4

5

VCC

OUT

O

-

Output of MOSFET gate driver

Connect this pin to the gate of the external MOSFET.

The gate driver has a 1-A peak current capability.

6

7

GND

System ground

Set the start-up and shutdown levels by connecting

this pin to the input voltage through a resistor divider.

A 20-µA current source provides hysteresis.

UVLO

I

Input undervoltage lockout

Current sense input

I

Input for the switch current used for current mode

control and for current limiting.

8

9

CS

An external resistor connected from this pin to GND

sets the oscillator frequency. This pin can also accept

an AC-coupled input for synchronization from an

external clock.

Oscillator frequency adjust pin and

synchronization input

RT/SYNC

I

An external capacitor placed from this pin to ground

will be charged by a 10-µA current source, creating a

ramp voltage to control the regulator start-up.

10

SS

Soft-start pin

3

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ZHCSES8 –MARCH 2016

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

MAX

65

UNIT

VIN to GND

V

VCC to GND

16

RT/SYNC to GND

OUT to GND

5.5

–1.5V for < 100 ns

–0.3

All other pins to GND

Power dissipation

Junction temperature⁽³⁾

7

V

Internally limited

150

215

220

°C

Vapor phase (60 sec.)

Infrared (15 sec.)

Soldering information

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings: LM5022-Q1

VALUE

±2000

±750

UNIT

V

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charged device model (CDM), per AEC Q100-011⁽²⁾

V_(ESD)

V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. This is the passing

level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD

control process

(2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe

manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

6

NOM

MAX

60

UNIT

V

Supply voltage

External voltage at V_CC

Junction temperature

7.5

–40

14

V

125

°C

(1) Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical

Characteristics

6.4 Thermal Information

LM5022-Q1

THERMAL METRIC⁽¹⁾

DGS (VSSOP)

UNIT

10 PINS

161.5

56

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

81.3

5.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

80

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

4

LM5022-Q1

www.ti.com.cn

ZHCSES8 –MARCH 2016

6.5 Electrical Characteristics

Typical limits apply for T_J= 25°C and are provided for reference purposes only; minimum and maximum limits apply over the

junction temperature (T_J) range of –40°C to +125°C. V_IN= 24 V and R_T= 27.4 kΩ, unless otherwise indicated.⁽¹⁾

PARAMETER

SYSTEM PARAMETERS

V_FBFB Pin Voltage

START-UP REGULATOR

TEST CONDITIONS

MIN

TYP

MAX UNIT

1.225 1.250 1.275

V

VCC Regulation

10 V ≤ V_IN≤ 60 V, I_CC= 1 mA

6.6

5

7

7.4

4

VCC⁽²⁾

VCC Regulation

Supply Current

VCC Current Limit

6 V ≤ V_IN< 10 V, VCC Pin Open Circuit

OUT Pin Capacitance = 0

VCC = 10 V

3.5

I_CC

mA

mV

(2)

I_CC-LIM

V_IN- VCC

VCC = 0 V, (⁽³⁾

,

)

15

35

Dropout Voltage Across Bypass

Switch

I_CC= 0 mA, ƒ_SW< 200 kHz

6 V ≤ V_IN≤ 8.5 V

200

V_BYP-HI

Bypass Switch Turn-off Threshold

Bypass Switch Threshold Hysteresis

V_INincreasing

V_INDecreasing

V_IN= 6 V

8.7

260

58

V

V_BYP-HYS

mV

VCC Pin Output Impedance

0 mA ≤ ICC ≤ 5 mA

Z_VCC

V_IN= 8 V

53

Ω

V_IN= 24 V

1.6

5

VCC_-HI

VCC Pin UVLO Rising Threshold

VCC Pin UVLO Falling Hysteresis

Start-up Regulator Leakage

Shutdown Current

V

VCC_-HYS

300

150

350

mV

µA

I_VIN

V_IN= 60 V

500

450

I_IN-SD

V_UVLO= 0 V, VCC = Open Circuit

ERROR AMPLIFIER

GBW

A_DC

Gain Bandwidth

DC Gain

4

75

17

MHz

dB

V_FB= 1.5 V

V_COMP= 1 V

5

I_COMP

COMP Pin Current Sink Capability

mA

UVLO

V_SD

Shutdown Threshold

1.22

16

1.25

20

1.28

24

V

Shutdown

Hysteresis Current Source

I_SD-HYS

µA

CURRENT LIMIT

t_LIM-DLY

CS steps from 0 V to 0.6 V

OUT transitions to 90% of VCC

30

Delay from ILIM to Output

ns

V_CS

Current Limit Threshold Voltage

Leading Edge Blanking Time

CS Pin Sink Impedance

0.434

0.5

65

40

0.55

75

V

ns

Ω

t_BLK

R_CS

Blanking active

SOFT-START

I_SS

Soft-start Current Source

Soft-start to COMP Offset

7

10

13

µA

V

V_SS-OFF

0.344

0.55

0.75

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and

applying statistical process control. The junction temperature (T_Jin °C) is calculated from the ambient temperature (T_Ain °C) and power

dissipation (P_Din Watts) as follows: T_J= T_A+ (P_D• R_θJA) where R_θJA(in °C/W) is the package thermal impedance provided in the

Thermal Information section.

(2) VCC provides bias for the internal gate drive and control circuits.

(3) Device thermal limitations may limit usable range.

5

LM5022-Q1

ZHCSES8 –MARCH 2016

www.ti.com.cn

Electrical Characteristics (continued)

Typical limits apply for T_J= 25°C and are provided for reference purposes only; minimum and maximum limits apply over the

junction temperature (T_J) range of –40°C to +125°C. V_IN= 24 V and R_T= 27.4 kΩ, unless otherwise indicated.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

OSCILLATOR

f_SW

RT to GND = 84.5 kΩ

See⁽⁴⁾

170

525

200

600

230 kHz

675 kHz

1115 kHz

2570 kHz

RT to GND = 27.4 kΩ

RT to GND = 16.2 kΩ

865

990

RT to GND = 6.65 kΩ

1910

2240

V_SYNC-HI

Synchronization Rising Threshold

3.8

V

PWM COMPARATOR

V_COMP= 2 V

CS stepped from 0 V to 0.4 V

25

t_COMP-DLY

Delay from COMP to OUT Transition

ns

D_MIN

Minimum Duty Cycle

V_COMP= 0 V

0%

D_MAX

Maximum Duty Cycle

90%

95%

0.33

5.2

A_PWM

COMP to PWM Comparator Gain

COMP Pin Open Circuit Voltage

COMP Pin Short Circuit Current

V/V

V

V_COMP-OC

I_COMP-SC

SLOPE COMPENSATION

V_FB= 0 V

4.3

0.6

6.1

1.5

V_COMP= 0 V, V_FB= 0V

1.1

mA

V_SLOPE

Slope Compensation Amplitude

83

110

137

mV

MOSFET DRIVER

V_SAT-HI

Output High Saturation Voltage

(VCC – VOUT)

I_OUT= 50 mA

I_OUT= 100 mA

0.25

0.75

V

V_SAT-LO

Output Low Saturation Voltage

(VOUT)

t_RISE

t_FALL

OUT Pin Rise Time

OUT Pin Fall Time

OUT Pin load = 1 nF

18

15

ns

THERMAL CHARACTERISTICS

T_SD

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

165

25

°C

T_SD-HYS

(4) Specification applies to the oscillator frequency.

6

LM5022-Q1

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ZHCSES8 –MARCH 2016

6.6 Typical Characteristics

V_O= 40 V

V_IN= 24 V

Figure 1. Efficiency, Example Circuit BOM

Figure 2. V_FBvs. Temperature

T_A= 25°C

Figure 3. V_FBvs. V_IN

Figure 4. V_CCvs. V_IN

R_T= 16.2 KΩ

T_A= 25°C

Figure 5. Maximum Duty Cycle vs. ƒ_SW

Figure 6. ƒ_SWvs. Temperature

7

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ZHCSES8 –MARCH 2016

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Typical Characteristics (continued)

2320

2310

2300

2290

2280

2270

2260

2250

2240

2230

2220

2210

-60 -40 -20

0

20

40

60

80 100 120 140

TEMPERATURE (^oC)

R_T= 6.65 KΩ

Figure 8. SS vs. Temperature

Figure 7. ƒ_SWvs. Temperature

Figure 9. OUT Pin T_RISEvs. Gate Capacitance

Figure 10. OUT Pin T_FALLvs. Gate Capacitance

85

75

65

55

45

35

25

15

5

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

SWITCHING FREQUNECY (kHz)

T_A= 25°C

Figure 11. R_Tvs. ƒ_SW

8

LM5022-Q1

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ZHCSES8 –MARCH 2016

7 Detailed Description

7.1 Overview

The LM5022-Q1 is a low-side N-channel MOSFET controller that contains all of the features needed to

implement single ended power converter topologies. The LM5022-Q1 includes a high-voltage startup regulator

that operates over a wide input range of 6 V to 60 V. The PWM controller is designed for high speed capability

including an oscillator frequency range up to 2.2 MHz and total propagation delays less than 100 ns. Additional

features include an error amplifier, precision reference, input under-voltage lockout, cycle-by-cycle current limit,

slope compensation, soft-start, oscillator sync capability and thermal shutdown.

The LM5022-Q1 is designed for current-mode control power converters that require a single drive output, such

as boost and SEPIC topologies. The LM5022-Q1 provides all of the advantages of current-mode control

including input voltage feed-forward, cycle-by-cycle current limiting and simplified loop compensation.

7.2 Functional Block Diagram

BYPASS

SWITCH

(6V to 8.7V)

VCC

VIN

7V SERIES

REGULATOR

5V

1.25V

REFERENCE

ENABLE

+

-

UVLO

LOGIC

1.25V

UVLO

HYSTERESIS

CLK

(20 mA)

RT/SYNC

OSC

DRIVER

45 mA

S

R

Q

OUT

GND

Max Duty

Limit

Q

0

5V

COMP

FB

5k

1.25V

PWM

100 kW

+

-

LOGIC

SS

1.4V

50 kW

10 mA

SS

+

CS

-

0.5V

CLK + LEB

2 kW

9

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ZHCSES8 –MARCH 2016

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7.3 Feature Description

7.3.1 High Voltage Start-Up Regulator

The LM5022-Q1 contains an internal high-voltage start-up regulator that allows the VIN pin to be connected

directly to line voltages as high as 60 V. The regulator output is internally current limited to 35 mA (typical). When

power is applied, the regulator is enabled and sources current into an external capacitor, C_F, connected to the

VCC pin. The recommended capacitance range for C_Fis 0.1 µF to 100 µF. When the voltage on the VCC pin

reaches the rising threshold of 5 V, the controller output is enabled. The controller will remain enabled until VCC

falls below 4.7 V. In applications using a transformer, an auxiliary winding can be connected through a diode to

the VCC pin. This winding should raise the VCC pin voltage to above 7.5 V to shut off the internal startup

regulator. Powering VCC from an auxiliary winding improves conversion efficiency while reducing the power

dissipated in the controller. The capacitance of C_Fmust be high enough that it maintains the VCC voltage greater

than the VCC UVLO falling threshold (4.7 V) during the initial start-up. During a fault condition when the

converter auxiliary winding is inactive, external current draw on the VCC line should be limited such that the

power dissipated in the start-up regulator does not exceed the maximum power dissipation capability of the

controller.

An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the

VCC and the VIN pins together and feeding the external bias voltage (7.5 V to 14 V) to the two pins.

7.3.2 Input Undervoltage Detector

The LM5022-Q1 contains an input undervoltage lockout (UVLO) circuit. UVLO is programmed by connecting the

UVLO pin to the center point of an external voltage divider from VIN to GND. The resistor divider must be

designed such that the voltage at the UVLO pin is greater than 1.25 V when V_INis in the desired operating

range. If the under voltage threshold is not met, all functions of the controller are disabled and the controller

remains in a low power standby state. UVLO hysteresis is accomplished with an internal 20 µA current source

that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the

current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below

the 1.25 V threshold the current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO pin

can also be used to implement a remote enable / disable function. If an external transistor pulls the UVLO pin

below the 1.25 V threshold, the converter will be disabled. This external shutdown method is shown in Figure 12.

VIN

V

IN

R

UV2

LM5022

UVLO

ON/OFF

R

UV1

2N7000 or

Equivalent

GND

Figure 12. Enable/Disable Using UVLO

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Feature Description (continued)

7.3.3 Error Amplifier

An internal high gain error amplifier is provided within the LM5022-Q1. The amplifier’s non-inverting input is

internally set to a fixed reference voltage of 1.25 V. The inverting input is connected to the FB pin. In non-

isolated applications such as the boost converter the output voltage, V_O, is connected to the FB pin through a

resistor divider. The control loop compensation components are connected between the COMP and FB pins. For

most isolated applications the error amplifier function is implemented on the secondary side of the converter and

the internal error amplifier is not used. The internal error amplifier is configured as an open drain output and can

be disabled by connecting the FB pin to ground. An internal 5-kΩ pullup resistor between a 5-V reference and

COMP can be used as the pull-up for an opto-coupler in isolated applications.

7.3.4 Current Sensing and Current Limiting

The LM5022-Q1 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an

internal current sense comparator. If the voltage at the current sense comparator input exceeds 0.5 V, the

MOSFET gate drive will be immediately terminated. A small RC filter, located near the controller, is

recommended to filter noise from the current sense signal. The CS input has an internal MOSFET which

discharges the CS pin capacitance at the conclusion of every cycle. The discharge device remains on an

additional 65 ns after the beginning of the new cycle to attenuate leading edge ringing on the current sense

signal.

The LM5022-Q1 current sense and PWM comparators are very fast, and may respond to short duration noise

pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated

with the CS filter must be located very close to the device and connected directly to the pins of the controller (CS

and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to

the sense resistor and the current sense filter network. The current sense resistor can be located between the

source of the primary power MOSFET and power ground, but it must be a low inductance type. When designing

with a current sense resistor all of the noise sensitive low-power ground connections should be connected

together locally to the controller and a single connection should be made to the high current power ground

(sense resistor ground point).

7.3.5 PWM Comparator and Slope Compensation

The PWM comparator compares the current ramp signal with the error voltage derived from the error amplifier

output. The error amplifier output voltage at the COMP pin is offset by 1.4 V and then further attenuated by a 3:1

resistor divider. The PWM comparator polarity is such that 0 V on the COMP pin will result in a zero duty cycle at

the controller output. For duty cycles greater than 50%, current mode control circuits can experience sub-

harmonic oscillation. By adding an additional fixed-slope voltage ramp signal (slope compensation) this

oscillation can be avoided. Proper slope compensation damps the double pole associated with current mode

control (see Control Loop Compensation) and eases the design of the control loop compensator. The LM5022-

Q1 generates the slope compensation with a sawtooth-waveform current source with a slope of 45 µA × ƒ_SW

,

generated by the clock (see Figure 13). This current flows through an internal 2-kΩ resistor to create a minimum

compensation ramp with a slope of 100 mV × ƒ_SW(typical). The slope of the compensation ramp increases when

external resistance is added for filtering the current sense (R_S1) or in the position R_S2. As shown in Figure 13 and

the Functional Block Diagram, the sensed current slope and the compensation slope add together to create the

signal used for current limiting and for the control loop itself.

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Feature Description (continued)

I

LM5022

SW

45 mA

0

R

S2

S1

2 kW

CS

Current

Limit

-

+

0.5V

R

SNS

C

SNS

V

CL

Figure 13. Slope Compensation

In peak current mode control the optimal slope compensation is proportional to the slope of the inductor current

during the power switch off-time. For boost converters the inductor current slope while the MOSFET is off is (V_O-

V_IN) / L. This relationship is combined with the requirements to set the peak current limit and is used to select

R_SNSand R_S2in Application and Implementation.

7.3.6 Soft Start

The soft-start feature allows the power converter output to gradually reach the initial steady state output voltage,

thereby reducing start-up stresses and current surges. At power on, after the VCC and input under-voltage

lockout thresholds are satisfied, an internal 10-µA current source charges an external capacitor connected to the

SS pin. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the switch current.

7.3.7 MOSFET Gate Driver

The LM5022-Q1 provides an internal gate driver through the OUT pin that can source and sink a peak current of

1 A to control external, ground-referenced N-channel MOSFETs.

7.3.8 Thermal Shutdown

Internal thermal shutdown circuitry is provided to protect the LM5022-Q1 in the event that the maximum junction

temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power standby

state, disabling the output driver and the VCC regulator. After the temperature is reduced (typical hysteresis is

25°C) the VCC regulator will be re-enabled and the LM5022-Q1 will perform a soft start.

7.4 Device Functional Modes

7.4.1 Oscillator, Shutdown, and SYNC

A single external resistor, R_T, connected between the RT/SYNC and GND pins sets the LM5022-Q1 oscillator

frequency. To set the switching frequency, ƒ_SW, R_Tcan be calculated from:

1- 8´10^-8´ f_SW

(

=

)

R_T

f_SW´ 5.77´10^-11

where

•

f_SWis in Hz

R_Tis in Ω

(1)

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Device Functional Modes (continued)

The LM5022-Q1 can also be synchronized to an external clock. The external clock must have a higher frequency

than the free running oscillator frequency set by the R_Tresistor. The clock signal should be capacitively coupled

into the RT/SYNC pin with a 100-pF capacitor as shown in Figure 14. A peak voltage level greater than 3.8 V at

the RT/SYNC pin is required for detection of the sync pulse. The sync pulse width should be set between 15 ns

to 150 ns by the external components. The R_Tresistor is always required, whether the oscillator is free running

or externally synchronized. The voltage at the RT/SYNC pin is internally regulated to 2 V, and the typical delay

from a logic high at the RT/SYNC pin to the rise of the OUT pin voltage is 120 ns. R_Tshould be located very

close to the device and connected directly to the pins of the controller (RT/SYNC and GND).

LM5022

EXTERNAL

CLOCK

C

SS

RT/SYNC

100 pF

R

T

15 ns to 150 ns

EXTERNAL

CLOCK

120 ns

(Typical)

OUT PIN

Figure 14. SYNC Operation

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The most common circuit controlled by the LM5022-Q1 is a non-isolated boost regulator. The boost regulator

steps up the input voltage and has a duty ratio D of:

V_O- V_IN+ V_D

D =

V_O+ V_D

where

•

V_Dis the forward voltage drop of the output diode

(2)

The following is a design procedure for selecting all the components for the boost converter circuit shown in

Figure 15. The application is "in-cabin" automotive, meaning that the operating ambient temperature ranges from

–20°C to 85°C. This circuit operates in continuous conduction mode (CCM), where inductor current stays above

0 A at all times, and delivers an output voltage of 40 V ±2% at a maximum output current of 0.5A. Additionally,

the regulator must be able to handle a load transient of up to 0.5 A while keeping V_Owithin ±4%. The voltage

input comes from the battery/alternator system of an automobile, where the standard range 9 V to 16 V and

transients of up to 32 V must not cause any malfunction.

8.2 Typical Application

V_IN= 9V to 16V

L1

V_O= 40V

D1

C

IN1,2

C

INX

Q1

R

C

O1,2

C

OX

R

S1

VIN

RT

OUT

R

T

R

S2

R

UV2

SNS

CS

C

CS

UVLO

SS

GND

C

SS

C

F

VCC

UV1

R

FB2

COMP

R1

FB

C2

R

FB1

C1

Figure 15. LM5022-Q1 Typical Application

8.2.1 Design Requirements

For typical low-side controller applications, use the parameters listed in Table 1.

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Typical Application (continued)

Table 1. Design Parameters

DESIGN PARAMETER

Minimum input voltage

Minimum output voltage

Output current

EXAMPLE VALUE

9 V to 16 V

40 V

500 mA

Switching frequency

500 kHz

Table 2. BOM for Example Circuit

ID

U1

PART NUMBER

LM5022-Q1

TYPE

Low-Side Controller

MOSFET

SIZE

10-pin VSSOP

SO-8

PARAMETERS

QTY

VENDOR

TI

60V

1

2

1

Q1

Si4850EY

60V, 31mΩ, 27nC

60V, 2A

Vishay

Central Semi

TDK

D1

CMSH2-60M

Schottky Diode

Inductor

SMA

L1

SLF12575T-M3R2

C4532X7R1H475M

C5750X7R2A475M

C2012X7R1E105K

12.5 x 12.5 x 7.5 mm

1812

33µH, 3.2A, 40mΩ

4.7µF, 50V, 3mΩ

4.7µF,100V, 3mΩ

1µF, 25V

Cin1, Cin2

Co1, Co2

Cf

Capacitor

TDK

Capacitor

2220

TDK

Capacitor

0805

TDK

Cinx

Cox

C2012X7R2A104M

Capacitor

0805

100nF, 100V

2

TDK

C1

C2

VJ0805A561KXXAT

VJ0805Y124KXXAT

VJ0805Y103KXXAT

VJ0805Y102KXXAT

CRCW08053011F

CRCW08056490F

CRCW08052002F

CRCW0805101J

Capacitor

Resistor

0805

1210

0805

560pF 10%

120nF 10%

10nF 10%

1nF 10%

1

Vishay

Panasonic

Vishay

Css

Ccs

R1

3.01kΩ 1%

649Ω 1%

Rfb1

Rfb2

Rs1

Rs2

Rsns

Rt

20kΩ 1%

100Ω 5%

CRCW08053571F

ERJL14KF10C

3.57kΩ 1%

100mΩ, 1%, 0.5W

33.2kΩ 1%

2.61kΩ 1%

10kΩ 1%

CRCW08053322F

CRCW08052611F

CRCW08051002F

Ruv1

Ruv2

8.2.2 Detailed Design Procedure

8.2.2.1 Switching Frequency

The selection of switching frequency is based on the tradeoffs between size, cost, and efficiency. In general, a

lower frequency means larger, more expensive inductors and capacitors will be needed. A higher switching

frequency generally results in a smaller but less efficient solution, as the power MOSFET gate capacitances must

be charged and discharged more often in a given amount of time. For this application, a frequency of 500 kHz

was selected as a good compromise between the size of the inductor and efficiency. PCB area and component

height are restricted in this application. Following the equation given for R_Tin Equation 1, a 33.2-kΩ 1% resistor

should be used to switch at 500 kHz.

8.2.2.2 MOSFET

Selection of the power MOSFET is governed by tradeoffs between cost, size, and efficiency. Breaking down the

losses in the MOSFET is one way to determine relative efficiencies between different devices. For this example,

the SO-8 package provides a balance of a small footprint with good efficiency.

Losses in the MOSFET can be broken down into conduction loss, gate charging loss, and switching loss.

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Conduction, or I²R loss, P_C, is approximately:

2

I_O

x R_DSONx 1.3

P_C= D x

1-D

(3)

The factor 1.3 accounts for the increase in MOSFET on resistance due to heating. Alternatively, the factor of 1.3

can be ignored and the maximum on resistance of the MOSFET can be used.

Gate charging loss, P_G, results from the current required to charge and discharge the gate capacitance of the

power MOSFET and is approximated as:

P_G= VCC × Q_G× f_SW

(4)

Q_Gis the total gate charge of the MOSFET. Gate charge loss differs from conduction and switching losses

because the actual dissipation occurs in the LM5022-Q1 and not in the MOSFET itself. If no external bias is

applied to the VCC pin, additional loss in the LM5022-Q1 IC occurs as the MOSFET driving current flows through

the VCC regulator. This loss, P_VCC, is estimated as:

P_VCC= (V_IN– VCC) × Q_G× f_SW

(5)

Switching loss, P_SW, occurs during the brief transition period as the MOSFET turns on and off. During the

transition period both current and voltage are present in the channel of the MOSFET. The loss can be

approximated as:

P_SW= 0.5 × V_IN× [I_O/ (1 – D)] × (t_R+ t_F) × ƒ_SW

where

•

t_Ris the rise time of the MOSFET

t_Fis the fall time of the MOSFET

(6)

For this example, the maximum drain-to-source voltage applied across the MOSFET is V_Oplus the ringing due to

parasitic inductance and capacitance. The maximum drive voltage at the gate of the high side MOSFET is VCC,

or 7 V typical. The MOSFET selected must be able to withstand 40V plus any ringing from drain to source, and

be able to handle at least 7V plus ringing from gate to source. A minimum voltage rating of 50V_D-Sand 10V_G-S

MOSFET will be used. Comparing the losses in a spreadsheet leads to a 60V_D-Srated MOSFET in SO-8 with an

R_DSONof 22 mΩ (the maximum vallue is 31 mΩ), a gate charge of 27 nC, and rise and falls times of 10 ns and

12 ns, respectively.

8.2.2.3 Output Diode

The boost regulator requires an output diode D1 (see Figure 15) to carrying the inductor current during the

MOSFET off-time. The most efficient choice for D1 is a Schottky diode due to low forward drop and near-zero

reverse recovery time. D1 must be rated to handle the maximum output voltage plus any switching node ringing

when the MOSFET is on. In practice, all switching converters have some ringing at the switching node due to the

diode parasitic capacitance and the lead inductance. D1 must also be rated to handle the average output current,

I_O.

The overall converter efficiency becomes more dependent on the selection of D1 at low duty cycles, where the

boost diode carries the load current for an increasing percentage of the time. This power dissipation can be

calculating by checking the typical diode forward voltage, V_D, from the I-V curve on the diode's datasheet and

then multiplying it by I_O. Diode datasheets will also provide a typical junction-to-ambient thermal resistance, R_θJA

,

which can be used to estimate the operating die temperature of the Schottky. Multiplying the power dissipation

(P_D= I_O× V_D) by R_θJAgives the temperature rise. The diode case size can then be selected to maintain the

Schottky diode temperature below the operational maximum.

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In this example a Schottky diode rated to 60 V and 1 A will be suitable, as the maximum diode current will be 0.5

A. A small case such as SOD-123 can be used if a small footprint is critical. Larger case sizes generally have

lower R_θJAand lower forward voltage drop, so for better efficiency the larger SMA case size will be used.

8.2.2.4 Boost Inductor

The first criterion for selecting an inductor is the inductance itself. In fixed-frequency boost converters this value

is based on the desired peak-to-peak ripple current, Δi_L, which flows in the inductor along with the average

inductor current, I_L. For a boost converter in CCM I_Lis greater than the average output current, I_O. The two

currents are related by the following expression:

I_L= I_O/ (1 – D)

(7)

As with switching frequency, the inductance used is a tradeoff between size and cost. Larger inductance means

lower input ripple current, however because the inductor is connected to the output during the off-time only there

is a limit to the reduction in output ripple voltage. Lower inductance results in smaller, less expensive magnetics.

An inductance that gives a ripple current of 30% to 50% of I_Lis a good starting point for a CCM boost converter.

Minimum inductance should be calculated at the extremes of input voltage to find the operating condition with the

highest requirement:

V_INx D

L₁=

f_SWx Di_L

(8)

By calculating in terms of amperes, volts, and megahertz, the inductance value will come out in micro henries.

In order to ensure that the boost regulator operates in CCM a second equation is needed, and must also be

evaluated at the corners of input voltage to find the minimum inductance required:

D(1-D) x V_IN

L₂=

I_Ox f_SW

(9)

By calculating in terms of volts, amps and megahertz the inductance value will come out in µH.

For this design Δi_Lwill be set to 40% of the maximum I_L. Duty cycle is evaluated first at V_IN(MIN)and at V_IN(MAX)

.

Second, the average inductor current is evaluated at the two input voltages. Third, the inductor ripple current is

determined. Finally, the inductance can be calculated, and a standard inductor value selected that meets all the

criteria.

1. Inductance for Minimum Input Voltage

D_VIN(MIN)= (40 – 9 + 0.5) / (40 + 0.5) = 78% I_L-VIN(MIN)= 0.5 / (1 – 0.78) = 2.3 A Δi_L= 0.4 × 2.3 A = 0.92 A

(10)

(11)

9 x 0.78

= 15.3 mH

L_1-VIN(MIN)

=

0.5 x 0.92

0.78 x 0.22 x 9

0.5 x 0.5

= 6.2 mH

L_2-VIN(MIN)

=

(12)

(13)

2. Inductance for Maximum Input Voltage

D_VIN(MAX)= (40 – 16 + 0.5) / (40 + 0.5) = 60% I_L-VIN(MIAX)= 0.5 / (1 – 0.6) = 1.25A Δi_L= 0.4 × 1.25 A = 0.5 A

16 x 0.6

0.5 x 0.5

= 38.4 mH

L_1-VIN(MAX)

=

(14)

0.6 x 0.4 x 16

0.5 x 0.5

L_2-VIN(MAX)

=

= 15.4 mH

(15)

Maximum average inductor current occurs at V_IN(MIN), and the corresponding inductor ripple current is 0.92 A_P-P

.

Selecting an inductance that exceeds the ripple current requirement at V_IN(MIN)and the requirement to stay in

CCM for V_IN(MAX)provides a tradeoff that allows smaller magnetics at the cost of higher ripple current at

maximum input voltage. For this example, a 33-µH inductor will satisfy these requirements.

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The second criterion for selecting an inductor is the peak current carrying capability. This is the level above

which the inductor will saturate. In saturation the inductance can drop off severely, resulting in higher peak

current that may overheat the inductor or push the converter into current limit. In a boost converter, peak current,

I_PK, is equal to the maximum average inductor current plus one half of the ripple current. First, the current ripple

must be determined under the conditions that give maximum average inductor current:

V_INx D

Di_L=

f_SWx L

(16)

Maximum average inductor current occurs at V_IN(MIN). Using the selected inductance of 33 µH yields the

following:

Δi_L= (9 × 0.78) / (0.5 × 33) = 425 mA_P-P

(17)

(18)

The highest peak inductor current over all operating conditions is therefore:

I_PK= I_L+ 0.5 × Δi_L= 2.3 + 0.213 = 2.51 A

Hence an inductor must be selected that has a peak current rating greater than 2.5 A and an average current

rating greater than 2.3A. One possibility is an off-the-shelf 33 µH ±20% inductor that can handle a peak current

of 3.2 A and an average current of 3.4 A. Finally, the inductor current ripple is recalculated at the maximum input

voltage:

Δi_L-VIN(MAX)= (16 × 0.6) / (0.5 × 33) = 0.58A_P-P

(19)

8.2.2.5 Output Capacitor

The output capacitor in a boost regulator supplies current to the load during the MOSFET on-time and also filters

the AC portion of the load current during the off-time. This capacitor determines the steady state output voltage

ripple, ΔV_O, a critical parameter for all voltage regulators. Output capacitors are selected based on their

capacitance, C_O, their equivalent series resistance (ESR) and their RMS or AC current rating.

The magnitude of ΔV_Ois comprised of three parts, and in steady state the ripple voltage during the on-time is

equal to the ripple voltage during the off-time. For simplicity the analysis will be performed for the MOSFET

turning off (off-time) only. The first part of the ripple voltage is the surge created as the output diode D1 turns on.

At this point inductor/diode current is at the peak value, and the ripple voltage increase can be calculated as:

ΔV_O1= I_PK× ESR

(20)

The second portion of the ripple voltage is the increase due to the charging of C_Othrough the output diode. This

portion can be approximated as:

ΔV_O2= (I_O/ C_O) × (D / ƒ_SW

)

(21)

The final portion of the ripple voltage is a decrease due to the flow of the diode/inductor current through the

output capacitor’s ESR. This decrease can be calculated as:

ΔV_O3= Δi_L× ESR

(22)

The total change in output voltage is then:

ΔV_O= ΔV_O1+ ΔV_O2– ΔV_O3

(23)

The combination of two positive terms and one negative term may yield an output voltage ripple with a net rise or

a net fall during the converter off-time. The ESR of the output capacitor(s) has a strong influence on the slope

and direction of ΔV_O. Capacitors with high ESR such as tantalum and aluminum electrolytic create an output

voltage ripple that is dominated by ΔV_O1and ΔV_O3, with a shape shown in Figure 16. Ceramic capacitors, in

contrast, have very low ESR and lower capacitance. The shape of the output ripple voltage is dominated by

ΔV_O2, with a shape shown in Figure 17.

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V_O

Âv_O

I_D

Figure 16. ΔV_OUsing High ESR Capacitors

V_O

Âv_O

I_D

Figure 17. ΔV_OUsing Low ESR Capacitors

For this example the small size and high temperature rating of ceramic capacitors make them a good choice.

The output ripple voltage waveform of Figure 17 is assumed, and the capacitance will be selected first. The

desired ΔV_Ois ±2% of 40V, or 0.8V_P-P. Beginning with the calculation for ΔV_O2, the required minimum

capacitance is:

C_O-MIN= (I_O/ ΔV_O) x (D_MAX/ f_SW) C_O-MIN= (0.5 / 0.8) x (0.77 / 5 x 10⁵) = 0.96 µF

(24)

The next higher standard 20% capacitor value is 1 µF, however to provide margin for component tolerance and

load transients two capacitors rated 4.7 µF each will be used. Ceramic capacitors rated 4.7 µF ±20% are

available from many manufacturers. The minimum quality dielectric that is suitable for switching power supply

output capacitors is X5R, while X7R (or better) is preferred. Careful attention must be paid to the DC voltage

rating and case size, as ceramic capacitors can lose 60% or more of their rated capacitance at the maximum DC

voltage. This is the reason that ceramic capacitors are often de-rated to 50% of their capacitance at their working

voltage. The output capacitors for this example will have a 100V rating in a 2220 case size.

The typical ESR of the selected capacitors is 3 mΩ each, and in parallel is approximately 1.5 mΩ. The worst-

case value for ΔV_O1occurs during the peak current at minimum input voltage:

ΔV_O1= 2.5 × 0.0015 = 4 mV

(25)

The worst-case capacitor charging ripple occurs at maximum duty cycle:

ΔV_O2= (0.5 / 9.4 × 10^-6) x (0.77 / 5 × 10⁵) = 82 mV

(26)

Finally, the worst-case value for ΔV_O3occurs when inductor ripple current is highest, at maximum input voltage:

ΔV_O3= 0.58 × 0.0015 = 1 mV (negligible)

(27)

The output voltage ripple can be estimated by summing the three terms:

ΔV_O= 4 mV + 82 mV - 1 mV = 85 mV

(28)

19

The RMS current through the output capacitor(s) can be estimated using the following, worst-case equation:

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I_O-RMS= 1.13 x I_Lx

D x (1 - D)

(29)

The highest RMS current occurs at minimum input voltage. For this example the maximum output capacitor RMS

current is:

I_O-RMS(MAX)= 1.13 × 2.3 × (0.78 x 0.22)^0.5= 1.08 A_RMS

(30)

These 2220 case size devices are capable of sustaining RMS currents of over 3A each, making them more than

adequate for this application.

8.2.2.6 VCC Decoupling Capacitor

The VCC pin should be decoupled with a ceramic capacitor placed as close as possible to the VCC and GND

pins of the LM5022-Q1. The decoupling capacitor should have a minimum X5R or X7R type dielectric to ensure

that the capacitance remains stable over voltage and temperature, and be rated to a minimum of 470 nF. One

good choice is a 1-µF device with X7R dielectric and 1206 case size rated to 25 V.

8.2.2.7 Input Capacitor

The input capacitors to a boost regulator control the input voltage ripple, ΔV_IN, hold up the input voltage during

load transients, and prevent impedance mismatch (also called power supply interaction) between the LM5022-Q1

and the inductance of the input leads. Selection of input capacitors is based on their capacitance, ESR, and RMS

current rating. The minimum value of ESR can be selected based on the maximum output current transient,

I_STEP, using the following expression:

(1-D) x Dv_IN

ESR_MIN

=

2 x I_STEP

(31)

For this example the maximum load step is equal to the load current, or 0.5A. The maximum permissible ΔV_IN

during load transients is 4%_P-P. ΔV_INand duty cycle are taken at minimum input voltage to give the worst-case

value:

ESR_MIN= [(1 – 0.77) × 0.36] / (2 × 0.5) = 83 mΩ

(32)

The minimum input capacitance can be selected based on ΔV_IN, based on the drop in V_INduring a load transient,

or based on prevention of power supply interaction. In general, the requirement for greatest capacitance comes

from the power supply interaction. The inductance and resistance of the input source must be estimated, and if

this information is not available, they can be assumed to be 1 µH and 0.1 Ω, respectively. Minimum capacitance

is then estimated as:

2 x L_Sx V_Ox I_O

C_MIN

=

V_IN²x R_S

(33)

As with ESR, the worst-case, highest minimum capacitance calculation comes at the minimum input voltage.

Using the default estimates for L_Sand R_S, minimum capacitance is:

2 x 1m x 40 x 0.5

= 4.9 mF

C_MIN

=

9²x 0.1

(34)

The next highest standard 20% capacitor value is 6.8 µF, but because the actual input source impedance and

resistance are not known, two 4.7 µF capacitors will be used. In general, doubling the calculated value of input

capacitance provides a good safety margin. The final calculation is for the RMS current. For boost converters

operating in CCM this can be estimated as:

I_RMS= 0.29 × Δi_L(MAX)

(35)

From the inductor section, maximum inductor ripple current is 0.58 A, hence the input capacitor(s) must be rated

to handle 0.29 × 0.58 = 170 mA_RMS

.

The input capacitors can be ceramic, tantalum, aluminum, or almost any type, however the low capacitance

requirement makes ceramic capacitors particularly attractive. As with the output capacitors, the minimum quality

dielectric used should X5R, with X7R or better preferred. The voltage rating for input capacitors need not be as

conservative as the output capacitors, as the need for capacitance decreases as input voltage increases. For this

example, the capacitor selected will be 4.7 µF ±20%, rated to 50 V, in the 1812 case size. The RMS current

rating of these capacitors is over 2A each, more than enough for this application.

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8.2.2.8 Current Sense Filter

Parasitic circuit capacitance, inductance and gate drive current create a spike in the current sense voltage at the

point where Q1 turns on. In order to prevent this spike from terminating the on-time prematurely, every circuit

should have a low-pass filter that consists of C_CSand R_S1, shown in Figure 15. The time constant of this filter

should be long enough to reduce the parasitic spike without significantly affecting the shape of the actual current

sense voltage. The recommended range for R_S1is between 10 Ω and 500 Ω, and the recommended range for

C_CSis between 100 pF and 2.2 nF. For this example, the values of R_S1and C_CSwill be 100Ω and 1 nF,

respectively.

8.2.2.9 R_SNS, R_S2and Current Limit

The current sensing resistor R_SNSis used for steady state regulation of the inductor current and to sense

overcurrent conditions. The slope compensation resistor is used to ensure control loop stability, and both

resistors affect the current limit threshold. The R_SNSvalue selected must be low enough to keep the power

dissipation to a minimum, yet high enough to provide good signal-to-noise ratio for the current sensing circuitry.

R_SNS, and R_S2should be set so that the current limit comparator, with a threshold of 0.5 V, trips before the

sensed current exceeds the peak current rating of the inductor, without limiting the output power in steady state.

For this example the peak current, at V_IN(MIN), is 2.5 A, while the inductor itself is rated to 3.2 A. The threshold for

current limit, I_LIM, is set slightly between these two values to account for tolerance of the circuit components, at a

level of 3 A. The required resistor calculation must take into account both the switch current through R_SNSand

the compensation ramp current flowing through the internal 2 kΩ, R_S1and R_S2resistors. R_SNSshould be selected

first because it is a power resistor with more limited selection. The following equation should be evaluated at

V_IN(MIN), when duty cycle is highest:

L x f_SWx V_CL

R_SNS

=

(V_Oœ V_IN) x 3 x D + L x f_SWx I_LIM

(36)

33 x 0.5 x 0.5

R_SNS

=

= 0.068W

(40 - 9) x 3 x 0.78 + 33 x 0.5 x 3

where

•

L is in µH

f_SWin MHz

(37)

The closest 5% value is 100 mΩ. Power dissipation in R_SNScan be estimated by calculating the average current.

The worst-case average current through R_SNSoccurs at minimum input voltage/maximum duty cycle and can be

calculated as:

2

I_O

x R_{SNS x D}

P_CS

=

1-D

(38)

(39)

P_CS= [(0.5 / 0.22)²x 0.1] × 0.78 = 0.4W

For this example a 0.1 Ω ±1%, thick-film chip resistor in a 1210 case size rated to 0.5W will be used.

With R_SNSselected, R_S2can be determined using the following expression:

V_CL- I_ILIMx R_SNS

- 2000 - R_S1

R_S2

=

45m x D

(40)

(41)

0.5 - 3 x 0.1

45m x 0.78

- 2000 - 100 = 3598W

R_S2

=

The closest 1% tolerance value is 3.57 kΩ.

8.2.2.10 Control Loop Compensation

The LM5022-Q1 uses peak current-mode PWM control to correct changes in output voltage due to line and load

transients. Peak current-mode provides inherent cycle-by-cycle current limiting, improved line transient response,

and easier control loop compensation.

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The control loop is comprised of two parts. The first is the power stage, which consists of the pulse width

modulator, output filter, and the load. The second part is the error amplifier, which is an op-amp configured as an

inverting amplifier. Figure 18 shows the regulator control loop components.

L

+

C

O

D

V

IN

R

O

+

-

R

SNS

R

C

+

-

R

FB2

FB1

R1

C2

C1

-

+

-

V

REF

Figure 18. Power Stage and Error Amplifier

One popular method for selecting the compensation components is to create Bode plots of gain and phase for

the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the

regulator easy to determine. Software tools such as Excel, MathCAD, and Matlab are useful for observing how

changes in compensation or the power stage affect system gain and phase.

The power stage in a CCM peak current mode boost converter consists of the DC gain, A_PS, a single low

frequency pole, ƒ_LFP, the ESR zero, ƒ_ZESR, a right-half plane zero, ƒ_RHP, and a double pole resulting from the

sampling of the peak current. The power stage transfer function (also called the Control-to-Output transfer

function) can be written:

æ

ç

è

öæ

÷ç

øè

ö

÷

ø

s²

s

1+

1-

w_ZESR

w_RHP

G_PS= A_PS

´

æ

ö

÷

ø

æ

ç

è

ö

÷

ø

s

1+

ç1+

+

w²

ç

è

w_LEP

Q_n´ w_n

n

where

•

the DC gain is defined as:

(1 - D) x R_O

(42)

A_PS

=

2 x R_SNS

where

R_O= V_O/ I_O

(43)

(44)

The system ESR zero is:

1

w_ZESR

=

R_Cx C_O

(45)

The low frequency pole is:

1

w_LEP

=

0.5 x (R_O+ ESR) x C_O

(46)

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The right-half plane zero is:

2

V_IN

V_O

R_Ox

w_RHP

=

L

(47)

The sampling double pole quality factor is:

1

Q_n=

S_e

-D + 0.5 + (1 - D)

p

S_n

(48)

(49)

(50)

(51)

The sampling double corner frequency is:

ω_n= π × f_SW

The natural inductor current slope is:

S_n= R_SNS× V_IN/ L

The external ramp slope is:

S_e= 45 µA × (2000 + R_S1+ R_S2)] x ƒ_SW

In the equation for A_PS, DC gain is highest when input voltage and output current are at the maximum. In this the

example those conditions are V_IN= 16 V and I_O= 500 mA.

DC gain is 44 dB. The low frequency pole f_P= 2πω_Pis at 423 Hz, the ESR zero f_Z= 2πω_Zis at 5.6 MHz, and the

right-half plane zero ƒ_RHP= 2πω_RHPis at 61 kHz. The sampling double-pole occurs at one-half of the switching

frequency. Proper selection of slope compensation (via R_S2) is most evident the sampling double pole. A well-

selected R_S2value eliminates peaking in the gain and reduces the rate of change of the phase lag. Gain and

phase plots for the power stage are shown in Figure 19 and Figure 20.

60

45

30

15

0

180

120

60

0

-60

-120

-180

-15

-30

100

1k

10k

100k

1M

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 19. Power Stage Gain and Phase

Figure 20. Power Stage Gain and Phase

The single pole causes a roll-off in the gain of –20 dB/decade at lower frequency. The combination of the RHP

zero and sampling double pole maintain the slope out to beyond the switching frequency. The phase tends

towards –90° at lower frequency but then increases to –180° and beyond from the RHP zero and the sampling

double pole. The effect of the ESR zero is not seen because its frequency is several decades above the

switching frequency. The combination of increasing gain and decreasing phase makes converters with RHP

zeroes difficult to compensate. Setting the overall control loop bandwidth to 1/3 to 1/10 of the RHP zero

frequency minimizes these negative effects, but requires a compromise in the control loop bandwidth. If this loop

were left uncompensated, the bandwidth would be 89 kHz and the phase margin -54°. The converter would

oscillate, and therefore is compensated using the error amplifier and a few passive components.

The transfer function of the compensation block, G_EA, can be derived by treating the error amplifier as an

inverting op-amp with input impedance Z_Iand feedback impedance Z_F. The majority of applications will require a

Type II, or two-pole one-zero amplifier, shown in Figure 18. The LaPlace domain transfer function for this Type II

network is given by the following:

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Z_F

1

s x R1 x C2 +1

s x R1 x C1 x C2

C1 + C2

x

=

G_EA

=

Z_IR_FB2(C1 + C2)

s

+1

(52)

Many techniques exist for selecting the compensation component values. The following method is based upon

setting the mid-band gain of the error amplifier transfer function first and then positioning the compensation zero

and pole:

1. Determine the desired control loop bandwidth: The control loop bandwidth, ƒ_0dB, is the point at which the total

control loop gain (H = G_PS× G_EA) is equal to 0 dB. For this example, a low bandwidth of 10 kHz, or

approximately 1/6th of the RHP zero frequency, is chosen because of the wide variation in input voltage.

2. Determine the gain of the power stage at ƒ_0dB: This value, A, can be read graphically from the gain plot of

G_PSor calculated by replacing the ‘s’ terms in G_PSwith ‘2 πf_0dB’. For this example the gain at 10 kHz is

approximately 16 dB.

3. Calculate the negative of A and convert it to a linear gain: By setting the mid-band gain of the error amplifier

to the negative of the power stage gain at f_0dB, the control loop gain will equal 0 dB at that frequency. For this

example, –16 dB = 0.15V/V.

4. Select the resistance of the top feedback divider resistor R_FB2: This value is arbitrary, however selecting a

resistance between 10 kΩ and 100 kΩ will lead to practical values of R1, C1 and C2. For this example, R_FB2

= 20 kΩ 1%.

5. Set R1 = A × R_FB2: For this example: R1 = 0.15 × 20000 = 3 kΩ

6. Select a frequency for the compensation zero, ƒ_Z1: The suggested placement for this zero is at the low

frequency pole of the power stage, ƒ_LFP= ωLFP / 2π. For this example, ƒ_Z1= ƒ_LFP= 423 Hz

7. Set

1

:

C2 =

2p x R1 x f_Z1

For this example, C2 = 125 nF

8. Select a frequency for the compensation pole, ƒ_P1: The suggested placement for this pole is at one-fifth of

the switching frequency. For this example, ƒ_P1= 100 kHz

9. Set

C2

:

C1 =

2p x C2 x R1 x f_P1-1

For this example, C1 = 530 pF

10. Plug the closest 1% tolerance values for R_FB2and R1, then the closest 10% values for C1 and C2 into G_EA

and model the error amp: The open-loop gain and bandwidth of the LM5022-Q1’s internal error amplifier are

75 dB and 4 MHz, respectively. Their effect on G_EAcan be modeled using the following expression:

2p x GBW

OPG =

2p x GBW

s +

A_DC

A_DCis a linear gain, the linear equivalent of 75 dB is approximately 5600V/V. C1 = 560 pF 10%, C2 = 120 nF

10%, R1 = 3.01 kΩ 1%

11. Plot or evaluate the actual error amplifier transfer function:

G_EAx OPG

G_EA-ACTUAL

=

1 + G_EAx OPG

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60

40

20

0

-20

-40

-60

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 21. Overall Loop Gain and Phase

180

120

60

0

-60

-120

-180

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 22. Overall Loop Gain and Phase

12. Plot or evaluate the complete control loop transfer function: The complete control loop transfer function is

obtained by multiplying the power stage and error amplifier functions together. The bandwidth and phase

margin can then be read graphically or evaluated numerically. The bandwidth of this example circuit at V_IN

16 V is 10.5 kHz, with a phase margin of 66°.

=

13. Re-evaluate at the corners of input voltage and output current: Boost converters exhibit significant change in

their loop response when V_INand I_Ochange. With the compensation fixed, the total control loop gain and

phase should be checked to ensure a minimum phase margin of 45° over both line and load.

8.2.2.11 Efficiency Calculations

A reasonable estimation for the efficiency of a boost regulator controlled by the LM5022-Q1 can be obtained by

adding together the loss is each current carrying element and using the equation:

P_O

h =

P_O+ P_total-loss

(53)

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The following shows an efficiency calculation to complement the circuit design from Device Functional Modes.

Output power for this circuit is 40 V x 0.5 A = 20 W. Input voltage is assumed to be 13.8 V, and the calculations

used assume that the converter runs in CCM. Duty cycle for V_IN= 13.8V is 66%, and the average inductor

current is 1.5 A.

8.2.2.11.1 Chip Operating Loss

This term accounts for the current drawn at the VIN pin. This current, I_IN, drives the logic circuitry and the power

MOSFETs. The gate driving loss term from MOSFET is included in the chip operating loss. For the LM5022-Q1,

I_INis equal to the steady state operating current, I_CC, plus the MOSFET driving current, I_GC. Power is lost as this

current passes through the internal linear regulator of the LM5022-Q1.

I_GC= Q_G× ƒ_SWI_GC= 27 nC × 500 kHz = 13.5 mA

(54)

I_CCis typically 3.5 mA, taken from the Electrical Characteristics table. Chip Operating Loss is then:

P_Q= V_IN× (I_Q+ I_GC) P_Q= 13.8 × (3.5 m + 13.5m) = 235 mW

(55)

8.2.2.11.2 MOSFET Switching Loss

P_SW= 0.5 × V_IN× I_L× (t_R+ t_F) x f_SWP_SW= 0.5 × 13.8 × 1.5 × (10 ns + 12 ns) x 5 × 10⁵= 114 mW

(56)

(57)

8.2.2.11.3 MOSFET and R_SNSConduction Loss

P_C= D × (I_L²× (R_DSON× 1.3 + R_SNS)) P_C= 0.66 × (1.5²× (0.029 + 0.1)) = 192 mW

8.2.2.11.4 Output Diode Loss

The average output diode current is equal to I_O, or 0.5 A. The estimated forward drop, V_D, is 0.5 V. The output

diode loss is therefore:

P_D1= I_O× V_DP_D1= 0.5 × 0.5 = 0.25 W

(58)

8.2.2.11.5 Input Capacitor Loss

This term represents the loss as input ripple current passes through the ESR of the input capacitor bank. In this

equation ‘n’ is the number of capacitors in parallel. The 4.7 µF input capacitors selected have a combined ESR

of approximately 1.5 mΩ, and Δi_Lfor a 13.8V input is 0.55A:

I_IN-RMS²x ESR

P_CIN

=

n

(59)

(60)

I_IN-RMS= 0.29 x Δi_L= 0.29 × 0.55 = 0.16 A P_CIN= [0.16²× 0.0015] / 2 = 0.02 mW (negligible)

8.2.2.11.6 Output Capacitor Loss

This term is calculated using the same method as the input capacitor loss, substituting the output capacitor RMS

current for V_IN= 13.8 V. The output capacitors' combined ESR is also approximately 1.5 mΩ.

I_O-RMS= 1.13 × 1.5 × (0.66 x 0.34)^0.5= 0.8 A P_CO= [0.8 × 0.0015] / 2 = 0.6 mW

(61)

8.2.2.11.7 Boost Inductor Loss

The typical DCR of the selected inductor is 40 mΩ.

P_DCR= I_L²× DCR P_DCR= 1.5²× 0.04 = 90 mW

(62)

Core loss in the inductor is estimated to be equal to the DCR loss, adding an additional 90 mW to the total

inductor loss.

8.2.2.11.8 Total Loss

P_LOSS= Sum of All Loss Terms = 972 mW

(63)

(64)

8.2.2.11.9 Efficiency

η = 20 / (20 + 0.972) = 95%

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8.2.3 Application Curves

10V/DIV

V_O

SW

10V/DIV

1 és/DIV

VIN = 9-V

I_O= 0.5-A

Figure 24. SW Node Voltage

Figure 23. Efficiency vs. Load Current

10V/DIV

V_O

SW

50 mV/DIV

10V/DIV

1 és/DIV

VIN = 16-V

I_O= 0.5-A

Figure 25. SW Node Voltage

VIN = 9-V

I_O= 0.5-A

Figure 26. Output Voltage Ripple (AC Coupled)

200 mA/DIV

I_O

V_O

2V/DIV

50 mV/DIV

400 és/DIV

1 és/DIV

VIN = 16-V

I_O= 0.5-A

VIN = 9-V

I_O= 50mA -

500mA

Figure 27. Output Voltage Ripple (AC Coupled)

Figure 28. Load Transient Response

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200 mA/DIV

I_O

V_O

1V/DIV

1 ms/DIV

VIN = 16-V

I_O= 50mA - 500mA

Figure 29. Load Transient Response

9 Power Supply Recommendations

LM5022-Q1 is a power management device. The power supply for the device can be any DC voltage source

within the specified input range.

10 Layout

10.1 Layout Guidelines

To produce an optimal power solution with the LM5022-Q1, good layout and design of the PCB are as critical as

component selection. The following are the several guidelines in order to create a good layout of the PCB, as

based on Figure 15.

1. Using a low ESR ceramic capacitor, place C_INXas close as possible to the VIN and GND pins of the

LM5022-Q1.

2. Using a low ESR ceramic capacitor, place C_OXclose to the load as possible of the LM5022-Q1

3. Using a low ESR ceramic capacitor place C_Fclose to the VCC and GND pins of the LM5022-Q1

4. Minimize the loop area formed by the output capacitor connections (C_o1, C_o2), by D1 and R_sns. Making

sure the cathode of D1 and R_snsare position next to each other and place C_o1(+ )and C_o1( -) close to D1

cathode and R_sns(-) respectively.

5. R_sns(+) should be connected to the CS pin with a separate trace made as short as possible. This trace

should be routed away from the inductor and the switch node (where D1, Q1, and L1 connect).

6. Minimize the trace length to the FB pin by positioning R_FB1and R_FB2close to the LM5022-Q1

7. Route the VOUT sense path away from noisy node and connect it as close as possible to the positive

side of C_OX

.

10.1.1 Filter Capacitors

The low-value ceramic filter capacitors are most effective when the inductance of the current loops that they filter,

is minimized. Place C_INXas close as possible to the VIN and GND pins of the LM5022-Q1. Place C_OXclose to

the load, and C_Fnext to the VCC and GND pins of the LM5022-Q1.

10.1.2 Sense Lines

The top of R_SNSshould be connected to the CS pin with a separate trace, made as short as possible. Route this

trace away from the inductor and the switch node (where D1, Q1, and L1 connect). For the voltage loop, keep

R_FB1and R_FB2close to the LM5022-Q1 and run a trace, as close as possible, to the positive side of C_OXto R_FB2

.

As with the CS line, the FB line should be routed away from the inductor and the switch node. These measures

minimize the length of high impedance lines and reduce noise pickup.

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Layout Guidelines (continued)

10.1.3 Compact Layout

1. Parasitic inductance can be reduced by keeping the power path components close together. As described

above in point 4 in the Layout Guidelines, keep the high slew-rate current loops as tight as possible. Short,

thick traces or copper pours (shapes) are best

2. The switch node should be just large enough to connect all the components together without excessive

heating from the current it carries. The LM5022-Q1 (boost converter) operates in two distinct cycles whose

high current paths are shown in Figure 30:

+

-

Figure 30. Boost Converter Current Loops

The dark grey, inner loops represent the high current paths during the MOSFET on-time. The light grey, outer

loop represents the high current path during the off-time.

10.1.4 Ground Plane and Shape Routing

The diagram of Figure 30 is useful for analyzing the flow of continuous current vs. the flow of pulsating currents.

The circuit paths with current flow during both the on-time and off-time are considered to be continuous current,

while those that carry current during the on-time or off-time only are pulsating currents. Preference in routing

should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit EMI.

The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as any

other circuit path. The continuous current paths on the ground net can be routed on the system ground plane

with less risk of injecting noise into other circuits. The path between the input source, input capacitor and the

MOSFET and the path between the output capacitor and the load are examples of continuous current paths. In

contrast, the path between the grounded side of the power switch and the negative output capacitor terminal

carries a large high slew-rate pulsating current. This path should be routed with a short, thick shape, preferably

on the component side of the PCB. Too keep the parasitic inductance low, multiple vias in parallel should be

placed on the negative pads of the input and output capacitors to connect the component side to the ground

plane. Vias should not be placed directly at the grounded side of the MOSFET (or R_SNS) as they tend to inject

noise into the ground plane. A second pulsating current loop is the gate drive loop formed by the OUT and VCC

pins, Q1, R_SNSand capacitor C_F. These loops must be kept small.

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10.2 Layout Example

Figure 31. Typical Top Layer Overlay of the LM5022 Evaluation Board

Figure 32. Typical Bottom Layer Overlay of the LM5022 Evaluation Board

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11 器件和文档支持

11.1 器件支持

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 设计支持

WEBENCH

软件采用一种迭代设计过程并可访问综合元件数据库。欲了解更多信息，请访问

www.ti.com/webench。

11.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

31

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE OUTLINE

DGS0010A

VSSOP - 1.1 mm max height

S

C

A

L

E

3

.

2

0

SMALL OUTLINE PACKAGE

C

SEATING PLANE

0.1 C

5.05

4.75

TYP

PIN 1 ID

AREA

A

8X 0.5

10

1

3.1

2.9

NOTE 3

2X

2

5

6

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.1

C A

B

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

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EXAMPLE BOARD LAYOUT

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

(R0.05)

TYP

SYMM

10X (0.3)

1

5

10

SYMM

6

8X (0.5)

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

SYMM

(R0.05) TYP

10X (0.3)

8X (0.5)

1

5

10

SYMM

6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221984/A 05/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

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所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

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邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	LM5022QDGSRQ1
厂家：	TEXAS INSTRUMENTS
描述：	符合 AEC-Q100 标准的 6V 至 60V 宽输入电压、电流模式升压、SEPIC 和反激式控制器 \| DGS \| 10 \| -40 to 125 控制器
文件：	总38页 (文件大小：1345K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM5022QDGSRQ1 [TI]

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