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LM5026MT [TI]

具有 P 或 N 沟道钳位 FET 和 CS 重启计时器的 100V 有源钳位电流模式 PWM 控制器 | PW | 16 | -40 to 125;
LM5026MT
型号： LM5026MT
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有 P 或 N 沟道钳位 FET 和 CS 重启计时器的 100V 有源钳位电流模式 PWM 控制器 | PW | 16 | -40 to 125

控制器 开关 光电二极管
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LM5026  
SNVS363E –AUGUST 2005–REVISED NOVEMBER 2015  
LM5026 Active Clamp Current Mode PWM Controller  
1 Features  
3 Description  
The LM5026 PWM controller contains all of the  
1
•
•
•
•
•
Current-Mode Control  
features necessary to implement power converters  
utilizing the active clamp and reset technique with  
current-mode control. With the active clamp  
technique, higher efficiencies and greater power  
densities can be realized compared to conventional  
catch winding or RDC clamp and reset techniques.  
Two control outputs are provided, the main power  
switch control (OUT_A) and the active clamp switch  
control (OUT_B). The device can be configured to  
control either a P-Channel or N-Channel clamp  
switch. The main gate driver features a compound  
configuration, consisting of both MOS and Bipolar  
devices, providing superior gate drive characteristics.  
The LM5026 can be configured to operate with bias  
voltages over a wide input range of 8 V to 100 V.  
Additional features include programmable maximum  
duty cycle, line undervoltage lockout, cycle-by-cycle  
current limit, hiccup mode fault operation with  
adjustable timeout delay, PWM slope compensation,  
Internal 100-V Start-Up Bias Regulator  
3-A Compound Main Gate Driver  
High Bandwidth Optocoupler Interface  
Programmable Line Undervoltage Lockout (UVLO)  
With Adjustable Hysteresis  
•
•
Versatile Dual Mode Overcurrent Protection With  
Hiccup Delay Timer  
Programmable Overlap or Deadtime between the  
Main and Active Clamp Outputs  
•
•
•
•
•
•
Programmable Maximum Duty Cycle Clamp  
Programmable Soft-Start  
Leading Edge Blanking  
Resistor Programmed 1-MHz Capable Oscillator  
Oscillator Sync I/O Capability  
Precision 5-V Reference  
soft-start,  
1-MHz  
capable  
oscillator  
with  
synchronization input and output capability, precision  
reference, and thermal shutdown.  
2 Applications  
•
•
•
Server Power Supplies  
Device Information(1)  
48-V Telecom Power Supplies  
High Efficiency DC–DC Power Supplies  
PART NUMBER  
LM5026  
PACKAGE  
WSON (16)  
TSSOP (16)  
BODY SIZE (NOM)  
5.00 mm × 5.00 mm  
4.40 mm × 5.00 mm  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Typical Application Circuit  
V
IN  
36 - 78V  
V
OUT  
3.3V  
T1  
CS  
V
CC  
V
IN  
CS  
LM5026  
UVLO  
OUT_A  
OUT_B  
REF  
TIME  
RES  
RT  
ERROR  
AMP and  
ISOLATION  
COMP  
SYNC  
SS  
AGND  
DCL  
PGND  
SYNC I/O  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
LM5026  
SNVS363E –AUGUST 2005–REVISED NOVEMBER 2015  
www.ti.com  
Table of Contents  
7.3 Feature Description................................................. 12  
7.4 Device Functional Modes........................................ 19  
Application and Implementation ........................ 20  
8.1 Application Information............................................ 20  
8.2 Typical Application ................................................. 25  
Power Supply Recommendations...................... 29  
1
2
3
4
5
6
Features.................................................................. 1  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
6.1 Absolute Maximum Ratings ...................................... 4  
6.2 ESD Ratings.............................................................. 4  
6.3 Recommended Operating Conditions....................... 4  
6.4 Thermal Information.................................................. 5  
6.5 Electrical Characteristics........................................... 5  
6.6 Typical Characteristics.............................................. 8  
Detailed Description ............................................ 11  
7.1 Overview ................................................................. 11  
7.2 Functional Block Diagram ....................................... 11  
8
9
10 Layout................................................................... 29  
10.1 Layout Guidelines ................................................. 29  
10.2 Layout Example .................................................... 30  
11 Device and Documentation Support ................. 31  
11.1 Community Resources.......................................... 31  
11.2 Trademarks........................................................... 31  
11.3 Electrostatic Discharge Caution............................ 31  
11.4 Glossary................................................................ 31  
7
12 Mechanical, Packaging, and Orderable  
Information ........................................................... 31  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision D (April 2013) to Revision E  
Page  
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation  
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and  
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1  
Changes from Revision C (April 2013) to Revision D  
Page  
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 25  
2
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LM5026  
www.ti.com  
SNVS363E –AUGUST 2005–REVISED NOVEMBER 2015  
5 Pin Configuration and Functions  
PW Package  
16-Pin TSSOP  
Top View  
NHQ Package  
16-Pin WSON  
Top View  
VIN  
UVLO  
CS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
DCL  
VIN 1  
16  
DCL  
UVLO  
2
CS 3  
15 SYNC  
14 RT  
SYNC  
RT  
RES 4  
13 COMP  
EP  
SS  
12  
TIME  
5
RES  
COMP  
SS  
11 AGND  
10 PGND  
REF  
VCC  
6
7
TIME  
REF  
AGND  
PGND  
OUT_B  
OUT_B  
9
OUT_A 8  
VCC  
OUT_A  
Pin Functions  
PIN  
TYPE(1)  
DESCRIPTION  
NO.  
NAME  
Input voltage source. Input to the start-up regulator. Operating input range is 13 V to 100 V  
with transient capability to 105 V. For power sources outside of this range, the LM5026 can  
be biased directly at VCC by an external regulator.  
1
VIN  
UVLO  
CS  
I
Line undervoltage lockout. An external voltage divider from the power source sets the  
shutdown and standby comparator levels. When UVLO reaches the 0.4-V threshold the VCC  
and REF regulators are enabled. At the 1.25-V threshold the SS pin is released and the  
device enters the active mode.  
2
3
I
I
Current Sense input for current mode control and current limit. If CS exceeds 0.5 V, the  
output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds  
CS low for 100 nS after OUT_A switches high to blank leading edge transients.  
Restart Timer. If cycle-by-cycle current limit is reached during any cycle, a 10-µA current is  
sourced to the RES pin capacitor. If the RES capacitor voltage reaches 2.5 V, the soft-start  
capacitor will be fully discharged and then released with a pullup current of 1 µA. After the  
first output pulse at OUT_A (when SS = 1.4 V), the SS pin charging current will revert back  
to 50 µA.  
4
5
RES  
I
I
Gate drive overlap or deadtime control. An external resistor (RSET) sets either the overlap  
time or deadtime for the active clamp output. An RSET resistor connected between TIME  
and AGND produces in-phase OUT_A and OUT_B pulses with overlap. An RSET resistor  
connected between TIME and REF produces out-of-phase OUT_A and OUT_B pulses with  
deadtime.  
TIME  
Output of 5-V reference. Maximum output current is 10 mA. Locally decouple with a 0.1-µF  
capacitor.  
6
7
REF  
VCC  
O
P
Output of the high voltage start-up regulator. The VCC voltage is regulated to 7.6 V. If an  
auxiliary winding raises the voltage on this pin above the regulation setpoint, the internal  
start-up regulator will shutdown, thus reducing the IC power dissipation.  
Main output driver. Output of the main switch PWM gate driver. Capable of 3-A peak sink  
current.  
8
9
OUT_A  
OUT_B  
O
O
Active clamp output driver. Output of the active clamp switch gate driver. Capable of 0.5-A  
peak source and sink current.  
10  
11  
PGND  
AGND  
G
G
Power ground. Connect directly to analog cround.  
Analog return. Connect directly to power cround.  
Soft-start. An external capacitor and an internal 50-µA current source set the soft-start ramp.  
The SS current source is reduced to 1 µA following a restart event. The soft-stop discharge  
current is 50 µA.  
12  
SS  
I
Input to the pulse width modulator. The external optocoupler connected to the COMP pin  
sources current into an internal NPN current mirror. The PWM duty cycle is maximum with  
zero input current, while 1 mA reduces the duty cycle to zero. The current mirror improves  
the frequency response by reducing the ac voltage across the optocoupler detector.  
13  
COMP  
I
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output  
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SNVS363E –AUGUST 2005–REVISED NOVEMBER 2015  
www.ti.com  
Pin Functions (continued)  
PIN  
TYPE(1)  
DESCRIPTION  
NO.  
NAME  
Oscillator frequency control. Normally biased at 2 V. The total external resistance connected  
between RT and AGND sets the internal oscillator frequency.  
14  
RT  
I
I/O  
I
Oscillator synchronization input/output. The internal oscillator can be synchronized to an  
external clock with an external pulldown device. Multiple LM5026 devices can be  
synchronized together by connection of their SYNC pins.  
15  
16  
SYNC  
DCL  
Maximum duty cycle control. An external resistor divider connected from RT to AGND sets  
the maximum output duty cycle for OUT_A.  
Exposed Pad  
(WSON  
Package  
Only)  
Exposed Pad, underside of WSON package. Connect to system ground plane for reduced  
thermal resistance.  
EP  
G
6 Specifications  
6.1 Absolute Maximum Ratings  
(1)(2)  
See  
.
MIN  
–0.3  
–0.3  
–0.3  
MAX  
105  
16  
UNIT  
V
VIN to GND  
VCC to GND  
V
CS to GND  
1
V
COMP input current  
All other inputs to GND  
Junction temperature  
Storage temperature, Tstg  
10  
mA  
V
–0.3  
7
150  
150  
°C  
°C  
–65  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.  
6.2 ESD Ratings  
VALUE  
±2000  
±500  
UNIT  
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)  
Charged-device model (CDM), per JEDEC specification JESD22-C101(3)  
V(ESD)  
Electrostatic discharge  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with  
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.  
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.  
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
6.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
13  
MAX  
100  
15  
UNIT  
V
VIN voltage  
External voltage applied to VCC  
Operating junction temperature  
8
V
–40  
125  
°C  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.  
4
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LM5026  
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SNVS363E –AUGUST 2005–REVISED NOVEMBER 2015  
6.4 Thermal Information  
LM5026  
THERMAL METRIC(1)  
NHQ (WSON)  
PW (TSSOP)  
16 PINS  
98.6  
UNIT  
16 PINS  
29.9  
25.8  
9.2  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
27.6  
44.1  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
0.2  
1.2  
ψJB  
9.5  
43.3  
RθJC(bot)  
2.3  
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report, SPRA953.  
6.5 Electrical Characteristics  
Specification typical values are for TJ = 25°C unless otherwise noted. VIN = 48 V, VCC = 10 V, RT = 30.0 kΩ, Rset = 34.8 kΩ  
unless otherwise stated. Minimum and maximum specifications apply over full operating junction temperature range.(1)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
START-UP REGULATOR  
TJ = 25°C  
7.6  
VCC Reg  
VCC regulation  
No Load  
V
over full operating junction  
temperature range  
7.3  
20  
7.9  
TJ = 25°C  
25  
165  
350  
(2)  
VCC current limit  
Start-up regulator  
leakage (external VCC VIN = 100 V  
supply)  
See  
mA  
µA  
µA  
over full operating junction  
temperature range  
TJ = 25°C  
I-VIN  
over full operating junction  
temperature range  
500  
450  
TJ = 25°C  
Shutdown current (Iin) UVLO = 0 V  
over full operating junction  
temperature range  
VCC SUPPLY  
VCC Reg –  
120 mV  
TJ = 25°C  
VCC undervoltage  
lockout voltage  
(positive going Vcc  
V
VCC Reg – 220  
mV  
)
over full operating junction temperature range  
TJ = 25°C  
1.5  
VCC undervoltage  
hysteresis  
V
over full operating junction temperature range  
1
2
VCC supply current  
(ICC  
Cgate = 0, UVLO = 1.3 V, over full operating junction  
temperature range  
4.2  
mA  
)
REFERENCE SUPPLY  
TJ = 25°C  
5
25  
20  
Ref voltage  
IREF = 0 mA  
V
over full operating junction  
temperature range  
4.85  
5.15  
50  
TJ = 25°C  
VREF  
Ref voltage regulation IREF = 0 to 10 mA  
mV  
mA  
over full operating junction  
temperature range  
TJ = 25°C  
Ref current limit  
over full operating junction temperature range  
10  
UVLO SHUTDOWN/STANDBY  
TJ = 25°C  
0.4  
Undervoltage  
shutdown threshold  
V
over full operating junction temperature range  
0.3  
0.5  
(1) Minimum and maximum limits are 100% production tested at 25ºC. Limits over the operating temperature range are specified through  
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). All  
electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are  
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.  
(2) Device thermal limitations may limit usable range.  
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SNVS363E –AUGUST 2005–REVISED NOVEMBER 2015  
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Electrical Characteristics (continued)  
Specification typical values are for TJ = 25°C unless otherwise noted. VIN = 48 V, VCC = 10 V, RT = 30.0 kΩ, Rset = 34.8 kΩ  
unless otherwise stated. Minimum and maximum specifications apply over full operating junction temperature range.(1)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Undervoltage  
shutdown hysteresis  
0.1  
V
TJ = 25°C  
over full operating junction temperature range  
1.25  
Undervoltage standby  
threshold  
V
1.21  
16  
1.29  
24  
Undervoltage sandby TJ = 25°C  
hysteresis current  
20  
µA  
over full operating junction temperature range  
source  
CURRENT LIMIT  
TJ = 25°C  
0.5  
Cycle-by-cycle  
threshold voltage  
V
over full operating junction temperature range  
0.45  
70  
0.55  
CS step from 0 to 0.6 V Time to onset of OUT transition  
(90%) Cgate=0  
ILIM delay-to-output  
40  
ns  
ns  
TJ = 25°C  
100  
Leading edge  
blanking time  
over full operating junction temperature range  
TJ = 25°C  
130  
65  
30  
CS sink impedance  
(clocked)  
ICS = 10 mA  
Ω
over full operating junction  
temperature range  
OVERCURRENT RESTART  
TJ = 25°C  
2.55  
10  
Restart threshold  
V
over full operating junction temperature range  
TJ = 25°C  
2.4  
7.5  
7.5  
2.7  
12.5  
12.5  
Fault-charging current  
µA  
µA  
over full operating junction temperature range  
TJ = 25°C  
10  
Discharging current  
over full operating junction temperature range  
SOFT-START  
TJ = 25°C  
50  
50  
1
Soft-start current  
source  
over full operating junction temperature range  
TJ = 25°C  
38  
38  
58  
58  
Soft-stop current sink  
µA  
over full operating junction temperature range  
TJ = 25°C  
Soft-start current  
source following a  
restart event  
over full operating junction temperature range  
0.6  
1.3  
OSCILLATOR  
TJ = 25°C  
200  
590  
Frequency1  
RT = 30 kΩ  
kHz  
kHz  
over full operating junction  
temperature range  
180  
520  
220  
660  
TJ = 25°C  
Frequency2  
RT = 10 kΩ  
over full operating junction  
temperature range  
SYNC source current  
200  
100  
µA  
SYNC sink  
impedance  
Can sync up to 5 like controllers minimum  
Ω
Sync threshold  
(falling)  
1.4  
V
Sync pulse width  
minimum  
over full operating junction temperature range  
15  
ns  
PWM COMPARATOR  
Delay-to-output  
CS stepped, time to onset of OUT_A transition low  
40  
ns  
Mimimum duty cycle  
ICOMP = 1 mA, over full operating junction temperature range  
0%  
Maximum duty cycle  
limit 1  
UVLO = 1.3 V, COMP = open, VDCL = 2.5 V  
80%  
70%  
Maximum duty cycle  
limit 2  
UVLO = 1.3 V, COMP = open, VDCL = VRT × 0.875  
6
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SNVS363E –AUGUST 2005–REVISED NOVEMBER 2015  
Electrical Characteristics (continued)  
Specification typical values are for TJ = 25°C unless otherwise noted. VIN = 48 V, VCC = 10 V, RT = 30.0 kΩ, Rset = 34.8 kΩ  
unless otherwise stated. Minimum and maximum specifications apply over full operating junction temperature range.(1)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
40%  
1.4  
MAX  
UNIT  
Maximum duty cycle  
limit 3  
UVLO = 2.92 V, COMP = open, VDCL = 2.5 V  
SS to PWM offset  
V
COMP input  
impedance  
Small signal impedance  
1700  
90  
Ω
TJ = 25°C  
Slope compensation  
amplitude  
Delta increase at PWM  
comparator to CS  
mV  
over full operating junction  
temperature range  
75  
115  
10  
OUTPUT SECTION  
TJ = 25°C  
5
MOS Device at  
IOUT = –10 mA,  
OUT_A high  
saturation  
Ω
A
over full operating junction  
temperature range  
OUTPUT_A peak  
current sink  
Bipolar Device at VCC/2  
3
6
TJ = 25°C  
MOS Device at  
IOUT = 10 mA,  
OUT_A low saturation  
Ω
over full operating junction  
temperature range  
9
OUTPUT_A rise time Cgate = 2.2 nF  
20  
15  
10  
ns  
ns  
OUTPUT_A fall time  
Cgate = 2.2 nF  
TJ = 25°C  
OUT_B high  
saturation  
IOUT = –10 mA  
Ω
Ω
over full operating junction  
temperature range  
20  
20  
TJ = 25°C  
10  
OUT_B low saturation IOUT = 10 mA  
OUTPUT_B rise time Cgate = 470 pF  
over full operating junction  
temperature range  
15  
15  
ns  
ns  
OUTPUT_B fall time  
Cgate = 470 pF  
OUTPUT TIMING CONTROL  
TJ = 25°C  
100  
100  
RSET = 34.8 kΩ connected  
to GND, 50% to 50%  
transitions  
Overlap time  
ns  
ns  
over full operating junction  
temperature range  
70  
70  
130  
130  
TJ = 25°C  
RSET = 30 kΩ connected to  
REF, 50% to 50%  
transitions  
Deadtime  
over full operating junction  
temperature range  
THERMAL SHUTDOWN  
Thermal shutdown  
temp.  
TSD  
150  
165  
25  
°C  
°C  
Thermal shutdown  
hysteresis  
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6.6 Typical Characteristics  
16  
14  
10  
8
V
IN  
12  
10  
8
6
V
CC  
4
6
4
2
2
0
0
0
2
4
6
8
10 12 14 16  
0
5
10  
15  
20  
25  
30  
35  
V
(V)  
IN  
I
(mA)  
CC  
Figure 1. VCC Regulator Start-Up Characteristics, VCC vs VIN  
Figure 2. VCC vs ICC  
54  
52  
50  
48  
46  
44  
42  
40  
1.4  
6
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
5
SOFT-STOP  
SOFT-START  
4
3
2
RESTART  
1
0
0
5
10  
15  
20  
25  
-25  
0
25 50 75 100 125 150  
-50  
TEMPERATURE (oC)  
I
(mA)  
REF  
Figure 4. Soft-Start, Soft-Stop and Restart Current vs  
Temperature  
Figure 3. VREF vs IREF  
210  
208  
206  
204  
202  
200  
198  
196  
194  
192  
190  
-50  
0
50  
100  
150  
TEMPERATURE (oC)  
Figure 6. Oscillator Frequency vs Temperature  
Figure 5. Oscillator Frequency vs RT  
8
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Typical Characteristics (continued)  
120  
400  
115  
110  
105  
100  
95  
350  
RSET to AGND  
300  
250  
200  
150  
100  
50  
90  
R
= 34.8 kW  
SET  
85  
80  
0
-50 -25  
0
25 50 75 100 125 150  
0
20  
40  
80  
100 120  
60  
(kW)  
TEMPERATURE (oC)  
R
SET  
Figure 7. Overlap Time vs RSET  
Figure 8. Overlap Time vs Temperature  
120  
400  
115  
110  
105  
100  
95  
350  
300  
250  
200  
150  
100  
50  
RSET to REF  
90  
R
= 30.0 kW  
SET  
85  
80  
0
-50 -25  
0
25 50 75 100 125 150  
0
20  
40  
60  
80  
(kW)  
100 120  
TEMPERATURE (oC)  
R
SET  
Figure 9. Deadtime vs RSET  
Figure 10. Deadtime vs Temperature  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
DCL = 2.5V  
UVLO = 1.26V  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0  
Üë[h (ë)  
ꢀ/[ (ë)  
Figure 11. Max Duty Cycle vs UVLO  
Figure 12. Max Duty Cycle vs DCL  
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Typical Characteristics (continued)  
800  
-40°C  
25°C  
85°C  
700  
600  
500  
400  
125°C  
300  
-0.10 0.00 0.10 0.20 0.30 0.40 0.50  
INVERTING INPUT TO PWM COMPARATOR (V)  
Figure 13. COMP Current vs INV PWM Comparator Voltage  
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7 Detailed Description  
7.1 Overview  
The LM5026 PWM controller contains all of the features necessary to implement power converters utilizing the  
active clamp reset technique with current mode control. With the active clamp reset, higher efficiencies and  
greater power densities can be realized compared to conventional catch winding or RDC clamp reset techniques.  
The LM5026 provides two control outputs, the main power switch control (OUT_A) and the active clamp switch  
control (OUT_B). The device can be configured to drive either a P-Channel or N-Channel clamp switch. The  
main switch gate driver features a compound configuration consisting of both MOS and bipolar devices, which  
provide superior gate drive characteristics. The LM5026 can be configured to operate with bias voltages over a  
wide input range from 8 V to 100 V. Additional features include programmable maximum duty cycle, line  
undervoltage lockout, cycle-by-cycle current limit, hiccup mode fault protection with adjustable delays, PWM  
slope compensation, soft-start, a 1-MHz capable oscillator with synchronization input and output capability,  
precision reference, and thermal shutdown.  
7.2 Functional Block Diagram  
7.6V BIAS  
REGULATOR  
V
CC  
V
IN  
REF  
V
UVLO  
CC  
5V  
STANDBY  
REFERENCE  
UVLO  
1.25V  
LOGIC  
HYSTERESIS (20 mA)  
SHUTDOWN  
V
CC  
THERMAL  
LIMIT  
0.4V/0.3V  
OUT_A  
TIME  
DRIVER  
RT  
CLK  
OSCILLATOR  
AND  
DUTY CYCLE  
LIMITER  
SYNC  
DCL  
DEADTIME  
OR  
OVERLAP  
CONTROL  
S
R
Q
SLOPE COMP  
RAMP  
V
CC  
5V  
45 mA  
0
OUT_B  
PGND  
5k  
DRIVER  
COMP  
2R  
PWM  
1.4V  
R
1 : 1  
AGND  
SS  
CURRENT  
LIMIT  
5V  
2k  
CS  
CURRENT  
LIMITING  
(10 mA)  
0.5V  
OUT_A + LEB  
5V  
CURRENT LIMIT  
RESTART  
TIMER  
RES  
5V  
&
SS CONTROL  
RESTART  
DELAY  
(1 mA)  
SOFT-START  
(50 mA)  
NOT  
SS  
CURRENT  
LIMITING  
(10 mA)  
SS  
SOFT-STOP  
(50 mA)  
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7.3 Feature Description  
7.3.1 High Voltage Start-Up Regulator  
The LM5026 contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected  
directly to a nominal 48-V DC line voltage. The regulator output (VCC) is internally current limited to 20 mA.  
When power is applied and the UVLO pin potential is greater than 0.4 V, the regulator is enabled and sources  
current into an external capacitor connected to the VCC pin. The recommended capacitance range for the VCC  
regulator is 0.1 µF to 100 µF. The VCC regulator provides power to the internal voltage reference, PWM  
controller and gate drivers. The controller outputs are enabled when the voltage on the VCC pin reaches the  
regulation point of 7.6 V, the internal voltage reference (REF) reaches its regulation point of 5 V and the UVLO  
voltage is greater than 1.25 V. In typical applications, an auxiliary transformer winding is connected through a  
diode to the VCC pin. This winding must raise the VCC voltage above 8 V to shut off the internal start-up  
regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the controller’s power  
dissipation.  
The external VCC capacitor must be sized such that the current delivered from the capacitor and the VCC  
regulator will maintain a VCC voltage greater than 6.2 V during the initial start-up. During a fault mode when the  
converter auxiliary winding is inactive, external current draw on the VCC line should be limited such that the  
power dissipated in the start-up regulator does not exceed the maximum power dissipation of the IC package. An  
external start-up or bias regulator can be used to power the LM5026 instead of the internal start-up regulator by  
connecting the VCC and the VIN pins together and connecting an external bias supply to these two pins.  
7.3.2 Line Undervoltage Detector  
The LM5026 contains a dual level undervoltage lockout (UVLO) circuit. When the UVLO pin voltage is below 0.4  
V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.4 V but less  
than 1.25 V, the controller is in standby mode. In standby mode the VCC and REF bias regulators are active  
while the controller outputs are disabled. When the VCC and REF outputs exceed the VCC and REF  
undervoltage thresholds and the UVLO pin voltage is greater than 1.25 V, the outputs are enabled and normal  
operation begins. An external set-point voltage divider from VIN to GND can be used to set the operational range  
of the converter. The divider must be designed such that the voltage at the UVLO pin will be greater than 1.25 V  
when VIN is in the desired operating range. UVLO hysteresis is accomplished with an internal 20-µA current  
source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is  
exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin  
voltage falls below the 1.25-V threshold, the current source is turned off causing the voltage at the UVLO pin to  
fall. The hysteresis of the 0.4-V shutdown comparator is fixed at 100 mV.  
The UVLO pin can also be used to implement various remote enable and disable functions. Pulling the UVLO pin  
below the 0.4-V threshold totally disables the controller. Pulling the UVLO pin to a potential between 1.25 and 0.4  
V places the controller in standby with the VCC and REF regulators operating. Turning off a converter by forcing  
the UVLO pin to the standby condition provides a controlled soft-stop. The controller outputs are not directly  
disabled in standby mode, rather the soft-start capacitor is discharged with a 50-µA sink current. Discharging the  
soft-start capacitor gradually reduces the PWM duty cycle to zero, providing a slow controlled discharge of the  
power converter output filter. This controlled discharge can help prevent uncontrolled behavior of self-driven  
synchronous rectifiers during turnoff.  
7.3.3 PWM Outputs  
The relative phase of the main switch gate driver OUT_A and active clamp gate driver OUT_B can be configured  
for multiple applications. For active clamp configurations utilizing a ground referenced P-Channel clamp switch,  
the two outputs should be in phase, with the active clamp output overlapping the main output. For active clamp  
configurations utilizing a high-side N-Channel switch, the active clamp output should be out of phase with main  
output and there should be a dead time between the two gate drive pulses. A distinguishing feature of the  
LM5026 is the ability to accurately configure either deadtime (both off) or overlap time (both on) of the gate driver  
outputs. The overlap / deadtime magnitude is controlled by the resistor value (RSET) connected to the TIME pin  
of the controller. The opposite end of the resistor can be connected to either REF for deadtime control or to  
AGND for overlap control. The internal configuration detector senses the direction of current flow in the TIME pin  
resistor and configures the phase relationship of the main and active clamp outputs.  
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Feature Description (continued)  
OUT_A  
K1 * RSET  
K1 * RSET  
P-Channel Active Clamp  
(RSET to GND)  
OUT_B  
OUT_A  
N-Channel Active Clamp  
(RSET to REF)  
K2 * RSET  
OUT_B  
K2 * RSET  
Figure 14. PWM Output Phasing / Timing  
The rising edge overlap or deadtime and the falling edge overlap or deadtime are identical and are independent  
of operating frequency or duty cycle. The magnitude of the overlap/deadtime can be calculated in Equation 1 and  
Equation 2:  
Overlap Time = 2.8 × RSET + 2  
where  
•
•
RSET in kΩ  
overlap is in ns  
(1)  
.
Deadtime = 2.9 × RSET + 14  
where  
•
•
RSET in kΩ  
deadtime is in ns  
(2)  
7.3.4 Gate Driver Outputs  
The LM5026 provides two-gate driver outputs, the main power switch control (OUT_A) and the active clamp  
switch control (OUT_B). The main gate driver features a compound configuration, consisting of both MOS and  
bipolar devices, which provide superior gate drive characteristics. The bipolar device provides most of the drive  
current capability and sinks a relatively constant current, which is ideal for driving large-power MOSFETs. As the  
switching event nears conclusion and the bipolar device saturates, the internal MOS device provides a low  
impedance to compete the switching event.  
During turnoff at the Miller plateau region, typically between 2 V to 4 V, the voltage differential between the  
output and PGND is small and the current source characteristic of the bipolar device is beneficial to reduce the  
transition time. During turnon, the resistive characteristics of a purely MOS gate driver is adequate since the  
supply to output voltage differential is fairly large in the Miller region.  
V
CC  
LM5026  
PWM  
OUT_A  
PGND  
Figure 15. Compound Gate Driver  
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Feature Description (continued)  
7.3.5 PWM Comparator/Slope Compensation  
The PWM comparator modulates the pulse width of the controller output by comparing the current sense ramp  
signal to the loop error signal. This comparator is optimized for speed in order to achieve minimum controllable  
duty cycles. The loop error signal is input into the controller in the form of a control current into the COMP pin.  
The COMP pin control current is internally mirrored by a matched pair of NPN transistors which sink current  
through a 5-kΩ resistor connected to the 5-V reference. The resulting error signal passes through a 1.4-V level  
shift and a gain reducing 3:1 resistor divider before being applied to the pulse width modulator.  
The optocoupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is  
controlled by a current input, the potential difference across the optocoupler detector is nearly constant. The  
bandwidth limiting phase delay which is normally introduced by the significant capacitance of the optocoupler is  
greatly reduced. Greater system loop bandwidth can be realized, since the bandwidth-limiting pole associated  
with the optocoupler is now at a much higher frequency. The PWM comparator polarity is configured such that  
with no current into the COMP pin, the controller produces the maximum duty cycle at the main gate driver  
output.  
CURRENT SENSE RAMP  
REF  
5V  
+
5k  
_
1.4V  
COMP  
PWM  
COMPARATOR  
2R  
Potential across Opto-  
coupler detector is  
constant  
R
1 : 1  
LM431  
FB  
SOFT-START  
LM5026  
Figure 16. Optocoupler to LM5026 COMP Interface  
For duty cycles greater than 50 percent, current mode control circuits are subject to sub-harmonic oscillation. By  
adding an additional fixed slope voltage ramp signal (slope compensation) to the current sense signal, this  
oscillation can be avoided. The LM5026 integrates this slope compensation by summing a current ramp  
generated by the oscillator with the current sense signal. The PWM comparator ramp signal is a combination of  
the current waveform at the CS pin, and an internally generated slope compensation ramp derived from the  
oscillator. The internal ramp has an amplitude of 0 to 45 µA which is sourced into an internal 2-kΩ resistor, plus  
the external impedance at the CS pin. Additional slope compensation may be added by increasing the source  
impedance of the current sense signal.  
7.3.6 Maximum Duty Cycle Clamp  
Controlling the maximum duty cycle of an active clamp reset PWM controller is necessary to limit the voltage  
stress on the main and active clamp MOSFETs. The relationship between the maximum drain-source voltage of  
the MOSFETs and the maximum PWM duty cycle is provided by Equation 3:  
V
IN  
Vds(max) =  
1- D(max)  
(3)  
The main output (OUT_A) duty cycle is normally controlled by the control current sourced into the COMP pin  
from the external feedback circuit. When the feedback demands maximum output from the converter, the duty  
cycle will be limited by one of two circuits within the LM5026: the user programmable duty cycle clamp and the  
voltage-dependent duty cycle limiter, which varies inversely with the input line voltage.  
Programmable Duty Cycle Clamp – The maximum allowed duty cycle can be programmed by setting a voltage at  
the DCL pin to a value less than 2 V. The recommended method to set the DCL pin voltage is with a resistor  
divider connected from the RT pin to AGND. The voltage at the RT pin is internally regulated to 2 V, while the  
current sourced from the RT pin sets the oscillator frequency. The maximum duty can be programmed, according  
to Equation 4:  
RT 2  
Programmable Duty Cycle Clamp = 80% ´  
RT1+ RT 2  
(4)  
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Feature Description (continued)  
RT  
OSCILLATOR  
FREQUENCY  
INVERSELY  
PROPORTIONAL  
TO: RT1 + RT2  
RT1  
RT2  
DCL  
MAX DUTY CYCLE  
CLAMP SET TO:  
80%  
x
RT2  
RT1 + RT2  
LM5026  
AGND  
Figure 17. Programming Oscillator Frequency and Maximum Duty Cycle Clamp  
Line Voltage Duty Cycle Limiter - The maximum duty cycle for the main output driver is also limited by the  
voltage at the UVLO pin, which is normally proportional to VIN. The controller outputs are disabled until the  
UVLO pin voltage exceeds 1.25 V. At the minimum operating voltage (when UVLO = 1.25 V) the maximum duty  
cycle starts at the duty cycle clamp level programmed by the DCL pin voltage (80% or less). As the line voltage  
increases, the maximum duty cycle decreases linearly with increasing UVLO voltage, as shown in Figure 18.  
Ultimately the duty cycle of the main output is controlled to the least of the following three variables: the duty  
cycle controlled by the PWM comparator, the programmable maximum duty cycle clamp, or the line voltage  
dependent duty cycle limiter.  
100  
Programmable  
80  
60  
40  
20  
0
Duty Cycle Clamp  
Line Voltage  
Duty Cycle Limiter  
1.25V  
2.0  
0
1.0  
3.0  
4.0  
5.0  
UVLO PIN VOLTAGE (V)  
Figure 18. Maximum Duty Cycle vs UVLO Voltage  
7.3.7 Soft-Start / Soft-Stop  
The soft-start circuit allows the regulator to gradually reach a steady-state operating point, thereby reducing start-  
up stresses and current surges. Upon turnon, the SS pin capacitor is discharged by an internal switch. When the  
UVLO, VCC and REF pins reach their operating thresholds, the SS capacitor is released and charged with a 50-  
µA current source. The PWM comparator control voltage is clamped to the SS pin voltage. When the PWM input  
reaches 1.4 V, output pulses commence with slowly increasing duty cycle. The voltage at the SS pin eventually  
increases to 5 V, while the voltage at the PWM comparator increases to the value required for regulation  
determined by the voltage feedback loop.  
If the UVLO pin voltage falls below the 1.25-V standby threshold but above the 0.4-V shutdown threshold, the 50-  
µA SS pin source current is disabled and a 50-µA sink current discharges the soft-start capacitor. As the SS  
voltage falls and clamps the PWM comparator input, the PWM duty cycle will gradually fall to zero. This soft-stop  
feature produces a gradual reduction of the power converter output voltage. This gradual discharge of the output  
filter prevents oscillations in the self-driven synchronous rectifiers on the secondary side of the converter during  
turnoff.  
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Feature Description (continued)  
7.3.8 Current Sense and Current Limit  
The CS input provides a control ramp for the pulse width modulator and current limit detection for overload  
protection. If the sensed voltage at the CS comparator exceeds 0.5 V, the present cycle is terminated (cycle-by-  
cycle current limit mode).  
A small RC filter, located near the controller, is recommended for the CS input pin. An internal FET connected to  
the CS input discharges the current sense filter capacitor at the conclusion of every cycle to improve dynamic  
performance. This same FET remains on for an additional 100 nS at the start of each main switch cycle to  
attenuate the leading edge spike in the current sense signal.  
The CS comparator is very fast and may respond to short duration noise pulses. Layout considerations are  
critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be placed  
very close to the device and connected directly to the pins of the LM5026 (CS and AGND pins). If a current  
sense transformer is used, both leads of the transformer secondary should be routed to the filter network, which  
should be located close to the IC. If a sense resistor located in the source of the main switch MOSFET is used  
for current sensing, a low inductance type of resistor is required. When designing with a current sense resistor,  
all of the noise-sensitive, low-power ground connections should be connected together near the AGND pin and a  
single connection should be made to the power ground (sense resistor ground point).  
7.3.9 Overload Protection Timer  
The LM5026 provides a current limit restart timer to disable the outputs and force a delayed restart (hiccup  
mode) if a current limit condition is repeatedly sensed. The number of cycle-by-cycle current limit events required  
to trigger the restart is programmable by means of an external capacitor at the RES pin. During each PWM cycle  
the LM5026 either sources or sinks current from the RES pin capacitor. If no current limit is detected during a  
cycle, a 10-µA discharge current sink is enabled to hold the RES pin at ground. If a current limit is detected, the  
10-µA sink current is disabled and a 10-µA current source causes the voltage at RES pin to gradually increase.  
In the event of an extended overload condition, the LM5026 protects the converter with cycle-by-cycle current  
limiting while the voltage at RES pin increases. If the RES voltage reaches the 2.5-V threshold, the following  
restart sequence occurs (see Figure 19):  
•
•
•
The RES capacitor and SS capacitors are fully discharged.  
The soft-start current source is reduced from 50 µA to 1 µA  
The SS capacitor voltage slowly increases. When the SS voltage reaches 1.4 V, the PWM comparator will  
produce the first output pulse. After the first pulse occurs, the SS source current reverts to the normal 50 µA  
level. The SS voltage increases at its normal rate gradually increasing the duty cycle of the output drivers  
•
•
If the overload condition persists after restart, cycle-by-cycle current limiting will cause the voltage on the RES  
capacitor to increase again, repeating the hiccup mode sequence.  
If the overload condition no longer exists after restart, the RES pin will be held at ground by the 10-µA current  
sink and normal operation resumes.  
The overload timer function is very versatile and can be configured for the following modes of protection:  
1. Cycle-by-cycle only: The hiccup mode can be completely disabled by connecting the RES pin to AGND. In  
this configuration, the cycle-by-cycle protection will limit the output current indefinitely and no hiccup  
sequences will occur.  
2. Hiccup only: The timer can be configured for immediate activation of a hiccup sequence upon detection of  
an overload by leaving the RES pin open circuit.  
3. Delayed Hiccup: The most common configuration as previously described, is a programmed interval of  
cycle-by-cycle limiting before initiating a hiccup mode restart. The advantage of this configuration is short-  
term overload conditions will not cause a hiccup mode restart, however during extended overload conditions  
the average dissipation of the power converter will be very low.  
4. Externally Controlled Hiccup: The RES pin can also be used as an input. By externally driving the pin to a  
level greater than the 2.5-V hiccup threshold, the controller will be forced into the delayed restart sequence.  
If the RES pin is used as an input, the driving source should be current limited to less than 5 mA. For  
example, the external trigger for a delayed restart sequence could come an overtemperature protection  
circuit.  
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Feature Description (continued)  
2.5V  
Current Limit  
Detected  
RES  
0V  
5.0V  
50 mA  
@1.4V  
SS  
1 mA  
OUTA  
t1  
t2  
t3  
Figure 19. Hiccup Overload Restart Timing  
7.3.10 Oscillator and Sync Capability  
The LM5026 oscillator frequency is set by the external resistance connected between the RT pin and ground  
(AGND). To set a desired oscillator frequency (F) the necessary value of total RT resistance can be calculated  
from Equation 5:  
1
RT =  
F ´167´10-12  
(5)  
The RT resistor(s) should be located very close to the device and connected directly to the pins of the IC (RT and  
AGND).  
The SYNC pin can be used to synchronize the internal oscillator to an external clock. An open drain output is the  
recommended interface between the external clock to the LM5026 SYNC pin as illustrated in Figure 20. The  
clock pulse width must be greater than 15 ns. The external clock frequency must be a higher than the free  
running frequency set by the RT resistance.  
LM5026  
SYNC  
AGND  
Figure 20. Sync from External Clock  
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Feature Description (continued)  
LM5026  
SYNC  
LM5026  
SYNC  
UP TO 5 TOTAL  
DEVICES  
Figure 21. Sync from Multiple Devices  
Multiple LM5026 devices can be synchronized together simply by connecting the devices SYNC pins together as  
shown in Figure 21. Take care to ensure the ground potential differences between devices are minimized. In this  
configuration all of the devices will be synchronized to the highest frequency device. The internal block diagram  
of the oscillator and synchronization circuit is shown in Figure 22. The SYNC I/O pin is a CMOS buffer with  
pullup current limited to 200 µA. If an external device forces the SYNC pin low before the internal oscillator ramp  
completes its charging cycle, the ramp will be reset and another cycle begins. If the SYNC pins of multiple  
LM5026 devices are connected together, the first SYNC pin that pulls low will reset the oscillator RAMP of all  
other devices. All controllers will operate in phase when synchronized using the SYNC I/O feature. Up to five  
LM5026 devices can be synchronized using this technique.  
SYNC  
200m  
I = f (RT)  
2V  
Q
Q
S
R
CLK  
DEADTIME  
ONE-SHOT  
Figure 22. Oscillator Sync I/O Block Diagram  
7.3.11 Thermal Protection  
Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction  
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power standby  
state with the output drivers and the bias regulator disabled. The device will restart after the thermal hysteresis  
(typically 25°C). During thermal shutdown, the soft-start capacitor is fully discharged and the controller follows a  
normal start-up sequence after the junction temperature falls to the operating level.  
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7.4 Device Functional Modes  
The LM5026 has five functional modes. Figure 23 shows the mode transition diagram.  
•
•
•
•
•
UVLO mode  
Soft-start mode  
Normal operation mode  
Hiccup mode  
Thermal shutdown mode  
UVLO  
Soft Start  
Hiccup  
Normal Operation  
Thermal Shut Down  
Figure 23. Mode Transition Diagram  
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8 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
8.1 Application Information  
8.1.1 Line Input (VIN)  
The LM5026 contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected  
directly to a nominal 48-V line voltage. The voltage applied to the VIN pin can vary in the range of 13 to 100 V  
with transient capability to 105 V. When power is applied and the UVLO pin potential is greater than 0.4 V, the  
VCC regulator is enabled and sources current into an external capacitor connected to the VCC pin. When the  
voltage on the VCC pin reaches the regulation point of 7.7 V, the internal voltage reference (REF) is enabled.  
The reference regulation set-point is 5 V. The controller outputs are enabled when the UVLO pin potential is  
greater than 1.25 V. In typical applications, an auxiliary transformer winding is connected through a diode to the  
VCC pin. This winding must raise the VCC voltage above 8 V to shut off the internal start-up regulator. TI  
recommends a filtering circuit shown in Figure 24 be used to suppress transients, which may occur at the input  
supply, in particular when VIN is operated close to the maximum operating rating.  
V
PWR  
50  
V
IN  
0.1 mF  
LM5026  
Figure 24. Input Transient Protection  
8.1.2 For Application > 100 V  
For applications where the system input voltage exceed 100 V or IC power dissipation is a concern, the LM5026  
can be powered from an external start-up regulator as shown in Figure 25. In this configuration, the VIN and the  
VCC pins should be connected together, which allows the LM5026 to be operated below 13 V. The voltage at the  
VCC pin must be greater than 8 V yet not exceed 15 V. An auxiliary winding can be used to reduce the  
dissipation in the external regulator once the power converter is active.  
V
PWR  
8V - 15V (from  
aux winding)  
V
IN  
V
CC  
0.1  
9V  
C1  
LM5026  
Figure 25. Start-Up Regulator for VPWR >100 V  
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Application Information (continued)  
8.1.3 Undervoltage Lockout (UVLO)  
When the UVLO pin voltage is below 0.4 V, the controller is in a low current shutdown mode. When the UVLO  
pin voltage is greater than 0.4 V but less than 1.25 V, the controller is in standby mode. When the UVLO pin  
voltage is greater than 1.25 V, the controller is fully enabled. Typically, two external resistors program the  
minimum operational voltage for the power converter as shown in Figure 26. When UVLO pin voltage is above  
the 1.25-V threshold, an internal 20-μA current source is enabled to raise the voltage at the UVLO pin, thus  
providing threshold hysteresis. Resistance values for R1 and R2 can be determined from Equation 6 and  
Equation 7:  
V
HYS  
R1=  
20mA  
where  
•
VHYS is the desired UVLO hysteresis at VPWR  
(6)  
.
1.25´R1  
-1.25  
R2 =  
V
PWR  
where  
•
VPWR is the desired turnon voltage  
(7)  
For example, if the LM5026 is to be enabled when VPWR reaches 33 V, and disabled when VPWR is decreased to  
30 V, R1 calculates to 150 kΩ, and R2 calculates to 5.9 kΩ. The voltage at the UVLO pin should not exceed 6 V  
at any time. Be sure to check both the power and voltage rating for the selected R1 resistor.  
Remote configuration of the controller’s operational modes can be accomplished with open drain device(s)  
connected to the UVLO pin as shown in Figure 27.  
V
PWR  
LM5026  
20 mA  
R1  
UVLO  
Enable Output  
Drivers  
1.25V  
R2  
Enable V  
& V  
REF  
CC  
Regulators  
0.4V  
Figure 26. Basic UVLO Configuration  
V
PWR  
LM5026  
20 mA  
R1  
UVLO  
Enable  
1.25V  
OFF  
R2  
STANDBY  
Standby  
0.4V  
Figure 27. Remote Standby and Disable Control  
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Application Information (continued)  
8.1.4 Oscillator (RT, SYNC)  
Oscillator (RT, SYNC) The oscillator frequency is generally selected in conjunction with the design of the system  
magnetic components along with the volume and efficiency goals for a given power converter design. The total  
RT resistance at the RT pin sets the oscillator frequency. The RT resistors should be one of the first components  
placed and connected when designing the PCB. Direct, short connections to each side of the RT resistors (RT,  
DCL and AGND pins) are recommended .  
The SYNC pin can be used to synchronize the internal oscillator to an external clock. An open-drain output is the  
recommended interface from the external clock to the SYNC pin. The clock pulse width should be greater than  
15 ns. The external clock must be a higher frequency than the free-running frequency set by the RT resistor.  
Multiple LM5026 devices can be synchronized together simply by connecting the devices SYNC pins together.  
Take care to ensure the ground potential differences between devices are minimized. In this configuration all of  
the devices will be synchronized to the highest frequency device.  
8.1.5 Voltage Feedback (COMP)  
The COMP pin is designed to accept the voltage loop feedback error signal from the regulated output through an  
error amplifier and (typically) an optocoupler. In a typical configuration, VOUT is compared to a precision  
reference voltage by the error amplifier. The output of the amplifier drives the optocoupler, which in turn drives  
the COMP pin. The parasitic capacitance of the optocoupler often limits the achievable loop bandwidth for a  
given power converter. The optocoupler LED and detector junction capacitance produce a low-frequency pole in  
the voltage regulation loop. The LM5026 current controlled optocoupler interface (COMP) previously described,  
greatly increases the pole frequency associated with the optocoupler.  
8.1.6 Current Sense (CS)  
The CS pin receives an input signal representative of the transformer primary current, either from a current sense  
transformer (Figure 28) or from a resistor in series with the source of the primary switch (Figure 29). In both  
cases the sensed current creates a ramping voltage across R1, while the RF/CF filter suppresses noise and  
transients. R1, RF and CF should be as physically close to the LM5026 as possible, and the ground connection  
from the current sense transformer, or R1, should be a dedicated track to the AGND pin. The current-sense  
components must provide > 0.5 V at the CS pin when an overcurrent condition exists.  
Current  
Sense  
Power  
Transformer  
V
PWR  
V
IN  
R
F
CS  
LM5026  
R1  
C
F
AGND  
Q1  
Q2  
OUTA  
OUTB  
Figure 28. Current Sense Using a Current-Sense Transformer  
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Application Information (continued)  
Power  
Transformer  
V
PWR  
V
IN  
Q1  
Q2  
LM5026  
OUTA  
CS  
R
F
F
C
R1  
AGND  
OUTB  
Figure 29. Current Sense Using a Source-Sense Resistor (R1)  
8.1.7 Hiccup Mode Current Limit Restart (RES)  
The basic operation of the hiccup mode current limit restart is described in the functional description. The delay  
time to restart is programmed with the selection of the RES pin capacitor CRES as shown in Figure 19. In the  
case of continuous cycle-by-cycle current limit detection at the CS pin, the time required for CRES to reach the  
2.5-V hiccup mode threshold is calculated by Equation 8 :  
CRES ´ 2.5  
t1=  
= 2.5´105 ´CRES  
10mA  
(8)  
For example, if CRES = 0.01 µF, the time t1 is approximately 2.5 ms.  
The cool down time, t2 is set by the soft-start capacitor (CSS) and the internal 1-µA SS current source, and is  
equal to Equation 9:  
CSS ´1.4V  
t2 =  
= 1.4´106 ´CSS  
1 mA  
(9)  
If CSS = 0.01 µF, t2 is approximately 14 ms.  
The soft-start time t3 is set by the internal 50-µA current source, and is equal to Equation 10:  
CSS ´ 3.5V  
t3 =  
= 7´104 ´CSS  
50 mA  
(10)  
The time t2 provides a periodic cool-down time for the power converter in the event of a sustained overload or  
short circuit. This results in lower average input current and lower power dissipated within the power  
components. It is recommended that the ratio of t2/(t1 + t3) be in the range of 5 to 10 to make good use of this  
feature. If the application requires no delay from the first detection of a current limit condition to the onset of the  
hiccup mode (t1 = 0), the RES pin can be left open (no external capacitor). If it is desired to disable the hiccup  
mode current limit operation, the RES pin should be connected to ground (AGND).  
8.1.8 Soft-Start (SS)  
An internal current source and an external soft-start capacitor determines the time required for the output duty  
cycle to increase from zero to its final value for regulation. The minimum acceptable time is dependent on the  
output capacitance and the response of the feedback loop. If the soft-start time is too quick, the output could  
overshoot its intended voltage before the feedback loop can regulate the PWM controller. After power is applied  
and the controller is fully enabled, the voltage at the SS pin ramps up as CSS is charged by an internal 50-µA  
current source. The voltage at the output of the COMP pin current mirror is clamped to the same potential as the  
SS pin by a voltage buffer with a sink-only output stage. When the SS voltage reaches approximately 1.4 V,  
PWM pulses appear at the driver output with very low duty cycle. The PWM duty cycle gradually increases as the  
voltage at the SS pin charges to approximately 5.0 V.  
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Application Information (continued)  
8.1.9 Voltage-Dependent Maximum Duty Cycle  
As the input source VPWR increases the voltage at the UVLO pin increases proportionately. To limit the Volt ×  
Seconds applied to the transformer, the maximum allowed PWM duty cycle decreases as the UVLO voltage  
increases. If it is desired to increase the slope of the voltage limited duty cycle characteristic, two possible  
configurations are shown in Figure 30. After the LM5026 is enabled, the zener diode causes the UVLO pin  
voltage to increase more rapidly with increasing input voltage (VPWR). The voltage dependent maximum duty  
cycle clamp varies with the UVLO pin voltage according to Equation 11:  
Voltage-Dependent Duty Cycle (%) = 107 - 21.8 X UVLO  
(11)  
V
PWR  
R1A  
LM5026  
20 mA  
R1B  
UVLO  
Z1  
1.25V  
R2  
Max. Duty  
Cycle Limiter  
V
PWR  
Z1  
R1  
LM5026  
20 mA  
UVLO  
1.25V  
Max. Duty  
R2  
Cycle Limiter  
Figure 30. Altering the Slope of Duty Cycle vs VPWR  
8.1.9.1 Programmable Maximum Duty Cycle Clamp (DCL)  
When the UVLO pin is biased at 1.25 V (minimum operating level), the maximum duty cycle of OUT_A is limited  
by the duty cycle of the internal clock signal. The duty cycle of the internal clock can be adjusted by  
programming a voltage set at the DCL pin. The default maximum duty cycle (80%) can be selected by  
connecting the DCL pin to the RT pin. The DCL pin should not be left open. A small decoupling capacitor located  
close to the DCL pin is recommended.  
The oscillator frequency set resistance (RT) must be determined first before programming the maximum duty  
cycle. Following the selection of the total RT resistance, the ratio of the RT resistors can be designed to set the  
desired maximum duty cycle. As the UVLO pin voltage increases from 1.25 V, the maximum duty cycle is  
reduced by the voltage dependent duty cycle limiter previously as described and shown in Figure 18.  
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8.2 Typical Application  
The following schematic shows an example of an LM5026 controlled 100-W active clamp forward power  
converter. The input voltage range (VPWR) is 36 V to 78 V, and the output voltage is 3.3 V. The output current  
capability is 30 Amps. Current sense transformer T2 provides information to the CS pin for current mode control  
and current limit protection. The error amplifiers and reference U3 and U4 provide voltage feedback through  
optocoupler U2. Synchronous rectifiers Q3-Q6 minimize rectification losses in the secondary. An auxiliary  
winding on inductor L2 provides power to the LM5026 VCC pin when the output is in regulation. The input  
voltage UVLO levels are approximately 34 V for increasing VPWR, and ≈32 V for decreasing VPWR. The circuit can  
be shut down by forcing the ON/OFF input (J2) below 1.25 V. An external synchronizing frequency can be  
applied to the SYNC input (J11) or like converters can be self-synchronized by connections of (J3). The regulator  
output is current limited at approximately 32 A.  
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Figure 31. Application Circuit: Input 36 V to 78 V, Output 3.3 V, 30 A  
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8.2.1 Design Requirements  
The design requirements of this application are as follows:  
•
•
•
•
•
•
•
•
•
Input range: 36 V to 78 V  
Output voltage: 3.3 V  
Output current: 0 to 30 A  
Measured efficiency: 90% at 30 A, 92.5% at 15 A  
Frequency of operation: 230 kHz  
Board size: 2.3 × 2.4 × 0.5 inches  
Load Regulation: 1%  
Line Regulation: 0.1%  
Line UVLO, Hiccup Current Limit  
8.2.2 Detailed Design Procedure  
8.2.2.1 Determine VIN Configuration  
First, determine the input voltage range of the application. If the maximum input voltage is less than 100 V, use  
VIN pin connection in Figure 24. If the maximum input voltage exceeds 100 V, use the configuration shown in  
Figure 25.  
8.2.2.2 Determine UVLO Configuration  
As described in Undervoltage Lockout (UVLO), two external resistors program the minimum operational voltage  
for the power converter. Use Equation 6 and Equation 7 to calculate the resistor values. If remote standby and  
disable control is needed, use the configuration in Figure 27.  
8.2.2.3 Configure Operating Frequency  
If internal oscillator is used, use Equation 5 to determine the RT resistor value. If external clock is used, use the  
configuration in Figure 20.  
8.2.2.4 Configure Hiccup Mode and Soft Start  
The delay time to restart is programmed with the selection of the RES pin capacitor. Soft-start time is  
programmed by the capacitor on SS pin. Refer to Hiccup Mode Current Limit Restart (RES) and Equation 8,  
Equation 9, and Equation 10 to determine the capacitor values.  
8.2.2.5 Determine Deadtime and Maximum Duty Cycle  
The PWM output phasing the timing is shown in Figure 14. Use Equation 1 and Equation 2 to determine the  
deadtime programming resistor value. Maximum duty cycle clamp is determined by DCL pin voltage. Use  
Equation 4 and Figure 17 to determine RT1 and RT2 values.  
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8.2.3 Application Curves  
1
Input Voltage = 48VDC  
Input Voltage = 48VDC  
Output Current = 5 A to 25 A  
Trace 1: Output Voltage V/div = 0.5 V  
Trace 2: Output Current, A/div = 5 V  
Horizontal Resolution = 1 ms/div  
Output Current = 5 A  
Trace 1: Output Voltage V/div = 1 V  
Horizontal Resolution = 1 ms/div  
Figure 32. Output Voltage  
Figure 33. Transient Response  
1
1
Input Voltage = 48VDC  
Output Current = 30 A  
Input Voltage = 38VDC  
Bandwidth Limit = 25 MHz  
Trace 1: Output Voltage V/div = 50 mV  
Horizontal Resolution = 2 µs/div  
Output Current = 25 A  
Trace 1: Q1 Drain Voltage V/div = 20 V  
Horizontal Resolution = 1 µs/div  
Figure 34. Typical Output Ripple  
Figure 35. Drain Voltage of Q1  
1
2
1
Input Voltage = 48VDC  
Output Current = 5 A  
Synchronous Rectifier, Q3 Gate V/div = 5 V Trance 1  
Synchronous Rectifier, Q3 Gate V/div = 5 V Trance 2  
Synchronous Rectifier, Q5 Gate V/div = 5 V  
Horizontal Resolution = 1 µs/div  
Input Voltage = 78VDC  
Output Current = 25 A  
Trace 1: Q1 Drain Voltage V/div = 20 V  
Horizontal Resolution = 1 µs/div  
Figure 37. Gate Voltages  
Figure 36. Drain Voltage of Q1  
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9 Power Supply Recommendations  
VCC pin is the power supply for the device. There should be a 0.1-µF to 100-μF capacitor directly from VCC to  
ground. REF pin should be bypassed to ground as close as possible to the device using a 0.1-μF capacitor.  
10 Layout  
10.1 Layout Guidelines  
The LM5026 current-sense and PWM comparators are very fast, and respond to short duration noise pulses. The  
components at the CS, COMP, SS, DCL, UVLO, TIME, SYNC and the RT pins should be as physically close as  
possible to the IC, thereby minimizing noise pick-up on the PCB tracks.  
Layout considerations are critical for the current-sense filter. If a current-sense transformer is used, both leads of  
the transformer secondary should be routed to the sense filter components and to the IC pins. The ground side  
of each transformer should be connected through a dedicated PCB track to the AGND pin, rather than through  
the ground plane.  
If the current-sense circuit employs a sense resistor in the drive transistor source, low inductance resistor should  
be used. In this case, all the noise-sensitive, low-current ground tracks should be connected in common near the  
IC, and then a single connection made to the power ground (sense resistor ground point). The gate drive outputs  
of the LM5026 should have short direct paths to the power MOSFETs in order to minimize inductance in the PCB  
traces.  
The two ground pins (AGND, PGND) must be connected together with a short direct connection to avoid jitter  
due to relative ground bounce.  
If the internal dissipation of the LM5026 produces high junction temperatures during normal operation, the use of  
multiple vias under the IC to a ground place can help conduct heat away from the IC. Judicious positioning of the  
PCB within the end product, along with use of any available air flow (forced or natural convection) can help  
reduce the junction temperatures.  
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10.2 Layout Example  
REF decoupling  
capacitor  
Connect the exposed  
thermal pad to the  
system ground plane  
VCC decoupling  
capacitor  
Short AGND and PGND  
together as close as  
possible to the pins  
Figure 38. Layout Example  
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11 Device and Documentation Support  
11.1 Community Resources  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
11.2 Trademarks  
E2E is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
11.3 Electrostatic Discharge Caution  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
11.4 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
12 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
12-Jul-2022  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
LM5026MT  
NRND  
TSSOP  
TSSOP  
TSSOP  
PW  
16  
16  
16  
92  
Non-RoHS  
& Green  
Call TI  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
-40 to 125  
LM5026  
MT  
LM5026MT/NOPB  
LM5026MTX/NOPB  
ACTIVE  
ACTIVE  
PW  
92  
RoHS & Green  
NIPDAU | SN  
NIPDAU | SN  
LM5026  
MT  
Samples  
Samples  
PW  
2500 RoHS & Green  
LM5026  
MT  
LM5026SD/NOPB  
LM5026SDX/NOPB  
ACTIVE  
ACTIVE  
WSON  
WSON  
NHQ  
NHQ  
16  
16  
1000 RoHS & Green  
4500 RoHS & Green  
SN  
SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
5026SD  
Samples  
Samples  
5026SD  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
12-Jul-2022  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LM5026MTX/NOPB  
LM5026SD/NOPB  
LM5026SDX/NOPB  
TSSOP  
WSON  
WSON  
PW  
16  
16  
16  
2500  
1000  
4500  
330.0  
178.0  
330.0  
12.4  
12.4  
12.4  
6.95  
5.3  
5.6  
5.3  
5.3  
1.6  
1.3  
1.3  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
NHQ  
NHQ  
5.3  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LM5026MTX/NOPB  
LM5026SD/NOPB  
LM5026SDX/NOPB  
TSSOP  
WSON  
WSON  
PW  
16  
16  
16  
2500  
1000  
4500  
367.0  
208.0  
367.0  
367.0  
191.0  
367.0  
35.0  
35.0  
35.0  
NHQ  
NHQ  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2022  
TUBE  
*All dimensions are nominal  
Device  
Package Name Package Type  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
LM5026MT  
LM5026MT  
PW  
PW  
PW  
PW  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
16  
16  
16  
16  
92  
92  
92  
92  
495  
495  
530  
495  
8
8
2514.6  
2514.6  
3600  
4.06  
4.06  
3.5  
LM5026MT/NOPB  
LM5026MT/NOPB  
10.2  
8
2514.6  
4.06  
Pack Materials-Page 3  
PACKAGE OUTLINE  
PW0016A  
TSSOP - 1.2 mm max height  
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE  
SEATING  
PLANE  
C
6.6  
6.2  
TYP  
A
0.1 C  
PIN 1 INDEX AREA  
14X 0.65  
16  
1
2X  
5.1  
4.9  
4.55  
NOTE 3  
8
9
0.30  
16X  
4.5  
4.3  
NOTE 4  
1.2 MAX  
0.19  
B
0.1  
C A B  
(0.15) TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.15  
0.05  
0.75  
0.50  
A
20  
0 -8  
DETAIL A  
TYPICAL  
4220204/A 02/2017  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.  
5. Reference JEDEC registration MO-153.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
PW0016A  
TSSOP - 1.2 mm max height  
SMALL OUTLINE PACKAGE  
SYMM  
16X (1.5)  
(R0.05) TYP  
16  
1
16X (0.45)  
SYMM  
14X (0.65)  
8
9
(5.8)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE: 10X  
METAL UNDER  
SOLDER MASK  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.05 MAX  
ALL AROUND  
0.05 MIN  
ALL AROUND  
NON-SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
15.000  
(PREFERRED)  
SOLDER MASK DETAILS  
4220204/A 02/2017  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
PW0016A  
TSSOP - 1.2 mm max height  
SMALL OUTLINE PACKAGE  
16X (1.5)  
SYMM  
(R0.05) TYP  
16  
1
16X (0.45)  
SYMM  
14X (0.65)  
8
9
(5.8)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE: 10X  
4220204/A 02/2017  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
MECHANICAL DATA  
NHQ0016A  
SDA16A (Rev A)  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
resources.  
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for  
TI products.  
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2022, Texas Instruments Incorporated  

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