LM5036_技术文档

LM5036

ZHCSI27C –APRIL 2018 –REVISED OCTOBER 2021

具有集成辅助偏置电源的LM5036 半桥PWM 控制器

1 特性

3 说明

• 适用于小外形尺寸、高密度直流/直流电源转换器的

高集成度控制器

• 集成100V、100mA 辅助偏置电源

• 全稳压预偏置启动

• 适用于低侧和高侧初级FET 的具有脉冲匹配的增强

型逐周期电流限制

LM5036 PWM 控制器，集成了辅助偏置电源，可为工

业隔离式电源应用提供高功率密度。它包含使用带有输

入电压前馈的电压模式控制来实现半桥功率转换器所需

的所有功能。此控制器适合在直流输入电压高达 100V

的隔离式转换器的初级侧运行。此控制器包含的功能可

提高功率密度和可靠性，同时降低系统成本：

• 针对初级侧FET 优化了最大占空比

• 带有输入电压前馈的电压模式控制

• 100V 高压启动稳压器

• 可配置锁存器，支持OVP

• 用于初级侧FET 的集成式100V、2A MOSFET 驱

动器

• 作为辅助偏置电源的集成Fly-Buck 转换器。为一级

和二级电路提供偏置电源，具有极少的外部组件。

• 全稳压预偏置启动。即使启动到预充电输出电容器

时，也可消除输出电压过冲或突降。

• 具有脉冲匹配的增强型逐周期峰值电流限制。此控

制器可限制正负电流。脉冲匹配可确保低侧和高侧

器件具有相等的脉宽，以避免变压器饱和。输出电

流限制在整个输入电压范围内保持大致恒定。

• 初级侧和同步整流器(SR) FET 之间的死区时间可

编程

• 使用LM5036 并借助Excel 计算器工具或

WEBENCH^®Power Designer 创建定制设计方案

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

LM5036

2 应用

WQFN (28)

5.00mm × 5.00mm

• 电信和数据通信隔离式电源

• 工业电源和工厂自动化

• 测试和测量设备

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

13 VIN

BST_AUX 15

SW_AUX 14

V_IN

V_AUX2

28 UVLO

V_AUX1

VCC 17

24 RAMP

FB_AUX 12

BST 21

1

6

7

RES

VCC

V_IN

RON

SR1

ON_OFF

V_IN

V_O

HSG 22

8

SS

SW 23

LSG 18

11 RD2

RD1

10

2

SR2

V_CS+

V_CSœ

SGND

AGND

V_AUX2

16 PGND

REF

SR1 20

SR2 19

SR1

SR2

V_O

5

RT

Isolated

Driver

V_IN

V_FB

V_AUX2

REF

4

25 CS_POS

V_CS+

26 CS_NEG

27 CS_SET

V_CSœ

+

COMP

SSSR

3

9

V_REF

V_AUX2

TH

+

简化版应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSB14

LM5036

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ZHCSI27C –APRIL 2018 –REVISED OCTOBER 2021

Table of Contents

7.4 Device Functional Modes..........................................41

8 Application and Implementation..................................42

8.1 Application Information............................................. 42

8.2 Typical Application.................................................... 42

9 Power Supply Recommendations................................57

10 Layout...........................................................................58

10.1 Layout Guidelines................................................... 58

10.2 Layout Example...................................................... 58

11 Device and Documentation Support..........................60

11.1 Device Support........................................................60

11.2 Documentation Support.......................................... 60

11.3 支持资源..................................................................60

11.4 Trademarks............................................................. 60

11.5 Electrostatic Discharge Caution..............................60

11.6 术语表..................................................................... 60

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................7

6.5 Electrical Characteristics.............................................7

6.6 Switching Characteristics..........................................10

6.7 Typical Characteristics.............................................. 11

7 Detailed Description......................................................13

7.1 Overview...................................................................13

7.2 Functional Block Diagram.........................................14

7.3 Feature Description...................................................15

Information.................................................................... 61

4 Revision History

Changes from Revision B (April 2019) to Revision C (October 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Updated footnote to standard language............................................................................................................. 7

• Deleted minimum and maximum peak value of current source for slope compensation (I_SLOPE) specifications.

Updated typical from 54 µA to 36 µA. Removed table note (1) from this parameter.......................................... 7

• Changed typical peak current (I_{SO_PRI}) specification from 1.5 A to 1 A .............................................................7

• Changed minimum BST_AUX undervoltage threshold (V_{BST_AUX(UVLO)}) specification from 2.1 V to 3.5 V ......7

• Changed typical BST_AUX undervoltage threshold (V_{BST_AUX(UVLO)}) specification from 2.8 V to 5.0 V .......... 7

• Changed maximum BST_AUX undervoltage threshold (V_{BST_AUX(UVLO)}) specification from 3.6 V to 6.5 V .....7

• Changed typical peak current source value references from "1.5 A" to "1 A" in 节7.3.6 ................................ 17

Changes from Revision A (June 2018) to Revision B (April 2019)

Page

• Added minimum recommended values for RD₁and RD₂..................................................................................6

• Changed minimum recommended input voltage from 18V to 16V. ....................................................................6

• Added current limit parameters K_CBC1, V_CSOFFSETand I_BiasOffset.......................................................................7

• Changed typical value of I_SLOPEfrom 50-µA to 54-µA........................................................................................7

• Added parameter names for some items that had none: I_OVL, V_SSSecEn, V_SSREn, t_CSLSG, t_CSBLK, V_RESTh2

,

V_RESTh3V_RTReg, V_RTSync,I_COSsrEn, I_AUX(LIM)........................................................................................................ 7

• Changed parameter name V_RESto V_RESTh1...................................................................................................... 7

• Changed parameter name V_PWM-OSto I_PWM-OS.................................................................................................7

• Changed parameter V_{AUX_UVLO}maximum value from 16.6V to 16V. ................................................................ 7

• Changed parameter name HC_BLK_TH to V_{HC_BLK_TH}....................................................................................7

• Added new parameters AUX SUPPLY CURRENT LIMIT: t_CSBLKA, t_AUX(LIM), τ_AuxSns.......................................7

• Added new conditions in Switching Characteristics for t_ON............................................................................. 10

• Added Reference to the Calculator tool............................................................................................................13

• Changed Positive and negative current limit shown to be affected by LEB signal. ......................................... 14

• Added reference to operation from voltages above 100V. Values replaced with parameter names. ...............15

• Added reference to table of device functional modes.......................................................................................15

• Changed Parameter name V_REFto V_REFSecto avoid confusion with primary reference voltage......................16

2

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• Changed Implied minimum value of t_Dfrom 0-ns to 30-ns............................................................................... 18

• Added note that minimum value of RD1/RD2 resistors should not be less that 5-kΩ.....................................18

• Added pre-biased start-up process is handled automatically by LM5036 ....................................................... 21

• Changed values to parameter names. V_REFchanged to V_REFSec, TH changed to V_THSec.............................. 21

• Changed values to parameter names. I_COMPis graphed instead of V_COMP. ....................................................21

• Changed V_COMPto I_COMP. ................................................................................................................................21

• Changed and expanded Section: 'Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching'.............. 24

• Changed and expanded Section: 'Reverse Current Protection'. ..................................................................... 28

• Added Section: 'CBC Threshold Accuracy'.......................................................................................................29

• Changed values to parameter names. .............................................................................................................31

• Changed Section: 'ON_OFF Pin' to 'Over-Voltage / Latch (ON_OFF Pin)'. Values replaced by parameter

names. .............................................................................................................................................................33

• Changed Section: 'Constant On-Time Control' to 'Auxiliary Constant On-Time Control'.................................. 34

• Changed Section: 'On-Time Generator' to 'Auxiliary On-Time Generator'........................................................35

• Added method to calculate peak Auxiliary transformer current. External schottky recommended to improve

Auxiliary efficiency during ASYNCH mode. ..................................................................................................... 36

• Deleted Section: 'Ripple Configuration Types'..................................................................................................38

• Added Section: 'Auxiliary Ripple Configuration and Control'. .......................................................................... 39

• Changed values to parameter names. .............................................................................................................41

• Changed C26 from 330-pF to 47-pF, R29 from 165-kΩto 220-kΩ. Added D11............................................. 42

• Changed voltage targets for auxiliary output voltage from 12.6 V / 9 V to 11.9 V / 8.5 V. ............................... 43

• Added reference to Excel Calculator Tool. .......................................................................................................43

• Added restriction on use of TL431 to implement secondary side error amplifier..............................................44

• Added reference to Power Stage Designer Tool. .............................................................................................44

• Changed values to parameter names. R_UV1and_RUV2replace R₁and R₂. .......................................................45

• Changed Section: 'ON_OFF Pin Voltage Divider Selection' to 'Over Voltage / Latch (ON_OFF Pin) Voltage

Divider Selection'. ............................................................................................................................................ 46

• Added new Section: 'Half-Bridge Power Stage Design' ...................................................................................47

• Changed and expanded Section:'Current Limit' .............................................................................................. 48

• Changed calculation of Auxiliary transformer inductance. ...............................................................................53

• Changed calculated value for R_ONresistor. .....................................................................................................54

• Changed calculated value of Auxiliary primary output capacitor value. ...........................................................54

• Changed calculation of secondary output capacitor. Now uses ripple peak amplitude not peak-to-peak

amplitude. ........................................................................................................................................................ 54

• Changed calculation of Auxiliary Feedback component values. ......................................................................55

• Changed expression for I_COMPto fix error. .......................................................................................................55

• Changed layout diagram to include external schottky diode connected between PGND and SW_AUX pins. ....

58

Changes from Revision * (April 2018) to Revision A (June 2018)

Page

• 将销售状态从“预告信息”更改为“初始发行版”。.........................................................................................1

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ZHCSI27C –APRIL 2018 –REVISED OCTOBER 2021

5 Pin Configuration and Functions

28 27 26 25 24 23 22

RES

AGND

COMP

REF

BST

1

2

3

4

5

6

7

21

20

19

18

17

16

15

SR1

SR2

29

Thermal Pad

LSG

RT

VCC

RON

PGND

BST_AUX

ON_OFF

8

9

10 11 12 13 14

图5-1. RJB Package, 28-Pin WQFN (Top View)

表5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

AGND

BST

NO.

2

G

I

Analog ground

21

15

3

Half-bridge high-side gate drive bootstrap

Auxiliary supply high-side gate drive bootstrap

Control current input to half-bridge PWM comparator

Current sense amplifier negative input terminal

Current sense amplifier positive input terminal

Current limit setting

BST_AUX

COMP

CS_NEG

CS_POS

CS_SET

FB_AUX

HSG

I

26

25

27

12

22

18

7

I

Auxiliary supply output voltage feedback

Half-bridge high-side MOSFET output driver

Half-bridge low-side MOSFET output driver

Configurable for over voltage protection (OVP) or latch mode

Power ground

O

I

LSG

ON_OFF

PGND

RAMP

RD1

16

24

10

11

4

G

I

RAMP signal input to half-bridge PWM comparator

Synchronous rectifier trailing-edge delay

Synchronous rectifier leading-edge delay

5-V reference regulator output

I

RD2

I

REF

O

I

RES

1

Hiccup mode restart timer

RON

6

I

Auxiliary supply on-time control

RT/SYNC

SR1

5

I

Oscillator frequency control or external clock synchronization

Synchronous rectifier PWM control output

Soft-start input

20

19

8

O

I

SR2

SS

SSSR

9

I

Synchronous rectifier soft-start input

4

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表5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

SW

NO.

23

14

28

17

13

29

I

Half-bridge switch node

SW_AUX

UVLO

VCC

Auxiliary supply switch node

Input undervoltage lockout

Bias supply

I

VIN

I

Input voltage

Pad

G

Exposed thermal pad

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.3

-5

MAX

UNIT

V

VIN to GND

105

16

SW/SW_AUX to GND

V

BST TO SW, BST_AUX TO SW_AUX

-0.3

V

HSG to SW

16

V

LSG to GND

16

V

SR1/SR2 to GND

5

V

VCC to GND

16

V

RT, UVLO, ON/OFF, RON, RAMP, RES, FB_AUX, CS_POS, CS_NEG, CS_SET to GND

5

V

COMP to GND

-0.3

10

V

COMP Input Current

Junction Temperature

Storage Temperature, Tstg

mA

°C

150

-55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

±2000

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per JEDEC specificationJESD22-

C101, all pins⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

16

8.5

5

NOM

MAX

100

14

UNIT

V

V_IN

Input voltage

External V_CC

Supply Voltage

V

RD_x

T_J

RD₁, RD₂Resistor value

Junction Temperature

kΩ

°C

125

–40

6

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6.4 Thermal Information

LM5036

THERMAL METRIC ⁽¹⁾

RJB (WQFN)

28 PINS

29.9

UNIT

R_ΘJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_ΘJC(top)

R_ΘJB

18.2

Junction-to-board thermal resistance

10.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JT

10.3

Ψ_JB

R_ΘJC(bot)

1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

MIN and MAX limits apply the junction temperature range of –40°C ≤T_J≤125°C. Unless otherwise specified, the following

conditions apply: V_IN= 48 V, R_T= 25 kΩ, RD₁= RD₂= 20 kΩ, R_ON= 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5

V, ON_OFF = 0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

START-UP REGULATOR

V_CC

V_CCvoltage

I_CC= 10 mA

7.5

69

7.8

81

8.1

94

V

I_{CC (Lim)}

Vcc current limit

V_CC= 6 V, V_IN= 20 V

mA

Supply current into Vcc from an

externally applied source. V_CC= 9 V,

FB_AUX = 0 V

I_CC(ext)

Vcc supply current

6.6

9

11

mA

V_CC(reg)

V_CC(UV)

Vcc load regulation

I_CCfrom 0 to 50 mA

31

7.4

6.1

276

49

7.7

73

8.0

6.7

670

mV

V

Vcc undervoltage threshold

Positive going Vcc

Negative going Vcc

6.3

V

V_INshutdown current

580

µA

V_IN= 20 V, V_UVLO= 0 V, R_ON= 100 kΩ

V_IN= 100 V, V_UVLO= 0 V, R_ON= 100

kΩ

299

180

600

234

717

304

µA

V_CC= 9 V, applied externally, FB_AUX

> 2 V, SS = 0 V, R_ON= 100 kΩ

V_INstart-up regulator leakage

VOLTAGE REFERENCE REGULATOR (REF PIN)

V_REF

REF voltage

I_REF= 0 mA

4.85

24

5

37

5.15

57

V

mV

mA

V

V_REF(REG)

I_REF(LIM)

V_REF(UV)

REF load regulation

REF current limit

REF undervoltage threshold

Hysteresis

I_REF= 0 to 25 mA

V_REF= 4.5 V, V_IN= 20 V

Positive going V_REF

28

39

47

4.3

0.16

4.5

0.26

4.7

0.37

V

UNDERVOLTAGE LOCK OUT AND SHUTDOWN (UVLO PIN)

V_UVLO

I_UVLO

UVLO threshold

1.205

15

1.25

20

1.305

24

V

UVLO Hysteresis current

µA

Internal startup regulator enable

threshold

V_SD

SS = 0 V, FB_AUX = 2.5 V

0.34

90

0.38

135

0.41

175

V

Hysteresis

mV

OVER-VOLTAGE/LATCH (ON_OFF PIN)

V_{ON_OFF}

I_OVL

ON_OFF threshold

1.18

40

1.25

50

1.32

60

V

ON_OFF hysteresis current

µA

SOFT-START (SS PIN, SSSR PIN)

I_SSSS charge current

SS = 0 V

17

20

24

µA

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ZHCSI27C –APRIL 2018 –REVISED OCTOBER 2021

MIN and MAX limits apply the junction temperature range of –40°C ≤T_J≤125°C. Unless otherwise specified, the following

conditions apply: V_IN= 48 V, R_T= 25 kΩ, RD₁= RD₂= 20 kΩ, R_ON= 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5

V, ON_OFF = 0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SS threshold to enable SSSR

charge current

V_SSSecEn

I_COMP< 800 µA

1.93

2.06

2.2

V

SS output low voltage

Sinking 100 µA

30

865

17

48

1000

20

57

1198

24

mV

µA

SS threshold to disable switching

SSSR charge current

I_SSSR

SS > 2 V, I_COMP< 800 µA

Sinking 100 µA

SSSR output low voltage

30

38.7

49

mV

SSSR threshold to enable SR

freewheeling pulse

V_SSREn

0.65

1.17

1.67

V

CURRENT SENSE (CS_POS, CS_NEG, and CS_SET PIN)

V_LIM

Current limit setting voltage

0.72

0.3

0.75

0.58

0.77

0.9

V

Ratio of internal negative to

positive current limit threshold

t_CSLSG

t_CSBLK

K_CBC1

CS to gate driver output delay

CS leading-edge blanking

60

33

85

53

122

76

ns

V

(1)

V_LIMx (K_2aX K_10b- K_10a

V_{CS_POS}- V_{CS_NEG}

I_BiasPOS- I_BiasNEG

)

At CBC trip threshold

7.28

-0.63

-0.67

7.51

-0.02

0.02

7.81

0.32

0.29

(1)

V_CSOffset

I_BiasOffset

mV

µA

Peak value of current source for

slope compensation

I_SLOPE

36

µA

REVERSE CURRENT PROTECTION

Number of switching periods to

N

reset negative over-current event

counter

4

SSSR threshold to reset SSSR

cap clamp event counter

SR_CTR_TH

4.8

4.94

5.1

V

HICCUP MODE (RES PIN)

R_RES

RES pulldown resistance

Termination of hiccup timer

24

0.90

3.91

1.95

12

36

1

55

1.04

4.07

2.04

18

Ω

V

V_RESTh1

V_RESTh3

V_RESTh2

I_RES-SRC1

I_RES-SRC2

I_RES-DIS1

I_RES-DIS2

RES hiccup threshold

RES upper counter threshold

RES lower counter threshold

Charge current source1

Charge current source2

Discharge current source1

Discharge current source2

4

V

2

V

V_RES< 1 V, CBC active

1 V < V_RES< 4 V

CBC not active

15

30

5

µA

25

36

3.2

5.5

2 V < V_RES< 4 V

2.5

5

7.5

HICCUP MODE BLANKING

SSSR threshold to disable the

hiccup blanking

V_{HC_BLK_TH}

5.26

3.9

5.5

6.0

5.66

9.1

V

VOLTAGE FEED-FORWARD (RAMP PIN)

RAMP sink impednace (clocked)

OSCILLATOR (RT PIN)

Ω

Frequency (half oscillator

frequency)

f_SW1

185

420

200

480

215

540

kHz

R_T= 25 kΩ

R_T= 10 kΩ

Frequency (half oscillator

frequency)

f_SW2

V_RTReg

V_RTSync

DC level

1.85

2.8

2

3

2.06

3.3

V

RT sync threshold

SYNCHRONOUS RECTIFIER TIMING CONTROL (RD1 and RD2 PINS)

8

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MIN and MAX limits apply the junction temperature range of –40°C ≤T_J≤125°C. Unless otherwise specified, the following

conditions apply: V_IN= 48 V, R_T= 25 kΩ, RD₁= RD₂= 20 kΩ, R_ON= 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5

V, ON_OFF = 0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

123

278

79

MAX

157

350

102

UNIT

SR trailing edge delay SR turn-off

to primary switch turn-on

t₁

94

ns

RD₁= 20 kΩ

213

60

ns

RD₁= 100 kΩ

RD₂= 20 kΩ

RD₂= 100 kΩ

SR leading edge delay primary

switch turn-off to SR turn-on

t₂

ns

188

47

250

65

315

87

ns

t_clk

Pulse width of the clock

COMP PIN

I_PWM-OS

V_SS-OS

COMP current to RAMP offset

SS to RAMP offset

RAMP = 0 V

596

0.86

800

1

1063

1.15

2936

0.74

µA

V

RAMP = 0 V

COMP current to RAMP gain

SS to RAMP gain

delta RAMP/delta I_COMP

delta SS/delta RAMP

1895

0.574

2400

0.646

Ω

COMP current for SSSR charge

curent enable

I_COSsrEn

SS > 2 V

600

100

750

120

900

µA

COMP to gate driver output delay

Minimum duty cycle

150

0

ns

%

I_COMP= 1 mA

BOOST (BST PIN)

V_BST(UV)BST under-voltage threshold

Hysteresis

LSG, HSG GATE DRIVERS

V_{OL_PRI}Low-state output voltage

V_BST- V_SWrising

3.2

4.137

0.481

5.6

V

0.37

0.65

I_HSG/LSG= 100 mA

0.1

0

0.3

0.41

1

V

I_HSG/LSG= 100 mA, V_{OHL_PRI}= V_CC

V_LSG, V_{OHH_PRI}= V_BST- V_HSG

-

V_{OH_PRI}

High-state output voltage

0.38

Rise Time

C-load =1000 pF

V_HSG/LSG= 0V

2

8

10

1

12

14

ns

A

Fall Time

I_{SO_PRI}

I_{SI_PRI}

Peak Source Current

Peak Sink Current

V_HSG/LSG= VCC

2

A

SR1, SR2 GATE DRIVERS

V_{OL_SR}Low-state output voltage

V_{OH_SR}

I_SR1/SR2= 10 mA

0.12

0.313

65

V

High-state output voltage

Rise Time

I_SR1/SR2= 10 mA, V_{OH_SR}= V_REF- V_SR

C-load = 1000 pF

V_SR= 0 V

25

4

45

10

ns

A

Fall Time

16

I_{SO_SR}

I_{SI_SR}

Peak Source Current

Peak Sink Current

0.05

0.1

0.09

0.2

0.14

0.4

V_SR= V_REF

A

HALF BRIDGE THERMAL SHUTDOWN

T_SD

Thermal Shutdown Temp

150

25

°C

Thermal Shutdown Hysteresis

AUX SUPPLY SWITCH CHARACTERISTICS

Buck Switch R_DS(ON)

I_TEST= 60 mA

3.0

1.2

5.2

2.8

7.5

4.5

Ω

Synchronous Switch R_DS(ON)

AUX SUPPLY UNDERVOLTAGE LOCKOUT

V_{BST_AUX(UV)}

V_{AUX_UVLO}

BST_AUX undervoltage threshold V_{BST_AUX}- V_{SW_AUX}rising

3.5

5.0

15

6.5

V

AUX supply UVLO input voltage

rising threshold

12.2

16.0

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MIN and MAX limits apply the junction temperature range of –40°C ≤T_J≤125°C. Unless otherwise specified, the following

conditions apply: V_IN= 48 V, R_T= 25 kΩ, RD₁= RD₂= 20 kΩ, R_ON= 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5

V, ON_OFF = 0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AUX supply UVLO input voltage

falling threshold

7.9

11.2

12.7

V

AUX SUPPLY REGULATION

OFF-State AUX Voltage

Regulation Level

V_AUX-OFF

V_AUX-ON

1.26

0.95

1.4

1

1.53

1.04

V

ON-State AUX Voltage

Regulation Level

AUX SUPPLY CURRENT LIMIT

AUX Supply Current Limit

I_AUX(LIM)

150

200

50

250

mA

ns

Threshold

Current limit comparator blanking

period measured from start of t_ON

period ⁽¹⁾

t_CSBLKA

Delay from Comparator

Threshold to upper MOSFET

turn-OFF ⁽¹⁾

t_AUX(LIM)

116

41

ns

Aux Current Limit Parasitic Filter

time constant ⁽¹⁾

τ_AuxSns

AUX SUPPLY THERMAL SHUTDOWN

AUX Supply Thermal Shutdown

T_{SD_AUX}

160

28

°C

Temp

AUX Supply Thermal Shutdown

Hysteresis

(1) Specified by design. Not production tested.

6.6 Switching Characteristics

MIN and MAX limits apply the junction temperature range –40°C ≤T_J≤125°C. Unless otherwise specified, the following

conditions apply: V_IN= 48 V, R_T= 25 kΩ, RD₁= RD₂= 20 kΩ, R_ON=100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5

V, ON_OFF = 0 V.

PARAMETER

TEST CONDITIONS

V_IN= 32 V, R_ON= 100 kΩ

V_IN=54 V, R_ON= 250 kΩ

V_IN=75V, R_ON= 250 kΩ

MIN

TYP

330

493

370

MAX

UNIT

t_ON

AUX SUPPLY ON-TIME

AUX SUPPLY ON-TIME⁽¹⁾

240

440

ns

AUX SUPPLY MINIMUM OFF-

TIME

t_OFF(MIN)

FB_AUX = 0 V

69

103

136

ns

(1) Specified by design. Not production tested.

10

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6.7 Typical Characteristics

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

8

7.5

7

6.5

6

5.5

5

4.5

4

3.5

3

2.5

2

V_IN= 36 V

V_IN= 48 V

V_IN= 75 V

1.5

1

0.5

0

1

2

3

4

5

Load Current (A)

6

7

8

0

10

20

30

40

50

60

VCC Supply Current (mV)

70

80

90 100

D001

D002

f_SW= 200 kHz

V_O= 12 V

图6-2. VCC Load Regulation

图6-1. Application Board Efficiency vs Load

Current

325

300

275

250

225

200

175

150

125

100

75

8

7

6

5

4

3

2

1

0

50

25

VCC

REF

0

9

19

29

39

49 59

Input Voltage (V)

69

79

89

99

2

4

6

8

10 12

Input Voltage (V)

14

16

18

20

D003

D004

图6-3. Input Leakage Current of Start-up Regulator

图6-4. VCC and REF Voltage vs Input Voltage

vs Input Voltage

2100

1800

1500

1200

900

600

300

0

300

275

250

225

R_D1= 20 kW, T₁

R_D1= 100 kW, T₁

R_D2= 20 kW, T₂

R_D2= 100 kW, T₂

200

175

150

125

100

75

50

0

5

10

15

20

25

30

35

40

45

50

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

R_TTiming Resistance (kW)

D001

D006

图6-5. Oscillator Frequency vs R_TTiming

图6-6. Dead Time vs Temperature

Resistance

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300

275

250

225

200

175

150

125

100

75

775

770

765

760

755

750

745

740

735

730

725

50

T₁

T₂

25

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

0

10

20

30

40

50

60

70

80

90 100

RD₁= RD₂Dead-Time Programming Resistance (kW)

D001

D007

图6-8. CS_SET Pin Voltage vs Temperature

图6-7. Dead Time vs Programming Resistance

1000

210

205

200

195

190

185

180

900

800

700

600

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

D009

D010

图6-9. COMP Pin to 1-V RAMP Offset vs

图6-10. Auxiliary Supply Current Limit vs

Temperature

5.5

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

5

10

15

20

25

30

REF Current (mA)

35

40

45

50

D011

图6-11. REF Load Regulation

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7 Detailed Description

7.1 Overview

The LM5036 device is a highly-integrated, half-bridge PWM controller with integrated auxiliary bias supply. It

provides a high power-density solution for telecom, datacom and industrial power converters. The device has all

of the features necessary to implement a power converter that uses half-bridge topology. The device employs

voltage-mode control and includes input voltage feed-forward to improve performance. This device operates on

the primary side of an isolated DC-DC power converter with input voltage up to 100-V.

The soft-start function provides a fully regulated and monotonic rise of output voltage, even when the converter

energizes into a pre-biased load. The device uses an enhanced cycle-by-cycle (CBC) current limit. This function

matches the pulse to maintain the voltage balance of the half-bridge capacitor divider. This method ensures flux

balance of the transformer during CBC operation. The input voltage compensation function helps to minimize the

variation of the current limit level across the entire input voltage range.

The LM5036 device has these other features:

• configurable latch protection

• configurable overvoltage protection (OVP)

• optimized maximum duty cycle operation for the primary MOSFETs

• integrated half-bridge MOSFET gate drivers

• programmable dead-time between the primary MOSFETs and synchronous rectifiers

• auxiliary supply synchronous and asynchronous mode transition

• 5-V synchronous rectifier PWM outputs

• programmable line undervoltage lockout (UVLO)

• hiccup mode overcurrent protection (OCP)

• reverse current protection

• a 2-MHz capable oscillator with synchronization capability

• two-level thermal shutdown protection

An Excel Calculator Tool is provided to ease the process of creating custom designs using this controller. This

tool calculates values for all the external components required by the controller to meet a given specification. It

also generates many key parameters of the power stage including, for example, the turns ratio of the half-bridge

transformer. The tool generates graphs predicting, for a given set of current limit components, how the output

current limit will vary with input voltage. Maximum flexibility is offered by calculating suggested values for most

components, but allowing the user to input values of their own choice.

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7.2 Functional Block Diagram

VCC

I_AUX

+

VCC

REF

Regulator

I_LIM

One-Shot

VIN 13

I_{AUX_LIM}

AUX

OCP

RES

RON

1

6

RES

RON

15 BST_AUX

Start-Up Regulator

VIN

+

V_{AUX_UVLO}

VIN

œ

UVLO 28

+

AUX

OFF

350 mV

VCC UV

REF UV

VCC UV

REF UV

AGND

SS

2

8

I_AUX

HB OFF

AUX

TEMP

160°C

+

1.25 V

14 SW_AUX

Supply

Control

Logic,

Driver

Logic,

Dead

Time,

Protection

Logic

20 µA

AUX OTP

RON

VIN

COT

Timers

+

ON_OFF

7

50 µA

Hiccup Mode

150°C OTP

AUX

ASYNC

Mode

HB OFF

UVLO<1.25 V

(LATCH RESET)

VCC

17 VCC

AUX OCP

11

10

RD2

RD1

FB_AUX

12 FB_AUX

OFF STATE

ON STATE

0

FB_AUX

REG

+

Analog

MUX

1

REF_AUX

21 BST

22 HSG

23 SW

RAMP 24

+

SS

CLK

2 V

T

Q

MAIN CLK

DELAYED CLK

Prog.

Delay

RT

5

3

OSC

Q

REF

VCC

REF

S

R

Q

COMP

RAMP

+

PWM

R

Main

Supply

Soft-Start,

Driver

Logic,

Dead-

Time

Control,

and

Pulse

18 LSG

20 SR1

19 SR2

R

MAIN CLK

V_COMP

+

1 V

+

TH

SSSR

HICCUP

BLANK

+

SS

I_SLOPE

SS

CS_POS 25

Matching

REF

SSSR Cap

Clamp Event

Counter

I_OFFSET

Hiccup

Mode

Timer

and

+

Amp

I_SENSE

POS_OCP

LEB

K

1/K

+

CBC

CS_NEG

26

RES

Clamp

SSSR Cap

Logic

I_{POS_LIM}

2

I_{CS_SET}

4

REF

NEG OC

Event Counter

CS_SET 27

NEG

+

I_{NEG_LIM}

1/2

NEG_OCP

+

16 PGND

V_LIM

œ

Clamp

SSSR Cap

0

+

AGND

9

SSSR

Duty

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7.3 Feature Description

7.3.1 High-Voltage Start-Up Regulator

The LM5036 device contains a high-voltage VCC start-up regulator that allows the input pin (VIN) to be

connected directly to an input voltage up to 100-V. Higher input voltages can be accommodated by adding some

additional external parts, as described in 节 8.2.2.4. When the UVLO pin voltage is greater than V_SD(0.38-V

typical), the start-up regulator is enabled to charge an external capacitor connected to the VCC pin. The output

voltage of the VCC regulator is regulated at V_CC(7.8-V typical). The VCC regulator provides power to the

reference (REF) regulator. The regulator output at VCC is internally current limited to I_CC(Lim)(81-mA typical) .

The value of the VCC capacitor depends on the total system design, and its start-up characteristics. The

recommended range of values for the VCC capacitor is 0.47-µF to 10-µF.

LM5036 can power itself using its internal high-voltage start-up linear regulator, but internal power dissipation

can be reduced by powering VCC from an auxiliary switched mode supply. LM5036 device integrates all of the

functions needed to implement a low-cost and easy-to-design isolated fly-buck auxiliary supply based on the

constant-on-time (COT) control scheme. The primary output V_AUX1of the auxiliary supply must be connected

through a diode to the VCC pin, as shown in 图 7-1. The auxiliary supply must raise the VCC voltage above the

internally generated V_CCvoltage in order to shut off the internal start-up regulator. Powering VCC from an

auxiliary switched mode supply improves efficiency while reducing the power dissipation of the controller IC. The

VCC under-voltage (UV) circuit will still function in this mode, requiring that VCC never falls below its UV

threshold during the start-up sequence. The VCC regulator series pass transistor includes a diode between VCC

and VIN that should not be forward biased in normal operation. Therefore, the auxiliary VCC voltage should

never exceed the V_INvoltage.

V_IN

V_AUX1

VCC

VIN

PGND

图7-1. External VCC Bias Supply Connection

7.3.2 Undervoltage Lockout (UVLO)

The LM5036 controller contains a three-level under-voltage lockout circuit. When the UVLO pin voltage is below

V_SD(0.38-V typical), the controller is in a low current shutdown mode where the functional circuit blocks are not

enabled including VCC startup regulator, auxiliary supply and the main half-bridge control logic and gate drive

circuitry, etc.

When UVLO pin voltage is above V_SD, the VCC and REF regulators become active.

When the VCC and REF outputs exceed their respective UV thresholds and the input voltage V_INrises above

V_{AUX_UVLO}(15-V typical), the auxiliary supply is enabled.

When UVLO pin voltage rises above V_UVLO(1.25-V typical) and VCC and REF voltage are above their

respective UV thresholds, the control logic of the main half-bridge converter is enabled. The soft-start capacitor

is released and normal operation begins. An external set-point voltage divider from V_INto GND can be used to

set the minimum operating voltage of the half-bridge converter. The divider must be designed such that the

voltage at the UVLO pin is greater than V_UVLOwhen V_INenters the desired operating range. UVLO hysteresis is

accomplished with an internal current sink I_UVLO(20-µA typical) that is switched on or off into the impedance of

the external set-point divider. When the UVLO pin voltage threshold of V_UVLOis exceeded, the current sink is

deactivated to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the V_UVLO

threshold, the current sink is enabled causing the voltage at the UVLO pin to quickly fall. See 表 7-1 for more

detail on functional modes of LM5036.

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7.3.3 Reference Regulator

The REF pin is the output of a 5-V linear regulator that can be used to bias an opto-coupler transistor, primary

side of an isolated gate driver or digital isolator, among other housekeeping circuits. The regulator output is

internally current limited to I_REF(LIM)(39-mA typical). The REF pin must be locally decoupled with a ceramic

capacitor, the recommended range of values is from 0.1-µF to 10-µF.

7.3.4 Oscillator, Synchronized Input

The oscillator frequency of LM5036 device is set by a resistor connected between the RT pin and AGND. The R_T

resistor should be located close to the device. To set a desired oscillator frequency (f_OSC), the value of R_T

resistor can be calculated from 方程式1.

1

R_T=

f_OSC× 1 × 10^F10

(1)

For example, if the desired oscillator frequency is 400-kHz, that is, each phase (LSG and HSG) switches at 200-

kHz, the value of R_Tis calculated to be 25-kΩ. If the LM5036 device is to be synchronized to an external clock,

that signal must be coupled into the RT pin through a 100-pF capacitor. The RT pin voltage is nominally

regulated at V_RTReg(2-V typical) and the external pulse amplitude should lift the pin to between 3.5-V and 5.0-V

on the low-to-high transition. The synchronization pulse width should be between 15-ns and 200-ns. The R_T

resistor is always required, whether the oscillator is free running or externally synchronized and SYNC frequency

must be equal to or greater than the frequency set by the R_Tresistor.

7.3.5 Voltage-Mode Control

The LM5036 device employs voltage-mode control with input voltage feed-forward for the main half-bridge

converter. A simplified block diagram of the voltage-mode feedback control loop is shown in 图7-2.

RAMP

COMP

REF

V_AUX2

V_O

REF

RAMP

5 kΩ

V_COMP

+

PWM

V_SS-OS

+

V_FB

COMP

R

E/A

+

R

+

V_REFSec

SS

图7-2. Voltage-Mode Feedback Control Loop for Half-Bridge Converter

The output voltage (V_O) is sensed and compared against a reference voltage (V_REFSec) on the secondary side

which produces an error voltage which is then processed by the error amplifier. The compensated error signal is

transmitted across the isolation boundary through an opto-coupler and then gets injected into the COMP pin in

the form of a control current. The COMP pin current is internally mirrored by a matching pair of NPN transistors

which sink current through a 5-kΩ resistor connected to the 5-V internal reference. The resulting control voltage

V_COMPis compared with the soft-start capacitor voltage (SS) and the smaller of the two passes through an offset

V_SS-OS(1-V typical), followed by a 2:1 resistor divider before being applied to the PWM comparator to determine

the duty cycle of the half-bridge converter. The PWM comparator polarity is configured such that with no current

flowing into the COMP pin, the controller produces maximum duty cycle for the primary FETs.

An opto-coupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is

controlled by a current input, the voltage across the opto-coupler detector is nearly constant. The bandwidth

limiting phase delay which is normally introduced by the significant capacitance of the opto-coupler is thereby

greatly reduced. Higher loop bandwidths can be realized because the bandwidth limiting pole associated with

the opto-coupler is now at a much higher frequency.

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The voltage at the RAMP pin provides the modulation ramp for the PWM comparator. The PWM comparator

compares the modulation ramp signal at the RAMP pin to the COMP voltage to control the duty cycle. The

modulation ramp signal can be implemented as a ramp proportional to the input voltage, known as feed-forward

voltage mode control, as shown in 图 7-3. The RAMP pin is reset by an internal MOSFET when RAMP voltage

passes COMP voltage, current limit event, or at the conclusion of each PWM cycle, whichever comes earlier.

REF

5 kΩ

Slope proportional to V_IN

COMP

1 V

R

V_IN

R

PWM

+

R_FF

RAMP

(1)

C_FF

Time

AGND

图7-4. Modulation Ramp Slope

A. Slope proportional to input voltage (see 图7-4)

图7-3. Feed-Forward Voltage-Mode Control

Configuration

An external resistor (R_FF) and capacitor (C_FF) connected to VIN, AGND, and the RAMP pins are required to

create a saw-tooth modulation ramp signal. The slope of the signal at RAMP will vary in proportion to the input

voltage. The varying slope provides line feed-forward information necessary to improve line transient response

with voltage-mode control. With a constant control signal, the on-time (t_ON) varies inversely with the input voltage

(V_IN) to stabilize the volt-second product of the transformer. Using a line feed-forward ramp for PWM control

requires very little change in the voltage regulation loop to compensate for changes in input voltage, as

compared to a ramp with fixed slope. In addition, voltage-mode control is less susceptible to noise. Therefore, it

is a good choice for wide input range power converter applications. However, voltage-mode control requires a

Type-III compensation network due to the complex-conjugate poles of the L-C output filter.

Assistance with half-bridge voltage control loop design may be obtained using the Power Stage Designer™ tool.

The recommended capacitor value range for C_FFis from 100-pF to 1800-pF. 图 7-3, shows that the C_FFvalue

must be small enough to be discharged within the clock pulse-width (t_CLK). The value of R_FFrequired can be

calculated from 方程式2

F1

R_FF

=

V_RAMP

f_OSC× C_FF× lnl1 F

p

V

:

;

IN min

(2)

For example, assuming a V_RAMPvoltage of 1.5-V (a good compromise of signal range and noise immunity),

_IN(min)of 36-V, oscillator frequency of 400-kHz and C_FF= 560-pF results in R_FF= 105-kΩ.

V

7.3.6 Primary-Side Gate Driver Outputs (LSG and HSG)

The LM5036 device provides two gate driver outputs for the primary FETs of the main half-bridge converter: one

floating high-side gate driver output HSG and one ground referenced low-side gate driver output LSG. Each

internal gate driver is capable of sourcing 1-A peak and sinking 2-A peak (typical). Initially, the LSG output is

turned on during the power transfer phase, followed by a freewheeling period during which both LSG and HSG

outputs are turned off. In the subsequent power transfer phase, the HSG output is turned on followed by another

freewheeling period.

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The low-side LSG gate driver is powered directly by the VCC bias supply. The HSG gate driver is powered from

a bootstrap capacitor connected between BST and SW. An external diode connected between VCC and BST

provides the high-side gate driver power by charging the bootstrap capacitor from VCC when the switching node

SW is low. When the high side FET is turned on, BST rises to a peak voltage equal to VCC + V_IN.

The BST and VCC capacitors should be placed close to the pins of the LM5036 device to minimize voltage

transients due to parasitic inductance because the peak current source to the MOSFET gates can exceed 1 A

(typical). The recommended value of the BST capacitor is 0.1-µF or greater. A low ESR/ESL capacitor, such as a

surface mount ceramic, should be used to prevent voltage drop during the HSG transitions.

7.3.7 Half-Bridge PWM Scheme

Synchronous rectification on the secondary side of the transformer provides higher efficiency, especially for low

output voltage and high output current converter, compared to the diode rectification. The reduction of the diode

forward voltage drop (0.5-V to 1.5-V) to 10-mV to 200-mV V_DSvoltage for a MOSFET significantly reduces

rectification losses. In a typical application, the secondary windings of the transformer can be center tapped, with

the output power inductor in series with the center tap, as shown in 图 7-5. The synchronous rectifiers (SRs)

provide the ground path for the energized secondary winding and the inductor current.

V_IN

SR1

V_O

HSG

LSG

SR2

SGND

PGND

图7-5. Half-bridge Topology with Center-Tap Rectification

The internal SR drivers are powered by the REF regulator and each SR output is capable of sourcing 0.1-A and

sinking 0.2-A peak (typical). The amplitude of the SR drivers is limited to 5-V. The 5-V SR signals enable the

transfer of SR control signals across the isolation barrier either through a digital isolator or isolated gate driver. It

should be noted that the actual gate sourcing and sinking currents for the SRs are provided by the secondary-

side gate drivers.

The timing diagram of the four PMW signals (LSG, HSG, SR1, and SR2) with dead-times is illustrated in 图 7-6.

The main clock is generated by the internal oscillator. A delayed clock is derived by adding a delay of t_Dto the

main clock. t_Dcan be calculated from 方程式 3, where RD₁is the value of the resistor connected between RD1

pin and AGND.

t_D= RD₁× 2 pF + 20 ns

(3)

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t_CLK

t_D

Main

CLK

t_{OSC .}

Delayed

CLK

t_{SW .}

LSG

HSG

t .

2

t .

2

t

1

t

1

SR1

SR2

Time

图7-6. PWM Signal Timing Diagram

As illustrated in 图 7-6, the rising edge of the main clock is used to turn off the SRs. Primary FET drive signal

LSG/HSG is turned on at the falling edge of the delayed clock. Therefore, the dead-time between the falling

edge of SR and the rising edge of the respective primary FET can be calculated from 方程式4

t₁= t_D+ t_CLK

(4)

where

• t_CLKis the pulse width of the clock which is 65 ns (typical).

The minimum achievable t₁is dominated by the pulse width of the clock when t_Dis set to minimum (30 ns).

After SR1 is turned off, the body diode of SR1 continues to carry about half the inductor current until the primary

power raises the drain voltage of the SR1 and reverse biases its body diode. Ideally, dead-time t₁would be set

to the minimum time that allows the SR to turn off before the body diode starts conducting.

Power is transferred from the primary to the secondary side when the LSG is turned on. During this power

transfer period, the SR2 is still turned on while the SR1 is turned off. The drain voltage of SR1 is twice the

voltage of the center tap at this time. Under the normal operation, the LSG is turned off either when the RAMP

signal exceeds the COMP signal or at the rising edge of the next delayed clock signal (maximum duty cycle

condition), whichever comes earlier. A dead-time t₂is inserted between the falling edge of LSG and rising edge

of SR1. t₂can be calculated from 方程式 5, where RD₂is the value of the resistor connected between RD2 pin

and AGND.

t₂= RD₂× 2 pF + 30 ns

(5)

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During the dead-time t₂, the inductor current continues to flow through the body diode of SR1. Because the body

diode causes more conduction loss than the SR, efficiency can be improved by minimizing the t₂period while

maintaining sufficient margin across the entire operating conditions (component tolerances, input voltages, etc.)

to prevent the cross conduction between the primary FET and SR.

During the freewheeling period where both of the primary FETs are turned off while both of the SRs are turned

on, the inductor current is almost equally shared between SR1 and SR2 which effectively shorts the secondary

winding of the transformer. SR2 is then turned off before HSG is turned on. The power is transferred from the

primary to secondary side again when HSG is turned on. After HSG is disabled and the dead-time t₂expires,

SR1 and SR2 both conduct again during the freewheeling period.

Resistor values of no less than 5-kΩshould be connected between the RD1/RD2 pins and AGND

7.3.8 Maximum Duty Cycle Operation

The LSG and HSG will operate at maximum duty cycle when they are turned off at the rising edge of the delayed

clock, instead of by the event where RAMP voltage passes COMP voltage, as shown in 图 7-7. In LM5036

device, it is intended to achieve optimized maximum duty cycle for the primary FETs in order to accommodate

wider range of operation.

t_CLK

t_D

Main

CLK

Delayed

CLK

LSG

HSG

t

1

t .

2

t

1

SR1

SR2

t .

2

Time

图7-7. PWM Signals at Maximum Duty Cycle Condition

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Use 方程式6 to calculate the maximum duty cycle for the primary FETs

1

F t_CLK

f_OSC

D_MAX

=

2

f_OSC

(6)

where

• f_OSCis the oscillator frequency which is twice the switching frequency

The pulse width of the clock is used in this case to prevent cross-conduction between the two primary FETs

during the maximum duty cycle operation.

7.3.9 Pre-Biased Start-Up Process

The soft-start functionality limits the inrush current and voltage stress of the power converter. A common

requirement for the power converters used in the telecom/datacom applications is to have a monotonic output

voltage start-up into pre-biased load conditions where the output capacitor is pre-charged prior to start-up. In a

pre-biased load condition, if the synchronous rectifiers are engaged prematurely they will sink current from the

pre-charged output capacitors resulting in undesired output voltage dip or even power converter damage. The

LM5036 device implements unique circuitry to ensure intelligent turn-on of the synchronous rectifiers such that

the output voltage has monotonic start-up.

The start-up process can be divided into two phases:

• soft-start of the primary FETs

• soft-start of the SRs

The pre-biased start-up process is handled automatically by LM5036. The user need only select values for C_SS

,

C_SSSR, and the ramp rate of the secondary reference (V_REFSec) soft-start 图 7-8. The circuit of 图 7-8 uses a

comparator to, detect the voltage change of V_AUX2and, release the FET shorting across the secondary soft-start

capacitor (C_SSSec). This comparator circuit may also be replaced by the transistor based circuit of 图8-3.

7.3.9.1 Primary FETs Soft-Start Process

图7-8 shows a simplified block diagram of the soft-start function.

FB_AUX

V_AUX2

V_O

0

REF

V_AUX-OFF

FB_AUX

AUX PWM

Analog

MUX

+

REF_AUX

1

V_AUX-ON

AUX Regulation

Comparator

V_FB

COMP

E/A

+

SS

+

V_SSSecEn

R_SSSec

V_REFSec

C_SSSec

V_AUX2

SS

V_AUX2

+

V_THSec

图7-8. Soft-Start Function

The auxiliary supply has two reference output voltage levels of V_AUX-OFF(1.4 -V typical, off state) and V_AUX-ON

(1-V typical, on state) which facilitates easy voltage level shift detection on the secondary side. The auxiliary

supply starts to operate as soon as V_IN> V_{AUX_UVLO}(15-V typical) and VCC and REF are above the respective

UV thresholds. When the soft-start capacitor is below V_SSSecEn(2.06-V typical), the auxiliary supply will produce

the off-state voltage on the primary (V_AUX1-OFF) and secondary side (V_AUX2-OFF), as shown in 图7-9.

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The off-state auxiliary output voltage level present on the secondary side V_AUX2-OFFis above the threshold

V_THSec, which activates a reset circuit that discharges the output voltage reference V_REFSec. This ensures that

the opto-coupler is producing a 0% duty-cycle command. When UVLO exceeds V_UVLO(1.25-V typical) and VCC

and REF are above the respective UV thresholds, the soft-start capacitor starts to charge. The auxiliary supply

will produce the on-state voltage level when the soft-start capacitor reaches V_SSSecEn

.

V_{AUX_UVLO}

V_IN

V_UVLO

V_SD

UVLO

V_AUX2-OFF

V_AUX2-ON

V_THSec

V_AUX2

V_SSSecEn

V_SS-OS

SS

Prebias

Voltage

V_O

V_REFSec

I_COSsrEn

Soft-Start of SR

Freewheeling

SYNC Mode

Pulse

SR

I_COMP

V_SSREn

SSSR

t₁

t₂

t₃

图7-9. Pre-biased Start-Up Waveform

The secondary side reset circuit will now be disabled because V_AUX2-ON< V_THSec, and the output voltage

reference is released. The reference capacitor soft-starts the output voltage under full regulation. By modulation

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of the auxiliary output voltage, the communication between the primary and secondary side is established

without the need of any additional opto-coupler.

Due to the introduced programmable soft-start delay (before SS capacitor reaches V_SSSecEn), the duty cycle is

controlled by the feedback control loop at all times without being interfered by the SS capacitor voltage (because

V_COMP< V_SS). When the reference voltage exceeds the pre-bias voltage at the output, the I_COMPstarts to fall as

the secondary side error amplifier demands increased power. As I_COMPfalls the internal V_COMPvoltage will rise

and when it exceeds V_SS-OS, which corresponds to zero duty cycle, the duty cycle of the primary FETs starts to

increase. Once the I_COMPcurrent falls below I_COSsrEnthe device starts to charge SSSR capacitor with current

I_SSSR(20-µA typical).

Main

Clk

Delayed

Clk

LSG

HSG

SR1

SR2

V_SSREn

SSSR

图7-10. PWM Timing During Startup Process

7.3.9.2 Synchronous Rectifier (SR) Soft-Start Process

Until SSSR capacitor reaches V_SSREn(1-V typical), the controller operates at SR synchronization (SYNC) mode

where the SR pulses are synchronized to the respective primary FET pulses, as shown in 图 7-10. This helps to

reduce the conduction loss of the SRs. In addition, due to the fact that the SRs only conduct during power

transfer phase, there is no risk of reverse current in SYNC mode. Since the pulse width of SRs gradually

increases, the output voltage disturbance due to the difference in the voltage drop between the body diode and

the on resistance of the SRs is prevented.

Once the SSSR capacitor crosses the V_SSREn, the LM5036 device begins the soft-start of the SRs freewheeling

period (highlighted in gray in 图 7-10) where the SRs may sink current from the output if they are engaged

prematurely. The V_SSREnoffset on the SSSR pin is intended to provide additional delay which ensures that the

primary duty cycle ramps up to a point where the output voltage is in-regulation, thereby avoiding reverse current

when the SRs are engaged. The SR soft-start follows a leading-edge modulation technique such that the

leading-edge of the SR pulse is soft-started as opposed to the trailing-edge modulation of the primary FETs. As

shown in 图 7-10, SR1 and SR2 are turned on simultaneously with a narrow pulse-width during the freewheeling

period. At the end of the freewheel period, that is, at the rising edge of the main CLK, the SR in phase with the

next power transfer cycle remains on while the SR out of phase with it is turned off. The in-phase SR remains on

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throughout the power transfer cycle and at the end of it, both the primary FET and the in-phase SR are turned off

simultaneously. At the end of the soft-start, the SR pulses will become complementary to the respective primary

FETs, as shown in 图7-6.

7.3.10 Zero Duty Cycle Operation

The zero duty cycle detection ensures that there is no excessive reverse current when the primary duty cycle is

zero. In that case, the SSSR capacitor would be clamped to ground and therefore SRs will be turned off (SR

SYNC mode). Normal operation will resume (SSSR capacitor start to charge) as soon as the load is applied. It

should be noted about a special application scenario where there is a low output capacitance value. During the

start-up under no load condition, the output capacitor acts like a load. With small output capacitor the converter

might get stuck in zero duty until load is applied.

7.3.11 Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching

图7-11 illustrates the half-bridge converter with low-side current sensing using a sense resistor.

V_IN

SR1

V_O

HSG

SW

LSG

SR2

V_CS+

V_CSœ

SGND

PGND

图7-11. Half-Bridge Converter with Low-Side Current Sensing

In LM5036 device, current limiting for the half-bridge converter is accomplished with three pins, including

CS_SET, CS_POS and CS_ NEG pins, as shown in 图 7-12. The current sense circuit limits positive current

flowing from input to output and also negative current flowing from output to input. An input voltage

compensation function helps to minimize the variation of effective output current limit across the range of input

voltage. A pulse matching function is automatically implemented when the peak current limit circuit is active. This

function matches the pulse width on the high and low primary FETs to maintain voltage balance of the half-

bridge capacitor divider. This method ensures flux balance of the transformer during peak current limit operation.

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V_IN

I_PRI

R₂

I_SLOPE

K_10a

R₁

CS_POS

+

Amp

C_F

R₃

R_CS

V_CS

1/K_10b

K_2a

+

CBC

CS_NEG

CS_SET

POS_OCP

NEG_OCP

PGND

I_{CS_SET}

R_LIM

1/K_2b

NEG

+

AGND

V_LIM

œ

AGND

图7-12. Block Diagram of the Current Limiting Function

CS_SET pin is used to set the internal current limit threshold with an external resistor R_LIMaccording to 方程式

7.

V

LIM

I_{CS_SET}

=

R_LIM

(7)

where

• V_LIM(0.75-V typical) is the internal current limit setting voltage.

The CS_POS pin is driven by a signal representative of the current flowing through the low-side FET of the half-

bridge converter. The current sense voltage at CS_POS pin (equal to CS_NEG pin voltage) is converted to a

current sense signal through R₃which is then sensed, scaled and compared against the internal current limit

thresholds. In order to blank the leading-edge transient noise seen when the low-side FET is turned on, the

current sense signal is blanked for t_CSBLKafter LSG is turned on. If the magnitude of the noise spike is

excessive, an additional filter capacitor C_Fmay be added to form an RC filter with R₁to reduce the high-

frequency noise spike. Both the leading-edge blanking and RC filter help to prevent false triggering of CBC

current limiting operation.

In order to achieve bi-directional current sensing, an internal offset current (K_10ax I_{CS_SET}), is injected to the

CS_POS pin. This offset allows positive internal thresholds on the CBC and NEG comparators that correspond

to effective I_{CS_SET}and -I_{CS_SET}/ 2 thresholds at the input.

When the current sense signal (I_R3x 1 / K_10b) reaches the positive threshold (K_2ax I_{CS_SET}), CBC current limiting

operation is activated. The controller essentially operates in peak current mode control, with the voltage loop

open, during the CBC operation. A common issue with peak current mode control is sub-harmonic oscillation.

This occurs when the effective duty cycle is greater than 50%. A common solution for sub-harmonic oscillation is

to add slope compensation. The slope of the compensation ramp must be set to at least one half the downslope

of the output inductor current transformed to the primary side across the current sense resistor. To eliminate sub-

harmonic oscillation after one switching cycle, the slope compensation must be equal to the downslope of the

output inductor current. This is known as deadbeat control. In LM5036, the slope compensation signal is a saw-

tooth current signal ramping up from 0 to I_SLOPEat the oscillator frequency (twice the switching frequency of

each primary FET).

However, another issue will arise after slope compensation is added. The current limit level varies with the input

voltage, as illustrated in 图 7-13. Because the slope compensation magnitude is different at different input

voltages, the actual current limit level varies with input voltage for a given internal current limit threshold.

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I_{CS_SET}x 20

I_SLOPEx D_max

I_{CS_SET}x 20

I_SLOPEx D_min

V_CS/ R₁

I_O/ N_PS

V_CS/ R₁

V_IN(min)/ R₂

V_IN(max)/ R₂

I_{CS_SET}x 10

I_{CS_SET}x 5

time

图7-13. Current Sense and Current Limit Waveforms

A new feature, input voltage compensation, is provided by LM5036. By adding an extra signal, which is a

function of input voltage, on top of the current sense signal and the slope compensation signal, variation of the

current limit level can be minimized over the entire input voltage range. The CS_POS pin voltage at time t, after

the rising edge of LSG, is expressed by 方程式8:

≈

V

_IN- v_{CS _POS}

t

( )

’

v_{CS _POS}t = v

( )

t + R ì I_{CS _ SET}ìK_10a

+

+I_SLOPEì t ì f_OSC

_CS( )

∆

÷

1

∆

R₂

«

◊

(8)

(9)

≈

’

V

IN

v_CSt + R ì I_{CS _ SET}ìK_10a

+

+I_SLOPEì t ì f_OSC

( )

∆

÷

◊

1

R₂

«

v_{CS _POS}t =

( )

R₁

1+

R₂

At the trip threshold, of the CBC comparator, both its inputs are at the same potential. In this case the voltage on

the CS_NEG pin is expressed by 方程式10.

v_{CS_NEG}= I_{CS_ SET}ìK_2aìK_10bìR₃

(10)

v_{CS _POS}t = v

( )

CS _NEG

(11)

For a given duty cycle (D) the current sense threshold voltage that will just trigger the CBC comparator can be

determined by combining 方程式9, 方程式10 and 方程式11.

≈

’

≈

∆

«

’

≈

∆

«

’

÷

V

1

IN

v_{CS_ CBCTh}= R ì I

ì K_2aìK_10bìR₃

+

-K

-

-I_SLOPEìD

∆

÷

◊

∆

÷

1

CS_ SET

10a

∆

R₁R_{2 ◊}

R₂

◊

«

(12)

Now if we assume:

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1

=

+

R₃R₁R₂

K_10a= K_10b= 10

K_2a= 2

2ì V_O

D = t_ONì f_OSC

=

ìN_PS

V

IN

N_P

N_PS

=

N_S

(13)

方程式12 simplifies to 方程式14.

≈

∆

«

’

÷

◊

K_CBC1

V

2ì V_O

IN

v_{CS _ CBCTh}= R ì

-

-I_SLOPE

ì

ìN_PS

1

R_LIM

R₂

V

IN

Where

K_CBC1= V_LIMì K_2aìK_10b-K_10a

(

)

(14)

节 8.2.2.11 gives an example design process for calculating the CBC external resistor values. The Excel

Calculator Tool can also be used to assist in the process of selecting these resistor values.

LM5036 ensures flux balance of the main transformer during CBC operation. The duty cycles of the two primary

FETs are always matched. If the low-side FET is terminated due to a current limit event, a matched duty cycle

will be applied to the high-side FET during the next half switching period, regardless of the current condition. The

matched duty cycles ensure voltage-second balance of the transformer which prevents transformer saturation.

The pulse matching operation is illustrated in 图 7-14. When the current limit is reached during the low-side

phase, a FLAG signal goes high. The RAMP signal is sampled at the rising edge of the FLAG signal and then

held through the next half switching period for the high-side phase. When the high-side phase RAMP signal rises

above the sampled value, the high-side PWM pulse is turned off so that the duty cycle are matched for both

phases. In the meantime, the hiccup restart capacitor is charged with a current source I_RES-SRC1(15-µA typical)

during CBC operation. The pulse matching feature is handled automatically by the LM5036 controller and

requires no action from the designer.

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Delayed

CLK

Current Limit

Sensed

Current

S&H

Ramp

Flag

LSG

HSG

图7-14. Pulse Matching Operation

7.3.12 Reverse Current Protection

In addition to the CBC current limit, a negative current limit, which is set to be half of the positive current limit as

shown in 图 7-15. This is used to prevent excessive reverse current which could cause significant output voltage

dip and potentially damage the power converter. When the negative current limit is exceeded twice, the SSSR

capacitor will be clamped to ground so the controller enters the SR SYNC mode where the SR pulses are

synchronized to the respective primary FET pulses. Therefore, the SR freewheeling pulses are turned off. The

negative current limit event counter will be reset if the number of negative current limit events detected within

four switching periods is less than two.

1/K_2b

Negative

Current Limit

Event Counter Clamping

SSSR cap

SSSR Cap

Clamp Event

Counter

+

Hiccup Mode ON

When Counter = 8

CS_SET

R_LIM

I_{NEG_LIM}

NEG_OCP

+

V_LIM

œ

AGND

图7-15. Reverse Current Protection Circuit

At the trip threshold of the NEG comparator both inputs are at the same potential. In this case the voltage on the

CS_NEG pin is expressed by 方程式15.

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1

v_{CS_NEG}= I_{CS_ SET}

ì

ìK_10bìR₃

K_2b

(15)

The voltage across the CS resistor at the trip threshold of the NEG comparator can therefore be determined by

combining 方程式9, 方程式11 and 方程式15.

≈

∆

«

’

÷

◊

K_CBC2

V

IN

v_{CS _ NEGTh}= R ì

-

-I_SLOPEì t_CSBLKì f_osc

1

R_LIM

R₂

Where :

K_2b= 2

≈

’

1

K_CBC2= V_LIM

ì

ìK_10b-K_10a

∆

«

÷

◊

K_2b

(16)

Notice that the inductor current has its most negative value at the start of the LSG on period. The NEG

comparator trip will occur immediately after the blanking period (t_CSBLK) has expired.

The Excel Calculator Tool predicts both the positive and negative output current limit levels as a function of input

voltage for a given set of resistor values.

7.3.13 CBC Threshold Accuracy

The CBC current limit amplifier deployed within LM5036 is a precise component. In common with all such

devices the input bias currents and input offset voltage will lead to small variations in the current trip threshold

between parts and across temperature.

V_IN

R₂

I_PRI

I_SLOPE

V_CSOffset

K_10a

R₁

I_BiasPOS

I_BiasNEG

CS_POS

+

Amp

C_F

R₃

R_CS

V_CS

1/K_10b

K_2a

+

CBC

CS_NEG

CS_SET

POS_OCP

NEG_OCP

PGND

I_{CS_SET}

R_LIM

1/K_2b

NEG

+

AGND

V_LIM

œ

AGND

图7-16. Diagram of Current Limiting Function with Error Terms Shown in Red

At its trip threshold the two inputs of the CBC comparator must be equal. At this condition the voltage on the

CS_NEG pin is given by 方程式17.

≈

∆

«

’

V_LIM

R_LIM

v_{CS _NEG}

=

ìK_2aìK_10b+ I_BiasNEGìR

÷

3

◊

(17)

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The voltage drop across the ideal amplifier input must be zero. The voltage of the CS_POS pin, at the trip

threshold can be expressed as follows:

v_{CS_POS}= v_{CS_NEG}+ v_CSOffset

(18)

V - v_{CS_POS}

≈

∆

«

’

÷

◊

V_LIM

R_LIM

IN

v_{CS_POS}= v_{CS_ CBCTh}

+

ìK_10a+I_BiasPOS+DìI_SLOPE

+

ìR

1

R₂

(19)

Combining 方程式 17, 方程式 18 and 方程式 19 and re-arranging gives an expression for the voltage across the

current sense resistor at the trip threshold 方程式20.

≈

’

÷

K

v_CSOffset

V

IN

v_{CS _ CBCTh}= R ì ^CBC1-I_BiasOffset

+

-DìI_SLOPE-

∆

1

R_LIM

R₃

R_{2 ◊}

«

Where :

I_BiasOffset= I_BiasPOS-I_BiasNEG

(20)

Hence, for a given set of external component values, the variation in current trip threshold across parts and

temperature can be found using data supplied in the Electrical Tables.

A short delay will exist (t_CSLSG), after the CBC comparator inputs reach their trip threshold, before the LSG falling

edge. During this delay the primary current will continue to ramp, giving rise to a further error in the apparent trip

threshold. The peak primary current flowing when the low side MOSFET switches OFF (I_PriCBC), is expressed by

方程式21.

≈

’

≈

’

V_{CS _ CBCTh}

V

V_O

1

2

IN

∆

«

÷

◊

I_PriCBC

=

+ t_CSLSG

ì

+

-

∆

«

÷

◊

2

R_CS

L_Mag

L_OìN_PS

(21)

The output current at which the primary peak current threshold is reached is expressed by 方程式22.

»

ÿ

_LMagŸ

⁄

DI_LO

N_PS

I_LIM= N_PSì I

-

- DI

…

PriCBC

(22)

(23)

ΔI_LOis the amplitude of ripple current in the output inductor and is expressed in 方程式23.

V_Oì(1-D)

DI_LO

=

2ìL_Oì f_OSC

ΔI_LMagis the amplitude of ripple current in the magnetising inductor and is expressed in 方程式24.

V

N_PSì V_O

2ìL_Magì f_OSC2ìL_Magì f_OSC

D

IN

DI_LMag

=

ì

=

2

(24)

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Combining 方程式 22, 方程式 23 and 方程式 24 gives an expression for output current limit as a function of

primary current limit threshold 方程式25.

»

ÿ

Ÿ

V ì 1-D

(

)

V_OìN_PS

O

I_LIM= N_PSì I

-

…

PriCBC

2ìL_Oì f_OSCìN_PS2ìL_Magì f_{OSC Ÿ}

…

⁄

(25)

The Excel Calculator Tool can be used to evaluate the tolerance of output current limit.

7.3.14 Hiccup Mode Protection

A block diagram of the hiccup mode function is shown in 图 7-17. Both the repetitive CBC and negative current

limit events will trigger hiccup mode operation in LM5036 device.

Continuous

CBC

Hiccup

Mode

Timer

and

RES

SSSR Cap

Clamp Event

Counter

Logic

Reset

SSSR

Hiccup

Blank

V_RES

1 V

TH

SSSR

+

图7-17. Hiccup Mode Circuitry

The device charges the hiccup restart capacitor with a current source I_RES-SRC1(15-µA typical) during CBC

operation. The hiccup mode is activated when V_RESexceeds 1 V. During hiccup mode operation, the SS and

SSSR capacitors are fully discharged and the half-bridge converter remains off for a period of time (t_HIC) before a

new soft-start sequence is initiated.

4 V

2 V

1 V

t_CBC

SS

t_HIC

图7-18. Hiccup Mode Activated By Continuous CBC Operation

Use 方程式26 to calculate the duration of CBC operation before entering the hiccup mode.

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C_RESì1V

I_RES-SRC1

t_CBC

=

(26)

where

• C_RESis the value of the hiccup capacitor

After the RES pin reaches 1.0-V, current source I_RES-SRC1(15-μA typical) is turned off and current source

_RES-SRC2(30-μA typical) is turned on which charges the RES capacitor to 4-V. Then current source I_RES-DIS2(5-

I

μA typical) is enabled which discharges the RES capacitor to 2-V.

Use 方程式27 to calculate the hiccup mode off-time.

C_RESì 2 V ì8 +1V

C_RESì 2 V ì8

(

)

t_HIC

=

+

I_RES-DIS2

I_RES-SRC2

(27)

In addition to the repetitive CBC current limit condition, the device also enters hiccup mode if the SSSR capacitor

is clamped for eight times due to repetitive negative current limit condition. The operating pattern of the hiccup

mode activated by the negative current limit is similar to that activated by CBC current limit. The only difference

is that at the beginning of the hiccup mode operation the RES capacitor is charged with current source I_RES-SRC2

when activated by negative current limit as illustrated in 图 7-19 whereas the RES capacitor is charged with

current source I_RES-SRC1when activated by CBC current limit condition.

4 V

2 V

0 V

Counter ⁽¹⁾

t_HIC

(1) SSSR capacitor clamp event counter

图7-19. Hiccup Mode Activated By Repetitive Negative OCP Condition

Once the hiccup off-timer expires, the SSSR capacitor clamp event counter will be reset. If SSSR capacitor gets

clamped for less than eight times before the SSSR capacitor voltage is fully ramped up to its maximum value,

the SSSR capacitor clamp event counter will also be reset. This is because the fact that SSSR capacitor voltage

is able to fully ramp up to its maximum value indicates that repetitive negative current limit condition no longer

exists.

7.3.15 Hiccup Mode Blanking

In some application scenarios such as high output capacitance and/or heavy load, there can be excessive inrush

current during the start-up process. This would trigger CBC current limit which in turn activates the hiccup mode

operation, thereby causing the converter to keep attempting to restart. In LM5036 device, a hiccup mode

blanking circuitry is implemented to disable the hiccup mode operation during the start-up. The hiccup capacitor

is clamped to ground until the SSSR capacitor voltage rises above the hiccup blank threshold V_{HC_BLK_TH}(5.5-V

typical).

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7.3.16 Over-Temperature Protection (OTP)

Two-level internal thermal shutdown circuitry is implemented in LM5036 device to protect the integrated circuit

should its maximum rated junction temperature be exceeded. When the internal temperature is above the lower-

level threshold of 150°C, the half-bridge converter is turned off and thereby the SS and SSSR capacitors are

fully discharged.

Typically, the internal temperature should drop after the main half-bridge converter is turned off. However, if the

temperature continues to rise above the higher-level threshold of 160°C, the auxiliary supply will be disabled in

order to prevent the device from catastrophic failure due to accidental device overheating . Note that the internal

VCC and REF bias regulators still remain active during thermal shutdown to provide the bias power for the

external house-keeping circuitry.

7.3.17 Over-Voltage / Latch (ON_OFF Pin)

The ON_OFF pin can be configured as a latch pin or OVP pin. In the latch configuration, the half-bridge

converter remains off even after the faults are cleared. A new soft-start sequence will not be initiated until the

latch is reset. One latch configuration is illustrated in 图7-20 where a large latch resistor R_L(for example, 50 kΩ)

and a diode are tied to the ON_OFF pin.

REF

I_OVL

V_IN

ON_OFF

V_{ON_OFF}

R_OV1

REF UV

+

R_OV2

R_L

Hiccup Mode

150°C OTP

VCC UV

HB OFF

UVLO < 1.25 V

(LATCH RESET)

UVLO < 1.25 V

图7-20. ON/OFF Pin Latch Function

When any of the faults is detected including OVP, hiccup mode OCP and 150 °C OTP, the ON_OFF pin current

source, I_OVL(50-µA typical), is activated, that raises the ON_OFF pin voltage quickly. As a result, the latch diode

is reverse biased. The current source I_OVLremains active even if the fault is cleared because the ON_OFF pin

voltage is latched above V_{ON_OFF}(1.25-V typical). To reset the latch operation, simply pulling down the UVLO pin

voltage below V_{ON_OFF}disables the current source and thus the ON_OFF pin voltage falls quickly. A new soft-

start sequence will be initiated as soon as the latch is reset and the faults are cleared.

Use 方程式28 to design the external voltage divider in latch mode.

V

_{ON_ OFF}+ V_FV_{ON_ OFF}

≈

∆

«

’

÷

◊

V

=

+

ìR_OV1+ V_{ON_ OFF}+ V_F

IN_L

R_OV2

R_L

(28)

where

• V_Fis the forward voltage drop of the latch diode

• V_{IN_L}is the desired input voltage latch threshold, and R_Lis the latch resistor.

Note that the current source I_OVLdoes not provide any hysteresis when ON_OFF pin is configured in latch mode.

The ON_OFF pin can also be configured as an OVP pin as shown in 图 7-21. In this configuration, the external

voltage divider should be designed such that the ON_OFF pin voltage is greater than V_{ON_OFF}when an over-

voltage condition occurs.

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REF

I_OVL

V_IN

ON_OFF

V_{ON_OFF}

R_OV1

REF UV

+

R_OV2

Hiccup Mode

150°C OTP

VCC UV

HB_OFF

UVLO < 1.25 V

AGND

图7-21. ON/OFF Pin Configured as OVP Pin

The OVP hysteresis is accomplished with the I_OVLcurrent source. When the ON_OFF pin voltage exceeds

V_{ON_OFF}, the I_OVLcurrent source is activated which quickly raises the voltage at the pin. The half-bridge

converter is turned off and the SS and SSSR capacitors are fully discharged. When the ON_OFF pin voltage

falls below V_{ON_OFF}, the current source is deactivated causing the voltage at the pin to quickly fall followed by a

new soft-start sequence. In addition to the OVP fault, hiccup mode and internal 150-°C thermal shutdown faults

will also cause the half-bridge converter to turn off. Once the faults are cleared, a new soft-start sequence

automatically begins. Because the hiccup mode or 150-°C thermal shutdown fault also activates the current

source, it is important to make sure that the ON_OFF pin voltage doesn't rise above V_{ON_OFF}when the input

voltage is high, which otherwise would lead to latch operation. Avoid this scenario by selecting a proper voltage

divider.

Use 方程式29 and 方程式30 to select the voltage divider for the OVP configuration.

V_HYS(OVP)

R_OV1

=

I_OVL

(29)

where

• V_HYS(OVP)is the OVP hysteresis

V_{ON_ OFF}ìR_OV1

R_OV2

=

V_IN(OFF)- V_{ON_ OFF}

(30)

where

• V_IN(OFF)is the OVP rising threshold

7.3.18 Auxiliary Constant On-Time Control

图 7-22 shows a block diagram of the constant on-time (COT) controlled fly-buck converter. The LM5036 device

integrates an N-channel high-side MOSFET and associated high-voltage gate driver. The gate driver circuit

works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.01-µF ceramic

capacitor connected between the BST_AUX pin and SW_AUX pin provides the voltage to the driver during the

on-time. During each off-time, the SW_AUX pin is at approximately 0-V, and the bootstrap capacitor charges

from VCC through the internal diode. The minimum off-timer ensures a minimum time in each cycle to recharge

the bootstrap capacitor. The LM5036 device also provides an internal N-channel SR MOSFET and associated

driver. This MOSFET provides a path for the inductor current to flow when the high-side MOSFET is turned off.

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The integrated auxiliary supply employs constant on-time (COT) hysteretic control which provides excellent

transient response and ease of use. The control principle is based on a comparator and a one-shot on-timer,

with the output voltage feedback (FB_AUX) compared to an internal reference. If the feedback voltage is below

the reference the internal buck switch is switched on for the one-shot timer period, which is a function of the

input voltage and the on-time resistor (R_ON). Following the on-time the switch remains off until the FB_AUX

voltage falls below the reference, and the forced minimum off-time has expired. When the feedback voltage falls

below the reference and the minimum off-time one-shot period expires, the high-side buck switch is then turned

on for another on-time one-shot period. This will continue until regulation is achieved.

VCC

BST_AUX

V_IN

PWMA

SW_AUX

V_AUX2

Constant

On-Time

(COT)

V_CC

V_AUX1

PWMB

Control

Logic

FB_AUX

+

REF_AUX

图7-22. COT Controlled Fly-Buck Auxiliary Supply Circuitry

In a fly-buck converter, the low-side SR MOSFET is on when the high-side switch is off. The inductor current

ramps up when the high-side switch is on and ramps down when the low-side switch is on.

The switching frequency remains relatively constant with load and line variations. Use 方程式 31 to calculate the

switching frequency of the auxiliary supply.

V_AUX1

9 × 10^F11× R_ON

f_{SW_AUX}

=

(31)

where

• V_AUX1is the primary output voltage of the auxiliary supply.

Two external resistor values set the value of V_AUX1. This regulation of the output voltage depends on ripple

voltage at the feedback input, requiring a minimum amount of ESR for the output capacitor (C_AUX1). A minimum

of 25-mV of ripple voltage at the feedback pin is required for stable operation of the auxiliary supply. The 节

7.3.22 section describes auxiliary ripple circuit configuration.

7.3.19 Auxiliary On-Time Generator

The on-time for the auxiliary supply is determined by the resistor R_ON, and is inversely proportional to the input

voltage, resulting in a nearly constant switching frequency as the input voltage is varied over its entire range. 图

7-23 shows the block diagram for the on-time generator.

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VIN

AUX RAMP

t

ON

AUX RAMP

RESET

RON

PWMA

R_ON

PWMB

图7-23. On-Time Generator

Time

图7-24. Constant On-Time Control Waveform

A current source, which is a function of the input voltage and the R_ONresistor value, charges a capacitor. The

capacitor voltage ramps up linearly and gets reset when it reaches the threshold.

Use 方程式32 to calculate the on time t_ONof the high-side switch.

9 × 10^F11× R_ON

t_ON

=

V

IN

(32)

7.3.20 Auxiliary Supply Current Limiting

The LM5036 controller contains an intelligent current limit off-timer for the auxiliary supply. If the current in the

high-side switch exceeds I_AUX(LIM)(200-mA typical), both the high-side MOSFET and the low-side SR are

immediately turned off, and a non-resetable off-timer is initiated. The length of the off-time is a function of the

FB_AUX pin voltage and the input voltage V_IN. As an example, when V_{FB_AUX}= 0 V and V_IN= 48 V, a maximum

off-time is set to 16 µs. This condition occurs when the output is shorted, and during the initial phase of start-up.

This amount of time ensures safe short-circuit operation up to the maximum input voltage of 100 V.

In cases of overload where the FB_AUX voltage is above zero volts (not a short circuit) the current limit off-time

is reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time,

and start-up time. The current limit off-time is calculated from 方程式33.

(0.07 × V )

IN

t_{OFF (ILIM )}

=

Js

V_{FB_AUX}+ 0.2 V

(33)

Because the current limit protection feature of the auxiliary supply is peak limited, the maximum average output

is less than the peak.

To prevent excessive reverse current during the off-time of the current limit, the auxiliary supply operates in

asynchronous (ASYNC) mode where the low-side SR is turned off during current limit operation. The body diode

of the internal low-side MOSFET (QB) incurs significant power loss during asynchronous operation. TI

recommends adding an external schottky diode (D_FW) between the PGND and SW_AUX pins to ensure robust

and efficient current limit operation. This schottky diode is particularly important when operating from high input

voltage. Use an external schottky diode (D_FW) that is rated to carry the maximum auxiliary current and block the

maximum input voltage (V_IN(max)).

For high density designs it is desirable to use an auxiliary transformer with low magnetising inductance and

saturation current. The peak magnetising current flowing in the auxiliary transformer can exceed I_AUX(LIM)due to

delays in the peak current detection and comparator circuit. The actual peak magnetising current reached is a

function of the maximum slope of the transformer magnetising current. This behavior depends upon both

maximum input voltage V_IN(max)and magnetising inductance value. The method outlined below allows designers

to estimate the peak magnetising current that will flow in the Aux transformer (I_LPk).

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As illustrated in 图7-25, it is convenient to model the internal current sense circuit as a simple RC time constant,

τ_AuxSns(41-ns typical), that delays the sensed current signal presented to the OCP comparator input. There is a

further delay t_AUX(LIM)(116-ns typical), after the comparator input reaches its trip threshold before the OCPb fault

flag is set. The controller applies this extended off time, t_OFF(ILIM), only if the OCPb fault flag is set before the

COT (t_ON) period ends. 方程式 34 is an expression for the sensed and delayed magnetising current inductor

signal applied to the non-inverting input of the OCP comparator.

V

IN

QA

t

AuxSns

PWMA

I

(t)

AuxSns

LPk

I (t)

QA

t

AUX(LIM)

I

(t)

LAux

+

OCPb

I

I (t)

QA

AUX(LIM)

œ

I

V

AUX2

LInit

SW_AUX

I

AUX(LIM)

I

(t)

AuxSns

QB

t

PWMB

AUX(LIM)

D

FW

t

ON

V

PGND

AUX1

PGND

图7-25. Aux Current Limit Circuit Model

-t

t_AuxSns

≈

∆

’

÷

I_AuxSns(t) = I

-m_Auxì t_AuxSnsì 1- e

+ m_Auxì t

(

)

LInit

∆

÷

«

◊

(34)

where

• m_Auxis the slope of Aux transformer magnetising inductor current during QA on period

• τ_AuxSnsis the time constant of the internal current sensing circuit feeding the OCP comparator

Maximum peak current occurs when the magnetising inductor current slope has its highest value. This peak

occurs at start-up, or when a short circuit is applied across the V_AUX1output, while operating from maximum

input voltage (V_IN(max)). The maximum inductor current slope is given by 方程式35.

V

IN(max)

m_Aux

=

L_AUX

(35)

where

• L_AUXis the magnetising inductance of the Aux transformer

For a use case where the inductor current slope is fixed at its maximum value (m_Aux), the highest peak current

occurs when the inductor current at the start of the pulse (I_LInit) is just high enough to trip the OCPb flag before

the COT period (t_ON) expires. After this trip occurrs, the controller applies the extended OFF period (t_OFF(ILIM)) to

reduce the inductor current for subsequent pulses. This condition is given in 方程式 36 and is shown graphically

in 图7-25

I_AuxSns

t

_ON- t_AUX(LIM)= I

(

)

AUX(LIM)

(36)

where

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• t_AUX(LIM)is the time delay between comparator input threshold being achieved and the OCPb flag set

Combining 方程式 34 and 方程式 36 determines the initial inductor current for a pulse containing the highest

peak current 方程式37.

I_AUX(LIM)- m_Auxì t_ON- t_AUX(LIM)

(

)

I_LInit

=

+ m_Auxì t_AuxSns

- t_ON-t_AUX(LIM)

(

)

t_AuxSns

1- e

(37)

(38)

方程式38 uses the COT period in 方程式37 for the maximum input voltage.

K_ONìR_ON

t_ON

=

V

IN(max)

where

• K_ON(9 × 10^–11typical) is an internal constant that defines the COT period for a given V_INand R_ON

Having calculated I_LInitthe estimated peak inductor current is given by 方程式39.

I_LPk= I_LInit+ m_Auxì t_ON

(39)

Use this method to ensure that the operation does not exceed the Aux transformer saturation current under

transient or fault conditions. This method assumes fixed transformer magnetising inductance. The method

provides only a reasonable accuracy if the transformer magnetising inductance has not fallen significantly at the

predicted peak current.

To avoid excessive peak magnetising current during transient or fault events, ensure that the COT period (t_ON) is

longer than the response time of the peak current protection circuit. 方程式 40 expresses it as a minimum

required value for R_ON

.

t

_AuxSns+ t_AUX(LIM)ì1.2

(

)

R_ON

í

ì V

= V_IN(max)ì 2.09 kW

IN(max)

K_ON

(40)

7.3.21 Auxiliary Primary Output Capacitor Ripple

方程式 41 describes the output ripple voltage amplitude for a buck converter. This equation may be used if there

is no secondary winding or if the current supplied by V_AUX2is small compared with that supplied by V_AUX1

(I_AUX1>>I_AUX2). 方程式 41 neglects capacitor ESR and therefore calculates only the capacitive component of

output voltage ripple.

DI_L(AUX)

DV_AUX1Cap

=

2ì f_{SW _ AUX}ìC_AUX1

(41)

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I_{L_PRI}/I

L_SEC

I

+ N₂/N₁× I

AUX2

AUX1

(1)

(2)

0 A

I

L_PRI

L_SEC

Time

图7-26. Auxiliary Transformer Current Waveform for C_AUX1Ripple Calculation

图 7-26 shows the flybuck primary and secondary winding current waveforms I_{L_PRI}and I_{L_SEC}. The reflected

secondary winding current adds to the primary winding current during the off-time of the high-side switch. Due to

this increased current, the output voltage ripple is not the same as in a conventional buck converter. In this case

the average current flowing into C_AUX1during the t_ONperiod is the reflected secondary current. Hence 方程式 42

can be used to calculate ΔV_AUX1Cap, the voltage ripple across the primary side capacitor, for the more typical

case when the secondary current cannot be neglected. Notice that 方程式 42 neglects capacitor ESR and

therefore calculates only the capacitive component of ripple voltage amplitude.

N₂

I_AUX2

ì

ì t_ON(max)

N₁

2ìC_AUX1

DV_AUX1Cap

=

(42)

7.3.22 Auxiliary Ripple Configuration and Control

The voltage ripple across the output capacitor C_AUX1is made up of two components:

• Resistive ripple appears across the equivalent series resistance (ESR) of the output capacitor. This

component of ripple is in phase with the inductor current and is 90° delayed compared with the applied PWM

signal.

• Capacitive ripple appears across the ideal capacitor. This component of ripple is 90° delayed compared with

the inductor current ripple and 180° delayed compared with the applied PWM signal.

With COT control, the on-time of the high-side FET is terminated by an on-timer, and the off-time is terminated

when the feedback voltage V_{FB_AUX}falls below the reference voltage (V_AUX-ON). For a buck topology this type of

hysteretic control provides stable operation if these two conditions are met:

• Output voltage ripple is dominated by the resistive ESR component. The resistive ripple amplitude must be

approximately five times the capacitive ripple amplitude to guarantee stable operation.

• Output voltage ripple amplitude present at the FB_AUX pin must be greater than noise coupled onto this pin

from other sources. For an output voltage ripple amplitude of 25 mV at the FB_AUX pin ensures that other

sources of noise coupled to the pin can be assumed small

Aux transformer magnetising inductor ripple current amplitude is expressed by 方程式43.

≈

’

≈

’

÷

◊

V_AUX1

K_ONìR_ON

2ìL_AUX

V_AUX1

1

DI_L(AUX)

=

ì

- t_ON

=

ì 1-

∆

«

÷

◊

∆

2ìL_AUX

f_{SW _ AUX}

V

IN

«

(43)

For a buck converter the capacitive component of output voltage ripple amplitude is expressed by 方程式 41.

The resistive component of output ripple voltage amplitude is expressed by 方程式44.

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DV_AUX1Res= DI_L(AUX)ìR_Esr

(44)

Our condition for stable operation requires that 方程式45 and 方程式46 are both satisfied.

DV_AUX1Resí 5 ì DV_AUX1Cap

(45)

(46)

DV_AUX1Resí 25 - mV

The method outlined above allows us to calculate the resistance (R_Esr) that must be present in series with the

output capacitor (C_AUX1) to provide stable operation of a buck converter. This simple method has disadvantages

of high output voltage ripple amplitude and high dissipation in the series resistor R_Esr. The method is also not

ideal for a flybuck topology, especially if most of the load current is drawn from the secondary winding. In this

case much of the magnetising inductor current flows into the secondary output capacitor (C_AUX2) and not the

primary output capacitor (C_AUX1) during the low-side FET conduction period (t_OFF). The circuit of 图 7-27

provides a better solution that is well suited to the flybuck topology. A series branch R_r–C_ris connected across

L_AUX. The controller applies the same PWM voltage across this series branch as appears across L_AUX

.

Assuming most of the PWM voltage is dropped across R_r, the voltage across C_rhas the almost the same shape

and phase as the inductor current. The voltage ripple across C_rcan be used to substitute the voltage across

R_ESRand thus provide stable operation without the need for high output ripple and dissipation. By coupling this

capacitor voltage signal directly to the FB_AUX pin we can achieve the same result as a large ESR resistor, but

without the penalty of dissipation and high output voltage ripple amplitude. The method is suitable for a flybuck

topology, since the down-slope of the magnetising current is synthesised, across C_r, and therefore available on

the primary side to couple onto the FB_AUX pin.

L_AUX

SW_AUX

V_AUX1

R_r

C_r

R_FB1

C_ac

C_AUX1

FB_AUX

R_FB2

PGND PGND

PGND

图7-27. Minimum Ripple Configuration

The impedance of the capacitor generating the synthesised inductor current ripple signal, at the Aux switching

frequency (f_{SW_AUX}), must be low compared with the impedance of the R_FBxdivider network.

R_FB1+ R_FB2

2ì p ì f_{SW _ AUX}R_FB1ìR_FB2

3

C_r>

ì

(47)

The synthesised inductor ripple, generated across C_r, is added to the ripple across the output capacitor (C_AUX1).

The resultant signal is coupled to the FB_AUX pin via capacitor C_ac. The value of series resistor R_ris chosen to

ensure the synthesised resistive ripple amplitude satisfies 方程式45 giving 方程式48.

≈

∆

«

’

K_ONìR_ON

10 ìC_rì DV_AUX1Cap

V_AUX1

R_rÇ

ì 1-

∆

÷

◊

V

IN(min)

(48)

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Capacitor C_accouples the ripple signal directly onto the FB_AUX pin. Ensure that the value of this capacitor is at

least five times greater than the value of C_r. This ratio ensures minimum attenuation and phase shift of the

coupled ripple signal.

C_ací 5 ìC_r

(49)

7.3.23 Asynchronous Mode Operation of Auxiliary Supply

In LM5036 device, there are two conditions where the auxiliary supply will enter asynchronous (ASYNC) mode

operation where the low-side SR is turned off and only its body diode is allowed to conduct. The first condition is

when the half-bridge converter is turned off (Refer to the 节 7.4 section). This helps to reduce the power

consumption of the auxiliary supply at light loads. As described in the 节 7.3.20 section, the auxiliary supply will

also be forced to operate at ASYNC mode during current limit operation to prevent excessive reverse current.

7.4 Device Functional Modes

The functional modes of the device are summarized in the following table. Faults include hiccup mode OCP,

OVP, and 150°C OTP.

表7-1. Device Functional Modes

VCC AND REF

REGULATORS

AUXILIARY

SUPPLY

HALF-BRIDGE

CONVERTER

CRITERIA

UVLO < V_SD

OFF

ON

OFF

( V_SD< UVLO < V_UVLO) & (V_IN

<

V_{AUX_UVLO}

( V_SD< UVLO < V_UVLO) & (VCC & REF >

UV) & (V_IN> V_{AUX_UVLO}

)

ON at ASYNC

Mode

ON

OFF

ON

)

(UVLO > V_UVLO) & (V_IN> V_{AUX_UVLO}) &

(VCC & REF > UV) & No Faults

ON at SYNC Mode

(UVLO > V_UVLO) & (V_IN> V_{AUX_UVLO}) &

(VCC & REF > UV) & Any Faults

ON at ASYNC

Mode

OFF

NA

(VCC & REF > UV) & (V_IN> V_{AUX_UVLO}

& AUX Current Limit

)

ON at ASYNC

Mode

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The LM5036 device is a highly integrated half-bridge PWM controller that contains all the features necessary for

implementing the half-bridge topology power converters using voltage-mode control with input voltage feed-

forward. The device targets isolated DC-DC converter applications with input voltage of up to 100 V_DC

.

8.2 Typical Application

The following schematic shows an example of an isolated half-bridge DC-DC converter controlled by LM5036

device. The operating input voltage range is 36-V to 75-V, and the output voltage is 12-V. The maximum load

current is 8-A and the output current limit is configured to be 10-A.

D10

TP4

VIN

TP1

L1

R39

VIN

VIN_PIN

Prebias source

1.21k

100V

J1

470nH

J7

Q1

6.8µF

R36

3.3

RM7/ILP

4:3:3

T1

1

HSG

R4

100k

C5

C6

3

5

6

TxOut

SW

131-5031-00

1

TP5

C2

220pF

C1

2.2µF

C3

2.2µF

C4

2.2µF

L2

C42

100µF

SGND

TxOut

TP9

J3

4.7µH

2

C14

470µF

C11

47µF

C12

47µF

C13

47µF

C15

0.1µF

12V/10A

R5

100k

Q2

R37

3.3

C7

C8

LSG

SGND

6.8µF

PGND

TP2

J2

TxOut

SGND

TP6

RCS

Q3

Q5

C9

470pF

Q4

Q6

C10

470pF

0.005

TP7

J5

PGND

R33

4.99

R38

4.99

R6

100

NT1

Add shunt on J5

TP8

Net-Tie

PGND

AGND

SGND

TP3

U1

VIN

D3

R13

511

RC

VIN_PIN

30V

D7

13

15

14

BST_AUX

SW_AUX

R7

25.5k

C19

100V

C16

0.1µF

C33

0.01µF

L3

SW_AUX

C34

16

28

1

2

4

PGND

UVLO

C17

1500pF

VIN

220pF

R14

150k

R24

46.4k

R21

2.2k

C31

1µF

C18

R30

100k

R31

D11

100V

PGND

D9

D4

SGND

VAUX1

R12

11.8k

17

12

3

VCC

C44

1000pF

C32

2.2µF

6800pF

150µH

VAUX2

1000pF

45V

100V

4.02k

R22

R16

240

24

R32

105k

C35

RAMP

FB_AUX

D2

7.50k

0.1µF

D8

C36

1µF

4.7V

VX

PGND

100V

AGND

C22

21

22

VAUX2

BST

D6

R23

1.00k

VX

C25

0.01µF

C43 0.068µF

VIN

Add shunt on J4

J4

1

C45

560pF

RES

HSG

R8

6.65k

HSG

SGND

30V

C46

0.1µF

0.01µF

U4

4

3

R28 24.9k

5

6

7

8

R27

RT

SGND

1

V+

V-

PGND

R10

5.11k

R9

10.0k

40.2k

R29

23

RON

ON/OFF

SS

SW

LM8261M5

220k

U5

NC

LM4040BIM3-2.5/NOPB

AGND

Add shunt on J6

U2

VCCI

REF

C21

0.47µF

C20

1000pF

D1

C39 0.047µF

18

20

4

7

13

12

11

45V

LSG

SR1

VDDA

LSG

SGND

0.018uF

VCCI

C40

C38

R11

R25

R26

715

9

SSSR

VOUTA

VSSA

C28

1µF

J6

R34

6.81k

49.9k

2

5

1000pF

INA

20.0k

10

11

RD1

RD2

SGND

R35 40.2k

19

4

SR2

REF

DISABLE

VIN

SGND

REF

R2

25

26

27

C29 C30

0.1µF 0.1µF

AGND

CS_POS

CS_NEG

CS_SET

6

3

1

10

9

1.96M

DT

VDDB

VOUTB

VSSB

Q7B

3

COMP

R1 576

VCS+

INB

GND

C27

1µF

0.1µF

C41

MMDT3946-7-F

R3

RLIM

56.2k

A1

A2

A3

A4

8

C26

R20

10k

A1

A2

A3

A4

576

29

2

EP

47pF

R18

1.15k

UCC21225ANPL

PGND

SGND

R19

10k

VAUX2

AGND

R17

10k

PGND

AGND

LM5036RJBR

D5

9.1V

C37

AGND

2200pF

Q7A

MMDT3946-7-F

PGND

SGND

C24

C23

0.1µF

0.01µF

U3

4

3

1

2

R15

1.82k

SGND

PS2811-1-M-A

图8-1. Evaluation Board Schematic

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8.2.1 Design Requirements

PARAMETER

VALUE

36 V to 75 V

12 V

V_IN

Input voltage

V_O

Output voltage

I_{O (max)}

I_LIM

η

Maximum load current

Output current limit

Peak efficiency

8 A

10 A

94.4 %

93.5 %

11.9 V

8.5 V

Efficiency at V_IN= 48 V and I_O= 8 A

Off-state auxiliary output voltage

On-state auxiliary output voltage

Load regulation

V_AUX1-OFF

V_AUX1-ON

0.2%

Line regulation

0.1%

Line UVLO rising threshold

Line UVLO falling threshold

Line OVP rising threshold

Line OVP falling threshold

Latch threshold

34 V

32 V

80 V

78 V

80 V

I_AUX(max)

Maximum load current for auxiliary supply

100 mA

8.2.2 Detailed Design Procedure

The Excel Calculator Tool can be used to assist with selecting both power stage and controller setup

components.

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5036 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Input Transient Protection

The voltage applied to the VIN pin of LM5036 device serves as the input voltage for the internal VCC startup

regulator and auxiliary supply. In typical applications, the VIN pin voltage is the same as the input voltage for the

main half-bridge converter. The recommended range of the VIN pin voltage is 18-V to 100-V. 图 8-2 shows the

recommended filter to suppress transients that may occur at the input supply. This suppression is particularly

important when the input voltage rises to a level near the maximum recommended operating rating (100-V) of

the LM5036 device.

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V_IN

50 Ω

VIN

0.1 mF

PGND

图8-2. Input Transient Protection

8.2.2.3 Level-Shift Detection Circuit

An example implementation of the V_AUX2level-shift detection circuit is shown in 图 8-3. The zener voltage must

be between the off-state and on-state level of V_AUX2. When V_AUX2is above the zener voltage, both Q1A and

Q1B are turned on and therefore the reference output voltage V_REFSecis clamped to ground. Once V_AUX2falls

below the zener voltage, both Q1A and Q1B are turned off, and the reference is released.

Designers who wish to benefit from the fully regulated pre-biased startup feature of LM5036 must use separate

voltage reference and error amplifier devices. Popular combined error amplifier and voltage reference devices,

such as TL431, can be used only when the fully regulated pre-biased startup feature is not required.

Assistance with half-bridge voltage control loop design may be obtained using the Power Stage Designer™ tool.

V

REFSec

Q1B

MMDT3946-7-F

V

AUX2

10 kꢀ

Q1A

MMDT3946-7-F

0.01 …F

0.1 …F

GND

图8-3. Secondary Auxiliary Voltage Level-Shift Detection Circuit

8.2.2.4 Applications with V_IN> 100-V

For applications where the input voltage exceeds 100-V, all of the 100V-rated internal circuit blocks, including

VCC start-up regulator, auxiliary supply and half-bridge gate drivers, need to be bypassed, or powered from a

reduced voltage. In this case, VIN pin can be powered from an external start-up regulator, as shown in 图 8-4. If

pre-biased start-up is required the integrated flybuck aux circuit should be used from the reduced VIN pin voltage

to supply the secondary control circuit. If pre-biased start-up is not required, the bias supply V_AUX1, can be

derived from an external auxiliary supply. An external gate driver with higher voltage rating should be used to

drive the half bridge.

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V_IN

V_AUX1

VCC

VIN

PGND

图8-4. External Start-Up Regulator

8.2.2.5 Applications without Pre-Biased Start-Up Requirement

For applications where the pre-biased startup is not required, the level-shift detection circuit described in the 节

7.3.9 section is not necessary. Without the level-shift detection circuit, the reference voltage on the secondary

side would be released as soon as the secondary bias is established. The external VCC bias supply can be

derived from the integrated auxiliary supply or an auxiliary winding of the main transformer.

8.2.2.6 UVLO Voltage Divider Selection

As described in 节 7.3.2 , two external resistors can be used to program the minimum operating voltage for the

power converter, as shown 图 8-5. When the UVLO pin voltage falls below V_UVLO(1.25-V typical), an internal

current sink I_UVLO(20-µA typical) is enabled to lower the voltage at the UVLO pin, thus providing threshold

hysteresis. Resistance values for R_UV1and R_UV2can be determined from 方程式50 and 方程式51.

H_HYS(UVLO)

R_UV1

=

I_UVLO

(50)

where

• V_HYS(UVLO)is the UVLO hysteresis

V_UVLOìR_UV1

_IN(on)- V_UVLO-I_UVLOìR_UV1

R_UV2

=

V

(51)

where

• V_IN(on)is the input voltage above which the main converter will start to operate.

图 8-6 illustrates one way to configure a latch reset operation by pulling the UVLO pin voltage below V_UVLO. The

diode voltage drop must be between 0.35 V and 1.25 V. The controller can be forced to enter shutdown mode by

pulling UVLO pin to GND.

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V_IN

R_UV1

V_IN

V_UVLO

+

UVLO

R_UV1

V_UVLO

UVLO

+

I_UVLO

R_UV2

LATCH

RESET

AGND

V_SD

+

图8-5. UVLO Configuration

图8-6. Latch Reset

8.2.2.7 Over Voltage, Latch (ON_OFF Pin) Voltage Divider Selection

As described in 节 7.3.17, the ON_OFF pin can be configured as a latch pin or an OVP pin. 图 7-20 shows the

latch configuration. The ON_OFF pin is latched when the pin voltage reaches I_OVL× R_Lwhen any of the internal

faults is detected. The latch diode is reverse-biased during latch operation. Select the latch resistor R_Lvalue

such that I_OVL× R_L> V_{ON_OFF}. This design example uses an R_Lvalue of 49.9 kΩ. If the latch threshold is 80 V,

use an R_OV1value of 40 kΩ, and use an R_OV2value of 710 Ω.

If the ON_OFF pin is configured as an OVP pin, two resistors can be used to program the maximum operating

input voltage for the half-bridge converter, as illustrated in 图 7-21. When the ON_OFF pin voltage rises above

the V_{ON_OFF}threshold, an internal current source I_OVLis enabled to raise the ON_OFF pin voltage, thus

providing the threshold hysteresis. Use 方程式 29 and 方程式 30 to determine resistance values for R_OV1and

R_OV2. If the LM5036 controller is to be disabled when V_INrises above 80 V and enabled when it falls below 78 V.

Use an R_OV1value of 40-kΩ, and an R_OV2value of 635-Ω. The ON_OFF pin can also be used for external

thermal protection with a thermistor.

8.2.2.8 SS Capacitor

The soft-start delay t_D(SS), which is the time it takes for the soft-start capacitor to rise from 0 V to V_SSSecEn(2.06-

V typical), can be programmed with the SS capacitor value according to 方程式52

I_SSì t_D(SS)

C_SS

=

V_SSSecEn

(52)

where

• I_SS(20-µA typical) is the current source of the soft-start pin

8.2.2.9 SSSR Capacitor

The SSSR capacitor value determines the rate at which the pulse width of the SRs of the half-bridge converter

increases. To achieve a monotonic start-up for the output voltage, the optimum SSSR capacitor value satisfies

the following two conditions:

• Ensure the SR soft-start sequence is completed before the controller reaches the regulation set-point of the

output voltage.

• With a lower control loop bandwidth, the primary-side duty cycle tends to increase at a slower rate. in order to

prevent excessive reverse current, reduce the ramp-up speed of the SSSR capacitor voltage accordingly.

A general rule is to maintain the control loop bandwidth of the half-bridge converter above 1 kHz. With a slow

control loop bandwidth, the output voltage needs to drop at least 25% from the regulation set-point during the

restart time period where the SS pin voltage rises from 0 V to V_SSSecEn(2.06-V typical) and then the secondary-

side reference V_REFrises to 75% of regulation set-point. To satisfy the first condition above, maintain the rise

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time of the SSSR capacitor voltage to less than 25% of the rise time of the output voltage, as described in 方程

式53.

I_SSSR× 25% × t_RAMP

C_SSSR

<

5 V

(53)

where

• I_SSSR(20-µA typical) is the current source of the SSSR pin. t_RAMPis the ramp-up time of the output voltage.

Use the SSSR capacitor value calculated from 方程式 53 as a starting point. Fine-tuning may be needed based

on the actual control loop design and other specific design requirements such as pre-bias conditions and loading

profile.

8.2.2.10 Half-Bridge Power Stage Design

For a PWM operating frequency of 400kHz applied to the output inductor the oscillator frequency of LM5036

must also be set to 400kHz. The value of resistor R_Tis obtained using 方程式54.

1

R_T

=

= 25 - kW

f_OSCì1ì10^-10

(54)

(55)

Maximum effective duty cycle that can be applied to the output inductor is 方程式55.

D_MAX= 1- t_CLKì f_OSC= 0.974

Maximum transformer turns ratio that will deliver the required output voltage from minimum input voltage is given

by 方程式56.

D_MAXì V

IN(min)

N_PS(max)

=

= 1.46

2ì V_O

(56)

For our example design we will opt for a planar transformer with 4 primary turns and 3 secondary turns. The

turns are located in an un-gapped RM7/ILP ferrite core made of 3C95 material. This core has an inductance

factor AL = 4.4-µH/turn². Hence the actual turns ratio (N_PS) and magnetising inductance (L_Mag) are given by 方程

式57 and 方程式58.

N_P

N_S

4

3

N_PS

=

(57)

(58)

L_Mag= N_P²ì AL = 70.4 - mH

Maximum inductor current ripple will occur at maximum input voltage. The output inductor value L_Owill be

selected to limit inductor current ripple amplitude to 20-% of the maximum output current I_LIM

V ì 1-D

(

)

O

MIN

L_O

=

= 4.3 - mH

20%ì 2ìI_LIMì f_OSC

(59)

Hence a catalog part with an inductance of 4.7-µH, capable of carrying the full output current, and with a

saturation current of more that 120-% of I_LIM, is selected.

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L_O= 4.7 - mH

(60)

8.2.2.11 Current Limit

节 7.3.11 describes the CBC current limiting functionality in detail. 图 8-7 illustrates the current limiting block

diagram of the LM5036 controller. These are the five resistors associated with the current limiting function of the

half-bridge converter:

• R_CS

• R₃

• R₂

• R_LIM

• R₁

Because R₃is equal to the equivalent resistance of R₁and R₂as given by 方程式 13, there are four unknown

resistor values to be determined.

V_IN

I_PRI

R₂

I_SLOPE

K_10a

R₁

CS_POS

+

Amp

C_F

R_CS

V_CS

1/K_10b

R₃

K_2a

+

CBC

CS_NEG

CS_SET

POS_OCP

NEG_OCP

PGND

I_{CS_SET}

R_LIM

1/K_2b

NEG

+

AGND

V_LIM

œ

AGND

图8-7. Current Limiting Block

The value of current sense resistor R_CSis determined based on the maximum power consumption requirement.

Typically, the current sense resistor should consume less than 0.5% of the input power of the converter at the

worst case scenario. The sense resistor conducts every alternate current pulse flowing in the primary winding.

The power dissipated in the sense resistor is determined by 方程式61.

2

I_{Pri _ RMS}

P_CS

=

ìR_CS

2

(61)

The RMS current flowing in the primary winding may be calculated using 方程式62.

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2

≈

’

÷

≈

∆

«

’

÷

◊

I_O

DI_Pri

I_O

1

3

∆

I_{Pri _RMS}

Where :

=

ì D ì 1+

ì

N_PS

∆

«

÷

◊

≈

∆

’

÷

DI_LO

N_PS

V_O

2ìL_OìN_PS

V

IN

1- D

D

DI_Pri

=

+ DI_LMag

=

ì

+

ì

f

4 ìL_Magf_OSC

« ^OSC◊

(62)

Maximum loss in the current sense resistor will occur while maximum output current (I_LIM) is delivered from

minimum input voltage (V_IN(min)). Evaluating 方程式62 gives 方程式63.

I_{Pri _RMS}= 7.07A

(63)

To achieve our target of dissipating less than 0.5% of maximum output power the current sense resistor must

satisfy 方程式64.

2

R_CS< 0.5%ì V_OìI_LIM

ì

= 0.024 W

2

I_{Pri _RMS}

(64)

(65)

In our example design the current sense resistor value selected is given in 方程式65.

R_CS= 5 mW

HSG

t

OFF

ON

OFF

LSG

V

IN

V

SW

V /2

IN

t

I

ON

/N

LO ps

I /N

O

ps

4I

4I /N

LO PS

Pri

4I /N

LO PS

4I

Pri

I

LMag

0

4I

LMag

4I

LMag

Ipri

图8-8. Main Converter Operating Waveforms

The resistor R₁is used to set the slope compensation magnitude. In LM5036 device, the slope of the

compensation ramp is given by 方程式 66. To eliminate sub-harmonic oscillation, set m_Cto at least one-half the

down-slope of output inductor current transformed to the primary side across the current sense resistor, as given

by 方程式 67 and 方程式 68. To damp the sub-harmonic oscillation after one cycle, m_Cmust be set equal to one

times the down-slope of the output inductor current. This configuration is known as deadbeat control. In LM5036

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controller, the slope compensation signal is a saw-tooth current waveform of magnitude I_SLOPEat the oscillator

frequency (twice the switching frequency).

m_C= I_SLOPEì f_OSCìR₁

where

(66)

• m_Cis the slope of the compensation ramp

• I_SLOPEis the amplitude of the saw-tooth current signal used for slope compensation

V_O

1

mV

m_L=

ì

ìR_CS= 9.57

L_ON_PS

ms

(67)

where

• m_Lis the down-slope of the output inductor current transformed to the primary side

• N_Pis the number of turns for the primary winding of the main transformer

• N_Sis the number of turns for the secondary winding of the main transformer

• V_Ois the output voltage of the half-bridge converter

• L_Ois the output inductor value of the half-bridge converter

• R_CSis the current sense resistor value

1

m_C> × m_L

2

(68)

Substituting 方程式66 and 方程式67 into 方程式68 gives an expression for the minimum value for resistor R₁to

avoid sub-harmonic oscillation.

V_O

1

2

1

R₁>

ì

ìR_CS

ì

= 221- W

L_ON_PS

I_SLOPEì f_OSC

(69)

Doubling this value ensures deadbeat control. For this example design, the value given in 方程式 70 are

selected

R₁= 576 W

(70)

Values have now been selected for both R_CSand R₁. Values for R_LIMand R₂are yet to be determined. These

values define the peak current limit threshold and how this level varies with input voltage. 方程式 20, 方程式 21

and 方程式 25 define the relationship between peak primary current limit and maximum output current. For this

design example ignore I_BiasOffsetand V_CSOffset, because these parameters have only a small effect on output

current limit. Setting these parameters to zero calculates 方程式71, 方程式72 and 方程式73.

»

ÿ

Ÿ

V_O

V_OìN_PS

2ìL_Magìf_{OSC Ÿ}

I_OV ,R_LIM,R₂= N ì I

V ,R_LIM,R₂

-

ì 1-D -

(

)

(

)

(

)

…

IN

PS

PriCBC

IN

2ìL_Oìf_OSCìN_PS

⁄

(71)

(72)

≈

’

≈

’

V_{CS_ CBCTh}(V ,R_LIM,R₂)

V

V_O

1

2

IN

∆

«

÷

◊

I_PriCBCV ,R_LIM,R₂

(

=

)

+ t_CSLSG

ì

+

-

∆

«

÷

◊

IN

2

R_CS

L_Mag

L_OìN_PS

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≈

’

÷

K

V

IN

V_{CS_ CBCTh}(V ,R_LIM,R ) = R ì ^CBC1-I_SLOPEìD -

∆

IN

2

1

R_LIM

R_{2 ◊}

«

(73)

The output current limit varies with input voltage. This design example limits the output current to I_LIMat the

extremes of input voltage giving 方程式 74 and 方程式 75. This value limits the spread of output current limit

across the range of input voltage.

I_O

V

_IN(min),R_LIM,R₂= I

(

)

LIM

(74)

(75)

I_O

V_IN(max),R_LIM,R₂= I

(

)

LIM

Solving 方程式74 and 方程式75 simultaneously yields values for resistors R_LIMand R₂.

1

R₂=

= 2.32 - MW

2

≈

’

≈

’

t

R_CS

V_O

R_CS

1

^CSLSGì

ì

+

-

ì

-I_SLOPEì 2ì V_OìN_PS

∆

«

÷

◊

∆

«

÷

◊

2

R₁ìN_PS

L_Mag

V

_IN(min)ì V

L_Oìf_OSCR₁

L_OìN_PS

IN(max)

(76)

(77)

K_CBC1

R_LIM

=

= 55.2 - kW

»

ÿ

Ÿ

≈

’

»

…

ÿ

Ÿ

V

IN(min)

R_CS

R₁

I_LIM

V_O

2ì V_OìN_PS

V_OìN_PS

2ìL_Magìf_OSC

t

V_O

2ì V_OìN_PS

IN(min)

ì

+

ì 1-

+

-

^CSLSGì

+

-

+I_SLOPEì

+

…

∆

÷

◊

2

∆

N

2ìL_OìN_PSìf_OSC

V

N_PS

2ìL_Mag

L_OìN_{PS Ÿ}

V

R₂

2ìL_OìN_PS

Ÿ

⁄

PS

IN(min)

«

⁄

Having determined values for R₁and R₂, the value of resistor R₃is fixed by 方程式13.

The selected values for R₂and R_LIMare given in 方程式78. 图8-9 presents the measured output current limit vs

input voltage for the circuit presented in 图 8-1. 图 8-9 also presents the output current limit vs line for the same

circuit predicted by 方程式 71, 方程式 72 and 方程式 73. There is good agreement between measured and

predicted results.

R₂= 1.96 MW

R_LIM= 56.2 kW

(78)

10.2

ILIM Calculated

ILIM Measured

10.1

10

9.9

9.8

9.7

9.6

9.5

9.4

9.3

36

41

46

51

56

61

Input Voltage (V)

66

71

76

D002

图8-9. Main Converter Measured vs Predicted Output Current Limit

If the magnitude of the leading-edge spike is excessive, add an additional filter capacitor C_Fto form an RC filter

with R₁, to reduce the high-frequency noise spike. Both the leading-edge blanking (t_CSBLK) and the RC filter help

to prevent false triggering of the CBC current limiting operation.

The circuit connected to the CS_POS pin may be approximated by the simplified circuit shown in 图8-10.

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I (t)

Pri

I (t) x R

Pri CS

R

1

V

CF

(t)

CS_POS

C

F

PGND

图8-10. CS_POS Filter Circuit Model and Waveform

The voltage across the current sense resistor during the conduction period of the low-side MOSFET is

represented by 方程式79.

I_Prit ìR = I + mì t ìR

( )

(

)

CS

P0

CS

(79)

Where I_P0is the primary current at the start of the on period of the lower switch, and m is the slope of the

primary current during the on period.

I_O

DI_LO

N_PS

I_P0

=

- DI_LMag

-

N_PS

(80)

(81)

V

IN(max)

≈

∆

«

’

÷

◊

1

IN(max)

m =

- V_O

ì

+

2ìN_PS

L_OìN_PS2ìL_Mag

The voltage across capacitor C_Ffor the circuit shown is expressed by 方程式82.

-t

C_FìR₁

»

…

ÿ

Ÿ

≈

∆

’

÷

V_CFt = R_CSì

( )

I

_P0-mìC_FìR₁ì 1- e

+ mì t

(

)

∆

÷

Ÿ

⁄

«

◊

(82)

Let us assume that the on period of the lower switch is more than four times longer than the time constant made

up of C_Fand R₁. In this case the exponential term of 方程式 82 tends to zero and the voltage across capacitor

C_Fat the end of the t_ONperiod may be expressed by 方程式83.

V_CF

t

= R ì I - mìC_FìR₁+ mì t_ON

(

)

[

]

ON

CS

P0

(83)

Comparing 方程式 79 and 方程式 83 shows that capacitor C_Fintroduces an error in the sensed peak current

given by 方程式84.

»

…

_IN(max)ÿ

V

≈

∆

«

’

÷

◊

1

IN(max)

- V_O

ì

+

ìC ìR

Ÿ

F

1

2ìN_PS

L_OìN_PS2ìL_{Mag Ÿ}

I_LIM

V_CS

t

- V

t

(

)

(

CF ON

)

mìC_FìR₁

I_LIM

ON

⁄

ErrCF =

=

I_LIM

ìR_CS

N_PS

(84)

Hence, to ensure the error introduced by the filter capacitor is less than 2%, the value of capacitor C_Fshould not

exceed the value given by 方程式85.

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0.02ìI_LIM

C_FÇ

= 84 - pF

»

≈

_IN(max)ÿ

V

’

÷

◊

1

IN(max)

- V_O

ì

+

ìR ìN

Ÿ

1 PS

…

∆

«

2ìN_PS

L_OìN_PS2ìL_{Mag Ÿ}

⁄

(85)

The Excel Calculator Tool can be used to facilitate the process of calculating all the external CBC component

values.

8.2.2.12 Auxiliary Transformer

A coupled inductor or a flyback-type transformer is required for this fly-buck topology auxiliary supply. Energy is

transferred from primary to secondary when the low-side SR MOSFET is conducting.

The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary output

voltage. In this design example, the two outputs are set to be equal and a 1:1 turns ratio transformer is selected,

i.e., N₂/N₁= 1. The primary output voltage is normally selected based on the input voltage range such that the

duty cycle of the converter does not exceed 50% at the minimum input voltage. This condition is satisfied if

V_AUX1< V_IN(min)/ 2.

Use 方程式86 to calculate the maximum inductor current ripple amplitude ΔI_{L (AUX)}that can be tolerated without

exceeding the peak current limit threshold I_AUX(LIM)(200-mA typical) of the high-side switch,

≈

’

÷

N₂

DI_L(AUX)= I_AUX(LIM)-I_AUX1-I_AUX2

ì

∆

N_{1 ◊}

«

(86)

where

• I_AUX1is the primary output current, and I_AUX2is the secondary output current of the auxiliary supply,

respectively.

In this design example, the maximum total output current I_AUX(max)of the auxiliary supply referred to the primary

side is 100-mA, as given by 方程式87.

N₂

I_{AUX (max )}= I_AUX1+ I_AUX2

×

= 0.1 A

N₁

(87)

Therefore, ΔI_L(AUX)= 0.1-A. Use 方程式88 to calculate the minimum inductor value for the auxiliary supply.

≈

∆

«

’

K_ONìR_ON

2ì DI_L(AUX)

V_AUX1

L_AUX

í

ì 1-

= 88 -mH

∆

÷

◊

V

IN(max)

(88)

Select a higher value of 150-µH to ensure the high-side switch current doesn’t exceed the minimum peak

current limit threshold.

8.2.2.13 Auxiliary Feedback Resistors

The two feedback resistors are selected to set the primary output voltage V_AUX1of the auxiliary supply. The

internal reference for the off-state and on-state auxiliary output voltage levels are V_AUX-OFF(1.4-V typical) and

V_AUX-ON(1-V typical). The feedback resistors are calculated such that both of the off-state and on-state auxiliary

output voltage fall into the recommended operating range (8.5-V to 14-V). In this design example, the off-state

and on-state auxiliary output voltages are set to 11.9-V and 8.5-V, respectively. R_FB2is selected to be 1-kΩ and

R_FB1is calculated to be 7.5-kΩ according to 方程式 89. Note that it is the valley of the output voltage that is

regulated at the reference value. Therefore the average output voltage is greater than the reference value due to

the ripple injected to the feedback node.

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≈

’

÷

R_FB1

V_AUX1-ON= V_AUX-ONì 1+

∆

R_{FB2 ◊}

«

(89)

8.2.2.14 R_ONResistor

Use 方程式 31 to calculate the value of R_ONrequired to achieve the desired switching frequency for the auxiliary

supply. Make sure that the calculated R_ONvalue is greater than the minimum value required by 方程式 40. For

this design example where on-state V_AUX1is 8.5-V and target f_{SW_AUX}is 500-kHz, the calculated value of R_ONis

189-kΩ. The minimum recommended value calculated using 方程式 40 is 209-kΩ. A standard value of 220-kΩ

is selected to satisfy this minimum R_ONrequirement giving and actual switching frequency (f_{SW_AUX}) of 430-kHz.

8.2.2.15 VIN Pin Capacitor

Place the required bypass capacitor close to the VIN pin of the LM5036 device. Ensure that the capacitance is

large enough to limit the ripple of the VIN pin voltage to a desired level. Use 方程式 90 to calculate the value of

C_INrequired to meet the ripple voltage ∆V_INrequirement.

I_{AUX max}

:

;

C_IN

R

4 × f_{SW_AUX}× ¿V

IN

(90)

Choosing a value of 0.5-V for ∆V_INyields a minimum C_INvalue of 0.12-µF. Select the standard value of 0.1-µF

for this design. Ensure that the voltage rating of the input capacitor is greater than the maximum input voltage

under all conditions.

8.2.2.16 Auxiliary Primary Output Capacitor

The output capacitor value (C_AUX1), needed to achieve our target output ripple amplitude (ΔV_AUX1Cap= 25-mV),

may be calculated using 方程式 94.Highest ripple voltage will be observed if all the Aux current is drawn from

V_AUX2(I_AUX2=I_AUX(max)). In this case a capacitor value of 1.1-µF is required to limit capacitive ripple voltage

amplitude to 25-mV. A standard 1-µF, 25-V capacitor is selected for this design.

8.2.2.17 Auxiliary Secondary Output Capacitor

A simplified waveform for the secondary winding current I_{L_SEC}is shown in 图8-11.

I

L_SEC

I

AUX2

0 A

Time

图8-11. Auxiliary Transformer Secondary Winding Current Waveforms for C_AUX2Ripple Calculation

The secondary output current I_AUX2is sourced by C_AUX2during on-time of the high-side switch, t_ON. Ignoring the

current transition times in the secondary winding, the secondary output capacitor ripple voltage amplitude can be

calculated using 方程式91.

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I_AUX2ì t_ON(max)

DV_AUX2Cap

=

2ìC_AUX2

(91)

For a 1:1 auxiliary transformer turns ratio, the primary and secondary voltage ripple equations are identical.

Therefore, C_AUX2is chosen to be equal to C_AUX1(1 µF) to achieve comparable ripple voltages on the primary

and secondary outputs.

8.2.2.18 Auxiliary Feedback Ripple Circuit

The auxiliary feedback ripple circuit employed is presented in 图 7-27. Having selected appropriate values for

R_ONin 节 8.2.2.14 and R_FBxin 节 8.2.2.13, the value of C_rrequired can be calculated using 方程式 47. For our

design we have opted to use a standard value C_r= 1-nF.

R_FB1+ R_FB2

2ì p ì f_{SW _ AUX}R_FB1ìR_FB2

3

C_r>

ì

= 1.3 - nF

(92)

Based on our target output ripple specification a value for the primary output capacitor (C_AUX1= 1-µF) was

chosen in 节 8.2.2.16. The primary output ripple voltage V_AUX1Capcan be calculated using 方程式 94. Since the

value of V_AUX1Capis already greater than 25-mV there is no danger that we will fail to meet the requirement of 方

程式 46. Hence the value of R_rneeded to ensure stable operation is calculated using 方程式 48. For our design

example a value of 46.4-kΩhas been selected.

≈

∆

«

’

K_ONìR_ON

10 ìC_rì DV_AUX1Cap

V_AUX1

R_rÇ

ì 1-

= 55 - kW

∆

÷

◊

V

IN(min)

(93)

The minimum value of C_acis determined using 方程式49. The precise value of this component is not very critical

and for our design example we selected a convenient value of C_ac= 100-nF.

C_ací 5ìC_r= 5 -nF

(94)

8.2.2.19 Auxiliary Secondary Diode

Use 方程式 95 to calculate the reverse voltage across secondary rectifier of the auxiliary supply when the high-

side switch is on.

N₂

V_D=

× V

IN(max )

N₁

(95)

For a maximum input voltage of 75-V and the 1:1 turns ratio of this design, select a schottky diode with a rating

of 75-V or higher.

8.2.2.20 VCC Diode

A diode must be connected between the primary output V_AUX1and the VCC pin. When V_AUX1is more than one

diode voltage drop greater than the internal VCC voltage, the VCC bias current is supplied from V_AUX1. This

results in reduced power losses in the internal VCC regulator, especially at high input voltage.

8.2.2.21 Opto-Coupler Interface

图 8-12 illustrates the opto-coupler interface for the main feedback control loop. The primary side of the opto-

coupler is biased with V_REFvoltage from LM5036 device. R_OPTOshould be selected such that with the minimum

error amplifier output, the comp current flowing into the COMP pin of the device is greater than I_PWM-OS(800-µA

typical) which corresponds to zero duty cycle, as given by 方程式96.

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V_b

V_REF

R_OPTO

COMP

V_O

V_e

+

V_REFSec

SGND

图8-12. Opto-Coupler Interface

V_b- V_f- V_e

R_opto

I_COMP

=

ìCTR

(96)

where

• V_bis the bias supply for the error amplifier and opto-coupler on the secondary side

• V_fis the diode forward voltage drop of the opto-coupler LED

• V_eis the error amplifier output

• CTR is the current transfer ratio of the opto-coupler

• I_COMPis the comp current flowing into the COMP pin

• V_REF(5-V typical) is the reference of LM5036 device

8.2.2.22 Full-Bridge Converter Applications

While LM5036 device is optimized for half-bridge applications, it can also be used for full-bridge applications.

External gate drivers are needed to support an additional pair of FETs in full-bridge configuration. In addition, a

DC-blocking capacitor is required to ensure voltage-second balance of the main transformer with the voltage-

mode control of LM5036 device. Only one phase current information is needed for current protection in the full-

bridge applications.

8.2.3 Application Curves

100%

95%

90%

85%

80%

75%

70%

65%

60%

V_IN= 36 V

V_IN= 48 V

V_IN= 75 V

55%

50%

0

1

2

3

4

5

Load Current (A)

6

7

8

D001

f_SW= 200-kHz

V_O= 12 V

V_IN= 48-V

I_O= 8-A

V_O= 12-V

图8-13. Efficiency

图8-14. Steady State Operation Waveform

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9 Power Supply Recommendations

The power converter controlled by LM5036 device can have considerable current level. Care should be taken

that components with the correct current rating are chosen. This includes magnetic components, power

MOSFETS and diodes, connectors and wire sizes. Input and output capacitors should have the correct ripple

current rating.

The recommended maximum input voltage for the VIN pin of LM5036 device is 100-V. The recommended

voltage for the VCC pin is between 8.5-V and 14-V. Both VCC pin and REF pin must be locally decoupled with a

ceramic capacitor. The recommended range of values is 0.47-µF to 10-µF for VCC pin, and 0.1-µF to 10-µF for

REF pin. To reduce the power consumption of the internal VCC regulator, an external bias supply can be

connected to VCC pin through a diode.

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10 Layout

10.1 Layout Guidelines

• The two ground planes (AGND and PGND) of LM5036 device should be tied together with a short and direct

connection to avoid jitter due to relative ground bounce. The connection point could be at the negative

terminal of the input power supply.

• The VIN, VCC, REF pin capacitors, and CS_NEG resistor should be tied to PGND plane. UVLO, ON_OFF,

RT, RON, RD1 and RD2 resistors, RAMP, RES, SS and SSSR capacitors, and the thermal pad should all be

tied to AGND plane.

• SW and SW_AUX are switching nodes which switch rapidly between VIN and GND every cycle which are

sources of high dv/dt noise. Therefore, large SW/SW_AUX node area should be avoided.

• The differential current sense signals at CS_POS and CS_NEG pins should be routed in parallel and close to

each other to minimize the common-mode noise.

• The area of the loop formed by the main feedback control signal traces (COMP and REF) should be

minimized in order to reduce the noise pick up. This can be accomplished by placing the COMP and REF

signal traces on top of each other in adjacent PCB layers. In addition, the main feedback control signal traces

should be routed away from the SW_AUX switching node to avoid high dv/dt noise coupling.

• The gate drive outputs (LSG and HSG) should have short and direct paths to the power MOSFETs to

minimize parasitic inductance in the gate driving loop.

• The VCC and REF decoupling capacitors should be placed close to their respective pins with short trace

inductance. Low ESR and ESL ceramic capacitors are recommended for the boot-strap, VCC and the REF

capacitors.

• A decoupling capacitor should be placed close to the IC, directly across VIN and PGND pins. The

connections to these two pins should be direct to minimize the loop area which carries switching currents.

• The boot-strap capacitors required for the high-side gate drivers of the half-bridge converter and auxiliary

supply should be located close to the IC and connected directly to the BST/BST_AUX and SW/SW_AUX

pins.

• The area of the switching loop of the power stage consisting of input capacitor, capacitive divider,

transformer, and the primary MOSFETs should be minimized.

10.2 Layout Example

See 图10-1 for an example layout that matches the schematic of 图8-1.

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图10-1. LM5036 PCB Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5036 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation

11.2.1.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

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11-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM5036RJBR

LM5036RJBT

WQFN

RJB

28

3000

250

330.0

180.0

12.4

5.25

1.1

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM5036RJBR

LM5036RJBT

WQFN

RJB

28

3000

250

367.0

213.0

367.0

191.0

38.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RJB0028A

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

6

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

0.65

0.45

5.1

4.9

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

3.4 0.1

2X 3

A3

SYMM

(0.2) TYP

4X ( 0.325)

A2

8

14

24X 0.5

7

15

(2.138) TYP

29

SYMM

2X

3

EXPOSED

THERMAL PAD

1

21

SEE TERMINAL

DETAIL

0.3

28X

0.2

A4

0.1

C A B

A1

28

22

0.05

0.65

0.45

PIN 1 ID

(OPTIONAL)

28X

(2.138) TYP

4223149/A 08/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RJB0028A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(2.138) TYP

22

28

4X ( 0.325)

28X (0.75)

28X (0.25)

1

21

(2.138)

TYP

24X (0.5)

29

SYMM

(4.65)

(1.45)

TYP

(R0.05)

TYP

7

15

(

0.2) TYP

VIA

8

14

(

3.4)

(4.65)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223149/A 08/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RJB0028A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(2.138) TYP

22

4X ( 1.47)

28

4X ( 0.325)

28X (0.75)

28X (0.25)

29

1

21

(2.138)

TYP

24X (0.5)

SYMM

(4.65)

(0.835)

TYP

(R0.05) TYP

15

7

METAL

TYP

8

14

(0.835) TYP

(4.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 29:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:18X

4223149/A 08/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	LM5036
厂家：	TEXAS INSTRUMENTS
描述：	具有集成辅助偏置电源和稳压预偏置启动的半桥 PWM 控制器控制器
文件：	总69页 (文件大小：3648K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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