LM5100BMAX [TI]
3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers; 3A ， 2A和1A高电压高侧和低侧栅极驱动器
| 型号： | LM5100BMAX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers |
| 文件： | 总28页 (文件大小：1319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
LM5100A/B/C
LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers
Check for Samples: LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
1
FEATURES
DESCRIPTION
The LM5100A/B/C and LM5101A/B/C High Voltage
Gate Drivers are designed to drive both the high-side
2
•
Drives Both a High-side and Low-side N-
Channel MOSFETs
and the low-side N-Channel MOSFETs in
a
•
•
•
•
Independent High and Low Driver Logic Inputs
Bootstrap Supply Voltage up to 118V DC
Fast Propagation Times (25 ns Typical)
synchronous buck or a half-bridge configuration. The
floating high-side driver is capable of operating with
supply voltages up to 100V. The “A” versions provide
a full 3A of gate drive while the “B” and “C” versions
provide 2A and 1A respectively. The outputs are
independently controlled with CMOS input thresholds
Drives 1000 pF Load with 8 ns Rise and Fall
Times
•
Excellent Propagation Delay Matching (3 ns
typical)
(LM5100A/B/C)
or
TTL
input
thresholds
(LM5101A/B/C). An integrated high voltage diode is
provided to charge the high-side gate drive bootstrap
capacitor. A robust level shifter operates at high
speed while consuming low power and providing
clean level transitions from the control logic to the
high-side gate driver. Under-voltage lockout is
provided on both the low-side and the high-side
power rails. These devices are available in the
standard SOIC-8 pin, SO PowerPad-8 pin and the
WSON-10 pin packages. The LM5100C and
LM5101C are also available in MSOP-PowerPad-8
package. The LM5101A is also available in WSON-8
pin package.
•
•
•
Supply Rail Under-voltage Lockout
Low Power Consumption
Pin Compatible with HIP2100/HIP2101
TYPICAL APPLICATIONS
•
•
•
•
•
Current Fed Push-pull Converters
Half and Full Bridge Power Converters
Synchronous Buck Converters
Two Switch Forward Power Converters
Forward with Active Clamp Converters
Package
•
•
•
•
•
SOIC-8
SO PowerPad-8
WSON-8 (4 mm x 4 mm)
WSON-10 (4 mm x 4 mm)
MSOP-PowerPad-8
Simplified Block Diagram
HB
HO
UVLO
DRIVER
LEVEL
SHIFT
HS
HI
VDD
UVLO
LO
LI
DRIVER
VSS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
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Table 1. Input/Output Options
Part Number
LM5100A
LM5101A
LM5100B
LM5101B
LM5100C
LM5101C
Input Thresholds
Peak Output Current
CMOS
TTL
3A
3A
2A
2A
1A
1A
CMOS
TTL
CMOS
TTL
Connection Diagrams
VDD
HB
1
2
3
4
8
7
6
5
LO
VSS
LI
VDD
HB
LO
1
2
3
4
8
7
6
5
VSS
SOIC-8
WSON-8
HO
HS
LI
HO
HS
HI
HI
LO
VSS
LI
VDD
1
10
LO
1
8
VDD
HB
2
3
4
5
9
HB
HO
HS
NC
7
6
5
VSS
LI
2
3
4
8
7
6
WSON-10
SO
PowerPad-8
HI
HO
HS
NC
HI
Exposed Pad
Connect to VSS
VDD
HB
LO
VSS
MSOP-
PowerPad-8
HO
HS
LI
HI
PIN DESCRIPTIONS(1)
Pin #
SO
MSOP-
Name
Description
Application Information
WSON-
8(1)
WSON-
10(1)
SOIC-8 Power
Pad-8
PowerPad
-8(1)
Positive gate
drive supply
Locally decouple to VSS using low ESR/ESL
capacitor located as close to the IC as possible.
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
VDD
HB
Connect the positive terminal of the bootstrap
capacitor to HB and the negative terminal to HS. The
bootstrap capacitor should be placed as close to the
IC as possible.
High-side gate
driver bootstrap
rail
High-side gate
driver output
Connect to the gate of high-side MOSFET with a
short, low inductance path.
HO
(1) Note: For WSON-8, WSON-10 and MSOP-PowerPad-8 package, it is recommended that the exposed pad on the bottom of the
package is soldered to ground plane on the PC board, and that ground plane should extend out from beneath the IC to help
dissipate heat. For WSON-10 package, pins 5 and 6 have no connection.
2
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
PIN DESCRIPTIONS(1) (continued)
Pin #
SO
MSOP-
Name
Description
Application Information
WSON-
WSON-
10(1)
SOIC-8 Power
Pad-8
PowerPad
8(1)
-8(1)
High-side
MOSFET
source
Connect to the bootstrap capacitor negative terminal
and the source of the high-side MOSFET.
4
5
6
4
5
6
4
4
7
8
4
5
6
HS
HI
LI
connection
The LM5100A/B/C inputs have CMOS type
High-side driver thresholds. The LM5101A/B/C inputs have TTL type
control input
5
6
thresholds. Unused inputs should be tied to ground
and not left open.
The LM5100A/B/C inputs have CMOS type
Low-side driver thresholds. The LM5101A/B/C inputs have TTL type
control input
thresholds. Unused inputs should be tied to ground
and not left open.
7
8
7
8
7
8
9
7
8
VSS
LO
Ground return
All signals are referenced to this ground.
Low-side gate
driver output
Connect to the gate of the low-side MOSFET with a
short, low inductance path.
10
EP (WSON and SO
PowerPad and MSOP-
PowerPad packages)
Solder to the ground plane under the IC to aid in heat
dissipation.
EP
EP
EP
EP
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
VDD to VSS
−0.3V to +18V
−0.3V to +18V
−0.3V to VDD +0.3V
−0.3V to VDD +0.3V
HS −0.3V to VHB +0.3V
−5V to +100V
118V
HB to HS
LI or HI Input
LO Output
HO Output
V
(3)
HS to VSS
HB to VSS
Junction Temperature
Storage Temperature Range
+150°C
−55°C to +150°C
2 kV
(4)
ESD Rating HBM
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not
exceed -1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage
transiently. If negative transients occur, the HS voltage must never be more negative than VDD-15V. For example if VDD = 10V, the
negative transients at HS must not exceed -5V.
(4) The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2,
Pin 3 and Pin 4 which are rated at 1000V for HBM. Machine Model (MM) ratings are : 100V(MM) for Options B and C; 50V(MM) for
Option A.
Recommended Operating Conditions
VDD
+9V to +14V
−1V to 100V
HS
HB
VHS +8V to VHS +14V
< 50 V/ns
HS Slew Rate
Junction Temperature
−40°C to +125°C
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
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Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD
=
(1)
VHB = 12V, VSS = VHS = 0V, No Load on LO or HO
.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current, LM5100A/B/C
VDD Quiescent Current, LM5101A/B/C
VDD Operating Current
LI = HI = 0V
0.1
0.25
2.0
0.2
0.4
3
mA
LI = HI = 0V
f = 500 kHz
LI = HI = 0V
f = 500 kHz
HS = HB = 100V
f = 500 kHz
IDDO
IHB
mA
mA
mA
µA
Total HB Quiescent Current
0.06
1.6
0.2
3
IHBO
IHBS
IHBSO
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
0.1
10
0.4
mA
INPUT PINS
VIL
Input Voltage Threshold LM5100A/B/C
Rising Edge
Rising Edge
4.5
1.3
5.4
1.8
500
50
6.3
2.3
V
VIL
Input Voltage Threshold LM5101A/B/C
Input Voltage Hysteresis LM5100A/B/C
Input Voltage Hysteresis LM5101A/B/C
Input Pulldown Resistance
V
VIHYS
VIHYS
RI
mV
mV
kΩ
100
6.0
5.7
200
400
7.4
7.1
UNDER VOLTAGE PROTECTION
VDDR
VDDH
VHBR
VHBH
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
6.9
0.5
6.6
0.4
V
V
V
V
HB Threshold Hysteresis
BOOT STRAP DIODE
VDL
VDH
RD
Low-Current Forward Voltage
High-Current Forward Voltage
IVDD-HB = 100 µA
IVDD-HB = 100 mA
0.52
0.8
0.85
1
V
V
Ω
Dynamic Resistance LM5100A/B/C, LM5101A/B/C IVDD-HB = 100 mA
1.0
1.65
LO & HO GATE DRIVER
VOL
VOH
IOHL
IOLL
Low-Level Output Voltage LM5100A/LM5101A
IHO = ILO = 100 mA
0.12
0.16
0.28
0.24
0.28
0.60
3
0.25
0.4
Low-Level Output Voltage LM5100B/LM5101B
Low-Level Output Voltage LM5100C/LM5101C
High-Level Output Voltage LM5100A/LM5101A
High-Level Output Voltage LM5100B/LM5101B
High-Level Output Voltage LM5100C/LM5101C
Peak Pullup Current LM5100A/LM5101A
Peak Pullup Current LM5100B/LM5101B
Peak Pullup Current LM5100C/LM5101C
Peak Pulldown Current LM5100A/LM5101A
Peak Pulldown Current LM5100B/LM5101B
Peak Pulldown Current LM5100C/LM5101C
V
V
A
A
0.65
0.45
0.60
1.10
IHO = ILO = 100 mA
VOH = VDD– LO or
VOH = HB - HO
HO, LO = 0V
2
1
HO, LO = 12V
3
2
1
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD
=
VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1)
.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
THERMAL RESISTANCE
SOIC-8
WSON-8(3)
170
40
40
40
80
(2)
(3)
θJA
Junction to Ambient
WSON-10
°C/W
SO PowerPad-8
MSOP-PowerPad-8
(3)
(2) The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
(3) 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See Application Note AN-1187.
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
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Switching Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD
=
(1)
VHB = 12V, VSS = VHS = 0V, No Load on LO or HO
.
Symbol
tLPHL
Parameter
Conditions
Min
Typ
Max
45
Units
LO Turn-Off Propagation Delay
LM5100A/B/C
LI Falling to LO Falling
LI Rising to LO Rising
HI Falling to HO Falling
HI Rising to HO Rising
20
ns
LO Turn-Off Propagation Delay
LM5101A/B/C
22
20
26
20
22
20
26
1
56
45
56
45
56
45
56
10
10
10
10
tLPLH
tHPHL
tHPLH
tMON
tMOFF
LO Turn-On Propagation Delay
LM5100A/B/C
ns
ns
LO Turn-On Propagation Delay
LM5101A/B/C
HO Turn-Off Propagation Delay
LM5100A/B/C
HO Turn-Off Propagation Delay
LM5101A/B/C
LO Turn-On Propagation Delay
LM5100A/B/C
ns
ns
LO Turn-On Propagation Delay
LM5101A/B/C
Delay Matching: LO on & HO off
LM5100A/B/C
Delay Matching: LO on & HO off
LM5101A/B/C
4
Delay Matching: LO off & HO on
LM5100A/B/C
1
ns
ns
ns
Delay Matching: LO on & HO off
LM5101A/B/C
4
8
tRC, tFC
tR
Either Output Rise/Fall Time
CL = 1000 pF
CL = 0.1 µF
Output Rise Time (3V to 9V)
LM5100A/LM5101A
430
Output Rise Time (3V to 9V)
LM5100B/LM5101B
570
990
260
430
715
50
Output Rise Time (3V to 9V)
LM5100C/LM5101C
tF
Output Fall Time (3V to 9V)
LM5100A/LM5101A
CL = 0.1 µF
Output Fall Time (3V to 9V)
LM5100B/LM5101B
ns
Output Fall Time (3V to 9V)
LM5100C/LM5101C
tPW
tBS
Minimum Input Pulse Width that Changes
the Output
ns
ns
Bootstrap Diode Reverse Recovery Time
IF = 100 mA,
IR = 100 mA
37
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
Typical Performance Characteristics
Peak Sourcing Current
Peak Sinking Current
vs
vs
VDD
VDD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
LM5100A/LM5101A
LM5100A/LM5101A
LM5100B/LM5101B
LM5100C/LM5101C
LM5100B/LM5101B
LM5100C/LM5101C
0.5
0.0
0.5
0.0
7
8
9
10 11 12 13 14 15
VDD (V)
7
8
9
10 11 12 13 14 15
VDD (V)
Figure 1.
Figure 2.
Sink Current
vs
Output Voltage
Source Current
vs
Output Voltage
3.5
3.0
2.5
2.0
1.5
1.0
3.5
3.0
2.5
2.0
1.5
1.0
V
= 12V
DD
V
= 12V
DD
LM5100A/LM5101A
LM5100A/LM5101A
LM5100B/LM5101B
LM5100B/LM5101B
LM5100C/LM5101C
LM5100C/LM5101C
0.5
0.0
0.5
0.0
0
2
4
8
10
12
6
0
2
4
8
10
12
6
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 3.
Figure 4.
LM5100A/B/C IDD
vs
LM5101A/B/C IDD
vs
Frequency
Frequency
100000
10000
1000
100000
10000
1000
100
V
= 12V
DD
V
DD
= 12V
C
= 4400 pF
L
C
L
= 4400 pF
C
= 1000 pF
L
C
= 1000 pF
L
C
= 0 pF
L
C
L
= 0 pF
100
0.1
10
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 5.
Figure 6.
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
Operating Current
vs
IHB
vs
Temperature
Frequency
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
100000
10000
1000
100
HB = 12V,
HS = 0V
I
(LM5101A/B/C)
DDO
C
= 4400 pF
L
I
(LM5100A/B/C)
DDO
C
L
= 1000 pF
I
HBO
C
= 0 pF
L
10
-50 -25
0
25 50 75 100 125 150
0.1
1
10
100
1000
TEMPERATURE (oC)
FREQUENCY (kHz)
Figure 7.
Figure 8.
Quiescent Current
vs
Supply Voltage
Quiescent Current
vs
Temperature
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
I
(LM5101A/B/C)
DD
I
(LM5101A/B/C)
DD
I
(LM5100A/B/C)
DD
I
(LM5100A/B/C)
DD
I
HB
I
HB
0
0
-50 -25
0
25 50 75 100 125 150
8
9
10 11 12 13 14 15 16
, V (V)
TEMPERATURE (°C)
V
DD HB
Figure 9.
Figure 10.
Undervoltage Rising Thresholds
Undervoltage Threshold Hysteresis
vs
vs
Temperature
Temperature
0.60
7.30
7.20
7.10
7.00
6.90
6.80
6.70
6.60
6.50
6.40
6.30
0.55
0.50
0.45
0.40
0.35
0.30
V
DDH
V
DDR
V
HBH
V
HBR
-50 -25 0_ 25 50_ 75_100_125_150_
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (oC)
TEMPERATURE (°C)
Figure 11.
Figure 12.
8
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
Typical Performance Characteristics (continued)
LM5100A/B/C Input Threshold
vs
Bootstrap Diode Forward Voltage
Temperature
1.00E-01
50
49
48
47
46
45
44
43
42
41
40
T = 150°C
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06
Rising
T = 25°C
Falling
T = -40°C
-50 -25
0
25 50 75 100 125 150
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
TEMPERATURE (°C)
V
(V)
D
Figure 13.
Figure 14.
LM5101A/B/C Input Threshold
LM5100A/B/C Input Threshold
vs
vs
Temperature
VDD
1.92
1.91
1.90
1.89
1.88
1.87
1.86
1.85
1.84
1.83
1.82
1.81
1.80
50
49
48
47
46
45
44
43
42
41
40
Rising
Rising
Falling
Falling
8
9
10 11 12 13 14 15 16
VDD (V)
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
Figure 15.
Figure 16.
LM5101A/B/C Input Threshold
LM5100A/B/C Propagation Delay
vs
vs
VDD
Temperature
1.92
1.91
35
30
25
20
15
1.90
1.89
1.88
1.87
1.86
Rising
1.85
1.84
T_PLH
T_PHL
Falling
1.83
1.82
1.81
1.80
8
9
10 11 12 13 14 15 16
VDD (V)
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
Figure 17.
Figure 18.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
LM5101A/B/C Propagation Delay
LO & HO Gate Drive - High Level Output Voltage
vs
vs
Temperature
Temperature
1.0
40
35
30
25
V
= 12V
DD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
LM5100C/LM5101C
T_PLH
LM5100B/LM5101B
T_PHL
LM5100A/LM5101A
20
15
0.0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19.
Figure 20.
LO & HO Gate Drive - Low Level Output Voltage
LO & HO Gate Drive - Output High Voltage
vs
Temperature
0.50
vs
VDD
0.8
V
= 12V
DD
I
= -100 mA
OUT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.7
0.6
0.5
0.4
0.3
0.2
0.1
LM5100C/LM5101C
LM5100C/LM5101C
LM5100B/LM5101B
LM5100B/LM5101B
LM5100A/LM5101A
LM5100A/LM5101A
0.00
-50 -25
0
25 50 75 100 125 150
7
8
9
10 11 12 13 14 15
VDD (V)
TEMPERATURE (°C)
Figure 21.
Figure 22.
LO & HO Gate Drive - Output Low Voltage
vs
VDD
0.35
I
= 100 mA
OUT
0.30
0.25
0.20
0.15
0.10
LM5100C/LM5101C
LM5100B/LM5101B
LM5100A/LM5101A
7
8
9
10 11 12 13 14 15
VDD (V)
Figure 23.
10
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Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
TIMING DIAGRAM
LI
LI
HI
HI
t
HPLH
t
LPLH
t
HPHL
t
LPHL
LO
LO
HO
HO
t
t
MOFF
MON
Figure 24.
Layout Considerations
The optimum performance of high and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. Low ESR / ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak currents being drawn from VDD during turn-on of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
–
a) The first priority in designing grounding connections is to confine the high peak currents that charge
and discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
–
b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
A recommended layout pattern for the driver is shown in the following figure. If possible a single layer placement
is preferred.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
www.ti.com
Recommended Layout for Driver IC and
Passives
VDD
HB
LO
VSS
LI
SO
PowerPAD-8
HO
HS
HI
Single Layer
Option
Multi Layer
Option
To Hi-Side FET
To Low-Side FET
Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply
voltage (VDD) and can be roughly calculated as:
2
PDGATES = 2 • f • CL • VDD
(1)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equation.Equation 1 This plot can be used
to approximate the power losses due to the gate drivers.
1.000
C
= 4400 pF
L
0.100
0.010
0.001
C
= 1000 pF
L
C
= 0 pF
L
0.1
1.0
10.0
100.0
1000.0
SWITCHING FREQUENCY (kHz)
Figure 25. Gate Driver Power Dissipation (LO + HO)
VDD = 12V, Neglecting Diode Losses
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the diode power dissipation.
The total IC power dissipation can be estimated from the previous plots by summing the gate drive losses with
the bootstrap diode losses for the intended application.
0.100
C
= 4400 pF
L
C
= 0 pF
L
0.010
0.001
1
10
100
1000
SWITCHING FREQUENCY (kHz)
Figure 26. Diode Power Dissipation VIN = 50V
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
REVISION HISTORY
www.ti.com
Changes from Revision O (March 2013) to Revision P
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
14
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Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LM5100AM
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
95
TBD
Call TI
CU SN
CU SN
SN
Call TI
L5100
AM
LM5100AM/NOPB
LM5100AMR/NOPB
LM5100AMRX/NOPB
LM5100AMX/NOPB
ACTIVE
D
95
95
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
-40 to 125
L5100
AM
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
D
Green (RoHS
& no Sb/Br)
L5100
AMR
2500
2500
Green (RoHS
& no Sb/Br)
L5100
AMR
ACTIVE
SOIC
Green (RoHS
& no Sb/Br)
CU SN
-40 to 125
L5100
AM
LM5100ASD
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
1000
1000
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5100ASD
LM5100ASD/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
5100ASD
LM5100ASDX
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
4500
4500
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5100ASD
5100ASD
LM5100ASDX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5100BMA
LM5100BMA/NOPB
LM5100BMAX
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
95
95
TBD
Call TI
CU SN
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
L5100
BMA
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
L5100
BMA
2500
2500
TBD
L5100
BMA
LM5100BMAX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
L5100
BMA
LM5100BSD
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
1000
1000
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5100BSD
LM5100BSD/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
5100BSD
LM5100BSDX
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
4500
4500
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5100BSD
5100BSD
LM5100BSDX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5100CMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5100
CMA
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
LM5100CMAX/NOPB
LM5100CMY/NOPB
LM5100CMYE/NOPB
LM5100CMYX/NOPB
LM5100CSD/NOPB
LM5100CSDX/NOPB
LM5101AM
ACTIVE
SOIC
D
8
8
2500
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
L5100
CMA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
DGN
DGN
DPR
DPR
D
1000
250
Green (RoHS
& no Sb/Br)
SXCB
MSOP-
PowerPAD
8
Green (RoHS
& no Sb/Br)
SXCB
MSOP-
PowerPAD
8
3500
1000
4500
95
Green (RoHS
& no Sb/Br)
SXCB
WSON
WSON
SOIC
10
10
8
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
5100CSD
5100CSD
Green (RoHS
& no Sb/Br)
SN
TBD
Call TI
CU SN
CU SN
CU SN
Call TI
CU SN
L5101
AM
LM5101AM/NOPB
LM5101AMR/NOPB
LM5101AMRX/NOPB
LM5101AMX
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
L5101
AM
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
D
8
95
Green (RoHS
& no Sb/Br)
L5101
AMR
8
2500
2500
2500
Green (RoHS
& no Sb/Br)
L5101
AMR
ACTIVE
ACTIVE
SOIC
SOIC
8
TBD
-40 to 125
-40 to 125
-40 to 125
L5101
AM
LM5101AMX/NOPB
D
8
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
L5101
AM
LM5101ASD
ACTIVE
ACTIVE
WSON
WSON
DPR
NGT
10
8
1000
1000
TBD
Call TI
SN
Call TI
5101ASD
LM5101ASD-1/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
5101A-1
LM5101ASD/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
-40 to 125
5101ASD
LM5101ASDX
ACTIVE
ACTIVE
WSON
WSON
DPR
NGT
10
8
4500
4500
TBD
Call TI
SN
Call TI
5101ASD
5101A-1
LM5101ASDX-1/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5101ASDX/NOPB
ACTIVE
WSON
DPR
10
4500
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
5101ASD
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
LM5101BMA
LM5101BMA/NOPB
LM5101BMAX
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
8
8
8
8
95
TBD
Call TI
CU SN
Call TI
CU SN
Call TI
L5101
BMA
ACTIVE
ACTIVE
ACTIVE
D
D
D
95
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
L5101
BMA
2500
2500
TBD
L5101
BMA
LM5101BMAX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
L5101
BMA
LM5101BSD
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
1000
1000
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5101BSD
LM5101BSD/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
5101BSD
LM5101BSDX
ACTIVE
ACTIVE
WSON
WSON
DPR
DPR
10
10
4500
4500
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5101BSD
5101BSD
LM5101BSDX/NOPB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5101CMA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
8
8
8
8
8
8
8
95
TBD
Call TI
CU SN
Call TI
CU SN
CU SN
CU SN
CU SN
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
L5101
CMA
LM5101CMA/NOPB
LM5101CMAX
95
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
L5101
CMA
D
2500
2500
1000
250
TBD
L5101
CMA
LM5101CMAX/NOPB
LM5101CMY/NOPB
LM5101CMYE/NOPB
LM5101CMYX/NOPB
D
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L5101
CMA
MSOP-
PowerPAD
DGN
DGN
DGN
Green (RoHS
& no Sb/Br)
SXDB
SXDB
SXDB
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
3500
Green (RoHS
& no Sb/Br)
LM5101CSD
ACTIVE
ACTIVE
WSON
DPR
DPR
10
10
1000
1000
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5101CSD
5101CSD
LM5101CSD/NOPB
WSON
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5101CSDX
ACTIVE
WSON
DPR
10
4500
TBD
Call TI
Call TI
-40 to 125
5101CSD
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
LM5101CSDX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
WSON
DPR
10
4500
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
5101CSD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5100AMRX/NOPB
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5100AMX/NOPB
LM5100ASD
SOIC
WSON
WSON
WSON
WSON
SOIC
D
8
2500
1000
1000
4500
4500
2500
2500
1000
1000
4500
4500
2500
1000
330.0
178.0
178.0
330.0
330.0
330.0
330.0
178.0
178.0
330.0
330.0
330.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.5
4.3
4.3
4.3
4.3
6.5
6.5
4.3
4.3
4.3
4.3
6.5
5.3
5.4
4.3
4.3
4.3
4.3
5.4
5.4
4.3
4.3
4.3
4.3
5.4
3.4
2.0
1.3
1.3
1.3
1.3
2.0
2.0
1.3
1.3
1.3
1.3
2.0
1.4
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
DPR
DPR
DPR
DPR
D
10
10
10
10
8
LM5100ASD/NOPB
LM5100ASDX
LM5100ASDX/NOPB
LM5100BMAX
LM5100BMAX/NOPB
LM5100BSD
SOIC
D
8
WSON
WSON
WSON
WSON
SOIC
DPR
DPR
DPR
DPR
D
10
10
10
10
8
LM5100BSD/NOPB
LM5100BSDX
LM5100BSDX/NOPB
LM5100CMAX/NOPB
LM5100CMY/NOPB
MSOP-
Power
PAD
DGN
8
LM5100CMYE/NOPB
MSOP-
DGN
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
Power
PAD
LM5100CMYX/NOPB
MSOP-
Power
PAD
DGN
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5100CSD/NOPB
LM5100CSDX/NOPB
LM5101AMRX/NOPB
WSON
WSON
DPR
DPR
DDA
10
10
8
1000
4500
2500
178.0
330.0
330.0
12.4
12.4
12.4
4.3
4.3
6.5
4.3
4.3
5.4
1.3
1.3
2.0
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
SO
Power
PAD
LM5101AMX
LM5101AMX/NOPB
LM5101ASD
SOIC
SOIC
D
8
8
2500
2500
1000
1000
1000
4500
4500
4500
2500
2500
1000
1000
4500
4500
2500
2500
1000
330.0
330.0
178.0
178.0
178.0
330.0
330.0
330.0
330.0
330.0
178.0
178.0
330.0
330.0
330.0
330.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.5
6.5
4.3
4.3
4.3
4.3
4.3
4.3
6.5
6.5
4.3
4.3
4.3
4.3
6.5
6.5
5.3
5.4
5.4
4.3
4.3
4.3
4.3
4.3
4.3
5.4
5.4
4.3
4.3
4.3
4.3
5.4
5.4
3.4
2.0
2.0
1.3
1.3
1.3
1.3
1.3
1.3
2.0
2.0
1.3
1.3
1.3
1.3
2.0
2.0
1.4
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
WSON
WSON
WSON
WSON
WSON
WSON
SOIC
DPR
NGT
DPR
DPR
NGT
DPR
D
10
8
LM5101ASD-1/NOPB
LM5101ASD/NOPB
LM5101ASDX
10
10
8
LM5101ASDX-1/NOPB
LM5101ASDX/NOPB
LM5101BMAX
10
8
LM5101BMAX/NOPB
LM5101BSD
SOIC
D
8
WSON
WSON
WSON
WSON
SOIC
DPR
DPR
DPR
DPR
D
10
10
10
10
8
LM5101BSD/NOPB
LM5101BSDX
LM5101BSDX/NOPB
LM5101CMAX
LM5101CMAX/NOPB
LM5101CMY/NOPB
SOIC
D
8
MSOP-
Power
PAD
DGN
8
LM5101CMYE/NOPB
LM5101CMYX/NOPB
MSOP-
Power
PAD
DGN
DGN
8
8
250
178.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
MSOP-
Power
PAD
3500
LM5101CSD
LM5101CSD/NOPB
LM5101CSDX
WSON
WSON
WSON
WSON
DPR
DPR
DPR
DPR
10
10
10
10
1000
1000
4500
4500
178.0
178.0
330.0
330.0
12.4
12.4
12.4
12.4
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
1.3
1.3
1.3
1.3
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
LM5101CSDX/NOPB
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5100AMRX/NOPB
LM5100AMX/NOPB
LM5100ASD
SO PowerPAD
SOIC
DDA
D
8
8
2500
2500
1000
1000
4500
4500
2500
2500
1000
1000
4500
4500
2500
1000
250
367.0
367.0
210.0
210.0
367.0
367.0
367.0
367.0
210.0
210.0
367.0
367.0
367.0
210.0
210.0
367.0
210.0
367.0
367.0
367.0
367.0
367.0
185.0
185.0
367.0
367.0
367.0
367.0
185.0
185.0
367.0
367.0
367.0
185.0
185.0
367.0
185.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
WSON
DPR
DPR
DPR
DPR
D
10
10
10
10
8
LM5100ASD/NOPB
LM5100ASDX
WSON
WSON
LM5100ASDX/NOPB
LM5100BMAX
WSON
SOIC
LM5100BMAX/NOPB
LM5100BSD
SOIC
D
8
WSON
DPR
DPR
DPR
DPR
D
10
10
10
10
8
LM5100BSD/NOPB
LM5100BSDX
WSON
WSON
LM5100BSDX/NOPB
LM5100CMAX/NOPB
LM5100CMY/NOPB
LM5100CMYE/NOPB
LM5100CMYX/NOPB
LM5100CSD/NOPB
LM5100CSDX/NOPB
LM5101AMRX/NOPB
LM5101AMX
WSON
SOIC
MSOP-PowerPAD
MSOP-PowerPAD
MSOP-PowerPAD
WSON
DGN
DGN
DGN
DPR
DPR
DDA
D
8
8
8
3500
1000
4500
2500
2500
10
10
8
WSON
SO PowerPAD
SOIC
8
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5101AMX/NOPB
LM5101ASD
SOIC
WSON
D
8
10
8
2500
1000
1000
1000
4500
4500
4500
2500
2500
1000
1000
4500
4500
2500
2500
1000
250
367.0
210.0
210.0
210.0
367.0
367.0
367.0
367.0
367.0
210.0
210.0
367.0
367.0
367.0
367.0
210.0
210.0
367.0
210.0
210.0
367.0
367.0
367.0
185.0
185.0
185.0
367.0
367.0
367.0
367.0
367.0
185.0
185.0
367.0
367.0
367.0
367.0
185.0
185.0
367.0
185.0
185.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
DPR
NGT
DPR
DPR
NGT
DPR
D
LM5101ASD-1/NOPB
LM5101ASD/NOPB
LM5101ASDX
WSON
WSON
10
10
8
WSON
LM5101ASDX-1/NOPB
LM5101ASDX/NOPB
LM5101BMAX
WSON
WSON
10
8
SOIC
LM5101BMAX/NOPB
LM5101BSD
SOIC
D
8
WSON
DPR
DPR
DPR
DPR
D
10
10
10
10
8
LM5101BSD/NOPB
LM5101BSDX
WSON
WSON
LM5101BSDX/NOPB
LM5101CMAX
WSON
SOIC
LM5101CMAX/NOPB
LM5101CMY/NOPB
LM5101CMYE/NOPB
LM5101CMYX/NOPB
LM5101CSD
SOIC
D
8
MSOP-PowerPAD
MSOP-PowerPAD
MSOP-PowerPAD
WSON
DGN
DGN
DGN
DPR
DPR
DPR
DPR
8
8
8
3500
1000
1000
4500
4500
10
10
10
10
LM5101CSD/NOPB
LM5101CSDX
WSON
WSON
LM5101CSDX/NOPB
WSON
Pack Materials-Page 4
MECHANICAL DATA
DGN0008A
MUY08A (Rev A)
BOTTOM VIEW
www.ti.com
MECHANICAL DATA
DDA0008B
MRA08B (Rev B)
www.ti.com
MECHANICAL DATA
NGT0008A
SDC08A (Rev A)
www.ti.com
MECHANICAL DATA
DPR0010A
SDC10A (Rev A)
www.ti.com
IMPORTANT NOTICE
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