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LM5105SD/NOPB [TI]

Half Bridge Gate Driver with Programmable Dead-Time; 半桥栅极驱动器，具有可编程死区时间
LM5105SD/NOPB
型号： LM5105SD/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Half Bridge Gate Driver with Programmable Dead-Time
半桥栅极驱动器，具有可编程死区时间

驱动器 MOSFET驱动器 栅极 驱动程序和接口 接口集成电路 光电二极管 栅极驱动
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LM5105  
www.ti.com  
SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
LM5105 100V Half Bridge Gate Driver with Programmable Dead-Time  
Check for Samples: LM5105  
1
FEATURES  
DESCRIPTION  
The LM5105 is a high voltage gate driver designed to  
drive both the high side and low side N –Channel  
MOSFETs in a synchronous buck or half bridge  
configuration. The floating high-side driver is capable  
of working with rail voltages up to 100V. The single  
control input is compatible with TTL signal levels and  
a single external resistor programs the switching  
transition dead-time through tightly matched turn-on  
delay circuits. A high voltage diode is provided to  
charge the high side gate drive bootstrap capacitor.  
The robust level shift technology operates at high  
speed while consuming low power and provides clean  
output transitions. Under-voltage lockout disables the  
gate driver when either the low side or the  
bootstrapped high side supply voltage is below the  
operating threshold. The LM5105 is offered in the  
thermally enhanced WSON plastic package.  
•
Drives Both a High Side and Low Side N-  
Channel MOSFET  
•
•
1.8A Peak Gate Drive Current  
Bootstrap Supply Voltage Range up to 118V  
DC  
•
•
•
•
•
Integrated Bootstrap Diode  
Single TTL Compatible Input  
Programmable Turn-On Delays (Dead-Time)  
Enable Input Pin  
Fast Turn-Off Propagation Delays (26ns  
Typical)  
•
•
•
Drives 1000pF with 15ns Rise and Fall Time  
Supply Rail Under-Voltage Lockout  
Low Power Consumption  
TYPICAL APPLICATIONS  
PACKAGE  
•
•
Solid State motor drives  
Half and Full Bridge power converters  
•
WSON-10 (4 mm x 4 mm)  
SIMPLIFIED BLOCK DIAGRAM  
HB  
V
DD  
HO  
HB  
UVLO  
LEVEL  
SHIFT  
DRIVER  
HS  
V
DD  
UVLO  
V
SS  
LEADING  
EDGE  
IN  
DELAY  
RDT  
LEADING  
EDGE  
V
DD  
DELAY  
LO  
DRIVER  
EN  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  
LM5105  
SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
www.ti.com  
Connection Diagram  
1
2
3
4
5
10  
9
LO  
V
DD  
HB  
V
SS  
8
IN  
HO  
HS  
7
EN  
RDT  
NC  
6
Figure 1. 10-Lead WSON  
PIN DESCRIPTIONS  
PIN  
DESCRIPTION  
NAME  
NO.  
Positive gate drive supply.Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close  
to the IC as possible.  
VDD  
1
High-side gate driver bootstrap rail. Connect the positive terminal of bootstrap capacitor to the HB  
pin and connect negative terminal to HS. The Bootstrap capacitor should be placed as close to IC  
as possible.  
HB  
HO  
2
3
High-side gate driver output. Connect to the gate of high side N-MOS device through a short, low  
inductance path.  
High-side MOSFET source connection. Connect to the negative terminal of the bootststrap  
capacitor and to the source of the high side N-MOS device.  
HS  
NC  
4
5
Not connected.  
Dead-time programming pin. A resistor from RDT to VSS programs the turn-on delay of both the  
high and low side MOSFETs. The resistor should be placed close to the IC to minimize noise  
coupling from adjacent PC board traces.  
RDT  
EN  
6
7
Logic input for driver disable or enable. TTL compatible threshold with hysteresis. LO and HO are  
held in the low state when EN is low.  
Logic input for gate driver. TTL compatible threshold with hysteresis. The high side MOSFET is  
turned on and the low side MOSFET turned off when IN is high.  
IN  
8
9
VSS  
LO  
Ground return. All signals are referenced to this ground.  
Low-side gate driver output. Connect to the gate of the low side N-MOS device with a short, low  
inductance path.  
10  
It is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PC  
board to aid thermal dissipation.  
Exposed Pad  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
2
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SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
Absolute Maximum Ratings(1)(2)  
VDD to VSS  
–0.3V to +18V  
–0.3V to +18V  
–0.3V to VDD + 0.3V  
–0.3V to VDD + 0.3V  
HS – 0.3V to HB + 0.3V  
−5V to +100V  
118V  
HB to HS  
IN and EN to VSS  
LO to VSS  
HO to VSS  
(3)  
HS to VSS  
HB to VSS  
RDT to VSS  
–0.3V to 5V  
Junction Temperature  
Storage Temperature Range  
ESD Rating HBM(4)  
+150°C  
–55°C to +150°C  
2 kV  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under  
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test  
conditions, see the Electrical Characteristics.  
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and  
specifications.  
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally  
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated  
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD  
= 10V, the negative transients at HS must not exceed -5V.  
(4) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 2, Pin 3 and Pin 4 are rated at  
500V.  
Recommended Operating Conditions  
VDD  
HS(1)  
+8V to +14V  
–1V to 100V  
HB  
HS + 8V to HS + 14V  
<50V/ns  
HS Slew Rate  
Junction Temperature  
–40°C to +125°C  
(1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally  
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated  
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD  
= 10V, the negative transients at HS must not exceed -5V.  
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SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
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Electrical Characteristics  
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction  
temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, EN = 5V. No load on LO or HO. RDT=  
100kΩ(1)  
.
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
SUPPLY CURRENTS  
IDD  
VDD Quiescent Current  
VDD Operating Current  
IN = EN = 0V  
0.34  
1.65  
0.06  
1.3  
0.6  
3
mA  
mA  
mA  
mA  
µA  
IDDO  
IHB  
f = 500 kHz  
Total HB Quiescent Current  
Total HB Operating Current  
HB to VSS Current, Quiescent  
HB to VSS Current, Operating  
IN = EN = 0V  
f = 500 kHz  
0.2  
3
IHBO  
IHBS  
IHBSO  
HS = HB = 100V  
f = 500 kHz  
0.05  
0.1  
10  
mA  
INPUT IN and EN  
VIL  
VIH  
Rpd  
Low Level Input Voltage Threshold  
0.8  
1.8  
1.8  
V
V
High Level Input Voltage Threshold  
2.2  
Input Pulldown Resistance Pin IN and EN  
100  
200  
500  
kΩ  
DEAD-TIME CONTROLS  
VRDT  
IRDT  
Nominal Voltage at RDT  
RDT Pin Current Limit  
2.7  
3
3.3  
V
RDT = 0V  
0.75  
1.5  
2.25  
mA  
UNDER VOLTAGE PROTECTION  
VDDR  
VDDH  
VHBR  
VHBH  
VDD Rising Threshold  
VDD Threshold Hysteresis  
HB Rising Threshold  
6.0  
5.7  
6.9  
0.5  
6.6  
0.4  
7.4  
7.1  
V
V
V
V
HB Threshold Hysteresis  
BOOT STRAP DIODE  
VDL  
VDH  
RD  
Low-Current Forward Voltage  
IVDD-HB = 100 µA  
IVDD-HB = 100 mA  
IVDD-HB = 100 mA  
0.6  
0.85  
0.8  
0.9  
1.1  
1.5  
V
V
Ω
High-Current Forward Voltage  
Dynamic Resistance  
LO GATE DRIVER  
VOLL  
VOHL  
Low-Level Output Voltage  
ILO = 100 mA  
0.25  
0.35  
0.4  
V
V
ILO = –100 mA,  
VOHL = VDD – VLO  
High-Level Output Voltage  
0.55  
IOHL  
IOLL  
Peak Pullup Current  
LO = 0V  
1.8  
1.6  
A
A
Peak Pulldown Current  
LO = 12V  
HO GATE DRIVER  
VOLH  
VOHH  
Low-Level Output Voltage  
IHO = 100 mA  
0.25  
0.35  
0.4  
V
V
IHO = –100 mA,  
VOHH = HB – HO  
High-Level Output Voltage  
0.55  
IOHH  
IOLH  
Peak Pullup Current  
HO = 0V  
1.8  
1.6  
A
A
Peak Pulldown Current  
HO = 12V  
THERMAL RESISTANCE  
θJA Junction to Ambient  
See(2)(3)  
40  
°C/W  
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation  
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).  
(2) 4 layer board with Cu finished thickness 1.5/1.0/1.0/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm  
ground and power planes embedded in PCB. See Application Note AN-1187.  
(3) The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.  
4
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SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
Switching Characteristics  
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction  
temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, No Load on LO or HO(1)  
.
Symbol  
tLPHL  
Parameter  
Lower Turn-Off Propagation Delay  
Upper Turn-Off Propagation Delay  
Lower Turn-On Propagation Delay  
Upper Turn-On Propagation Delay  
Lower Turn-On Propagation Delay  
Upper Turn-On Propagation Delay  
Enable and Shutdown propagation delay  
Conditions  
Min  
Typ  
26  
Max  
56  
Units  
ns  
tHPHL  
tLPLH  
tHPLH  
tLPLH  
tHPLH  
ten, tsd  
26  
56  
ns  
RDT = 100k  
485  
485  
75  
595  
595  
105  
105  
28  
705  
705  
150  
150  
ns  
RDT = 100k  
RDT = 10k  
RDT = 10k  
ns  
ns  
75  
ns  
ns  
RDT = 100k  
570  
80  
ns  
DT1, DT2  
Dead-Time LO OFF to HO ON & HO OFF to LO ON  
RDT = 10k  
ns  
MDT  
tR, tF  
tBS  
Dead-Time Matching  
RDT = 100k  
50  
ns  
Either Output Rise/Fall Time  
Bootstrap Diode Turn-On or Turn-Off Time  
CL = 1000pF  
15  
ns  
IF = 20 mA, IR = 200 mA  
50  
ns  
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation  
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).  
Copyright © 2005–2013, Texas Instruments Incorporated  
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SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
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Typical Performance Characteristics  
VDD Operating Current  
vs Frequency  
Operating Current vs Temperature  
100  
2.2  
2.0  
V
V
= HB = 12V  
= HS = 0V  
DD  
SS  
VDD = HB = 12V  
CL = 2200 pF  
RDT = 10K  
f = 500 kHz  
VSS = HS = 0  
CL = 1000 pF  
1.8  
1.6  
1.4  
C
= 0 pF  
L
IDDO  
CL = 470 pF  
10  
IHBO  
1.2  
1.0  
CL = 0 pF  
100 1000  
1
-50 -30 -10 10 30 50 70 90 110 130 150  
1
10  
TEMPERATURE (oC)  
FREQUENCY (kHz)  
Figure 2.  
Figure 3.  
Quiescent Current vs Supply Voltage  
Quiescent Current vs Temperature  
1.20  
1.00  
0.80  
0.60  
0.40  
0.20  
0.00  
1.20  
1.00  
0.80  
0.60  
0.40  
0.20  
0.00  
IDD @ RDT = 10k  
IDD @ RDT = 10k  
V
V
= HB = 12V  
= HS = 0V  
V
V
= HB  
DD  
SS  
DD  
SS  
= HS = 0V  
IDD @ RDT = 100k  
IDD @ RDT = 100k  
IHB @ RDT = 10k, 100k  
IHB @ RDT = 10k, 100k  
8
9
10 11 12 13 14 15 16 17 18  
-50 -25  
0
25 50 75 100 125 150  
V
, V (V)  
DD HB  
TEMPERATURE (°C)  
Figure 4.  
Figure 5.  
HB Operating Current  
vs Frequency  
HO & LO Peak Output Current  
vs Output Voltage  
100000  
10000  
1000  
100  
2.00  
1.80  
1.60  
1.40  
1.20  
1.00  
0.80  
0.60  
0.40  
0.20  
0.00  
V
= HB = 12V, HS = 0V  
DD  
HB = 12V,  
HS = 0V  
CL = 4400 pF  
CL = 2200 pF  
CL = 1000 pF  
SOURCING  
SINKING  
CL = 0 pF  
CL = 470 pF  
10  
0
2
4
6
8
10  
12  
0.1  
1
10  
100  
1000  
HO, LO (V)  
FREQUENCY (kHz)  
Figure 6.  
Figure 7.  
6
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Typical Performance Characteristics (continued)  
Undervoltage Hysteresis  
vs Temperature  
Diode Forward Voltage  
0.60  
0.55  
0.50  
0.45  
0.40  
0.35  
0.30  
1.00E-01  
1.00E-02  
1.00E-03  
1.00E-04  
1.00E-05  
1.00E-06  
T = 150°C  
V
DDH  
T = 25°C  
V
HBH  
T = -40°C  
-50 -25  
0
25 50 75 100 125 150  
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
TEMPERATURE (oC)  
FORWARD VOLTAGE (V)  
Figure 8.  
Figure 9.  
Undervoltage Rising Threshold  
vs Temperature  
LO & HO - High Level Output Voltage  
vs Temperature  
7.30  
7.20  
7.10  
7.00  
6.90  
6.80  
6.70  
6.60  
6.50  
6.40  
6.30  
0.700  
V
V
= V  
DD  
- V  
SS  
Output Current = 100 mA  
DDR  
= HB - HS  
HBR  
0.600  
0.500  
0.400  
0.300  
0.200  
0.100  
V
= HB = 8V  
DD  
V
DDR  
V
= HB = 12V  
DD  
V
HBR  
V
= HB = 16V  
DD  
-50 -25  
0
25 50 75 100 125 150  
-50 -25  
0
25 50 75 100 125 150  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 10.  
Figure 11.  
LO & HO - Low Level Output Voltage  
vs Temperature  
Input Threshold vs Temperature  
0.400  
1.96  
1.94  
1.92  
1.90  
1.88  
1.86  
1.84  
1.82  
1.80  
1.78  
1.76  
Output Current - 100 mA  
= HB = 8V  
0.350  
0.300  
0.250  
0.200  
0.150  
0.100  
V
DD  
V
= HB = 12V  
DD  
V
= HB = 16V  
DD  
-50 -25  
0
25 50 75 100 125 150  
-50 -30 -10 10 30 50 70 90 110 130 150  
TEMPERATURE (°C)  
TEMPERATURE (oC)  
Figure 12.  
Figure 13.  
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Typical Performance Characteristics (continued)  
Dead-Time vs RT Resistor Value  
Dead-Time vs Temperature (RT = 10k)  
88  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
86  
VDD = HB = 12V  
VSS = HS = 0  
84  
82  
80  
78  
76  
90  
10  
30  
50  
70  
110 130 150  
-50 -30 -10 10 30 50 70 90 110 130 150  
RDT (kW)  
TEMPERATURE (oC)  
Figure 14.  
Figure 15.  
Dead-Time vs Temperature (RT = 100k)  
600  
V
V
= HB = 12V  
= HS = 0V  
DD  
SS  
590  
580  
570  
560  
550  
540  
-50 -30 -10 10 30 50 70 90 110 130 150  
TEMPERATURE (oC)  
Figure 16.  
8
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SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
Timing Diagrams  
IN  
t
t
t
t
LPLH  
LPHL  
HPHL  
HPLH  
EN  
t
en  
t
DT1  
DT2  
DT1  
DT2  
sd  
LO  
HO  
t
en  
t
sd  
Figure 17. LM5105 Input - Output Waveforms  
V
V
IL  
IH  
IN  
t
LPHL  
t
LPLH  
90%  
LO  
HO  
10%  
90%  
t
HPLH  
t
HPHL  
10%  
Figure 18. LM5105 Switching Time Definitions: tLPLH, tLPHL, tHPLH, tHPHL  
90%  
V
IH  
HO  
EN  
10%  
DT1  
MDT = |DT1-DT2|  
DT2  
90%  
10%  
LO  
90%  
t
sd  
LO or HO  
Figure 19. LM5105 Enable: tsd  
Figure 20. LM5105 Dead-Time: DT  
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Operational Notes  
The LM5105 is a single PWM input Gate Driver with Enable that offers a programmable dead-time. The dead-  
time is set with a resistor at the RDT pin and can be adjusted from 100ns to 600ns. The wide dead-time  
programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETS and  
applications.  
The RDT pin is biased at 3V and current limited to 1 mA maximum programming current. The time delay  
generator will accommodate resistor values from 5k to 100k with a dead-time time that is proportional to the RDT  
resistance. Grounding the RDT pin programs the LM5105 to drive both outputs with minimum dead-time.  
STARTUP AND UVLO  
Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply  
voltage (VDD) and bootstrap capacitor voltage (HB – HS) independently. The UVLO circuit inhibits each driver  
until sufficient supply voltage is available to turn-on the external MOSFETs, and the UVLO hysteresis prevents  
chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of LM5105, the top  
and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.9V. Any UVLO condition  
on the bootstrap capacitor will disable only the high side output (HO).  
LAYOUT CONSIDERATIONS  
The optimum performance of high and low side gate drivers cannot be achieved without taking due  
considerations during circuit board layout. Following points are emphasized.  
1. A low ESR/ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between  
HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external MOSFET.  
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be  
connected between MOSFET drain and ground (VSS).  
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the  
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.  
4. Grounding considerations:  
–
The first priority in designing grounding connections is to confine the high peak currents from charging  
and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and  
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as  
possible to the gate driver.  
–
The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground  
referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on  
the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.  
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length  
and area on the circuit board is important to ensure reliable operation.  
5. The resistor on the RDT pin must be placed very close to the IC and seperated from high current paths to  
avoid noise coupling to the time delay generator which could disrupt timer operation.  
POWER DISSIPATION CONSIDERATIONS  
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate  
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply  
voltage (VDD) and can be roughly calculated as:  
2
PDGATES = 2 • f • CL • VDD  
(1)  
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and  
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load  
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the  
power losses driving the output loads and agrees well with the above equation. This plot can be used to  
approximate the power losses due to the gate drivers.  
10  
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Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: LM5105  
LM5105  
www.ti.com  
SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
1.000  
C
L
= 4400 pF  
C
= 2200 pF  
L
0.100  
0.010  
C
= 1000 pF  
L
C
L
= 470 pF  
C
L
= 0 pF  
0.001  
0.1  
1.0  
10.0  
100.0  
1000.0  
SWITCHING FREQUENCY (kHz)  
Figure 21. Gate Driver Power Dissipation (LO + HO)  
VCC = 12V, Neglecting Diode Losses  
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the  
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these  
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads  
require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to  
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations  
and lab measurements of the diode recovery time and current under several operating conditions. This can be  
useful for approximating the diode power dissipation.  
1.000  
0.100  
0.010  
0.001  
1.000  
0.100  
0.010  
0.001  
C
= 4400 pF  
L
C
= 4400 pF  
L
C
= 0 pF  
L
C
= 0 pF  
L
1.0 kHz  
10.0 kHz  
100.0 kHz  
1000.0 kHz  
1.0 kHz  
10.0 kHz  
100.0 kHz  
1000.0 kHz  
SWITCHING FREQUENCY (kHz)  
SWITCHING FREQUENCY (kHz)  
Figure 22. Diode Power Dissipation VIN = 80V  
Figure 23. Diode Power Dissipation VIN = 40V  
The total IC power dissipation can be estimated from the above plots by summing the gate drive losses with the  
bootstrap diode losses for the intended application. Because the diode losses can be significant, an external  
diode placed in parallel with the internal bootstrap diode (refer to Figure 24) and can be helpful in removing  
power from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series  
inductance and have a significantly lower forward voltage drop than the internal diode.  
Copyright © 2005–2013, Texas Instruments Incorporated  
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SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
www.ti.com  
HS Transient Voltages Below Ground  
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board  
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS  
node can swing below ground provided:  
1. HS must always be at a lower potential than HO. Pulling HO more than -0.3V below HS can activate  
parasitic transistors resulting in excessive current to flow from the HB supply possibly resulting in damage to  
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed  
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must  
be placed as close to the IC pins as possible in order to be effective.  
2. HB to HS operating voltage should be 15V or less . Hence, if the HS pin transient voltage is -5V, VDD should  
be ideally limited to 10V to keep HB to HS below 15V.  
3. A low ESR bypass capacitor between HB to HS as well as VCC to VSS is essential for proper operation. The  
capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO  
and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the  
leads of the IC which must be avoided for reliable operation.  
(Optional external  
fast recovery diode)  
V
IN  
V
CC  
R
GATE  
HB  
HO  
HS  
V
V
DD  
DD  
C
BOOT  
0.1 mF  
IN  
OUT1  
T1  
CONTROLLER  
LM5105  
EN  
ENABLE  
LO  
R
GATE  
0.47 mF  
RDT  
GND  
V
SS  
Figure 24. LM5105 Driving MOSFETs Connected in Half-Bridge Configuration  
12  
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LM5105  
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SNVS349C –FEBRUARY 2005–REVISED MARCH 2013  
REVISION HISTORY  
Changes from Revision B (March 2013) to Revision C  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12  
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13  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
LM5105SD  
ACTIVE  
WSON  
WSON  
DPR  
10  
10  
1000  
TBD  
Call TI  
SN  
Call TI  
-40 to 125  
-40 to 125  
L5105SD  
LM5105SD/NOPB  
ACTIVE  
DPR  
1000  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
L5105SD  
LM5105SDX  
ACTIVE  
ACTIVE  
WSON  
WSON  
DPR  
DPR  
10  
10  
4500  
4500  
TBD  
Call TI  
SN  
Call TI  
-40 to 125  
-40 to 125  
L5105SD  
L5105SD  
LM5105SDX/NOPB  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
21-Mar-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LM5105SD  
LM5105SD/NOPB  
LM5105SDX  
WSON  
WSON  
WSON  
WSON  
DPR  
DPR  
DPR  
DPR  
10  
10  
10  
10  
1000  
1000  
4500  
4500  
178.0  
178.0  
330.0  
330.0  
12.4  
12.4  
12.4  
12.4  
4.3  
4.3  
4.3  
4.3  
4.3  
4.3  
4.3  
4.3  
1.3  
1.3  
1.3  
1.3  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
Q1  
LM5105SDX/NOPB  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
21-Mar-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LM5105SD  
LM5105SD/NOPB  
LM5105SDX  
WSON  
WSON  
WSON  
WSON  
DPR  
DPR  
DPR  
DPR  
10  
10  
10  
10  
1000  
1000  
4500  
4500  
210.0  
210.0  
367.0  
367.0  
185.0  
185.0  
367.0  
367.0  
35.0  
35.0  
35.0  
35.0  
LM5105SDX/NOPB  
Pack Materials-Page 2  
MECHANICAL DATA  
DPR0010A  
SDC10A (Rev A)  
www.ti.com  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
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