LM5109B-Q1 [TI]
High Voltage 1-A Peak Half Bridge Gate Driver;
| 型号： | LM5109B-Q1 |
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TEXAS INSTRUMENTS |
| 描述： | High Voltage 1-A Peak Half Bridge Gate Driver 栅 |
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LM5109B-Q1
SNVSAG6A –NOVEMBER 2015–REVISED DECEMBER 2015
LM5109B-Q1 High Voltage 1-A Peak Half Bridge Gate Driver
1 Features
3 Description
The LM5109B-Q1 is a cost effective, high voltage
1
•
•
Qualified for Automotive Applications
gate driver designed to drive both the high-side and
the low-side N-Channel MOSFETs in a synchronous
buck or a half bridge configuration. The floating high-
side driver is capable of working with rail voltages up
to 90 V. The outputs are independently controlled
with TTL/CMOS compatible logic input thresholds.
The robust level shift technology operates at high
speed while consuming low power and providing
clean level transitions from the control input logic to
the high-side gate driver. Under-voltage lockout is
provided on both the low-side and the high-side
power rails. The device is available in the thermally
enhanced WSON(8) packages.
AEC-Q100 Qualified With the Following Results
–
–
–
Device Temperature Grade 1
Device HBM ESD Classification Level 1C
Device CDM ESD Classification Level C4A
•
•
Drives Both a High-Side and Low-Side N-Channel
MOSFET
1-A Peak Output Current (1.0-A Sink/1.0-A
Source)
•
•
•
•
Independent TTL/CMOS Compatible Inputs
Bootstrap Supply Voltage to 108-V DC
Fast Propagation Times (30 ns Typical)
Device Information(1)
Drives 1000-pF Load with 15-ns Rise and Fall
Times
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM5109B-Q1
WSON (8)
4.00 mm × 4.00 mm
•
Excellent Propagation Delay Matching (2 ns
Typical)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
Supply Rail Under-Voltage Lockout
Low Power Consumption
Thermally-Enhanced WSON-8 Package
2 Applications
•
•
•
•
Push-Pull Converters
Half and Full Bridge Power Converters
Solid State Motor Drives
Two Switch Forward Power Converters
Simplified Application Diagram
D
Boot
R
Boot
VIN
VCC
HB
VDD
HO
HI
LI
HS
LO
LOAD
LM5109
VSS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5109B-Q1
SNVSAG6A –NOVEMBER 2015–REVISED DECEMBER 2015
www.ti.com
Table of Contents
7.3 Feature Description................................................... 9
7.4 HS Transient Voltages Below Ground .................... 10
7.5 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
Power Supply Recommendations...................... 16
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1 Community Resources.......................................... 18
11.2 Trademarks........................................................... 18
11.3 Electrostatic Discharge Caution............................ 18
11.4 Glossary................................................................ 18
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2015) to Revision A
Page
•
Changed device from Product Preview to Production Data and released full data sheet...................................................... 1
2
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SNVSAG6A –NOVEMBER 2015–REVISED DECEMBER 2015
5 Pin Configuration and Functions
NGT Package
8-Pin WSON
Top View
1
2
3
4
8
7
6
5
HB
HO
HS
LO
V
DD
HI
WSON-8
LI
V
SS
Pin Functions
PIN
I/O(1)
DESCRIPTION
APPLICATIONS INFORMATION
NO.(2)
NAME
Locally decouple to VSS using low ESR/ESL capacitor located as close
to IC as possible.
1
VDD
P
I
Positive gate drive supply
High side control input
The HI input is TTL/CMOS Compatible input thresholds. Unused HI
input should be tied to ground and not left open.
2
HI
The LI input is TTL/CMOS Compatible input thresholds. Unused LI
input should be tied to ground and not left open.
3
4
5
LI
I
Low side control input
Ground reference
VSS
LO
G
O
All signals are referenced to this ground.
Low side gate driver
output
Connect to the gate of the low-side N-MOS device.
High side source
connection
Connect to the negative terminal of the bootstrap capacitor and to the
source of the high-side N-MOS device.
6
7
HS
HO
P
High side gate driver
output
O
Connect to the gate of the high-side N-MOS device.
Connect the positive terminal of the bootstrap capacitor to HB and the
negative terminal of the bootstrap capacitor to HS. The bootstrap
capacitor should be placed as close to IC as possible.
High side gate driver
positive supply rail
8
HB
P
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
(2) For WSON-8 package, it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB
and the ground plane should extend out from underneath the package to improve heat dissipation.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
18
UNIT
VDD to VSS
HB to HS
V
V
–0.3
18
LI or HI to VSS
LO to VSS
–0.3
VDD + 0.3
VDD + 0.3
VHB + 0.3
90
V
–0.3
V
HO to VSS
VHS – 0.3
–5
V
(2)
HS to VSS
V
HB to VSS
108
V
Junction temperature
Storage temperature, Tstg
–40
–55
150
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) In the application, the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15 V. For example, if
VDD = 10 V, the negative transients at HS must not exceed –5 V.
6.2 ESD Ratings
VALUE
1500
750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
8
NOM
MAX
14
UNIT
V
VDD
HS(1)
–1
90
V
HB
VHS+8
VHS+14
< 50
125
V
HS Slew Rate
Junction Temperature
V/ns
°C
–40
(1) In the application, the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15 V. For example, if
VDD = 10 V, the negative transients at HS must not exceed –5 V.
4
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SNVSAG6A –NOVEMBER 2015–REVISED DECEMBER 2015
6.4 Thermal Information
LM5109B-Q1
THERMAL METRIC(1)
NGT (WSON)
8-PINS
42.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
34.0
19.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
19.5
RθJC(bot)
8.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
TJ = 25°C (unless otherwise noted)
VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO.
PARAMETER
Supply Currents
TEST CONDITIONS
MIN
TYP
0.3
1.8
0.06
1.4
0.1
0.5
1.8
1.8
200
MAX UNIT
IDD
VDD Quiescent Current
LI = HI = 0V
f = 500 kHz
LI = HI = 0V
f = 500 kHz
VHS = VHB = 90V
f = 500 kHz
TJ = 25°C
mA
0.6
TJ = –40°C to 125°C
TJ = 25°C
IDDO
VDD Operating Current
mA
2.9
TJ = –40°C to 125°C
TJ = 25°C
IHB
Total HB Quiescent Current
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
mA
0.2
TJ = –40°C to 125°C
TJ = 25°C
IHBO
IHBS
IHBSO
mA
2.8
TJ = –40°C to 125°C
TJ = 25°C
µA
10
TJ = –40°C to 125°C
mA
Input Pins Li and Hi
VIL
VIH
RI
Low Level Input Voltage
Threshold
TJ = 25°C
V
TJ = –40°C to 125°C
TJ = 25°C
0.8
High Level Input Voltage
Threshold
V
TJ = –40°C to 125°C
TJ = 25°C
2.2
Input Pulldown Resistance
kΩ
TJ = –40°C to 125°C
100
6.0
5.7
500
Under Voltage Protection
VDDR
VDD Rising Threshold
VDDR = VDD - VSS
TJ = 25°C
6.7
V
TJ = –40°C to 125°C
7.4
VDDH
VHBR
VDD Threshold Hysteresis
HB Rising Threshold
0.5
6.6
V
VHBR = VHB - VHS
TJ = 25°C
V
TJ = –40°C to 125°C
7.1
VHBH
HB Threshold Hysteresis
0.4
0.38
0.72
V
LO Gate Driver
VOLL
ILO = 100 mA, VOHL = VLO – VSS
TJ = 25°C
Low-Level Output Voltage
V
TJ = –40°C to 125°C
TJ = 25°C
0.65
VOHL
ILO = −100 mA, VOHL = VDD– VLO
High-Level Output Voltage
V
TJ = –40°C to 125°C
1.20
IOHL
IOLL
Peak Pullup Current
VLO = 0V
1.0
1.0
A
A
Peak Pulldown Current
VLO = 12V
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Electrical Characteristics (continued)
TJ = 25°C (unless otherwise noted)
VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO.
PARAMETER
TEST CONDITIONS
MIN
TYP
0.38
0.72
MAX UNIT
HO Gate Driver
VOLH
IHO = 100 mA, VOLH = VHO– VHS
TJ = 25°C
TJ = –40°C to 125°C
IHO = −100 mA, VOHH = VHB– VHO TJ = 25°C
Low-Level Output Voltage
High-Level Output Voltage
V
0.65
VOHH
V
TJ = –40°C to 125°C
1.20
IOHH
IOLH
Peak Pullup Current
VHO = 0V
1.0
1.0
A
A
Peak Pulldown Current
VHO = 12V
6.6 Switching Characteristics
TJ = 25°C (unless otherwise noted)
VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tLPHL
tHPHL
tLPLH
tHPLH
tMON
tMOFF
Lower Turn-Off Propagation Delay
(LI Falling to LO Falling)
TJ = 25°C
30
30
32
32
2
ns
TJ = –40°C to 125°C
TJ = 25°C
56
56
56
56
15
15
Upper Turn-Off Propagation Delay
(HI Falling to HO Falling)
ns
ns
ns
ns
ns
TJ = –40°C to 125°C
TJ = 25°C
Lower Turn-On Propagation Delay
(LI Rising to LO Rising)
TJ = –40°C to 125°C
TJ = 25°C
Upper Turn-On Propagation Delay
(HI Rising to HO Rising)
TJ = –40°C to 125°C
Delay Matching: Lower Turn-On and Upper TJ = 25°C
Turn-Off
TJ = –40°C to 125°C
Delay Matching: Lower Turn-Off and Upper TJ = 25°C
Turn-On
2
TJ = –40°C to 125°C
CL = 1000 pF
tRC, tFC
tPW
Either Output Rise/Fall Time
15
50
ns
ns
Minimum Input Pulse Width that Changes
the Output
[L
[L
IL
IL
t
t
HPLH
HPHL
t
t
HPLH
LPLH
[h
[h
Ih
Ih
t
t
MOFF
MON
Figure 1. Typical Test Timing Diagram
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6.7 Typical Characteristics
100
100
V
= V = 12V
HB
DD
C
= 1000 pF
L
V
= V = 0V
HS
SS
C
= 1000 pF
L
10
1
C
= 2200 pF
L
10
1
C
L
= 2200 pF
C
L
= 4400 pF
C
L
= 4400 pF
C
L
= 0 pF
0.1
0.01
C
= 0 pF
L
C
= 470 pF
L
C
L
= 470 pF
0.1
1
10
100
1000
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
VDD = VHB = 12 V
VSS = VHS = 0 V
Figure 3. HB Operating Current vs Frequency
Figure 2. VDD Operating Current vs Frequency
0.45
0.40
0.35
2.2
2.0
1.8
1.6
1.4
1.2
1.0
I
DDO
I
DDO
C
= 0 pF
L
0.30
0.25
0.20
0.15
0.10
0.05
0.00
f = 500 kHz
LI = HI = 0V
V
= V = 12V
HB
DD
SS
V
V
= V = 12V
HB
DD
SS
V
= V = 0V
HS
= V = 0V
HS
I
HBO
50
I
HBO
50
-40 -25 -10
5
20 35
65
80 95 110 125
5
20 35
65
80 95 110 125
-40 -25 -10
TEMPERATURE (oC)
TEMPERATURE (°C)
Figure 5. Quiescent Current vs Temperature
Figure 4. Operating Current vs Temperature
600
44
C
= 0 pF
L
t
LI = HI = 0V
LPHL
t
HPHL
V
V
= V = 12V
HB
DD
SS
V
V
= V
HB
DD
500
40
36
32
28
24
20
= V
HS
= 0V
= V = 0V
SS HS
I
DD
400
300
200
turn off
t
HPLH
t
LPLH
I
HB
turn on
100
0
8
10
12
14
, V (V)
16
18
50
20 35
65
-40 -25 -10
5
80 95 110 125
TEMPERATURE (oC)
V
DD HB
Figure 6. Quiescent Current vs Voltage
Figure 7. Propagation Delay vs Temperature
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Typical Characteristics (continued)
1.6
0.6
0.5
0.4
0.3
0.2
Output Current : -100 mA
= V = 0V
Output Current : -100 mA
1.4
V
SS
HS
V
= V = 0V
HS
SS
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= V = 8V
HB
DD
V
= V = 8V
HB
DD
V
DD
= V = 12V
HB
V
= V = 12V
HB
DD
V
DD
= V = 16V
V
= V = 16V
HB
HB
DD
50
-40 -25 -10
5
20 35
65
80 95 110 125
50
20 35
-40 -25 -10
5
65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. LO and HO High Level Output Voltage vs
Temperature
Figure 9. LO and HO Low Level Output Voltage vs
Temperature
0.50
0.48
0.46
7.0
V
V
= V - V
DD
DDR
SS
6.9
6.8
6.7
6.6
6.5
6.4
6.3
= V - V
HB
HBR
HS
V
DDH
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
V
DDR
V
HBR
V
HBH
50
-40 -25 -10
5
20 35
65
80 95 110 125
50
-40 -25 -10
5
20 35
65
80 95 110 125
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 11. Undervoltage Hysteresis vs Temperature
Figure 10. Undervoltage Rising Thresholds vs Temperature
1.92
2.00
1.91
V
= 12V
= 0V
DD
Rising
1.95
1.90
1.85
1.80
1.75
1.70
V
1.90
1.89
1.88
1.87
1.86
SS
Rising
Falling
1.85
Falling
1.84
1.83
1.82
1.81
1.80
12
(V)
8
9
10
11
13
14 15 16
50
-40 -25 -10
5
20 35
65
80 95 110 125
V
DD
TEMPERATURE (oC)
Figure 13. Input Thresholds vs Supply Voltage
Figure 12. Input Thresholds vs Temperature
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7 Detailed Description
7.1 Overview
The LM5109B-Q1 is a cost-effective, high voltage gate driver designed to drive both the high-side and the low-
side N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently
controlled with TTL/CMOS compatible input thresholds. The floating high-side driver is capable of working with
HB voltage up to 108 V. An external high voltage diode must be provided to charge high side gate drive
bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean
level transitions from the control logic to the high side gate driver. Under-voltage lockout (UVLO) is provided on
both the low side and the high side power rails.
7.2 Functional Block Diagram
VDD
HV
HB
HO
Level
Shift
Driver
UVLO
HS
HI
VDD
UVLO
LO
Driver
LI
VSS
7.3 Feature Description
7.3.1 Start-up and UVLO
Both top and bottom drivers include UVLO protection circuitry which monitors the supply voltage (VDD) and
bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each output until sufficient supply
voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering
during supply voltage variations. When the supply voltage is applied to the VDD pin of the LM5109B-Q1, the top
and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.7 V. Any UVLO condition
on the bootstrap capacitor (VHB–HS) will only disable the high- side output (HO).
Table 1. VDD UVLO Feature Logic Operation
Condition (VHB-HS>VHBR for all case below)
VDD-VSS < VDDR during device start-up
VDD-VSS < VDDR during device start-up
VDD-VSS < VDDR during device start-up
VDD-VSS < VDDR during device start-up
VDD-VSS < VDDR – VDDH after device start-up
VDD-VSS < VDDR – VDDH after device start-up
VDD-VSS < VDDR – VDDH after device start-up
VDD-VSS < VDDR – VDDH after device start-up
HI
H
L
LI
L
HO
L
LO
L
H
H
L
L
L
H
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
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Table 2. VHB-HS UVLO Feature Logic Operation
Condition (VDD>VDDR for all case below)
VHB-HS < VHBR during device start-up
VHB-HS < VHBR during device start-up
VHB-HS < VHBR during device start-up
VHB-HS < VHBR during device start-up
VHB-HS < VHBR – VHBH after device start-up
VHB-HS < VHBR – VHBH after device start-up
VHB-HS < VHBR – VHBH after device start-up
VHB-HS < VHBR – VHBH after device start-up
HI
H
L
LI
L
HO
L
LO
L
H
H
L
L
H
H
L
H
L
L
L
H
L
L
L
L
H
H
L
L
H
H
L
H
L
L
L
7.3.2 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and
provides excellent delay matching with the low-side driver.
7.3.3 Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,
and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The low-
side output stage is referenced to VSS and the high-side is referenced to HS.
7.4 HS Transient Voltages Below Ground
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS
node can swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling HO more than –0.3 V below HS can activate
parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must
be placed as close to the IC pins as possible in order to be effective.
2. HB to HS operating voltage should be 15 V or less. Hence, if the HS pin transient voltage is –5 V, VDD
should be ideally limited to 10 V to keep HB to HS below 15 V.
3. Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The
capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable operation.
7.5 Device Functional Modes
The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO
operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold, the output stage is
dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating.
Table 3. INPUT/OUTPUT Logic Table
HI
LI
HO(1)
LO(2)
L
L
L
L
L
H
L
L
H
H
H
L
H
H
H
L
H
L
Floating
Floating
(1) HO is measured with respect to the HS.
(2) LO is measured with respect to the VSS.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To operate fast switching of power MOSFETs at high switching frequencies and to reduce associated switching
losses, a powerful gate driver is employed between the PWM output of controller and the gates of the power
semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to
directly drive the gates of the switching devices. With the advent of digital power, this situation is often
encountered because the PWM signal from the digital controller is often a 3.3 V logic signal which cannot
effectively turn on a power switch. Level shift circuit is needed to boost the 3.3 V signal to the gate-drive voltage
(such as 12 V) in order to fully turn-on the power device and minimize conduction losses. Traditional buffer drive
circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise (by
placing the high-current driver IC physically close to the power switch), driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
The LM5109B-Q1 is the high voltage gate drivers designed to drive both the high-side and low-side N-Channel
MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit. The floating high side driver
is capable of operating with supply voltages up to 90V. This allows for N-Channel MOSFETs control in half-
bridge, full-bridge, push-pull, two switch forward and active clamp topologies. The outputs are independently
controlled. Each channel is controlled by its respective input pins (HI and LI), allowing full and independent
flexibility to control ON and OFF state of the output.
8.2 Typical Application
VIN
VCC
Anti-parallel Diode
R
Secondary
Side Circuit
BOOT
D
BOOT
(Optional)
HB
RGATE
VDD
VDD
HO
C
BOOT
0.1 µF
OUT1
OUT2
HI
LI
HS
LO
PWM
Controller
T1
LM5109
VSS
RGATE
1.0 µF
Figure 14. LM5109B-Q1 Driving MOSFETs in a Half Bridge Converter
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Typical Application (continued)
8.2.1 Design Requirements
Table 4. Design Example
PARAMETER
Gate Driver
MOSFET
VDD
VALUE
LM5109B-Q1
CSD19534KCS
10 V
QG
17 nC
fSW
500 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Select Bootstrap and VDD Capacitor
The bootstrap capacitor must maintain the VHB-HS voltage above the UVLO threshold for normal operation.
Calculate the maximum allowable drop across the bootstrap capacitor with Equation 1.
DVHB = VDD - VDH - VHBL = 10 V -1V - 6.7 V = 2.3 V
where
•
•
•
VDD = Supply voltage of the gate drive IC;
VDH = Bootstrap diode forward voltage drop;
VHBL = VHBRmax – VHBH, HB falling threshold;
(1)
Then, the total charge needed per switching cycle could be estimated by Equation 2.
DMax
IHB
0.95
0.2 mA
QTotal = QG +IHBS
ì
+
= 17 nC +10 mA ì
+
= 17.5 nC
ƒSW ƒSW
500 kHz 500 kHz
where
•
•
•
•
QG: Total MOSFET gate charge
IHBS: HB to VSS Leakage current
DMax: Converter maximum duty cycle
IHB: HB Quiescent current
(2)
(3)
Therefore, the minimum CBoot should be:
QTotal
17.5 nC
2.3 V
CBoot
=
=
= 7.6 nF
DVHB
In practice, the value of the CBoot capacitor should be greater than calculated to allow for situations where the
power stage may skip pulse due to load transients. It is recommended to have enough margins and place the
bootstrap capacitor as close to the HB and HS pins as possible.
CBoot = 100 nF
(4)
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBoot, as shown in
Equation 5.
CVDD = 1 µF
(5)
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be
twice that of the maximum VDD considering capacitance tolerances once the devices have a DC bias voltage
across them and to ensure long-term reliability.
8.2.2.2 Select External Bootstrap Diode and Its Series Resistor
The bootstrap capacitor is charged by the VDD through the external bootstrap diode every cycle when low side
MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power
dissipation in the bootstrap diode may be significant and the conduction loss also depends on its forward voltage
drop. Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate
driver circuit.
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For the selection of external bootstrap diodes, please refer to the application note SNVA083A. Bootstrap resistor
RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of voltage of VHB-HS
during each switching cycle, especially when HS pin have excessive negative transient voltage. RBOOT
recommended value is between 2 Ω and 10 Ω depending on diode selection. A current limiting resistor of 2.2 Ω
is selected to limit inrush current of bootstrap diode, and the estimated peak current on the DBoot is shown in
Equation 6.
VDD - VDH
10 V -1V
2.2 W
IDBoot(pk)
=
=
ö 4 A
RBoot
where
•
VDH is the Bootstrap diode forward voltage drop
(6)
8.2.2.3 Selecting External Gate Driver Resistor
External Gate Driver Resistor, RGATE, is sized to reduce ringing caused by parasitic inductances and
capacitances and also to limit the current coming out of the gate driver.
Peak HO pull-up current are calculated by the following equations.
VDD - VDH
10 V -1V
IOHH
=
=
= 0.48 A
RHOH + RGate + RGFET_Int 1.2 V /100 mA + 4.7 W + 2.2 W
where
•
•
•
IOHH – Peak pull-up current;
VDH – Bootstrap diode forward voltage drop;
RHOH – Gate driver internal HO pull-up resistance, provide by driver datasheet directly or estimated from the
testing conditions, i.e. RHOH=VOHH/IHO
;
•
•
RGate – External gate drive resistance;
R(GFET_Int) – MOSFET internal gate resistance, provided by transistor datasheet;
(7)
(8)
Similarly, Peak HO pull-down current is shown in Equation 8.
VDD - VDH
RHOL + RGate + RGFET_Int
IOLH
=
where
•
RHOL is HO pull-down resistance
Peak LO pullup current is shown in Equation 9.
VDD
IOHL
=
RLOH + RGate + RGFET_Int
where
•
RLOH is LO pull-up resistance.
(9)
Peak LO pulldown current is shown in Equation 10.
VDD
IOLL
=
RLOL + RGate + RFET_Int
where
•
RLOL is LO pull-down resistance
(10)
For some scenarios, if the applications require fast turn-off, an anti-paralleled diode on RGate could be used to
bypass the external gate drive resistor and speed-up turn-off transition.
8.2.2.4 Estimate the Driver Power Loss
The total driver IC power dissipation can be estimated through the following components.
1. Static power losses, PQC, due to quiescent current – IDD and IHB
;
PQC = VDD × IDD + (VDD – VDH) × IHB
(11)
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2. Level-shifter losses, PIHBS, due high side leakage current – IHBS;
PIHBS = VHB × IHBS × D
where
•
D is high side switch duty cycle
(12)
3. Dynamic losses, PQG1&2, due to the FETs gate charge – QG;
RGD_R
PQG1&2 = 2ì VDD ìQG ì ƒSW
ì
RGD_R + RGate + RGFET_Int
where
•
•
•
•
•
QG is total FETs gate charge;
fSW is switching frequency;
RGD_R is average value of pull-up and pull-down resistor;
RGate is external gate drive resistor;
RGFET_Int is internal FETs gate resistor;
(13)
4. Level-shifter dynamic losses, PLS, during high side switching due to required level-shifter charge on each
switching cycle – QP;
PLS = VHB × QP × fSW
(14)
In this example, the estimated gate driver loss in LM5109B-Q1 is shown in Equation 15.
12 W
P
= 10 V ì0.6 mA + 9 V ì0.2 mA + 72 V ì10 mA ì0.95 + 2ì10ì17 nCì 500 kHzì
+ 72 V ì 0.5 nCì 500 kHz = 0.134 W
LM5109BQ
12 W + 4.7 W + 2.2 W
(15)
For a given ambient temperature, the maximum allowable power loss of the IC can be defined as shown in
Equation 16.
TJ - TA
RqJA
P
=
LM5109BQ
where
•
•
•
•
PLM5109BQ = The total power dissipation of the driver
TJ = Junction temperature
TA = Ambient temperature
RθJA = Junction-to-ambient thermal resistance
(16)
The thermal metrics for the driver package is summarized in the Thermal Information section of the datasheet.
For detailed information regarding the thermal information table, please refer to the Texas Instruments
application note entitled Semiconductor and IC Package Thermal Metrics (SPRA953.).
8.2.3 Application Curves
Figure 15 and Figure 16 shows the rising/falling time and turn-on/off propagation delay testing waveform in room
temperature, and waveform measurement data (see the bottom part of the waveform). Each channel,
HI/LI/HO/LO, is labeled and displayed on the left hand of the waveforms.
The testing condition: load capacitance is 1 nF, VDD = 12 V, fSW = 500 kHz.
HI and LI share one same input from function generator, therefore, besides the propagation delay and
rising/falling time, the difference of the propagation delay between HO and LO gives the propagation delay
matching data.
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CL = 1 nF
VDD = 12 V
fSW = 500 kHz
CL = 1 nF
VDD = 12 V
fSW = 500 kHz
Figure 15. Rising Time and Turn-On Propagation Delay
Figure 16. Falling Time and Turn-Off Propagation Delay
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9 Power Supply Recommendations
The recommended bias supply voltage range for LM5109B-Q1 is from 8 V to 14 V. The lower end of this range is
governed by the internal under voltage-lockout (UVLO) protection feature of the VDD supply circuit blocks. The
upper-end of this range is driven by the 18-V absolute maximum voltage rating of the VDD. It is recommended to
keep a 4-V margin to allow for transient voltage spikes.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification,
the device will shut down. Therefore, while operating at or near the 8-V range, the voltage ripple on the auxiliary
power supply output should be smaller than the hysteresis specification of LM5109B-Q1 to avoid triggering
device-shutdown.
A local bypass capacitor should be placed between the VDD and GND pins. And this capacitor should be located
as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. TI
recommends using 2 capacitors across VDD and GND: a 100 nF ceramic surface-mount capacitor for high
frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to 10
µF, for IC bias requirements. In a similar manner, the current pulses delivered by the HO pin are sourced from
the HB pin. Therefore, a 22-nF to 220-nF local decoupling capacitor is recommended between the HB and HS
pins.
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10 Layout
10.1 Layout Guidelines
Optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations
during circuit board layout. The following points are emphasized:
1. Low ESR/ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB
and HS pins to support high peak currents drawn from VDD and HB during the turn-on of the external
MOSFETs.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between
the source of the high side MOSFET and the drain of the low side MOSFET (synchronous rectifier) must be
minimized.
4. Grounding considerations:
–
The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close
as possible to the MOSFETs.
–
The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
10.2 Layout Example
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-Dec-2015
PACKAGING INFORMATION
Orderable Device
LM5109BQNGTRQ1
LM5109BQNGTTQ1
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
WSON
WSON
NGT
8
8
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
L5109Q
L5109Q
ACTIVE
NGT
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5109B-Q1 :
Catalog: LM5109B
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
MECHANICAL DATA
NGT0008A
SDC08A (Rev A)
www.ti.com
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