LM5113-Q1 [TI]
适用于 GaNFET 的汽车类 1.2A/5A、100V 半桥栅极驱动器;
| 型号： | LM5113-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 GaNFET 的汽车类 1.2A/5A、100V 半桥栅极驱动器 栅极驱动 驱动器 |
| 文件： | 总28页 (文件大小：2791K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
LM5113-Q1 汽车 90V、1.2A/5A 半桥 GaN 驱动器
1 特性
3 说明
1
•
•
符合汽车应用 标准
具有符合 AEC-Q100 标准的下列特性：
LM5113-Q1 专为同时驱动采用同步降压、升压或半桥
配置的高侧和低侧增强模式氮化镓 (GaN) FET 或硅质
MOSFET 而设计，适用于汽车 应用。此器件具有一个
集成于内部的 100V 自举二极管，还为高侧和低侧输出
分别提供了独立的输入，可实现最大程度的灵活控制。
高侧偏置电压在内部被钳位为 5.2V，可防止栅极电压
超过增强模式 GaN FET 的最大栅极/源极电压额定
值。器件的输入与 TTL 逻辑兼容，无论 VDD 电压多
高，它都能够承受高达 14V 的输入电压。LM5113-Q1
具有分栅输出的能力，可独立灵活地调节开通和关断强
度。
–
器件温度 1 级：–40°C 至 125°C 的环境工作温
度范围
–
–
器件 HBM ESD 分类等级 1C
器件带电器件模型 (CDM) ESD 分类等级 C6
•
•
•
独立的高侧和低侧TTL 逻辑输入
1.2A 峰值拉电流能力，5A 峰值灌电流能力
高侧浮动偏置电压轨
工作电压高达 100VDC
•
•
内部自举电源电压钳位
分离输出实现可调的
开通和关断应力
此外，LM5113-Q1 具有非常可靠的灌电流能力，使栅
极保持低电平，从而防止开关操作期间发生误导通。
LM5113-Q1 的工作频率最高可达数 MHz。LM5113-
Q1 采用带有裸露焊盘的标准 10 引脚 WSON 封装，
可改善功耗。
•
•
•
0.6Ω 下拉电阻，2.1Ω 上拉电阻
快速传播时间（典型值为 28ns）
优异的传播延迟
（典型值为 1.5ns)
•
•
电源轨欠压锁定
低功耗
器件信息(1)
器件型号
LM5113-Q1
封装
封装尺寸（标称值）
WSON (10)
4.00mm x 4.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
•
•
•
•
移动无线充电器
音频功率放大器
音频电源
电流馈入型推挽式转换器
半桥和全桥转换器
同步降压转换器
简化应用示意图
0.1 ꢀF
VIN
HB
HOH
VDD
HI
HOL
1 ꢀF
Input
Filter 1
HS
Load
LM5113-Q1
Input
Filter 2
LI
LOH
LOL
EP
VSS
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSAR1
LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 15
Power Supply Recommendations...................... 19
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 4
6.5 Electrical Characteristics .......................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 器件和文档支持 ..................................................... 21
11.1 文档支持................................................................ 21
11.2 接收文档更新通知 ................................................. 21
11.3 社区资源................................................................ 21
11.4 商标....................................................................... 21
11.5 静电放电警告......................................................... 21
11.6 Glossary................................................................ 21
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (November 2017) to Revision B
Page
•
将数据表标题从“LM5113-Q1 汽车 90V、1.2A/5A 半桥 GaN 驱动器”更改成了“LM5113-Q1 汽车 90V、1.2A/5A 半桥
GaN 驱动器” ........................................................................................................................................................................... 1
•
•
•
在简化应用图 中添加了输入滤波器......................................................................................................................................... 1
Added EXT HI and EXT LO references to the Functional Block Diagram ........................................................................... 11
Changed the last paragraph and add new images to the Input and Output section ........................................................... 11
Changes from Original (March 2017) to Revision A
Page
•
将数据表标题从“LM5113-Q1 汽车 80V、1.2A/5A 半桥 GaN 驱动器”更改成了“LM5113-Q1 汽车 90V、1.2A/5A 半桥
GaN 驱动器” ........................................................................................................................................................................... 1
更改了简化应用图表 ............................................................................................................................................................... 1
Changed the Functional Block Diagram............................................................................................................................... 11
Added content to the Input and Output section.................................................................................................................... 11
Added content to the Start-up and UVLO section ................................................................................................................ 12
•
•
•
•
2
Copyright © 2017–2018, Texas Instruments Incorporated
LM5113-Q1
www.ti.com.cn
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
5 Pin Configuration and Functions
DPR Package
10-Pin WSON With Exposed Thermal Pad
Top View
VDD
HB
1
2
3
4
5
10 LOH
LOL
VSS
9
8
7
6
HOH
Thermal Pad
HOL
HS
LI
HI
Pin Functions
PIN
(1)
TYPE
DESCRIPTION
NO.
NAME
5-V positive gate drive supply: locally decouple to VSS using low-ESR/ESL capacitor
located as close as possible to the IC.
1
VDD
P
High-side gate driver bootstrap rail: connect the positive terminal of the bootstrap capacitor
to HB and the negative terminal to HS. The bootstrap capacitor must be placed as close to
the IC as possible.
2
HB
P
High-side gate driver turnon output: connect to the gate of high-side GaN FET with a short,
low inductance path. A gate resistor can be used to adjust the turnon speed.
3
4
5
6
HOH
HOL
HS
O
O
P
I
High-side gate driver turnoff output: connect to the gate of high-side GaN FET with a short,
low inductance path. A gate resistor can be used to adjust the turnoff speed.
High-side GaN FET source connection: connect to the bootstrap capacitor negative
terminal and the source of the high-side GaN FET.
High-side driver control input. The LM5113-Q1 inputs have TTL type thresholds. Unused
inputs must be tied to ground and not left open.
HI
Low-side driver control input. The LM5113-Q1 inputs have TTL type thresholds. Unused
inputs must be tied to ground and not left open.
7
8
9
LI
I
VSS
LOL
G
O
Ground return: all signals are referenced to this ground.
Low-side gate driver sink-current output: connect to the gate of the low-side GaN FET with
a short, low inductance path. A gate resistor can be used to adjust the turnoff speed.
Low-side gate driver source-current output: connect to the gate of high-side GaN FET with
a short, low inductance path. A gate resistor can be used to adjust the turnon speed.
10
LOH
—
O
Exposed pad: TI recommends that the exposed pad on the bottom of the package be
soldered to ground plane on the printed-circuit board to aid thermal dissipation.
EP
—
(1) I = Input, O = Output, G = Ground, P = Power
Copyright © 2017–2018, Texas Instruments Incorporated
3
LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
VHS – 0.3
–5
MAX
7
UNIT
VDD to VSS
V
V
V
HB to HS
7
LI or HI input
15
LOH, LOL output
HOH, HOL output
HS to VSS
VDD + 0.3
VHB + 0.3
93
V
V
V
HB to VSS
0
100
V
Operating junction temperature
Storage temperature, Tstg
150
°C
°C
–55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±1000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
5.5
UNIT
VDD
V
V
LI or HI input
0
14
HS
–5
90
V
HB
VHS + 4
VHS + 5.5
50
V
HS slew rate
V/ns
°C
Operating junction temperature
–40
125
6.4 Thermal Information
LM5113-Q1
DPR (WSON)
10 PINS
37.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
35.8
14.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
14.9
RθJC(bot)
4.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017–2018, Texas Instruments Incorporated
LM5113-Q1
www.ti.com.cn
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
6.5 Electrical Characteristics
Specifications are TJ = 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V.
No load on LOL and HOL or HOH and HOL(1)
PARAMETER
.
TEST CONDITIONS
MIN
TYP
0.07
2
MAX
UNIT
SUPPLY CURRENTS
TJ = 25°C
IDD
VDD quiescent current
LI = HI = 0 V
f = 500 kHz
mA
mA
mA
mA
µA
TJ = –40°C to 125°C
TJ = 25°C
0.1
3
IDDO
VDD operating current
TJ = –40°C to 125°C
TJ = 25°C
0.08
1.5
0.1
0.4
IHB
Total HB quiescent current
Total HB operating current
HB to VSS quiescent current
LI = HI = 0 V
f = 500 kHz
TJ = –40°C to 125°C
TJ = 25°C
0.1
2.5
10
1
IHBO
TJ = –40°C to 125°C
TJ = 25°C
IHBS
HS = HB = 90 V
f = 500 kHz
TJ = –40°C to 125°C
TJ = 25°C
IHBSO HB to VSS operating current
mA
TJ = –40°C to 125°C
INPUT PINS
TJ = 25°C
2.06
1.66
VIR
VIF
Input voltage threshold
Input voltage threshold
Rising edge
Falling edge
V
TJ = –40°C to 125°C
TJ = 25°C
1.89
1.48
2.18
1.76
V
TJ = –40°C to 125°C
VIHYS Input voltage hysteresis
RI Input pulldown resistance
400
200
mV
kΩ
TJ = 25°C
TJ = –40°C to 125°C
100
3.2
2.5
300
4.5
3.9
UNDERVOLTAGE PROTECTION
VDDR VDD rising threshold
TJ = 25°C
3.8
V
V
V
V
TJ = –40°C to 125°C
VDDH VDD threshold hysteresis
0.2
3.2
TJ = 25°C
VHBR
VHBH
HB rising threshold
TJ = –40°C to 125°C
HB threshold hysteresis
0.2
0.45
0.90
1.85
5.2
BOOTSTRAP DIODE
TJ = 25°C
VDL
VDH
RD
Low-current forward voltage
IVDD-HB = 100 µA
IVDD-HB = 100 mA
IVDD-HB = 100 mA
V
V
Ω
V
TJ = –40°C to 125°C
TJ = 25°C
0.65
1
High-current forward voltage
Dynamic resistance
TJ = –40°C to 125°C
TJ = 25°C
TJ = –40°C to 125°C
TJ = 25°C
3.60
5.45
HB-HS clamp regulation voltage
TJ = –40°C to 125°C
4.7
(1) Parameters that show only a typical value are ensured by design and may not be tested in production.
Copyright © 2017–2018, Texas Instruments Incorporated
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LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
Electrical Characteristics (continued)
Specifications are TJ = 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V.
No load on LOL and HOL or HOH and HOL(1)
PARAMETER
.
TEST CONDITIONS
MIN
TYP
0.06
0.21
MAX
UNIT
LOW- AND HIGH-SIDE GATE DRIVER
TJ = 25°C
VOL
Low-level output voltage
IHOL = ILOL = 100 mA
IHOH = ILOH = 100 mA
V
V
TJ = –40°C to 125°C
TJ = 25°C
0.10
0.31
High-level output voltage
VOH = VDD – LOH
VOH
TJ = –40°C to 125°C
or VOH = HB – HOH
IOHL
IOLL
Peak source current
Peak sink current
HOH, LOH = 0 V
HOL, LOL = 5 V
HOH, LOH = 0 V
HOL, LOL = 5 V
1.2
5
A
A
IOHLK High-level output leakage current
IOLLK Low-level output leakage current
TJ = –40°C to 125°C
TJ = –40°C to 125°C
1.5
1.5
µA
µA
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
45
UNIT
TJ = 25°C
26.5
tLPHL
tLPLH
tHPHL
tHPLH
tMON
tMOFF
LO turnoff propagation delay
LI falling to LOL falling
LI rising to LOH rising
HI falling to HOL falling
HI rising to HOH rising
ns
TJ = –40°C to 125°C
TJ = 25°C
28.0
26.5
28
LO turnon propagation delay
HO turnoff propagation delay
HO turnon propagation delay
ns
ns
ns
ns
ns
TJ = –40°C to 125°C
TJ = 25°C
45
TJ = –40°C to 125°C
TJ = 25°C
45
TJ = –40°C to 125°C
45.0
8
TJ = 25°C
1.5
Delay matching
LO on and HO off
TJ = –40°C to 125°C
TJ = 25°C
1.5
Delay matching
LO off and HO on
TJ = –40°C to 125°C
CL = 1000 pF
CL = 1000 pF
CL = 1000 pF
CL = 1000 pF
8
tHRC
tLRC
tHFC
tLFC
HO rise time (0.5 V – 4.5 V)
LO rise time (0.5 V – 4.5 V)
HO fall time (0.5 V – 4.5 V)
LO fall time (0.5 V – 4.5 V)
7
7
ns
ns
ns
ns
3.5
3.5
Minimum input pulse width
that changes the output
tPW
tBS
10
40
ns
ns
Bootstrap diode
reverse recovery time
IF = 100 mA, IR = 100 mA
6
Copyright © 2017–2018, Texas Instruments Incorporated
LM5113-Q1
www.ti.com.cn
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
LI
LI
HI
HI
t
HPLH
t
LPLH
t
HPHL
t
LPHL
LO
LO
HO
HO
t
t
MON
MOFF
Figure 1. Timing Diagram
Copyright © 2017–2018, Texas Instruments Incorporated
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LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
6.7 Typical Characteristics
Figure 2. Peak Source Current vs Output Voltage
Figure 3. Peak Sink Current vs Output Voltage
Figure 4. IDDO vs Frequency
Figure 5. IHBO vs Frequency
Figure 6. IDD vs Temperature
Figure 7. IHB vs Temperature
8
Copyright © 2017–2018, Texas Instruments Incorporated
LM5113-Q1
www.ti.com.cn
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
Typical Characteristics (continued)
Figure 8. UVLO Rising Thresholds vs Temperature
Figure 9. UVLO Falling Thresholds vs Temperature
Figure 10. Input Thresholds vs Temperature
Figure 11. Input Threshold Hysteresis vs Temperature
Figure 12. Bootstrap Diode Forward Voltage
Figure 13. Propagation Delay vs Temperature
Copyright © 2017–2018, Texas Instruments Incorporated
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LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
Typical Characteristics (continued)
Note: Unless otherwise specified, VDD = VHB = 5 V,
VSS = VHS = 0 V.
Figure 14. LO and HO Gate Drive – High/Low Level
Output Voltage vs Temperature
Figure 15. HB Regulation Voltage vs Temperature
10
Copyright © 2017–2018, Texas Instruments Incorporated
LM5113-Q1
www.ti.com.cn
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
7 Detailed Description
7.1 Overview
The LM5113-Q1 is a high-frequency, high- and low- side gate driver for enhancement mode Gallium Nitride
(GaN) FETs in a synchronous buck, boost, or half bridge configuration. The high-side bias voltage is generated
using a bootstrap technique and is internally clamped at 5.2 V, which prevents the gate voltage from exceeding
the maximum gate-source voltage rating of enhancement mode GaN FETs. The LM5113-Q1 has split-gate
outputs with strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently.
The LM5113-Q1 can operate up to several MHz, and is available in a standard 10-pin WSON package that
contains an exposed pad to aid power dissipation.
7.2 Functional Block Diagram
HB
UVLO
& CLAMP
HOH
LEVEL
SHIFT
HOL
HS
EXT HI
HI
VDD
UVLO
LOH
LOL
EXT LI
LI
VSS
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Input and Output
The input pins of the LM5113-Q1 are independently controlled with TTL input thresholds and can withstand
voltages up to 12 V regardless of the VDD voltage. This allows the inputs to be directly connected to the outputs
of an analog PWM controller with up to 12-V power supply, eliminating the need for a buffer stage
The output pulldown and pullup resistance of LM5113-Q1 is optimized for enhancement mode GaN FETs to
achieve high frequency and efficient operation. The 0.6-Ω pulldown resistance provides a robust low impedance
turnoff path necessary to eliminate undesired turnon induced by high dv/dt or high di/dt. The 2.1-Ω pullup
resistance helps reduce the ringing and over-shoot of the switch node voltage. The split outputs of the LM5113-
Q1 offer flexibility to adjust the turnon and turnoff speed by independently adding additional impedance in either
the turnon path, the turnoff path, or both.
If the input signal for either of the two channels, HI or LI, is not used, the control pin must be tied to either VDD
or VSS. These inputs must not be left floating.
Copyright © 2017–2018, Texas Instruments Incorporated
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LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
Feature Description (continued)
Additionally, the input signals avoid pulses shorter than 3 ns by using the input filter to the HI and LI input pins.
The values and part numbers of the circuit components are shown in the Figure 16.
1 kꢀ
EXT HI
HI
22 pF
Figure 16. Input Filter 1 (High-Side Input Filter)
If short pulses or short delays are required, the circuit in Figure 17 is recommended.
SN74LVC2G32YZP
HI
EXT HI
100 kꢀ
50 pF
Copyright © 2017, Texas Instruments Incorporated
Figure 17. Input Filter 1 for Short Pulses (High-Side Input Filter)
7.3.2 Start-Up and UVLO
The LM5113-Q1 has an undervoltage lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD
voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored to prevent the GaN FETs
from being partially turned on. Also, if there is insufficient VDD voltage, the UVLO actively pulls the LOL and HOL
low. When the VDD voltage is above its UVLO threshold, but the HB to HS bootstrap voltage is below the UVLO
threshold of 3.2 V, only HOL is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid
chattering.
The startup voltage sequencing for this device is as follows: VDD voltage first, with the VIN voltage present
thereafter.
The LM5113-Q1 requires an external bootstrap diode with a 100 Ω series resistor from VDD to HB to charge the
high side supply on a cycle by cycle basis. The recommended bootstrap diode options are BAT46, BAT41, or
LL4148.
Table 1. VDD UVLO Feature Logic Operation
CONDITION (VHB-HS > VHBR for all cases below)
VDD – VSS < VDDR during device start-up
VDD – VSS < VDDR during device start-up
VDD – VSS < VDDR during device start-up
VDD – VSS < VDDR during device start-up
VDD – VSS < VDDR – VDDH after device start-up
VDD – VSS < VDDR – VDDH after device start-up
VDD – VSS < VDDR – VDDH after device start-up
VDD – VSS < VDDR – VDDH after device start-up
HI
H
L
LI
L
HO
L
LO
L
H
H
L
L
L
H
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
12
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LM5113-Q1
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ZHCSG45B –MARCH 2017–REVISED MARCH 2018
Table 2. VHB-HS UVLO Feature Logic Operation
CONDITION (VDD > VDDR for all cases below)
HI
H
L
LI
L
HO
L
LO
L
VHB-HS < VHBR during device start-up
VHB-HS < VHBR during device start-up
VHB-HS < VHBR during device start-up
VHB-HS < VHBR during device start-up
VHB-HS < VHBR – VHBH after device start-up
VHB-HS < VHBR – VHBH after device start-up
VHB-HS < VHBR – VHBH after device start-up
VHB-HS < VHBR – VHBH after device start-up
H
H
L
L
H
H
L
H
L
L
L
H
L
L
L
L
H
H
L
L
H
H
L
H
L
L
L
7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
Due to the intrinsic nature of enhancement mode GaN FETs, the source-to-drain voltage of the bottom switch is
usually higher than a diode forward voltage drop when the gate is pulled low. This causes negative voltage on
HS pin. Moreover, this negative voltage transient may become even more pronounces due to the effects of board
layout and device drain/source parasitic inductances. With high-side driver using the floating bootstrap
configuration, negative HS voltage can lead to an excessive bootstrap voltage, which can damage the high-side
GaN FET. The LM5113-Q1 solves this problem with an internal clamping circuit that prevents the bootstrap
voltage from exceeding 5.2 V typical.
7.3.4 Level Shift
The level-shift circuit is the interface from the high-side input to the high-side driver stage, which is referenced to
the switch node (HS). The level shift allows control of the HO output, which is referenced to the HS pin and
provides excellent delay matching with the low-side driver. Typical delay matching between LO and HO is around
1.5 ns.
7.4 Device Functional Modes
Table 3 shows the device truth table.
Table 3. Truth Table
HI
L
LI
L
HOH
Open
Open
H
HOL
L
LOH
Open
H
LOL
L
L
H
L
L
Open
L
H
H
Open
Open
Open
H
H
H
Open
Copyright © 2017–2018, Texas Instruments Incorporated
13
LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To operate GaN transistors at very high switching frequencies and to reduce associated switching losses, a
powerful gate driver is employed between the PWM output of controller and the gates of the GaN transistor.
Also, gate drivers are indispensable when the outputs of the PWM controller do not meet the voltage or current
levels needed to directly drive the gates of the switching devices. With the advent of digital power, this situation
is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal, which
cannot effectively turn on a power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive
voltage (such as 12 V) to fully turn on the power device and minimize conduction losses. Traditional buffer-drive
circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also address other needs such as minimizing the effect of high-frequency switching noise
(by placing the high-current driver IC physically close to the power switch), driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate-charge power losses from the controller into the driver.
The LM5113-Q1 is a MHz high- and low-side gate driver for enhancement mode GaN FETs in a synchronous
buck, boost, or half-bridge configuration. The high-side bias voltage is generated using a bootstrap technique
and is internally clamped at 5.2 V, which prevents the gate voltage from exceeding the maximum gate-source
voltage rating of enhancement mode GaN FETs. The LM5113-Q1 has split gate outputs with strong sink
capability, providing flexibility to adjust the turnon and turnoff strength independently.
14
Copyright © 2017–2018, Texas Instruments Incorporated
LM5113-Q1
www.ti.com.cn
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
8.2 Typical Application
The circuit in Figure 18 shows a synchronous buck converter to evaluate the LM5113-Q1 device. Detailed
synchronous buck converter specifications are listed in Design Requirements. The active clamping voltage mode
controller LM5025 is used for close-loop control and generates the PWM signals of the buck switch and the
synchronous switch. For more information, see Figure 18.
5
2
1 1
9
0 1
8
6
4
7
5
3
2
1
E P
2
Input 15 V to 60 V, output 10 V, 800 kHz
Figure 18. LP5113-Q1 Application Circuit
Copyright © 2017–2018, Texas Instruments Incorporated
15
LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
Typical Application (continued)
8.2.1 Design Requirements
Table 4 lists the design requirements for the typical application.
Table 4. Design Parameters
PARAMETER
Input operating range
Output voltage
SPECIFICATION
15 – 60 V
10 V
Output current, 48-V input
Output current, 60-V input
Efficiency at 48 V, 10 A
Frequency
10 A
7 A
>90%
800 kHz
8.2.2 Detailed Design Procedure
This procedure outlines the design considerations of LM5113-Q1 in a synchronous buck converter with
enhancement mode GaN FET. Refer to Figure 18 for component names and network locations. For additional
design help, see Figure 18.
8.2.2.1 VDD Bypass Capacitor
The VDD bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the
reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with
Equation 1.
QgH + QgL + Qrr
CVDD
>
DV
where
•
•
•
QgH and QgL are gate charge of the high-side and low-side transistors, respectively.
Qrr is the reverse recovery charge of the bootstrap diode, which is typically around 4 nC.
ΔV is the maximum allowable voltage drop across the bypass capacitor.
(1)
TI recommends a 0.1-µF or larger value, good quality, ceramic capacitor. The bypass capacitor must be placed
as close as possible to the pins of the ICto minimize the parasitic inductance.
8.2.2.2 Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side switch, DC bias power for HB UVLO circuit,
and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with
Equation 2.
QgH +IHB ì tON + Qrr
CBST
>
DV
where
•
•
IHB is the quiescent current of the high-side driver.
ton is the maximum on-time period of the high-side transistor.
(2)
A good-quality, ceramic capacitor must be used for the bootstrap capacitor. TI recommends placement of the
bootstrap capacitor as close as possible to the HB and HS pin.
16
Copyright © 2017–2018, Texas Instruments Incorporated
LM5113-Q1
www.ti.com.cn
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
8.2.2.3 Power Dissipation
The power consumption of the driver is an important measure that determines the maximum achievable
operating frequency of the driver. It must be kept below the maximum power-dissipation limit of the package at
the operating temperature. The total power dissipation of the LM5113-Q1 is the sum of the gate driver losses and
the bootstrap diode power loss.
The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated as:
P = CLoadH + CLoadL ì VD2D ì fSW
where
•
CLoadH and CLoadL are the high-side and the low-side capacitive loads, respectively.
(3)
(4)
It can also be calculated with the total input gate charge of the high-side and the low-side transistors as:
P = QgH + QgL ì VDD ì fSW
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. Figure 19 shows the measured gate-driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equations. This plot can be used to
approximate the power losses due to the gate drivers.
Gate-driver power dissipation (LO+HO), VDD = +5 V
Figure 19. Neglecting Bootstrap Diode Losses
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these
events happens once per cycle, the diode power loss is proportional to the operating frequency. Larger
capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input
voltages (VIN) to the half bridge also result in higher reverse recovery losses.
Figure 20 and Figure 21 show the forward bias power loss and the reverse bias power loss of the bootstrap
diode, respectively. The plots are generated based on calculations and lab measurements of the diode reverse
time and current under several operating conditions. The plots can be used to predict the bootstrap diode power
loss under different operating conditions.
Copyright © 2017–2018, Texas Instruments Incorporated
17
LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
The load of high-side driver is a GaN FET with total gate charge of
10 nC.
The load of high-side driver is a GaN FET with total gate charge of
10 nC.
Figure 21. Reverse Recovery Power Loss of
Figure 20. Forward Bias Power Loss of
Bootstrap Diode VIN = 50 V
Bootstrap Diode VIN = 50 V
The sum of the driver loss and the bootstrap diode loss is the total power loss of the IC. For a given ambient
temperature, the maximum allowable power loss of the IC can be defined as Equation 5.
(TJ - TA)
P =
qJA
(5)
8.2.3 Application Curves
Conditions:
Conditions:
Input Voltage = 48 V DC, Load Current = 5 A
Traces:
Input Voltage = 48 V DC,
Load Current = 10 A
Top Trace: Gate of Low-Side eGaN FET, Volt/div = 2 V
Bottom Trace: LI of LM5113-Q1, Volt/div = 5 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 0.2 µs/div
Figure 22. Low-Side Driver Input and Output
Traces:
Trace: Switch-Node Voltage, Volts/div = 20 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 50 ns/div
Figure 23. Switch-Node Voltage
18
Copyright © 2017–2018, Texas Instruments Incorporated
LM5113-Q1
www.ti.com.cn
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
9 Power Supply Recommendations
The recommended bias supply voltage range for LM5113-Q1 is from 4.5 V to 5.5 V. The lower end of this range
is governed by the internal undervoltage lockout (UVLO) protection feature of the VDD supply circuit. TI
recommends keeping proper margin to allow for transient voltage spikes while not violating the LM5113-Q1
absolute maximum VDD voltage rating and the GaN transistor gate breakdown voltage limit.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification,
the device shuts down. Therefore, while operating at or near the 4.5-V range, the voltage ripple on the VDD
power supply output must be smaller than the hysteresis specification of LM5113-Q1 UVLO to avoid triggering
device shutdown.
A local bypass capacitor must be placed between the VDD and VSS pins. This capacitor must be located as
close as possible to the device. A low-ESR, ceramic surface-mount capacitor is recommended. TI recommends
using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high frequency filtering
placed very close to VDD and GND pin, and another surface-mount capacitor, 220-nF to 10-μF, for IC bias
requirements.
Copyright © 2017–2018, Texas Instruments Incorporated
19
LM5113-Q1
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
Small gate capacitance and miller capacitance enable enhancement mode GaN FETs to operate with fast
switching speed. The induced high dv/dt and di/dt, coupled with a low gate-threshold voltage and limited
headroom of enhancement mode GaN FETs gate voltage, make the circuit layout crucial to the optimum
performance. Following are some recommendations.
1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and
discharge the GaN FETs gate into a minimal physical area. This decreases the loop inductance and
minimize noise issues on the gate terminal of the GaN FETs. The GaN FETs must be placed close to the
driver.
2. The second high current path includes the bootstrap capacitor, the local ground referenced VDD bypass
capacitor, and low-side GaN FET. The bootstrap capacitor is recharged on a cycle-by-cycle basis through
the bootstrap diode from the ground referenced VDD capacitor. The recharging occurs in a short time interval
and involves high peak current. Minimizing this loop length and area on the circuit board is important to
ensure reliable operation.
3. The parasitic inductance in series with the source of the high-side FET and the low-side FET can impose
excessive negative voltage transients on the driver. TI recommends connecting the HS pin and VSS pin to
the respective source of the high-side and low-side transistors with a short and low-inductance path.
4. The parasitic source inductance, along with the gate capacitor and the driver pulldown path, can form an
LCR resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to
damp the ringing.
5. Low ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak current being drawn from VDD during turnon of the FETs. Keeping
guideline number 1 above (minimized GaN FETs gate driver loop) as the first priority, it is also desirable to
place the VDD decoupling capacitor and the HB to HS bootstrap capacitor on the same side of the PC board
as the driver. The inductance of vias can impose excessive ringing on the IC pins.
6. To prevent excessive ringing on the input power bus, good decoupling practices are required by placing low-
ESR ceramic capacitors adjacent to the GaN FETs.
Figure 24 and Figure 25 show recommended layout patterns for the 10-pin WSON package. Two cases are
considered: (1) Without any gate resistors, and (2) with an optional turnon gate resistor. Note that 0402 surface
mount package is assumed for the passive components in Figure 24 and Figure 25.
10.2 Layout Example
Bootstrap
Capacitor
Bootstrap
Capacitor
HO
HS
To Hi-Side FET
HO
HS
To Hi-Side FET
Bypass
Capacitor
Bypass
Capacitor
LO
GND
To Low-Side FET
LO
GND
To Low-Side FET
Figure 24. 10-Pin WSON Without Gate Resistors
Figure 25. 10-Pin WSON With HOH and LOH Gate
Resistors
20
版权 © 2017–2018, Texas Instruments Incorporated
LM5113-Q1
www.ti.com.cn
ZHCSG45B –MARCH 2017–REVISED MARCH 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
相关文档如下：
AN-2149 LM5113 评估板 (SNVA484)
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我 进行注册，即可每周接收
产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5113QDPRRQ1
ACTIVE
WSON
DPR
10
4500 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5113Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Mar-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5113QDPRRQ1
WSON
DPR
10
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Mar-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DPR 10
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LM5113QDPRRQ1
4500
Pack Materials-Page 2
PACKAGE OUTLINE
DPR0010A
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
(0.2)
4.1
3.9
PIN 1 INDEX AREA
FULL R
BOTTOM VIEW
SIDE VIEW
20.000
ALTERNATIVE LEAD
DETAIL
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
2.6 0.1
(0.1) TYP
SEE ALTERNATIVE
LEAD DETAIL
5
6
2X
3.2
11
3
0.1
8X 0.8
1
10
0.35
0.25
0.1
10X
0.5
0.3
PIN 1 ID
10X
C A B
C
0.05
4218856/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
10X (0.6)
SYMM
10
1
10X (0.3)
(1.25)
SYMM
11
(3)
8X (0.8)
6
5
(
0.2) VIA
TYP
(1.05)
(R0.05) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EDGE
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218856/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPR0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
10X (0.6)
METAL
TYP
(0.68)
10
1
10X (0.3)
(0.76)
11
SYMM
8X (0.8)
4X
(1.31)
5
6
(R0.05) TYP
4X (1.15)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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SI9137DB
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