LM5116WG/NOPB [TI]
100V 宽输入电压同步降压控制器 | NAR | 20 | -40 to 125;
| 型号： | LM5116WG/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 100V 宽输入电压同步降压控制器 | NAR | 20 | -40 to 125 控制器 |
| 文件： | 总34页 (文件大小：1013K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
LM5116WG Wide Range Synchronous Buck Controller
Check for Samples: LM5116WG
1
FEATURES
DESCRIPTION
The LM5116WG is a synchronous buck controller
intended for step-down regulator applications from a
high voltage or widely varying input supply. The
control method is based upon current mode control
utilizing an emulated current ramp. Current mode
control provides inherent line feed-forward, cycle by
cycle current limiting and ease of loop compensation.
The use of an emulated control ramp reduces noise
sensitivity of the pulse-width modulation circuit,
allowing reliable control of very small duty cycles
necessary in high input voltage applications. The
operating frequency is programmable from 50 kHz to
1 MHz. The LM5116WG drives external high-side and
low-side NMOS power switches with adaptive dead-
time control. A user-selectable diode emulation mode
enables discontinuous mode operation for improved
efficiency at light load conditions. A low quiescent
current shutdown disables the controller and
consumes less than 10 µA of total input current.
2
•
Hermetic Package for Harsh Operating
Environments
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Emulated Peak Current Mode
Wide Operating Range up to 100V
Low IQ Shutdown (< 10 µA)
Drives Standard or Logic Level MOSFETs
Robust 3.5A Peak Gate Drive
Free-Run or Synchronous Operation to 1 MHz
Optional Diode Emulation Mode
Programmable Output from 1.215V to 80V
Precision 1.5% Voltage Reference
Programmable Current Limit
Programmable Soft-Start
Programmable Line Under-Voltage Lockout
Automatic Switch to External Bias Supply
CPGA-20 with No Thermal Shutdown
Additional features include
a high voltage bias
regulator, automatic switch-over to external bias for
improved efficiency, frequency synchronization, cycle
by cycle current limit and adjustable line under-
voltage lockout. The device is available in a CPGA-20
high temperature ceramic package with the thermal
shutdown feature disabled.
Typical Application
VIN
VCC
VIN
LM5116WG
C
VCC
R
R
C
UV2
IN
HB
UVLO
V
IN
UV1
C
HB
HO
SW
L
EN
VOUT
C
SYNC
RT/SYNC
C
OUT
LO
CS
R
T
R
S
COMP
FB
CSG
C
COMP
DEMB
C
HF
R
COMP
VOUT
VCCX
R
R
FB2
SS
RAMP
C
AGND PGND
RAMP
C
SS
FB1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
Connection Diagram
VIN
UVLO
RT/SYNC
EN
1
2
20
19
18
17
16
15
14
13
12
11
SW
HO
3
HB
4
VCCX
VCC
LO
RAMP
AGND
SS
5
6
7
PGND
CSG
CS
FB
8
COMP
VOUT
9
10
DEMB
Figure 1. Top View
See Package Number NAR0020A
2
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
PIN DESCRIPTIONS
Pin
1
Name
Description
VIN
Chip supply voltage, input voltage monitor and input to the VCC regulator.
2
UVLO
If the UVLO pin is below 1.215V, the regulator will be in standby mode (VCC regulator running, switching regulator
disabled). If the UVLO pin voltage is above 1.215V, the regulator is operational. An external voltage divider can be used
to set an under-voltage shutdown threshold. There is a fixed 5 µA pull up current on this pin when EN is high. UVLO is
pulled to ground in the event a current limit condition exists for 256 clock cycles.
3
RT/SYN The internal oscillator is set with a single resistor between this pin and the AGND pin. The recommended frequency
C
range is 50 kHz to 1 MHz. The internal oscillator can be synchronized to an external clock by AC coupling a positive
edge onto this node.
4
5
EN
If the EN pin is below 0.5V, the regulator will be in a low power state drawing less than 10 µA from VIN. EN must be
pulled above 3.3V for normal operation.
RAMP Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope used for
current mode control.
6
7
AGND Analog ground. Connect directly to PGND under the LM5116WG.
SS
An external capacitor and an internal 10 µA current source set the soft start time constant for the rise of the error amp
reference. The SS pin is held low during VCC < 4.5V, UVLO < 1.215V, or EN input low.
8
9
FB
Feedback signal from the regulated output. This pin is connected to the inverting input of the internal error amplifier. The
regulation threshold is 1.215V.
COMP Output of the internal error amplifier. The loop compensation network should be connected between this pin and the FB
pin.
10
11
VOUT
Output monitor. Connect directly to the output voltage.
DEMB Low-side MOSFET source voltage monitor for diode emulation. For start-up into a pre-biased load, tie this pin to ground
at the CSG connection. For fully synchronous operation, use an external series resistor between DEMB and ground to
raise the diode emulation threshold above the low-side SW on-voltage.
12
13
CS
Current sense amplifier input. Connect to the top of the current sense resistor or the drain of the low-sided MOSFET if
RDS(ON) current sensing is used.
CSG
Current sense amplifier input. Connect to the bottom of the sense resistor or the source of the low-side MOSFET if
RDS(ON) current sensing is used.
14
15
16
17
PGND Power ground. Connect directly to AGND under the LM5116WG.
LO
Connect to the gate of the low-side synchronous MOSFET through a short, low inductance path.
Locally decouple to PGND using a low ESR/ESL capacitor located as close to the controller as possible.
VCC
VCCX
Optional input for an externally supplied VCC. If VCCX > 4.5V, VCCX is internally connected to VCC and the internal
VCC regulator is disabled. If VCCX is unused, it should be connected to ground.
18
HB
High-side driver supply for bootstrap gate drive. Connect to the cathode of the bootstrap diode and the positive terminal
of the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side MOSFET gate and should be
placed as close to the controller as possible.
19
20
HO
SW
Connect to the gate of the high-side synchronous MOSFET through a short, low inductance path.
Switch node. Connect to the negative terminal of the bootstrap capacitor and the source terminal of the high-side
MOSFET.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
Absolute Maximum Ratings(1)(2)
VIN to GND
-0.3V to 100V
-0.3 to 16V
(3)
VCC, VCCX, UVLO to GND
SW, CS to GND
HB to SW
-3.0 to 100V
-0.3 to 16V
HO to SW
-0.3 to HB+0.3V
-0.3 to 100V
-1V to 1V
VOUT to GND
CSG to GND
LO to GND
SS to GND
FB to GND
-0.3 to VCC+0.3V
-0.3 to 7V
-0.3 to 7V
DEMB to GND
RT to GND
EN to GND
ESD Rating
-0.3 to VCC
-0.3 to 7V
-0.3 to 100V
(4)
HBM
2 kV
-55°C to +150°C
+150°C
Storage Temperature Range
Junction Temperature
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) These pins must not exceed VIN.
(4) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. LO, HO and HB are rated at 1 kV. 2
kV rating for all pins except VIN which is rated for 1.5 kV.
Operating Ratings(1)(2)
VIN
6V to 100V
4.75V to 15V
4.75V to 15V
-0.3V to 2V
VCC, VCCX
HB to SW
DEMB to GND
Junction Temperature
-40°C to +125°C
(1) Operating Ratings are conditions under which operation of the device is intended to be functional. Operating Ratings do not imply
guaranteed performance limits.
(2) Note: RAMP, COMP are output pins. As such they are not specified to have an external voltage applied.
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -40°C to
+125°C and are provided for reference only. Unless otherwise specified, the following conditions apply: VIN = 48V, VCC =
7.4V, VCCX = 0V, EN = 5V, RT = 16 kΩ, no load on LO and HO.
Symbol
VIN Supply
Parameter
Conditions
Min
Typ
Max
Units
IBIAS
IBIASX
ISTDBY
VIN Operating Current
VIN Operating Current
VIN Shutdown Current
VCCX = 0V, VIN = 48V
VCCX = 0V, VIN = 100V
VCCX = 5V, VIN = 48V
VCCX = 5V, VIN = 100V
EN = 0V, VIN = 48V
5
5.9
1.2
1.6
1
7
mA
mA
mA
mA
µA
8
1.7
2.3
10
EN = 0V, VIN = 100V
1
µA
4
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -40°C to
+125°C and are provided for reference only. Unless otherwise specified, the following conditions apply: VIN = 48V, VCC =
7.4V, VCCX = 0V, EN = 5V, RT = 16 kΩ, no load on LO and HO.
Symbol
VCC Regulator
VCC(REG)
Parameter
Conditions
Min
Typ
Max
7.7
6.0
4.7
6.2
Units
VCC Regulation
7.1
7.4
10.6
5.9
V
V
VCC LDO Mode Turn-off
VCC Regulation
VIN = 6V
5.0
15
V
VCC Sourcing Current Limit
VCCX Switch Threshold
VCCX Switch Hysteresis
VCCX Switch RDS(ON)
VCCX Leakage
VCC = 0V
VCCX Rising
26
mA
V
4.3
4.5
0.25
3.8
V
ICCX = 10 mA
VCCX = 0V
VCCX = 3V
VCC Rising
Ω
-200
100
4.5
nA
kΩ
V
VCCX Pull- down Resistance
VCC Under-voltage Threshold
VCC Under-voltage Hysteresis
HB DC Bias Current
4.3
4.7
200
0.5
0.2
V
HB - SW = 15V
125
µA
EN Input
VIL max
VIH min
EN Input Low Threshold
EN Input High Threshold
EN Input Bias Current
EN Input Bias Current
EN Input Bias Current
V
3.3
-7.5
-1
V
VEN = 3V
-3
0
1
1
µA
µA
µA
VEN = 0.5V
VEN = 100V
20
90
UVLO Thresholds
UVLO Standby Threshold
UVLO Threshold Hysteresis
UVLO Pull-up Current Source
UVLO Pull-down RDS(ON)
UVLO Rising
UVLO = 0V
1.170
1.215
0.1
1.262
V
V
5.4
µA
Ω
80
210
14
Soft Start
SS Current Source
SS = 0V
8
11
3
µA
V
SS Diode Emulation Ramp Disable
Threshold
SS Rising
SS to FB Offset
FB = 1.25V
160
45
mV
mV
SS Output Low Voltage
Sinking 100 µA, UVLO = 0V
Error Amplifier
VREF
FB Reference Voltage
Measured at FB pin, FB =
COMP
1.195
3
1.215
15
1.231
500
V
FB Input Bias Current
COMP Sink/Source Current
DC Gain
FB = 2V
nA
mA
dB
AOL
fBW
80
3
Unity Gain Bandwidth
MHz
PWM Comparators
tHO(OFF)
Forced HO Off-time
320
450
100
580
ns
ns
tON(min)
Minimum HO On-time
VIN = 80V, CRAMP = 50 pF
Oscillator
fSW1
Frequency 1
RT = 16 kΩ
RT = 5 kΩ
180
480
200
535
220
590
kHz
kHz
V
fSW2
Frequency 2
RT output voltage
RT sync positive threshold
1.191
3.0
1.215
3.5
1.239
4.0
V
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -40°C to
+125°C and are provided for reference only. Unless otherwise specified, the following conditions apply: VIN = 48V, VCC =
7.4V, VCCX = 0V, EN = 5V, RT = 16 kΩ, no load on LO and HO.
Symbol
Current Limit
Parameter
Conditions
Min
Typ
Max
Units
VCS(TH)
Cycle-by-cycle Sense Voltage Threshold VCCX = 0V, RAMP = 0V
(CSG - CS)
94
105
-1
110
122
126
139
mV
mV
VCS(THX)
Cycle-by-cycle Sense Voltage Threshold VCCX = 5V, RAMP = 0V
(CSG - CS)
CS Bias Current
CS = 100V
CS = 0V
1
µA
µA
µA
ms
CS Bias Current
90
90
125
125
CSG Bias Current
Current Limit Fault Timer
CSG = 0V
RT = 16 kΩ, (200 kHz), (256
1.28
clock cycles)
RAMP Generator
IR1
IR2
RAMP Current 1
VIN = 60V, VOUT=10V
VIN = 10V, VOUT = 10V
VOUT = 36V
235
21
285
28
335
35
µA
µA
µA
mV
RAMP Current 2
VOUT Bias Current
RAMP Output Low Voltage
200
265
VIN = 60V, VOUT = 10V
Diode Emulation
SW Zero Cross Threshold
DEMB Output Current
DEMB Output Current
DEMB Output Current
-6
2.7
38
65
mV
µA
µA
µA
DEMB = 0V, SS = 1.25V
DEMB =0V, SS = 2.8V
1.6
28
45
3.8
48
85
DEMB = 0V, SS = Regulated
by FB
LO Gate Driver
VOLL
LO Low-state Output Voltage
LO High-state Output Voltage
ILO = 100 mA
0.08
0.25
0.17
V
V
VOHL
ILO = -100 mA, VOHL = VCC
VLO
-
LO Rise Time
C-load = 1000 pF
C-load = 1000 pF
VLO = 0V
18
12
ns
ns
A
LO Fall Time
IOHL
IOLL
Peak LO Source Current
Peak LO Sink Current
1.8
3.5
VLO = VCC
A
HO Gate Driver
VOLH
HO Low-state Output Voltage
HO High-state Output Voltage
IHO = 100 mA
0.17
0.45
0.27
V
V
VOHH
IHO = -100 mA, VOHH = VHB
VHO
-
HO Rise Time
C-load = 1000 pF
C-load = 1000 pF
VHO = 0V
19
13
1
ns
ns
A
HO High-side Fall Time
Peak HO Source Current
Peak HO Sink Current
HB to SW under-voltage
IOHH
IOLH
VHO = VCC
2.2
3
A
V
Switching Characteristics
LO Fall to HO Rise Delay
HO Fall to LO Rise Delay
C-load = 0
C-load = 0
75
70
ns
ns
Thermal
θJA
Junction to Ambient
Junction to Case
115
13
°C/W
°C/W
θJC
6
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
Typical Performance Characteristics
FB Reference Voltage vs Temperature
FB Input Bias Current vs Temperature
Figure 2.
Figure 3.
EN Input Threshold vs Temperature
VIN Operating Current vs Temperature
Figure 4.
Figure 5.
SS Current vs Temperature
RAMP Current vs Temperature
Figure 6.
Figure 7.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
Typical Performance Characteristics (continued)
VCC UVLO vs Temperature
VCC LDO Switch vs Temperature
Figure 8.
Figure 9.
VCC Regulation vs Temperature
VCC Current Limit vs Temperature
Figure 10.
Figure 11.
VCCX Switch Threshold vs Temperature
VCCX Switch RDS(ON) vs Temperature
Figure 12.
Figure 13.
8
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
Typical Performance Characteristics (continued)
Frequency vs Temperature
Frequency vs Temperature
Figure 14.
Figure 15.
RT/SYNC Threshold vs Temperature
RT/SYNC Hysteresis vs Temperature
Figure 16.
Figure 17.
Forced HO Off-Time vs Temperature
DEMB Output Current vs Temperature
Figure 18.
Figure 19.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
Typical Performance Characteristics (continued)
Current Limit Threshold vs Temperature
HO UVLO vs Temperature
Figure 20.
Figure 21.
CS & CSG Input Bias Current vs Temperature
HO & LO Delay vs Temperature
Figure 22.
Figure 23.
CS Input Bias Current vs Temperature
HB Input Bias Current vs Temperature
Figure 24.
Figure 25.
10
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
Block Diagram and Typical Application Circuit
VCCX
17
VCCX
C
VCCX
LM5116WG
+
-
4.5V
V
IN
6V-100V
VCC
1
4
2
16
VIN
7. 4 V
REGULATOR
UVLO
R
C
EN
VCC
D1
C
IN
SLEEP
MODE
SHUTDOWN
EN
EN
STANDBY
1.215V
D2
HB 18
R
R
5 mA
UV2
UV1
UVLO
UVLO
LOGIC
C
FT
DIS
C
HB
HICCUP FAULT TIMER
256 CLOCK CYCLES
UVLO
V
IN
DRIVER
HO 19
CLK
Q1
10 mA
S
R
Q
Q
L1
SS
ADAPTIVE
TIMER
7
8
VOUT
3V
1V
SW 20
PWM
C
SS
VCC
DRIVER
1.215V
FB
Q2
C
CURRENT
LIMIT
SNUB
LO 15
C
OUT
R
SNUB
12
CS
TRACK
SAMPLE
and
C
ERROR
AMP
COMP
1.6V
10 x RS V/A
0.5V
A=10
C
HF
R
S
HOLD
R
COMP
13
CSG
COMP
9
+
CLK
DIODE
EMULATION
CONTROL
SW
11
DEMB
SS
VOUT 10
VIN
CLK
C
SYNC
SYNC
RT/SYNC
3
OSCILLATOR
R
FB2
RAMP GENERATOR
= 5mA/V x (VIN - VOUT) + 25 mA
I
R
R
T
IR
R
FB1
RAMP
AGND
PGND
5
6
14
C
RAMP
Figure 26.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
DETAILED OPERATING DESCRIPTION
The LM5116WG high voltage switching regulator features all of the functions necessary to implement an efficient
high voltage buck regulator using a minimum of external components. This easy to use regulator integrates high-
side and low-side MOSFET drivers capable of supplying peak currents of 2 Amps. The regulator control method
is based on current mode control utilizing an emulated current ramp. Emulated peak current mode control
provides inherent line feed-forward, cycle by cycle current limiting and ease of loop compensation. The use of an
emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing
of the very small duty cycles necessary in high input voltage applications. The operating frequency is user
programmable from 50 kHz to 1 MHz. An oscillator/synchronization pin allows the operating frequency to be set
by a single resistor or synchronized to an external clock. Fault protection features include current limiting and
remote shutdown capability. An under-voltage lockout input allows regulator shutdown when the input voltage is
below a user selected threshold, and an enable function will put the regulator into an extremely low current
shutdown via the enable input.
High Voltage Start-Up Regulator
The LM5116WG contains a dual mode internal high voltage startup regulator that provides the VCC bias supply
for the PWM controller and a boot-strap gate drive for the high-side buck MOSFET. The input pin (VIN) can be
connected directly to an input voltage source as high as 100 volts. For input voltages below 10.6V, a low dropout
switch connects VCC directly to VIN. In this supply range, VCC is approximately equal to VIN. For VIN voltages
greater than 10.6V, the low dropout switch is disabled and the VCC regulator is enabled to maintain VCC at
approximately 7.4V. The wide operating range of 6V to 100V is achieved through the use of this dual mode
regulator.
Upon power-up, the regulator sources current into the capacitor connected to the VCC pin. When the voltage at
the VCC pin exceeds 4.5V and the UVLO pin is greater than 1.215V, the output switch is enabled and a soft-start
sequence begins. The output switch remains enabled until VCC falls below 4.5V, EN is pulled low or the UVLO
pin falls below 1.215V.
VCCX
C
VCCX
V
OUT
SW
L
C
OUT
Figure 27. VCCX Bias Supply with Additional Inductor Winding
An output voltage derived bias supply can be applied to the VCCX pin to reduce the IC power dissipation. If the
bias supply voltage is greater than 4.5V, the internal regulator will essentially shut off, reducing the IC power
dissipation. The VCC regulator series pass transistor includes a diode between VCC and VIN that should not be
forward biased in normal operation. For an output voltage between 5V and 15V, VOUT can be connected directly
to VCCX. For VOUT < 5V, a bias winding on the output inductor can be added to VOUT. If the bias winding can
supply VCCX greater than VIN, an external blocking diode is required from the input power supply to the VIN pin
to prevent VCC from discharging into the input supply.
The output of the VCC regulator is current limited to 15 mA minimum. The VCC current is determined by the
MOSFET gate charge, switching frequency and quiescent current (see MOSFETs section in the Application
Information). If VCCX is powered by the output voltage or an inductor winding, the VCC current should be
evaluated during startup to ensure that it is less than the 15 mA minimum current limit specification. IF VCCX is
powered by an external regulator derived from VIN, there is no restriction on the VCC current.
12
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
V
IN
1
6
VIN
0.1 mF
AGND
Figure 28. Input Blocking Diode for VCCX > VIN
In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute
maximum voltage rating of 100V. During line or load transients, voltage ringing on the VIN line that exceeds the
Absolute Maximum Ratings can damage the IC. Both careful PC board layout and the use of quality bypass
capacitors located close to the VIN and GND pins are essential.
Enable
The LM5116WG contains an enable function allowing a very low input current shutdown. If the enable pin is
pulled below 0.5V, the regulator enters shutdown, drawing less than 10 µA from the VIN pin. Raising the EN
input above 3.3V returns the regulator to normal operation. The maximum EN transition time for proper operation
is one switching period. For example, the enable rise time must be less than 4 μs for 250 kHz operation.
A 1 MΩ pull-up resistor to VIN can be used to interface with an open collector control signal. At low input voltage
the pull-up resistor may be reduced to 100 kΩ to speed up the EN transition time. The EN pin can be tied directly
to VIN if this function is not needed. It must not be left floating. If low-power shutdown is not needed, the UVLO
pin should be used as an on/off control.
Internal 5V rail
3 mA
EN
6V
Figure 29. Enable Circuit
Figure 30. EN Bias Current vs Voltage
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
UVLO
An under-voltage lockout pin is provided to disable the regulator without entering shutdown. If the UVLO pin is
pulled below 1.215V, the regulator enters a standby mode of operation with the soft-start capacitor discharged
and outputs disabled, but with the VCC regulator running. If the UVLO input is pulled above 1.215V, the
controller will resume normal operation. A voltage divider from input to ground can be used to set a VIN threshold
to disable the supply in brown-out conditions or for low input faults. The UVLO pin has a 5 µA internal pull up
current that allows this pin to left open if the input under-voltage lockout function is not needed. For applications
which require fast on/off cycling, the UVLO pin with an open collector control signal may be used to ensure
proper start-up sequencing.
The UVLO pin is also used to implement a “hiccup” current limit. If a current limit fault exists for more than 256
consecutive clock cycles, the UVLO pin will be internally pulled down to 200 mV and then released. A capacitor
to ground connected to the UVLO pin will set the timing for hiccup mode current limit. When this feature is used
in conjunction with the voltage divider, a diode across the top resistor may be used to discharge the capacitor in
the event of an input under-voltage condition. There is a 5 µs filter at the input to the fault comparator. At higher
switching frequency (greater than approximately 250 kHz) the hiccup timer may be disabled if the fault capacitor
is not used.
Oscillator and Sync Capability
The LM5116WG oscillator frequency is set by a single external resistor connected between the RT/SYNC pin
and the AGND pin. The resistor should be located very close to the device and connected directly to the pins of
the IC (RT/SYNC and AGND). To set a desired oscillator frequency (fSW), the necessary value for the resistor
can be calculated from the following equation:
T - 450 ns
RT =
284 pF
(1)
Where T = 1 / fSW and RT is in ohms. 450 ns represents the fixed minimum off time.
The LM5116WG oscillator has a maximum programmable frequency that is dependent on the VCC voltage. If
VCC is above 6V, the frequency can be programmed up to 1 MHz. If VCCX is used to bias VCC and VCCX <
6V, the maximum programmable oscillator frequency is 750 kHz.
The RT/SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must
be a higher frequency than the free-running frequency set by the RT resistor. The internal oscillator can be
synchronized to an external clock by AC coupling a positive edge into the RT/SYNC pin. The voltage at the
RT/SYNC pin is nominally 1.215V and must exceed 4V to trip the internal synchronization pulse detection. A 5V
amplitude signal and 100 pF coupling capacitor are recommended. The free-running frequency should be set
nominally 15% below the external clock. Synchronizing above twice the free-running frequency may result in
abnormal behavior of the pulse width modulator.
Error Amplifier and PWM Comparator
The internal high-gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision reference (1.215V). The output of the error amplifier is
connected to the COMP pin allowing the user to provide loop compensation components, generally a type II
network. This network creates a pole at very low frequency, a mid-band zero, and a noise reducing high
frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to
the error amplifier output voltage at the COMP pin.
Ramp Generator
The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the
buck switch current. This switch current corresponds to the positive slope portion of the inductor current. Using
this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides
inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for
PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the
current measurement may introduce significant propagation delays. The filtering, blanking time and propagation
delay limit the minimal achievable pulse width. In applications where the input voltage may be relatively large in
14
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
comparison to the output voltage, controlling small pulse widths and duty cycles is necessary for regulation. The
LM5116WG utilizes a unique ramp generator which does not actually measure the buck switch current but rather
reconstructs the signal. Representing or emulating the inductor current provides a ramp signal to the PWM
comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is
comprised of two elements, a sample-and-hold DC level and an emulated current ramp.
t
ON
(5 mA/V x (VIN-VOUT) + 25 mA) x
C
RAMP
RAMP
Sample and Hold
DC Level
10 x R V/A
S
t
ON
Figure 31. Composition of Current Sense Signal
The sample-and-hold DC level is derived from a measurement of the recirculating current through either the low-
side MOSFET or current sense resistor. The voltage level across the MOSFET or sense resistor is sampled and
held just prior to the onset of the next conduction interval of the buck switch. The current sensing and sample-
and-hold provide the DC level of the reconstructed current signal. The positive slope inductor current ramp is
emulated by an external capacitor connected from the RAMP pin to the AGND and an internal voltage controlled
current source. The ramp current source that emulates the inductor current is a function of the VIN and VOUT
voltages per the following equation:
IR = 5 µA/V x (VIN - VOUT) + 25 µA
(2)
Proper selection of the RAMP capacitor (CRAMP) depends upon the value of the output inductor (L) and the
current sense resistor (RS). For proper current emulation, the DC sample and hold value and the ramp amplitude
must have the same dependence on the load current. That is:
gm x L
, so
RS x A =
CRAMP
gm x L
A x RS
CRAMP
=
(3)
Where gm is the ramp generator transconductance (5 µA/V) and A is the current sense amplifier gain (10 V/V).
The ramp capacitor should be located very close to the device and connected directly to the pins of the IC
(RAMP and AGND).
The difference between the average inductor current and the DC value of the sampled inductor current can
cause instability for certain operating conditions. This instability is known as sub-harmonic oscillation, which
occurs when the inductor ripple current does not return to its initial value by the start of next switching cycle.
Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch
node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this
oscillation. The 25 µA of offset current provided from the emulated current source adds the optimal slope
compensation to the ramp signal for a 5V output. For higher output voltages, additional slope compensation may
be required. In these applications, a resistor is added between RAMP and VCC to increase the ramp slope
compensation.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
SW
LO
CS
R
R
G
G
CSG
DEMB
R
DEMB
Figure 32. RDS(ON) Current Sensing without Diode Emulation
The DC current sample is obtained using the CS and CSG pins connected to either a source sense resistor (RS)
or the RDS(ON) of the low-side MOSFET. For RDS(ON) sensing, RS = RDS(ON) of the low-side MOSFET. In this case
it is sometimes helpful to adjust the current sense amplifier gain (A) to a lower value in order to obtain the
desired current limit. Adding external resistors RG in series with CS and CSG, the current sense amplifier gain A
becomes:
10k
A ,
1k + RG
(4)
Current Limit
The LM5116WG contains a current limit monitoring scheme to protect the circuit from possible over-current
conditions. When set correctly, the emulated current sense signal is proportional to the buck switch current with a
scale factor determined by the current limit sense resistor. The emulated ramp signal is applied to the current
limit comparator. If the emulated ramp signal exceeds 1.6V, the current cycle is terminated (cycle-by-cycle
current limiting). Since the ramp amplitude is proportional to VIN - VOUT, if VOUT is shorted, there is an immediate
reduction in duty cycle. To further protect the external switches during prolonged current limit conditions, an
internal counter counts clock pulses when in current limit. When the counter detects 256 consecutive clock
cycles, the regulator enters a low power dissipation hiccup mode of current limit. The regulator is shut down by
momentarily pulling UVLO low, and the soft-start capacitor discharged. The regulator is restarted with a full soft-
start cycle once UVLO charges back to 1.215V. This process is repeated until the fault is removed. The hiccup
off-time can be controlled by a capacitor to ground on the UVLO pin. In applications with low output inductance
and high input voltage, the switch current may overshoot due to the propagation delay of the current limit
comparator. If an overshoot should occur, the sample-and-hold circuit will detect the excess recirculating current.
If the sample-and-hold DC level exceeds the internal current limit threshold, the buck switch will be disabled and
skip pulses until the current has decayed below the current limit threshold. This approach prevents current
runaway conditions due to propagation delays or inductor saturation since the inductor current is forced to decay
following any current overshoot.
CURRENT SENSE
AMPLIFIER
CURRENT LIMIT
COMPARATOR
1.6V
10k
CS
1k
R
G
LO
-
+
-
R
I
L
S
+
gm x (VIN - VOUT) + 25 mA
1k CSG
R
G
10k
0.5V
10k
1k + R
HO
A =
RAMP
G
C
RAMP
Figure 33. Current Limit and Ramp Circuit
16
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
Using a current sense resistor in the source of the low-side MOSFET provides superior current limit accuracy
compared to RDS(ON) sensing. RDS(ON) sensing is far less accurate due to the large variation of MOSFET RDS(ON)
with temperature and part-to-part variation. The CS and CSG pins should be Kelvin connected to the current
sense resistor or MOSFET drain and source.
The peak current which triggers the current limit comparator is:
x tON
CRAMP
A x RS
25 mA
-
1.1V
1.1V
A x RS
IPEAK
=
,
(5)
Where tON is the on-time of the high-side MOSFET. The 1.1V threshold is the difference between the 1.6V
reference at the current limit comparator and the 0.5V offset at the current sense amplifier. This offset at the
current sense amplifier allows the inductor ripple current to go negative by 0.5V / (A x RS) when running full
synchronous operation.
Current limit hysteresis prevents chatter around the threshold when VCCX is powered from VOUT. When 4.5V <
VCC < 5.8V, the 1.6V reference is increased to 1.72V. The peak current which triggers the current limit
comparator becomes:
x tON
CRAMP
A x RS
25 mA
-
1.22V
1.22V
A x RS
IPEAK
=
,
(6)
This has the effect of a 10% fold-back of the peak current during a short circuit when VCCX is powered from a
5V output.
Soft-Start and Diode Emulation
The soft-start feature allows the regulator to gradually reach the initial steady state operating point, thus reducing
start-up stresses and surges. The LM5116WG will regulate the FB pin to the SS pin voltage or the internal
1.215V reference, whichever is lower. At the beginning of the soft-start sequence when SS = 0V, the internal 10
µA soft-start current source gradually increases the voltage of an external soft-start capacitor (CSS) connected to
the SS pin resulting in a gradual rise of FB and the output voltage.
DIODE EMULATION
COMPARATOR
R
DEMB
S
SW
+
-
R
DEMB
1.215V
5V
40k
SS Latch
+
SS
-
Figure 34. Diode Emulation Control
During this initial charging of CSS to the internal reference voltage, the LM5116WG will force diode emulation.
That is, the low-side MOSFET will turn off for the remainder of a cycle if the sensed inductor current becomes
negative. The inductor current is sensed by monitoring the voltage between SW and DEMB. As the SS capacitor
continues to charge beyond 1.215V to 3V, the DEMB bias current will increase from 0 µA up to 40 µA. With the
use of an external DEMB resistor (RDEMB), the current sense threshold for diode emulation will increase resulting
in the gradual transition to synchronous operation. Forcing diode emulation during soft-start allows the
LM5116WG to start up into a pre-biased output without unnecessarily discharging the output capacitor. Full
synchronous operation is obtained if the DEMB pin is always biased to a higher potential than the SW pin when
LO is high. RDEMB = 10 kΩ will bias the DEMB pin to 0.45V minimum, which is adequate for most applications.
The DEMB bias potential should always be kept below 2V. At very light loads with larger values of output
inductance and MOSFET capacitance, the switch voltage may fall slowly. If the SW voltage does not fall below
the DEMB threshold before the end of the HO fall to LO rise dead-time, switching will default to diode emulation
mode. When RDEMB = 0Ω, the LM5116WG will always run in diode emulation.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
Once SS charges to 3V the SS latch is set, increasing the DEMB bias current to 65 µA. An amplifier is enabled
that regulates SS to 160 mV above the FB voltage. This feature can prevent overshoot of the output voltage in
the event the output voltage momentarily dips out of regulation. When a fault is detected (VCC under-voltage,
UVLO pin < 1.215, or EN = 0V) the soft-start capacitor is discharged. Once the fault condition is no longer
present, a new soft-start sequence begins.
HO Ouput
The LM5116WG contains a high current, high-side driver and associated high voltage level shift. This gate driver
circuit works in conjunction with an external diode and bootstrap capacitor. A 1 µF ceramic capacitor, connected
with short traces between the HB pin and SW pin, is recommended. During the off-time of the high-side
MOSFET, the SW pin voltage is approximately -0.5V and the bootstrap capacitor charges from VCC through the
external bootstrap diode. When operating with a high PWM duty cycle, the buck switch will be forced off each
cycle for 450 ns to ensure that the bootstrap capacitor is recharged.
The LO and HO outputs are controlled with an adaptive deadtime methodology which insures that both outputs
are never enabled at the same time. When the controller commands HO to be enabled, the adaptive block first
disables LO and waits for the LO voltage to drop below approximately 25% of VCC. HO is then enabled after a
small delay. Similarly, when HO turns off, LO waits until the SW voltage has fallen to ½ of VCC. LO is then
enabled after a small delay. In the event that SW does not fall within approximately 150 ns, LO is asserted high.
This methodology insures adequate dead-time for appropriately sized MOSFETs.
In some applications it may be desirable to slow down the high-side MOSFET turn-on time in order to control
switching spikes. This may be accomplished by adding a resistor is series with the HO output to the high-side
gate. Values greater than 10Ω should be avoided so as not to interfere with the adaptive gate drive. Use of an
HB resistor for this function should be carefully evaluated so as not cause potentially harmful negative voltage to
the high-side driver, and is generally limited to 2.2Ω maximum.
Thermal Protection
For high temperature applications in the CPGA-20, the internal thermal shutdown circuitry is disabled.
Application Information
EXTERNAL COMPONENTS
The procedure for calculating the external components is illustrated with the following design example. The Bill of
Materials for this design is listed in Table 1. The circuit shown in Figure 41 is configured for the following
specifications:
•
•
•
•
Output voltage = 5V
Input voltage = 7V to 60V
Maximum load current = 7A
Switching frequency = 250 kHz
Simplified equations are used as a general guideline for the design method. Comprehensive equations are
provided at the end of this section.
TIMING RESISTOR
RT sets the oscillator switching frequency. Generally, higher frequency applications are smaller but have higher
losses. Operation at 250 kHz was selected for this example as a reasonable compromise for both small size and
high efficiency. The value of RT for 250 kHz switching frequency can be calculated as follows:
1
- 450 ns
250 kHz
= 12.5 kW
RT =
284 pF
(7)
The nearest standard value of 12.4 kΩ was chosen for RT.
18
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
OUTPUT INDUCTOR
The inductor value is determined based on the operating frequency, load current, ripple current and the input and
output voltages.
I
I
PP
O
0
1
T =
f
SW
Figure 35. Inductor Current
Knowing the switching frequency (fSW), maximum ripple current (IPP), maximum input voltage (VIN(MAX)) and the
nominal output voltage (VOUT), the inductor value can be calculated:
VOUT
VOUT
VIN(MAX)
1 -
x
L =
IPP x fSW
(8)
The maximum ripple current occurs at the maximum input voltage. Typically, IPP is 20% to 40% of the full load
current. When running diode emulation mode, the maximum ripple current should be less than twice the
minimum load current. For full synchronous operation, higher ripple current is acceptable. Higher ripple current
allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple
current for low output ripple voltage. For this example, 40% ripple current was chosen for a smaller sized
inductor.
5V
5V
1 -
x
= 6.5mH
L =
60V
0.4 x 7A x 250kHz
(9)
The nearest standard value of 6 µH will be used. The inductor must be rated for the peak current to prevent
saturation. During normal operation, the peak current occurs at maximum load current plus maximum ripple.
During overload conditions with properly scaled component values, the peak current is limited to VCS(TH) / RS
(See next section). At the maximum input voltage with a shorted output, the valley current must fall below VCS(TH)
/ RS before the high-side MOSFET is allowed to turn on. The peak current in steady state will increase to VIN(MAX)
x tON(min) / L above this level. The chosen inductor must be evaluated for this condition, especially at elevated
temperature where the saturation current rating may drop significantly.
CURRENT SENSE RESISTOR
The current limit is set by the current sense resistor value (RS).
VCS(TH)
ILIM
=
RS
(10)
For a 5V output, the maximum current sense signal occurs at the minimum input voltage, so RS is calculated
from:
VCS(TH)
RS
Ç
VOUT
VOUT
x 1 +
IO
+
VIN(MIN)
2 x L x fSW
(11)
(12)
For this example VCCX = 0V, so VCS(TH) = 0.11V. The current sense resistor is calculated as:
0.11V
0.011W
Ç
RS Ç
5V
5V
7V
x
1 +
7A +
2 x 6 mH x 250 kHz
The next lowest standard value of 10 mΩ was chosen for RS.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
RAMP CAPACITOR
With the inductor and sense resistor value selected, the value of the ramp capacitor (CRAMP) necessary for the
emulation ramp circuit is:
gm x L
CRAMP
,
A x RS
(13)
Where L is the value of the output inductor in Henrys, gm is the ramp generator transconductance (5 µA/V), and
A is the current sense amplifier gain (10 V/V). For the 5V output design example, the ramp capacitor is
calculated as:
5 mA/V x 6 mH
= 300 pF
CRAMP
=
10V/V x 10 mW
(14)
The next lowest standard value of 270 pF was selected for CRAMP. A COG type capacitor with 5% or better
tolerance is recommended.
OUTPUT CAPACITORS
The output capacitors smooth the inductor ripple current and provide a source of charge for transient loading
conditions. For this design example, five 100 µF ceramic capacitors where selected. Ceramic capacitors provide
very low equivalent series resistance (ESR), but can exhibit a significant reduction in capacitance with DC bias.
From the manufacturer’s data, the ESR at 250 kHz is 2 mΩ / 5 = 0.4 mΩ, with a 36% reduction in capacitance at
5V. This is verified by measuring the output ripple voltage and frequency response of the circuit. The
fundamental component of the output ripple voltage is calculated as:
2
1
ESR2 +
DVOUT = IPP
x
€
With typical values for the 5V design example:
8 x fSW x COUT
(15)
2
1
DVOUT = 3A x 0.4 mW2 +
8 x 250 kHz x 320 mF
DVOUT = 4.8 mV
(16)
INPUT CAPACITORS
The regulator supply voltage has a large source impedance at the switching frequency. Good quality input
capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current
during the on-time. When the buck switch turns on, the current into the switch steps to the valley of the inductor
current waveform, ramps up to the peak value, and then drops to zero at turn-off. The input capacitors should be
selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current
rating is IRMS > IOUT / 2.
Quality ceramic capacitors with a low ESR were selected for the input filter. To allow for capacitor tolerances and
voltage rating, four 2.2 µF, 100V ceramic capacitors were used for the typical application circuit. With ceramic
capacitors, the input ripple voltage will be triangular and peak at 50% duty cycle. Taking into account the
capacitance change with DC bias, the input ripple voltage is approximated as:
IOUT
7A
DVIN
=
=
= 1V
4 x 250 kHz x 7 mF
4 x fSW x CIN
(17)
When the converter is connected to an input power source, a resonant circuit is formed by the line impedance
and the input capacitors. If step input voltage transients are expected near the maximum rating of the
LM5116WG, a careful evaluation of the ringing and possible overshoot at the device VIN pin should be
completed. To minimize overshoot make CIN > 10 x LIN. The characteristic source impedance and resonant
frequency are:
LIN
1
fS
=
ZS
=
2p
CIN
LIN x CIN
(18)
20
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
The converter exhibits a negative input impedance which is lowest at the minimum input voltage:
2
VIN
ZIN = -
POUT
(19)
(20)
The damping factor for the input filter is given by:
ZS
RIN + ESR
ZS
1
2
d =
+
ZIN
where RIN is the input wiring resistance and ESR is the series resistance of the input capacitors. The term ZS/ZIN
will always be negative due to ZIN.
When δ = 1, the input filter is critically damped. This may be difficult to achieve with practical component values.
With δ < 0.2, the input filter will exhibit significant ringing. If δ is zero or negative, there is not enough resistance
in the circuit and the input filter will sustain an oscillation. When operating near the minimum input voltage, an
aluminum electrolytic capacitor across CIN may be needed to damp the input for a typical bench test setup. Any
parallel capacitor should be evaluated for its RMS current rating. The current will split between the ceramic and
aluminum capacitors based on the relative impedance at the switching frequency.
VCC CAPACITOR
The primary purpose of the VCC capacitor (CVCC) is to supply the peak transient currents of the LO driver and
bootstrap diode (D1) as well as provide stability for the VCC regulator. These current peaks can be several
amperes. The recommended value of CVCC should be no smaller than 0.47 µF, and should be a good quality, low
ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused
by trace inductance. A value of 1 µF was selected for this design.
BOOTSTRAP CAPACITOR
The bootstrap capacitor (CHB) between the HB and SW pins supplies the gate current to charge the high-side
MOSFET gate at each cycle’s turn-on as well as supplying the recovery charge for the bootstrap diode (D1).
These current peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1
µF, and should be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially
damaging voltage transients caused by trace inductance. The absolute minimum value for the bootstrap
capacitor is calculated as:
Qg
CHB
í
DVHB
(21)
Where Qg is the high-side MOSFET gate charge and ΔVHB is the tolerable voltage droop on CHB, which is
typically less than 5% of VCC. A value of 1 µF was selected for this design.
SOFT-START CAPACITOR
The capacitor at the SS pin (CSS) determines the soft-start time, which is the time for the reference voltage and
the output voltage to reach the final regulated value. The soft-start time tSS should be substantially longer than
the time required to charge COUT to VOUT at the maximum output current. To meet this requirement:
tSS > VOUT x COUT / (ICURRENT LIMIT − IOUT
)
(22)
The value of CSS for a given time is determined from:
tSS x 10 mA
CSS
=
1.215V
(23)
For this application, a value of 0.01 µF was chosen for a soft-start time of 1.2 ms.
OUTPUT VOLTAGE DIVIDER
RFB1 and RFB2 set the output voltage level, the ratio of these resistors is calculated from:
RFB2
VOUT
- 1
=
RFB1
1.215V
(24)
RFB1 is typically 1.21 kΩ for a divider current of 1 mA. The divider current can be reduced to 100 µA with
RFB1=12.1 kΩ. For the 5V output design example used here, RFB1 = 1.21 kΩ and RFB2 = 3.74 kΩ.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
UVLO DIVIDER
A voltage divider and filter can be connected to the UVLO pin to set a minimum operating voltage VIN(MIN) for the
regulator. If this feature is required, the following procedure can be used to determine appropriate resistor values
for RUV2, RUV1 and CFT.
1. RUV2 must be large enough such that in the event of a current limit, the internal UVLO switch can pull UVLO
< 200mV. This can be guaranteed if:
RUV2 > 500 x VIN(MAX)
where
•
VIN(MAX) is the maximum input voltage and RUV2 is in ohms.
2. With an appropriate value for RUV2, RUV1 can be selected using the following equation:
RUV2
RUV1 = 1.215 x
VIN(MIN) + (5 mA x RUV2) - 1.215
where
•
VIN(MIN) is the desired shutdown voltage.
3. Capacitor CFT provides filtering for the divider and determines the off-time of the “hiccup” duty cycle during
current limit. When CFT is used in conjunction with the voltage divider, a diode across the top resistor should
be used to discharge CFT in the event of an input under-voltage condition.
RUV1 x RUV2
RUV1 + RUV2
1.215 x (RUV1 + RUV2
VIN x RUV1
)
x CFT x ln
tOFF = -
1 -
If under-voltage shutdown is not required, RUV1 and RUV2 can be eliminated and the off-time becomes:
1.215V
tOFF = CFT
x
5 mA
(25)
The voltage at the UVLO pin should never exceed 16V when using an external set-point divider. It may be
necessary to clamp the UVLO pin at high input voltages. For the design example, RUV2 = 102 kΩ and RUV1 = 21
kΩ for a shut-down voltage of 6.6V. If sustained short circuit protection is required, CFT ≥ 1 µF will limit the short
circuit power dissipation. D2 may be installed when using CFT with RUV1 and RUV2
.
MOSFETs
Selection of the power MOSFETs is governed by the same tradeoffs as switching frequency. Breaking down the
losses in the high-side and low-side MOSFETs is one way to determine relative efficiencies between different
devices. When using discrete SO-8 MOSFETs the LM5116WG is most efficient for output currents of 2A to 10A.
Losses in the power MOSFETs can be broken down into conduction loss, gate charging loss, and switching loss.
Conduction, or I2R loss PDC, is approximately:
PDC(HO-MOSFET) = D x (IO2 x RDS(ON) x 1.3)
PDC(LO-MOSFET) = (1 - D) x (IO2 x RDS(ON) x 1.3)
(26)
(27)
Where D is the duty cycle. The factor 1.3 accounts for the increase in MOSFET on-resistance due to heating.
Alternatively, the factor of 1.3 can be ignored and the on-resistance of the MOSFET can be estimated using the
RDS(ON) vs Temperature curves in the MOSFET datasheet. Gate charging loss, PGC, results from the current
driving the gate capacitance of the power MOSFETs and is approximated as:
PGC = n x VCC x Qg x fSW
(28)
Qg refer to the total gate charge of an individual MOSFET, and ‘n’ is the number of MOSFETs. If different types
of MOSFETs are used, the ‘n’ term can be ignored and their gate charges summed to form a cumulative Qg.
Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the
LM5116WG and not in the MOSFET itself. Further loss in the LM5116WG is incurred as the gate driving current
is supplied by the internal linear regulator. The gate drive current supplied by the VCC regulator is calculated as:
IGC = (Qgh + Qgl) x fSW
(29)
Where Qgh + Qgl represent the gate charge of the HO and LO MOSFETs at VGS = VCC. To ensure start-up, IGC
should be less than the VCC current limit rating of 15 mA minimum when powered by the internal 7.4V regulator.
Failure to observe this rating may result in excessive MOSFET heating and potential damage. The IGC run
current may exceed 15 mA when VCC is powered by VCCX.
22
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
Switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition
period both current and voltage are present in the channel of the MOSFET. The switching loss can be
approximated as:
PSW = 0.5 x VIN x IO x (tR + tF) x fSW
(30)
Where tR and tF are the rise and fall times of the MOSFET. Switching loss is calculated for the high-side
MOSFET only. Switching loss in the low-side MOSFET is negligible because the body diode of the low-side
MOSFET turns on before the MOSFET itself, minimizing the voltage from drain to source before turn-on. For this
example, the maximum drain-to-source voltage applied to either MOSFET is 60V. VCC provides the drive
voltage at the gate of the MOSFETs. The selected MOSFETs must be able to withstand 60V plus any ringing
from drain to source, and be able to handle at least VCC plus ringing from gate to source. A good choice of
MOSFET for the 60V input design example is the Si7850DP. It has an RDS(ON) of 20 mΩ, total gate charge of 14
nC, and rise and fall times of 10 ns and 12 ns respectively. In applications where a high step-down ratio is
maintained for normal operation, efficiency may be optimized by choosing a high-side MOSFET with lower Qg,
and low-side MOSFET with lower RDS(ON)
.
For higher voltage MOSFETs which are not true logic level, it is important to use the UVLO feature. Choose a
minimum operating voltage which is high enough for VCC and the bootstrap (HB) supply to fully enhance the
MOSFET gates. This will prevent operation in the linear region during power-on or power-off which can result in
MOSFET failure. Similar consideration must be made when powering VCCX from the output voltage. For the
high-side MOSFET, the gate threshold should be considered and careful evaluation made if the gate threshold
voltage exceeds the HO driver UVLO.
MOSFET SNUBBER
A resistor-capacitor snubber network across the low-side MOSFET reduces ringing and spikes at the switching
node. Excessive ringing and spikes can cause erratic operation and couple spikes and noise to the output.
Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead
lengths for the snubber connections are very short. Start with a resistor value between 5Ω and 50Ω. Increasing
the value of the snubber capacitor results in more damping, but higher snubber losses. Select a minimum value
for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at high load.
ERROR AMPLIFIER COMPENSATION
RCOMP, CCOMP and CHF configure the error amplifier gain characteristics to accomplish a stable voltage loop gain.
One advantage of current mode control is the ability to close the loop with only two feedback components, RCOMP
and CCOMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For the 5V
output design example, the modulator is treated as an ideal voltage-to-current converter. The DC modulator gain
of the LM5116WG can be modeled as:
DC Gain(MOD) = RLOAD / (A x RS)
(31)
The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD) and output
capacitance (COUT). The corner frequency of this pole is:
fP(MOD) = 1 / (2π x RLOAD x COUT
)
(32)
For RLOAD = 5V / 7A = 0.714Ω and COUT = 320 µF (effective) then fP(MOD) = 700 Hz
DC Gain(MOD) = 0.714Ω / (10 x 10 mΩ) = 7.14 = 17 dB
For the 5V design example the modulator gain vs. frequency characteristic was measured as shown in Figure 36.
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
Figure 36. Modulator Gain and Phase
Components RCOMP and CCOMP configure the error amplifier as a type II configuration. The DC gain of the
amplifier is 80 dB which has a pole at low frequency and a zero at fZEA = 1 / (2π x RCOMP x CCOMP). The error
amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the
voltage loop. A single pole response at the crossover frequency yields a very stable loop with 90° of phase
margin. For the design example, a target loop bandwidth (crossover frequency) of one-tenth the switching
frequency or 25 kHz was selected. The compensation network zero (fZEA) should be selected at least an order of
magnitude less than the target crossover frequency. This constrains the product of RCOMP and CCOMP for a
desired compensation network zero 1 / (2π x RCOMP x CCOMP) to be 2.5 kHz. Increasing RCOMP, while
proportionally decreasing CCOMP, increases the error amp gain. Conversely, decreasing RCOMP while
proportionally increasing CCOMP, decreases the error amp gain. For the design example CCOMP was selected as
3300 pF and RCOMP was selected as 18 kΩ. These values configure the compensation network zero at 2.7 kHz.
The error amp gain at frequencies greater than fZEA is: RCOMP / RFB2, which is approximately 4.8 (13.6 dB).
Figure 37. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.
24
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
Figure 38. Overall Voltage Loop Gain and Phase
If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be
configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier
compensation components can be designed with the guidelines given. Step load transient tests can be
performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response.
CHF can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value
of CHF must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer
function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of
the pole added by CHF is: fP2 = fZEA x CCOMP / CHF. The value of CHF was selected as 100 pF for the design
example.
PCB BOARD LAYOUT and THERMAL CONSIDERATIONS
In a buck regulator the primary switching loop consists of the input capacitor, MOSFETs and current sense
resistor. Minimizing the area of this loop reduces the stray inductance and minimizes noise and possible erratic
operation. The input capacitor should be placed as close as possible to the MOSFETs, with the VIN side of the
capacitor connected directly to the high-side MOSFET drain, and the GND side of the capacitor connected as
close as possible to the low-side source or current sense resistor ground connection. A ground plane in the PC
board is recommended as a means to connect the quiet end (input voltage ground side) of the input filter
capacitors to the output filter capacitors and the PGND pin of the regulator. Connect all of the low power ground
connections (CSS, RT, CRAMP) directly to the regulator AGND pin. Connect the AGND and PGND pins together
through to a topside copper area covering the entire underside of the device. Place several vias in this underside
copper area to the ground plane.
The highest power dissipating components are the two power MOSFETs. The easiest way to determine the
power dissipated in the MOSFETs is to measure the total conversion losses (PIN - POUT), then subtract the power
losses in the output inductor and any snubber resistors. The resulting power losses are primarily in the switching
MOSFETs.
If a snubber is used, the power loss can be estimated with an oscilloscope by observation of the resistor voltage
drop at both turn-on and turn-off transitions. Assuming that the RC time constant is << 1 / fSW
.
P = C x V2 x fSW
(33)
Selecting MOSFETs with exposed pads will aid the power dissipation of these devices. Careful attention to
RDS(ON) at high temperature should be observed. Also, at 250 kHz, a MOSFET with low gate capacitance will
result in lower switching losses.
Comprehensive Equations
CURRENT SENSE RESISTOR AND RAMP CAPACITOR
T = 1 / fSW, gm = 5 µA/V, A = 10 V/V. IOUT is the maximum output current at current limit.
General Method for VOUT < 5V:
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
VCS(TH)
RS
=
5 - VOUT
VIN(MIN)
1 +
1 +
VOUT x T
2 x L
VOUT
VOUT x T
L
IOUT
-
x 1 -
x
+
VIN(MIN)
5 - VOUT
VIN(MAX)
(34)
(35)
5 - VOUT
VIN(MAX)
gm x L
A x RS
x
1 +
CRAMP
=
General Method for 5V < VOUT < 7.5V:
VCS(TH)
RS
=
VOUT x T
2 x L
VOUT
VOUT x T
L
IOUT
-
1 -
x
+
VIN(MIN)
(36)
(37)
gm x L
A x RS
5 - VOUT
VIN(MIN)
x
1 +
CRAMP
=
Best Performance Method:
This minimizes the current limit deviation due to changes in line voltage, while maintaining near optimal slope
compensation.
Calculate optimal slope current, IOS = (VOUT / 3) x 10 µA/V. For example, at VOUT = 7.5V, IOS = 25 µA.
VCS(TH)
IOS x L
RS
=
CRAMP =
VOUT x A x RS
VOUT x T
IOUT
+
L
(38)
(39)
(40)
Calculate VRAMP at the nominal input voltage.
VOUT ((VIN œ VOUT) x gm + IOS) x T
x
VRAMP
=
VIN
CRAMP
For VOUT > 7.5V, install a resistor from the RAMP pin to VCC.
VCC - VRAMP
RRAMP
=
IOS - 25 mA
VCC
R
RAMP
RAMP
C
RAMP
Figure 39. RRAMP to VCC for VOUT > 7.5V
For VOUT < 7.5V, a negative VCC is required. This can be made with a simple charge pump from the LO gate
output. Install a resistor from the RAMP pin to the negative VCC.
VCC œ 0.5V + VRAMP
RRAMP
=
25 mA - IOS
(41)
26
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
LO
10 nF
1N914
10 nF
R
RAMP
RAMP
-VCC
RAMP
C
Figure 40. RRAMP to -VCC for VOUT < 7.5V
If a large variation is expected in VCC, say for VIN < 11V, a Zener regulator may be added to supply a constant
voltage for RRAMP
.
MODULATOR TRANSFER FUNCTION
The following equations can be used to calculate the control-to-output transfer function:
s
wZ
1 +
RLOAD
1
VOUT
x
x
=
s
wP
s
s2
A x RS
VCOMP
RLOAD
x
1 +
1 +
+
1 +
2
wn x Q
wn
Km x A x RS
(42)
1
Km
=
(D œ 0.5) x A x RS x T
VSL
+ (1 - 2 x D) x KSL
+
L
VIN
(43)
(44)
gm x T
IOS x T
CRAMP
VSL
=
KSL
=
CRAMP
p
T
1
1
1
1
x
+
wn =
wP =
wZ =
Km x A x RS
COUT x ESR
COUT
RLOAD
(45)
(VIN œ VOUT) x KSL + VSL
VIN x A x RS
L
Se =
Sn =
T
1
Se
mC =
Sn
Q =
p x (mC œ 0.5)
(46)
Km is the effective DC gain of the modulating comparator. The duty cycle D = VOUT / VIN. KSL is the proportional
slope compensation term. VSL is the fixed slope compensation term. Slope compensation is set by mc, which is
the ratio of the external ramp to the natural ramp. The switching frequency sampling gain is characterized by ωn
and Q, which accounts for the high frequency inductor pole.
For VSL without RRAMP, use IOS = 25 µA
For VSL with RRAMP to VCC, use IOS = 25 µA + VCC/RRAMP
For VSL with RRAMP to -VCC, use IOS = 25 µA - VCC/RRAMP
ERROR AMPLIFIER TRANSFER FUNCTION
The following equations are used to calculate the error amplifier transfer function:
1
VCOMP
-GEA(S) x
=
GEA(S)
KFB
VOUT(FB)
1
s
1 +
1 +
+
x
AOL
wBW
(47)
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
s
wZEA
1 +
RFB1
KFB
=
GEA(S)
=
RFB1 + RFB2
s
wHF
s
wO
1 +
x
(48)
1
1
wO
=
wZEA
=
CCOMP x RCOMP
(CHF + CCOMP) x RFB2
(CHF + CCOMP
)
wHF
=
CHF x CCOMP x RCOMP
(49)
Where AOL = 10,000 (80 dB) and ωBW = 2π x fBW. GEA(S) is the ideal error amplifier gain, which is modified at DC
and high frequency by the open loop gain of the amplifier and the feedback divider ratio.
28
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
www.ti.com
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
Figure 41. 5V 7A Typical Application Schematic
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
www.ti.com
Table 1. Bill of Materials for 7V-60V Input, 5V 7A Output, 250kHz
ID
C1, C2, C14
C3
Part Number
Type
Size
0805
0603
0603
0603
Parameters
1µF, 25V, X7R
Qty
3
Vendor
TDK
C2012X7R1E105K
VJ0603Y103KXAAT
VJ0603A271JXAAT
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
0.01µF, 50V, X7R
270pF, 50V, COG, 5%
100pF, 50V, X7R
1
Vishay
Vishay
Vishay
C4
1
C5, C15
VJ0603Y101KXAT
W1BC
2
C6
C7
VJ0603Y332KXXAT
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
0603
0603
1812
3300pF, 25V, X7R
Not Used
1
0
4
Vishay
TDK
C8, C9, C10,
C11
C4532X7R2A225M
2.2µF, 100V X7R
C12
C13
C3225X7R2A105M
C2012X7R2A104M
C4532X6S0J107M
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
1210
0805
1812
1µF, 100V X7R
0.1µF, 100V X7R
1
1
5
TDK
TDK
TDK
C16, C17, C18,
C19, C20
100µF, 6.3V, X6S, 105°C
C21, C22
C23
Capacitor, Tantalum
Capacitor, Ceramic
Diode, Switching
D Case
0805
Not Used
Not Used
0
0
1
D1
CMPD2003
CMPD2003
SOT-23
200mA, 200V
Central
Semi
D2
Diode, Switching
SOT-23
Not Used
0
Central
Semi
JMP1
L1
Connector, Jumper
Inductor
2 pin sq. post
6µH, 16.5A
1
1
4
5
2
HC2LP-6R0
1514-2
Cooper
Keystone
Keystone
P1-P4
TP1-TP5
Q1, Q2
Turret Terminal
Test Point
.090” dia.
.040” dia.
5012
Si7850DP
N-CH MOSFET
SO-8 Power PAK
10.3A, 60V
Vishay
Siliconix
R1
R2
CRCW06031023F
CRCW06032102F
CRCW06033741F
CRCW06031211F
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
0603
0603
0603
0603
0603
0603
0603
0603
0603
2010
102kΩ, 1%
21.0kΩ, 1%
3.74kΩ, 1%
1.21kΩ, 1%
Not Used
0Ω
1
1
1
1
0
2
1
1
1
1
Vishay
Vishay
Vishay
Vishay
R3
R4
R5
R6, R7
R8
CRCW06030R0J
CRCW0603103J
CRCW06031242F
CRCW0603183J
Vishay
Vishay
Vishay
Vishay
IRC
10kΩ, 5%
12.4kΩ, 1%
18kΩ, 5%
0.010Ω, 1%
R9
R10
R11
LRC-LRF2010-01-
R010-F
R12
R13
R14
U1
Resistor
Resistor
Resistor
0603
0603
Not Used
1MΩ, 5%
Not Used
0
1
0
1
CRCW0603105J
LM5116WG
Vishay
TI
1206
Synchronous Buck
Controller
CPGA-20
30
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5116WG
LM5116WG
SNVS599D –OCTOBER 2008–REVISED FEBRUARY 2013
Page
www.ti.com
Changes from Revision B (February 2013) to Revision C
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 30
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: LM5116WG
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5116WG/NOPB
ACTIVE
CFP
NAR
20
30
RoHS-Exempt
& Green
Call TI
Level-1-NA-UNLIM
-40 to 125
LM5116WG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
NAR0020A
WG20A (Rev D)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明