LM5119PSQ/NOPB [TI]

5.5V 至 65V 宽输入电压、电流模式双路同步降压控制器 | RTV | 32 | -40 to 125;


型号：	LM5119PSQ/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	5.5V 至 65V 宽输入电压、电流模式双路同步降压控制器 \| RTV \| 32 \| -40 to 125 控制器开关电视
文件：	总44页 (文件大小：1821K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LM5119

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

LM5119 宽输入范围双路同步降压控制器

1 特性

3 说明

•

仿真峰值电流模式控制

LM5119 器件是一款双路同步降压控制器，适用于高

压电源或变化范围较大的输入电源的降压稳压器应

用。此控制方法基于采用仿真电流斜坡的电流模式控

制。电流模式控制可提供内部线路前馈、逐周期电流限

制和简化的环路补偿。通过使用仿真电流斜坡可降低脉

宽调制电路的噪声灵敏度，从而对高输入电压应用中所

需的极小占空比进行可靠控制。开关频率可设定在

50kHz 至 750kHz 范围内。LM5119 器件可驱动支持

自适应死区时间控制的外部高侧和低侧 NMOS 功率开

关。用户可选二极管仿真模式可实现断续模式运行，从

而提高轻负载条件下的效率。凭借高压偏置稳压器以及

自动切换至外部偏置的功能，可以进一步提高效率。其

他功能包括：热关断、频率同步、逐周期和断续模式

电流限制以及可调节线路欠压锁定。该器件采用功耗增

强型 32 引脚无引线 WQFN 封装，并且配有利于散热

的外露芯片连接焊盘。

宽工作电压范围（5.5V 至 65V）

可轻松配置为双路输出或交错单路输出

稳健耐用的 3.3A 峰值栅极驱动

开关频率最高可通过编程设定为 750kHz

可选二极管仿真模式

可编程输出（基准电压为 0.8V）

精度为 1.5% 的基准电压

可编程电流限制

断续模式过载保护

可编程软启动

可编程线路欠压锁定

自动切换至外部偏置电源

通道 2 使能逻辑输入

热关断

32 引脚超薄型四方扁平无引线 (WQFN) 封装

器件信息⁽¹⁾

2 应用

器件型号

LM5119

封装

封装尺寸（标称值）

•

工业 DC-DC 电机驱动器

WQFN (32)

5.00mm × 5.00mm

电信：服务器和路由器

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

简化应用电路

V_IN

VIN

VCC1

VCC2

HB1

HO1

HB2

HO2

V_OUT1

V_OUT2

SW1

SW2

LO1

CS1

LO2

CS2

LM5119

CSG1

CSG2

PGND1

RAMP1

FB1

PGND2

RAMP2

FB2

V_IN

COMP1

COMP2

SS2 RES

UVLO AGND SS1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVS676

LM5119

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

www.ti.com.cn

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 18

Application and Implementation ........................ 19

8.1 Application Information............................................ 19

8.2 Typical Applications ................................................ 21

Power Supply Recommendations...................... 34

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics.......................................... 8

6.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 12

10 Layout................................................................... 34

10.1 Layout Guidelines ................................................. 34

10.2 Layout Example .................................................... 35

11 器件和文档支持 ..................................................... 36

11.1 接收文档更新通知 ................................................. 36

11.2 社区资源................................................................ 36

11.3 商标....................................................................... 36

11.4 静电放电警告......................................................... 36

11.5 术语表 ................................................................... 36

12 机械、封装和可订购信息....................................... 36

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision H (May 2016) to Revision I

Page

•

将汽车级器件 LM5119Q 参考移到了产品说明书 SLUSD96 中。........................................................................................... 1

Changed Two-Phase to Interleaved Two-Phase Operation section header ........................................................................ 19

Added Interleaved 4-Phase Operation section..................................................................................................................... 20

Added Two-Phase Design Example .................................................................................................................................... 32

Changes from Revision G (January 2014) to Revision H

Page

•

添加了 ESD 额定值表、特性说明部分、器件功能模式、应用和实施部分、电源建议部分、布局部分、器件和文档

支持部分以及机械、封装和可订购信息部分 ......................................................................................................................... 1

Changes from Revision F (February 2013) to Revision G

Page

•

Changed LLP-32 to WQFN-32 ............................................................................................................................................. 11

LM5119

www.ti.com.cn

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

5 Pin Configuration and Functions

RTV Package

32-Pin WQFN

Top View

32 31 30 29 28 27 26 25

VCC1

VCC2

LO2

LO1

PGND1

PGND2

CSG1

CSG2

CS2

CS1

RAMP1

SS1

RAMP2

SS2

VCCDIS

DEMB

10 11 12 13 14 15 16

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

AGND

Analog ground. Return for the internal 0.8-V voltage reference and analog circuits.

Output of the channel1 internal error amplifier. The loop compensation network must be connected

between this pin and the FB1 pin.

COMP1

COMP2

Output of the channel2 internal error amplifier. The loop compensation network must be connected

between this pin and the FB2 pin.

CS1

CS2

Current sense amplifier input. Connect to the high side of the channel1 current sense resistor.

Current sense amplifier input. Connect to the high side of the channel2 current sense resistor.

Kelvin ground connection to the external current sense resistor. Connect directly to the low side of the

channel1 current sense resistor.

CSG1

CSG2

Kelvin ground connection to the external current sense resistor. Connect directly to the low side of the

channel2 current sense resistor.

Logic input that enables diode emulation when in the low state. In diode emulation mode, the low-side

MOSFET is latched off for the remainder of the PWM cycle when the buck inductor current reverses

direction (current flow from output to ground). When DEMB is high, diode emulation is disabled allowing

current to flow in either direction through the low-side MOSFET. A 50-kΩ pulldown resistor internal to the

LM5119 holds DEMB pin low and enables diode emulation if the pin is left floating.

DEMB

If the EN2 pin is low, channel2 is disabled. Channel1 and all other functions remain active. The EN2 has

a 50-kΩ pullup resistor to enable channel2 when the pin is left floating.

EN2

FB1

FB2

Feedback input and inverting input of the channel1 internal error amplifier. A resistor divider from the

channel1 output to this pin sets the output voltage level. The regulation threshold at the FB1 pin is 0.8 V.

Feedback input and inverting input of the channel2 internal error amplifier. A resistor divider from the

channel2 output to this pin sets the output voltage level. The regulation threshold at the FB2 pin is 0.8 V.

High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel1 external

bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the

high-side MOSFET gate and must be placed as close to controller as possible.

HB1

(1) G = Ground, I = Input, O = Output, P = Power

LM5119

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

www.ti.com.cn

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

HB2

NO.

High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel2 external

bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the

high-side MOSFET gate and must be placed as close to the controller as possible.

High-side MOSFET gate drive output. Connect to the gate of the channel1 high-side MOSFET through a

short, low inductance path.

HO1

High-side MOSFET gate drive output. Connect to the gate of the channel2 high-side MOSFET through a

short, low inductance path.

HO2

Low-side MOSFET gate drive output. Connect to the gate of the channel1 low-side synchronous

MOSFET through a short, low inductance path.

LO1

Low-side MOSFET gate drive output. Connect to the gate of the channel2 low-side synchronous

MOSFET through a short, low inductance path.

LO2

Power ground return pin for low-side MOSFET gate driver. Connect directly to the low side of the

channel1 current sense resistor.

PGND1

PGND2

Power ground return pin for low-side MOSFET gate driver. Connect directly to the low side of the

channel2 current sense resistor.

PWM ramp signal. An external resistor and capacitor connected between the SW1 pin, the RAMP1 pin

and the AGND pin sets the channel1 PWM ramp slope. Proper selection of component values produces

a RAMP1 signal that emulates the current in the buck inductor.

RAMP1

RAMP2

PWM ramp signal. An external resistor and capacitor connected between the SW2 pin, the RAMP2 pin

and the AGND pin sets the channel2 PWM ramp slope. Proper selection of component values produces

a RAMP2 signal that emulates the current in the buck inductor.

The restart timer pin for an external capacitor that configures the hiccup mode current limiting. A

capacitor on the RES pin determines the time the controller remains off before automatically restarting in

hiccup mode. The two regulator channels operate independently. One channel may operate in normal

mode while the other is in hiccup mode overload protection. The hiccup mode commences when either

channel experiences 256 consecutive PWM cycles with cycle-by-cycle current limiting. After this occurs, a

10-µA current source charges the RES pin capacitor to the 1.25-V threshold which restarts the

overloaded channel.

RES

The internal oscillator is set with a single resistor between RT and AGND. The recommended maximum

oscillator frequency is 1.5 MHz which corresponds to a maximum switching frequency of 750 kHz for

either channel. The internal oscillator can be synchronized to an external clock by coupling a positive

pulse into RT through a small coupling capacitor.

An external capacitor and an internal 10-µA current source set the ramp rate of the channel1 error amp

reference. The SS1 pin is held low when VCC1 or VCC2 < 4.9 V, UVLO < 1.25 V or during thermal

shutdown.

SS1

SS2

An external capacitor and an internal 10-µA current source set the ramp rate of the channel2 error amp

reference. The SS2 pin is held low when VCC1 or VCC2 < 4.9 V, UVLO < 1.25 V or during thermal

shutdown.

Switching node of the buck regulator. Connect to channel1 bootstrap capacitor, the source terminal of the

high-side MOSFET and the drain terminal of the low-side MOSFET.

SW1

SW2

I/O

Switching node of the buck regulator. Connect to channel2 bootstrap capacitor, the source terminal of the

high-side MOSFET and the drain terminal of the low-side MOSFET.

Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the shutdown

mode with all function disabled. If the UVLO pin is greater than 0.4 V and below 1.25 V, the regulator is

in standby mode with the VCC regulators operational, the SS pins grounded and no switching at the HO

and LO outputs. If the UVLO pin voltage is above 1.25 V, the SS pins are allowed to ramp and pulse

width modulated gate drive signals are delivered at the LO and HO pins. A 20-µA current source is

enabled when UVLO exceeds 1.25 V and flows through the external UVLO resistors to provide

hysteresis.

UVLO

Optional input that disables the internal VCC regulators when external biasing is supplied. If VCCDIS >

1.25 V, the internal VCC regulators are disabled. The externally supplied bias must be coupled to the

VCC pins through a diode. VCCDIS has a 500-kΩ pulldown resistor to ground to enable the VCC

regulators when the pin is left floating. The pulldown resistor can be overridden by pulling VCCDIS above

1.25 V with a resistor divider connected to the external bias supply.

VCCDIS

VIN

Supply voltage input source for the VCC regulators.

Thermal pad of WQFN package. No internal electrical connections. Solder to the ground plane to reduce

thermal resistance.

Thermal Pad

—

LM5119

www.ti.com.cn

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–3

MAX

UNIT

VIN to AGND

SW1, SW2 to AGND

HB1 to SW1, HB2 to SW2

–0.3

(2)

VCC1, VCC2 to AGND

FB1, FB2, DEMB, RES, VCCDIS, UVLO to AGND

HO1 to SW1, HO2 to SW2

LO1, LO2 to AGND

HB + 0.3

VCC + 0.3

SS1, SS2 to AGND

EN2, RT to AGND

CS1, CS2, CSG1, CSG2 to AGND

PGND to AGND

0.3

150

Junction temperature, T_J

Storage temperature, T_stg

°C

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These pins must not exceed VIN.

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VIN

5.5

–40

VCC

HB to SW

T_J

Junction temperature

125

°C

LM5119

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

www.ti.com.cn

6.4 Thermal Information

LM5119

THERMAL METRIC⁽¹⁾

RTV (WQFN)

UNIT

32 PINS

36.7

20.9

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

8.9

R_θJC(bot)

2.2

(1) For more information regarding traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature

range. V_IN= 36 V, V_CC= 8 V, V_VCCDIS = 0 V, V_EN2= 5 V, R_T= 25 kΩ, and no load on LO or HO (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾MAX⁽¹⁾

UNIT

VIN SUPPLY

SS1 = SS2 = 0 V

400

3.9

1.4

7.3

550

4.5

µA

I_BIAS

VIN operating current

VCCDIS = 2V, SS1 = SS2 = 0 V

VCCDIS = 2 V, SS1 = SS2 = 0 V

UVLO = 0 V, SS1 = SS2 = 0 V

VCC1 operating current

VCC2 operating current

VIN shutdown current

µA

I_VCC

I_SHUTDOWN

VCC REGULATOR⁽³⁾

6.77

5.9

7.6

5.95

8.34

1.29

5.2

V_CC(REG)

VCC regulation

VIN = 6 V, no external load

VCC = 0 V

Sourcing current limit

VCCDIS switch threshold

VCCDIS switch hysteresis

VCCDIS input current

Undervoltage threshold

Undervoltage hysteresis

VCCDIS rising

1.19

1.25

0.07

–20

4.9

VCCDIS = 0 V

Positive going VCC

4.7

2.9

0.2

EN2 INPUT

V_IL

V_IH

EN2 input low threshold

EN2 input high threshold

EN2 input pullup resistor

2.5

1.5

kΩ

UVLO

Threshold

UVLO rising

1.2

1.25

1.29

µA

Hysterisis current

Shutdown threshold

Shutdown hysteresis voltage

UVLO = 1.4 V

0.4

0.1

SOFT START

Current source

Pulldown R_DSON

SS = 0 V

µA

Ω

(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instrument's Average Outgoing Quality Level

(AOQL).

(2) Typical specifications represent the most likely parametric normal at 25°C operation.

(3) Per VCC Regulator.

LM5119

www.ti.com.cn

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

Electrical Characteristics (continued)

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature

range. V_IN= 36 V, V_CC= 8 V, V_VCCDIS = 0 V, V_EN2= 5 V, R_T= 25 kΩ, and no load on LO or HO (unless otherwise noted).

PARAMETER

ERROR AMPLIFIER

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾MAX⁽¹⁾

UNIT

V_REF

FB reference voltage

FB input bias current

FB disable threshold

COMP VOH

Measured at FB pin, FB = COMP

FB = 0.8 V

0.788

0.8

0.812

0.31

430

Interleaved threshold

Isource = 3 mA

2.5

2.8

COMP VOL

Isink = 3 mA

A_OL

f_BW

DC gain

MHz

Unity gain bandwidth

PWM COMPARATORS

t_HO(OFF)

t_ON(min)

OSCILLATOR

f_SW1

Forced HO OFF-time

220

320

100

Minimum HO ON-time

C_RAMP= 50 pF

Frequency 1

R_T= 25 kΩ

R_T= 10 kΩ

180

430

200

480

1.25

3.2

220

530

kHz

f_SW2

Frequency 2

RT output voltage

RT sync positive threshold

Sync pulse minimum width

2.5

100

CURRENT LIMIT

Cycle-by-cycle sense voltage

threshold (CS – CSG)

V_CS(TH)

RAMP = 0

CS = 0 V

106

120

134

–95

CS bias current

–70

256

µA

Hiccup mode fault timer

Cycles

RES

I_RES

Current source

Threshold

9.7

µA

V_RES

C_REScharging

1.2

2.9

1.25

1.3

DIODE EMULATION

V_IL

V_IH

DEMB input low threshold

2.6

1.65

DEMB input high threshold

DEMB input pulldown resistance

SW zero cross threshold

kΩ

–5

LO GATE DRIVER

V_OLL

V_OHL

LO low-state output voltage

I_LO= 100 mA

0.1

0.17

0.18

0.26

LO high-state output voltage

LO rise time

I_LO= –100 mA, V_OHL= VCC – V_LO

C-load = 1000 pF

V_LO= 0 V

LO fall time

I_OHL

I_OLL

Peak LO source current

Peak LO sink current

2.5

3.3

V_LO= VCC

HO GATE DRIVER

V_OLH

V_OHH

HO low-state output voltage

I_HO= 100 mA

0.11

0.18

0.19

0.27

HO high-state output voltage

HO rise time

I_HO= –100 mA, V_OHH= V_HB– V_HO

C-load = 1000 pF

HO fall time

C-load = 1000 pF

I_OHH

I_OLH

Peak HO Source current

Peak HO sink current

HB to SW undervoltage

V_HO= 0 V, SW = 0, HB = 8 V

V_HO= V_HB= 8 V

2.2

3.3

LM5119

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

www.ti.com.cn

Electrical Characteristics (continued)

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature

range. V_IN= 36 V, V_CC= 8 V, V_VCCDIS = 0 V, V_EN2= 5 V, R_T= 25 kΩ, and no load on LO or HO (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾MAX⁽¹⁾

UNIT

HB DC bias current

HB – SW = 8 V

Rising

100

µA

THERMAL

T_SD

Thermal shutdown

165

°C

Thermal shutdown hysteresis

6.6 Switching Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature

range. VIN = 36 V, VCC = 8 V, VCCDIS = 0 V, EN2 = 5 V, R_T= 25 kΩ, and no load on LO or HO (unless otherwise noted).

PARAMETER

LO fall to HO rise delay

HO fall to LO rise delay

TEST CONDITIONS

MIN

TYP

MAX

UNIT

No load

LM5119

www.ti.com.cn

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

6.7 Typical Characteristics

Figure 1. HO Peak Driver Current vs Output Voltage

Figure 2. LO Peak Driver Current vs Output Voltage

Figure 3. Driver Dead Time vs VCC

Figure 4. Driver Dead Time vs Temperature

Figure 5. VCC vs I_VCC

Figure 6. Switching Frequency vs R_T

LM5119

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

www.ti.com.cn

Typical Characteristics (continued)

Figure 7. Error Amp Gain and Phase vs Frequency

LM5119

www.ti.com.cn

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

7 Detailed Description

7.1 Overview

The LM5119 high voltage switching regulator features all of the functions necessary to implement an efficient

dual channel buck regulator that operates over a very wide input voltage range. The LM5119 may be configured

as two independent regulators or as a single high current regulator with two interleaved channels. This easy-to-

use regulator integrates high-side and low-side MOSFET drivers capable of supplying peak currents of 2.5 A

(VCC = 8 V). The regulator control method is based on current mode control using an emulated current ramp.

Emulated peak current mode control provides inherent line feedforward, cycle-by-cycle current limiting and ease-

of-loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width

modulation circuit, allowing reliable processing of the very small duty cycles necessary in high input voltage

applications. The switching frequency is user programmable from 50 kHz to 750 kHz. An oscillator or

synchronization pin allows the operating frequency to be set by a single resistor or synchronized to an external

clock. An undervoltage lockout and channel2 enable pin allows either both regulators to be disabled or channel2

to be disabled with full operation of channel1. Fault protection features include current limiting, thermal shutdown,

and remote shutdown capability. The undervoltage lockout input enables both channels when the input voltage

reaches a user selected threshold and provides a very low quiescent shutdown current when pulled low. The 32-

pin WQFN package features an exposed pad to aid in thermal dissipation.

LM5119

ZHCS571I –AUGUST 2010–REVISED APRIL 2018

www.ti.com.cn

7.2 Functional Block Diagram

COMMON

CLK 1

CLK 2

OSCILLATOR /

SYNC DETECTOR

BIAS

0.8V

VIN

COMMON BIAS

GENERATOR

AGND

UVLO

LOGIC

CHANNEL 1

CHANNEL 2

SHUTDOWN

STANDBY

CONTROL

THERMAL

SHUTDOWN

VCCDIS

CHANNEL 1

STANDBY

CHANNEL 2

STANDBY

VCC

REGULATORS

VCC DISABLE

LOGIC

RES Current

10 mA

500 kW

HICCUP

FAULT TIMER

256 CYCLES

RES

RESTART

LOGIC

CHANNEL 1

CHANNEL 2

DEMB

LOGIC

DECODER

CHANNEL 1

FAULT

CHANNEL 2

FAULT

50 kW

CHANNEL 1

VIN

VCC1

7.6V

REGULATOR

VCC

UVLO

VCC DISABLE

LOGIC

HB1

SS1 Current

10 mA

DISABLE

UVLO

1.2V

SS1

FB1

HO1

SW1

LEVEL SHIFT/

ADAPTIVE

TIMER

CLK 1

0.8V

DRIVER

VCC1

COMP1

RAMP1

LO1

DRIVER

LOGIC DECODER/

DIODE EMULATION

1.2V

CS1

TRACK

SAMPLE

and

CSG1

HOLD

A = 10

PGND1

CLK 1

CHANNEL 2

VIN

VCC2

7.6V

REGULATOR

VCC

UVLO

50 kW

EN2

VCC DISABLE

LOGIC

HB2

SS2 Current

10 mA

DISABLE

UVLO

1.2V

SS2

FB2

HO2

SW2

LEVEL SHIFT/

ADAPTIVE

TIMER

CLK 2

EN2

LOGIC

0.8V

DRIVER

VCC2

COMP2

RAMP2

LO2

DRIVER

LOGIC DECODER/

DIODE EMULATION

1.2V

CS2

CSG2

TRACK

SAMPLE

and

HOLD

A = 10

PGND2

CLK 2

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7.3 Feature Description

7.3.1 High Voltage Start-Up Regulator

The LM5119 contains two internal high voltage bias regulators, VCC1 and VCC2, that provide the bias supply for

the PWM controllers and gate drive for the MOSFETs of each regulator channel. The input pin (VIN) can be

connected directly to an input voltage source as high as 65 V. The outputs of the VCC regulators are set to

7.6 V. When the input voltage is below the VCC set-point level, the VCC output tracks the VIN with a small

dropout voltage. If VCC1 is in an undervoltage condition, channel2 is disabled. This interdependence is

necessary to prevent channel2 from running open-loop in the single output interleaved mode when the channel2

error amplifier is disabled (if either VCC is in UV, both channels are disabled).

The outputs of the VCC regulators are current limited at 25-mA (minimum) output capability. Upon power up, the

regulators source current into the capacitors connected to the VCC pins. When the voltage at the VCC pins

exceed 4.9 V and the UVLO pin is greater than 1.25 V, both channels are enabled and a soft-start sequence

begins. Both channels remain enabled until either VCC pin falls below 4.7 V, the UVLO pin falls below 1.25 V or

the die temperature exceeds the thermal limit threshold.

When operating at higher input voltages the bias power dissipation within the controller can be excessive. An

output voltage derived bias supply can be applied to a VCC pins to reduce the IC power dissipation. The

VCCDIS input can be used to disable the internal VCC regulators when external biasing is supplied.

If VCCDIS >1.25 V, the internal VCC regulators are disabled. The externally supplied bias must be coupled to

the VCC pins through a diode, preferably a Schottky (low forward voltage). VCCDIS has a 500-kΩ internal

pulldown resistance to ground for normal operation with no external bias. The internal pulldown resistance can

be overridden by pulling VCCDIS above 1.25 V through a resistor divider connected to an external bias supply.

The VCC regulator series pass transistor includes a diode between VCC and VIN that must not be forward

biased in normal operation.

If the external bias winding can supply VCC greater than VIN, an external blocking diode is required from the

input power supply to the VIN pin to prevent the external bias supply from passing current to the input supply

through the VCC pins. For VOUT between 6 V and 14.5 V, VOUT can be connected directly to VCC through a

diode. For VOUT < 6 V, a bias winding on the output inductor can be added as shown in Figure 8.

VCC

OUT

Figure 8. VCC Bias Supply With Additional Inductor Winding

In high voltage applications, take extra care to ensure the VIN pin does not exceed the absolute maximum

voltage rating of 75 V. During line or load transients, voltage ringing on the VIN line that exceeds the Absolute

Maximum Rating can damage the IC. Both careful PCB layout and the use of quality bypass capacitors placed

close to the VIN and AGND pins are essential.

7.3.2 UVLO

The LM5119 contains a dual-level undervoltage lockout (UVLO) circuit. When the UVLO pin is less than 0.4 V,

the LM5119 is in shutdown mode. The shutdown comparator provides 100 mV of hysteresis to avoid chatter

during transitions. When the UVLO pin voltage is greater than 0.4 V but less than 1.25 V, the controller is in

standby mode. In the standby mode the VCC bias regulators are active but the controller outputs are disabled.

This feature allows the UVLO pin to be used as a remote enable or disable function. When the VCC outputs

exceed their respective undervoltage thresholds (4.9 V) and the UVLO pin voltage is greater than 1.25 V, the

outputs are enabled and normal operation begins.

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Feature Description (continued)

An external set-point voltage divider from the VIN to GND is used to set the minimum VIN operating voltage of

the regulator. The divider must be designed such that the voltage at the UVLO pin is greater than 1.25 V when

the input voltage is in the desired operating range. UVLO hysteresis is accomplished with an internal 20-μA

current source that is switched on or off into the impedance of the set-point divider. When the UVLO pin voltage

exceeds 1.25-V threshold, the current source is activated to quickly raise the voltage at the UVLO pin. When the

UVLO pin voltage falls below the 1.25-V threshold, the current source is turned off causing the voltage at the

UVLO pin to quickly fall. The UVLO pin must not be left floating.

7.3.3 Enable 2

The LM5119 contains an enable function allowing shutdown control of channel2, independent of channel1. If the

EN2 pin is pulled below 2 V, channel2 enters shutdown mode. If the EN2 input is greater than 2.5 V, channel2

returns to normal operation. An internal 50-kΩ pullup resistor on the EN2 pin allows this pin to be left floating for

normal operation. The EN2 input can be used in conjunction with the UVLO pin to sequence the two regulator

channels. If EN2 is held low as the UVLO pin increases to a voltage greater than the 1.25-V UVLO threshold,

channel1 begins operation while channel2 remains off. Both channels become operational when the UVLO, EN2,

VCC1, and VCC2 pins are above their respective operating thresholds. Either channel of the LM5119 can also

be disabled independently by pulling the corresponding SS pin to AGND.

7.3.4 Oscillator and Sync Capability

The LM5119 switching frequency is set by a single external resistor connected between the RT pin and the

AGND pin (R_T). The resistor must be located very close to the device and connected directly to the pins of the IC

(RT and AGND). To set a desired switching frequency (f_SW) of each channel, the resistor can be calculated with

Equation 1.

5.2ì10⁹

R_T=

- 948

f_SW

where

•

RT is in ohms

f_SWis in hertz

(1)

The frequency f_SWis the output switching frequency of each channel. The internal oscillator runs at twice the

switching frequency and an internal frequency divider interleaves the two channels with 180° phase shift between

PWM pulses at the HO pins.

The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be

synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25 V and

the voltage at the RT pin must exceed 4 V to trip the internal synchronization pulse detector. A 5-V amplitude

signal and 100-pF coupling capacitor are recommended. Synchronizing at greater than twice the free-running

frequency may result in abnormal behavior of the pulse width modulator. Also, note that the output switching

frequency of each channel is one-half the applied synchronization frequency.

7.3.5 Error Amplifiers and PWM Comparators

Each of the two internal high-gain error amplifiers generates an error signal proportional to the difference

between the regulated output voltage and an internal precision reference (0.8 V). The output of each error

amplifier is connected to the COMP pin allowing the user to provide loop compensation components. Generally a

Type II network is recommended. This network creates a pole at 0 Hz, a mid-band zero, and a noise-reducing,

high-frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP

generator to the error amplifier output voltage at the COMP pin. Only one error amplifier is required when

configuring the controller as a two-channel, single-output interleaved regulator. For these applications, the

channel1 error amplifier (FB1, COMP1) is configured as the master error amplifier. The channel2 error amplifier

must be disabled by connecting the FB2 pin to the VCC2 pin. When configured in this manner the output of the

channel2 error amplifier (COMP2) is disabled and have a high output impedance. To complete the interleaved

configuration the COMP1 and the COMP2 pins must be connected together to facilitate PWM control of channel2

and current sharing between channels.

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Feature Description (continued)

7.3.6 Ramp Generator

The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the

buck switch current. This switch current corresponds to the positive slope portion of the inductor current. Using

this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides

inherent input voltage feedforward compensation. The disadvantage of using the buck switch current signal for

PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the

current measurement may introduce significant propagation delays. The filtering, blanking time and propagation

delay limit the minimum achievable pulse width. In applications where the input voltage may be relatively large in

comparison to the output voltage, controlling small pulse widths and duty cycles are necessary for regulation.

The LM5119 using a unique ramp generator which does not actually measure the buck switch current but rather

reconstructs the signal. Representing or emulating the inductor current provides a ramp signal to the PWM

comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is

comprised of two elements; a sample-and-hold DC level and the emulated inductor current ramp as shown in

Figure 9.

VIN x t_ON

RAMP =

R_RAMPx C_RAMP

RAMP

Sample and

10 x R_SV/A

Hold DC Level

t_ON

Figure 9. Composition of Current Sense Signal

The sample-and-hold DC level is derived from a measurement of the recirculating current flowing through the

current sense resistor. The voltage across the sense resistor is sampled and held just prior to the onset of the

next conduction interval of the buck switch. The current sensing and sample-and-hold provide the DC level of the

reconstructed current signal. The positive slope inductor current ramp is emulated by an external capacitor

connected from RAMP pin to AGND and a series resistor connected between SW and RAMP. The ramp resistor

must not be connected to VIN directly because the RAMP pin voltage rating could be exceeded under high VIN

conditions. The ramp created by the external resistor and capacitor has a slope proportional to the rising inductor

current plus some additional slope required for slope compensation. Connecting the RAMP pin resistor to SW

provides optimum slope compensation with a RAMP capacitor slope that is proportional to VIN. This adaptive

slope compensation eliminates the requirement for additional slope compensation circuitry with high output

voltage set points and frees the user from additional concerns in this area. The emulated ramp signal is

approximately linear and the ramp slope is given in Equation 2.

dV_RAMP10ìK ì V ìR_S

(2)

The factor of 10 in Equation 2 corresponds to the internal current sense amplifier gain of the LM5119. The K

factor is a constant which adds additional slope for robust pulse-width modulation control at lower input voltages.

In practice this constant can be varied from 1 to 3. R_Sis the external sense resistor value.

The voltage on the ramp capacitor is given with Equation 3 and Equation 4.

t_PERIOD

≈

∆

’

R_RAMPìC_RAMP

V_RAMP= V ì 1- e

∆

◊

∆

(3)

(4)

V ì t_PERIOD

R_RAMPìC_RAMP

V_RAMP

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Feature Description (continued)

The approximation is the first order term in a Taylor Series expansion of the exponential and is valid because

t_PERIODis small relative to the RAMP pin R-C time constant.

Multiplying Equation 2 by t_PERIODto convert the slope to a peak voltage, and then equating Equation 2 with

Equation 4 allows us to solve for C_RAMPusing Equation 5.

C_RAMP

10ìR_SìK ìR_RAMP

(5)

Choose either C_RAMPor R_RAMPand use Equation 5 to calculate the other component.

The difference between the average inductor current and the DC value of the sampled inductor current can

cause instability for certain operating conditions. This instability is known as sub-harmonic oscillation, which

occurs when the inductor ripple current does not return to its initial value by the start of next switching cycle.

Sub-harmonic oscillation is normally characterized by alternating wide and narrow pulses at the switch node. The

ramp equation above contains the optimum amount of slope compensation, however extra slope compensation is

easily added by selecting a lower value for R_RAMPor C_RAMP

7.3.7 Current Limit

The LM5119 contains a current limit monitoring scheme to protect the regulator from possible overcurrent

conditions. When set correctly, the emulated current signal is proportional to the buck switch current with a scale

factor determined by the current limit sense resistor, R_S, and current sense amplifier gain. The emulated signal is

applied to the current limit comparator. If the emulated ramp signal exceeds 1.2 V, the present cycle is

terminated (cycle-by-cycle current limiting). The current limit comparator and a simplified current measurement

schematic is shown in Figure 10. In applications with small output inductance and high input voltage, the switch

current may overshoot due to the propagation delay of the current limit comparator. If an overshoot must occur,

the sample-and-hold circuit detects the excess recirculating current before the buck switch is turned on again. If

the sample-and-hold DC level exceeds the internal current limit threshold, the buck switch is disabled and skip

pulses until the current has decayed below the current limit threshold. This approach prevents current runaway

conditions due to propagation delays or inductor saturation because the inductor current is forced to decay to a

controlled level following any current overshoot.

CURRENT SENSE

AMPLIFIER

CURRENT LIMIT

COMPARATOR

1.2V

CLK

A=10

CSG

RAMP

Figure 10. Current Limit and Ramp Circuit

7.3.8 Hiccup Mode Current Limiting

To further protect the regulator during prolonged current limit conditions, an internal counter counts the PWM

clock cycles during which cycle-by-cycle current limiting occurs. When the counter detects 256 consecutive

cycles of current limiting, the regulator enters a low power dissipation hiccup mode with the HO and LO outputs

disabled. The restart timer pin, RES, and an external capacitor configure the hiccup mode current limiting. A

capacitor on the RES pin (C_RES) determines the time the controller remains in low power standby mode before

automatically restarting. A 10-µA current source charges the RES pin capacitor to the 1.25-V threshold which

restarts the overloaded channel. The two regulator channels operate independently. One channel may operate

normally while the other is in the hiccup mode overload protection. The hiccup mode commences when either

channel experiences 256 consecutive PWM cycles with cycle-by-cycle current limiting. If that occurs, the

overloaded channel turns off and remains off for the duration of the RES pin timer.

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Feature Description (continued)

The hiccup mode current limiting function can be disabled. The RES configuration is latched during initial power

up when UVLO is above 1.25 V and VCC1 and VCC2 are above their UV thresholds, determining hiccup or non-

hiccup current limiting. If the RES pin is tied to VCC at initial power on, hiccup current limit is disabled.

7.3.9 Soft Start

The soft-start feature allows the regulator to gradually reach the steady-state operating point, thus reducing start-

up stresses and surges. The LM5119 regulates the FB pin to the SS pin voltage or the internal 0.8-V reference,

whichever is lower. At the beginning of the soft-start sequence when SS = 0 V, the internal 10-µA soft-start

current source gradually increases the voltage on an external soft-start capacitor (C_SS) connected to the SS pin

resulting in a gradual rise of the FB and output voltages.

Either regulator channel of the LM5119 can be disabled by pulling the corresponding SS pin to AGND.

7.3.10 HO and LO Output Drivers

The LM5119 contains a high current, high-side driver and associated high voltage level shift to drive the buck

switch of each regulator channel. This gate driver circuit works in conjunction with an external diode and

bootstrap capacitor. A 0.1-µF or larger ceramic capacitor, connected with short traces between the HB pin and

SW pin, is recommended. During the OFF-time of the high-side MOSFET, the SW pin voltage is approximately 0

V and the bootstrap capacitor charges from VCC through the external bootstrap diode. When operating with a

high PWM duty cycle, the buck switch is forced off each cycle for 320 ns to ensure that the bootstrap capacitor is

recharged.

The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs

are never enabled at the same time. When the controller commands HO to be enabled, the adaptive dead-time

logic first disables LO and waits for the LO voltage to drop. HO is then enabled after a small delay. Similarly, the

LO turnon is disabled until the HO voltage has discharged. This methodology insures adequate dead-time for any

size MOSFET.

Exercise care when selecting an output MOSFET with the appropriate threshold voltage, especially if VCC is

supplied from the regulator output. During start-up at low input voltages the MOSFET threshold must be lower

than the 4.9-V VCC undervoltage lockout threshold. Otherwise, there may be insufficient VCC voltage to

completely turn on the MOSFET as VCC undervoltage lockout is released during start-up. If the buck switch

MOSFET gate drive is not sufficient, the regulator may not start or it may hang up momentarily in a high power

dissipation state. This condition can be avoided by selecting a MOSFET with a lower threshold voltage or if VCC

is supplied from an external source higher than the output voltage. If the minimum input voltage programmed by

the UVLO pin resistor divider is above the VCC regulation level, this precaution is of no concern.

7.3.11 Maximum Duty Cycle

When operating with a high PWM duty cycle, the buck switch is forced off each cycle for 320 ns to ensure the

bootstrap capacitor is recharged and to allow time to sample and hold the current in the low-side MOSFET. This

forced OFF-time limits the maximum duty cycle of the controller. When designing a regulator with high switching

frequency and high duty cycle requirements, a check must be made of the required maximum duty cycle

(including losses) against the graph shown in Figure 11.

D_MAX= 1- f_SWì320ì10^-9

(6)

The actual maximum duty cycle varies with the operating frequency as shown in Equation 6.

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Feature Description (continued)

Figure 11. Maximum Duty Cycle vs Switching Frequency

7.3.12 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction

temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power reset state,

disabling the output driver and the VCC bias regulators. This feature is designed to prevent catastrophic failures

from overheating and destroying the device.

7.4 Device Functional Modes

7.4.1 Diode Emulation

A fully synchronous buck regulator implemented with a free-wheel MOSFET rather than a diode has the

capability to sink current from the output in certain conditions such as light load, overvoltage, or prebias start-up.

The LM5119 provides a diode emulation feature that can be enabled to prevent reverse (drain to source) current

flow in the low-side free-wheel MOSFET. When configured for diode emulation, the low-side MOSFET is

disabled when reverse current flow is detected. The benefit of this configuration is lower power loss at no load or

light load conditions and the ability to turn on into a prebiased output without discharging the output. The diode

emulation mode allows for start-up into prebiased loads, because it prevents reverse current flow as the soft-start

capacitor charges to the regulation level during start-up. The negative effect of diode emulation is degraded light

load transient response times. Enabling the diode emulation feature is recommended and allows discontinuous

conduction operation. The diode emulation feature is configured with the DEMB pin. To enable diode emulation,

connect the DEMB pin to ground or leave the pin floating. If continuous conduction operation is desired, the

DEMB pin must be tied to either VCC1 or VCC2.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Miscellaneous Functions

EN2 is left floating which allows channel2 to always remain enabled. If EN2 is pulled below 2 V, channel2 is

disabled.

The DEMB pin is left floating because this design uses diode emulation. For fully synchronous (continuous

conduction) operation, connect the DEMB to a voltage greater than 2.6 V.

VCCDIS is left floating to enable the internal VCC regulators. To disable the internal VCC regulators, connect this

pin to a voltage greater than 1.25 V.

8.1.2 Interleaved Two-Phase Operation

Interleaved operation can offer many advantages in single-output, high-current applications. The output power

path is split between two identical channels reducing the current in each channel by one-half. Ripple current

reduction in the output capacitors is reduced significantly because each channel operates 180 degrees out of

phase from the other. Ripple reduction is greatest at 50% duty cycle and decreases as the duty cycle varies

away from 50%.

Refer to Figure 12 to estimate the ripple current reduction. Also, the effective ripple in the input and output

capacitors occurs at twice the frequency of a single-channel design due to the combining of the two channels. All

of these factors are advantageous in managing the higher currents and their effects in a high power design.

Figure 12. Cancellation Factor vs Duty Cycle for Output Capacitor

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Application Information (continued)

To begin an interleaved design, use the previous equations in this datasheet to first calculate the required value

of components using one-half the current in the output power path. The attenuation factor in Figure 12 is the ratio

of the output capacitor ripple to the inductor ripple versus duty cycle. The inductor ripple used in this calculation

is the ripple in either inductor in a two phase design, not the ripple calculated for a single-phase design of the

same output power. It can be observed that operation around 50% duty cycle results in almost complete ripple

attenuation in the output capacitor. Figure 12 can be used to calculate the amount of ripple attenuation in the

output capacitors.

Figure 13. Normalized Input Capacitor RMS Ripple Current vs Duty Cycle

Figure 13 illustrates the ripple current reduction in the input capacitors due to interleaving. As with the output

capacitors, there is near perfect ripple reduction near 50% duty cycle. This plot can be used to calculate the

ripple in the input capacitors at any duty cycle. In designs with large duty cycle swings, use the worst-case ripple

reduction for the design.

To configure the LM5119 for interleaved operation, connect COMP1 and COMP2 pins together at the IC.

Connecting the FB2 pin to VCC2 pin disables the channel2 error amplifier with a high output impedance at

COMP2. Connect the compensation network between FB1 and the common COMP pins. Connect the two power

stages together at the output capacitors. Finally use the plots in Figure 12 and Figure 13 along with the duty

cycle range to determine the amount of output and input capacitor ripple reduction. Frequently more capacitance

than necessary is used in a design just to meet ESR requirements. Reducing the capacitance based solely on

ripple reduction graphs alone may violate this requirement.

8.1.3 Interleaved 4-Phase Operation

Two LM5119 devices can be designed for 4-phase operation with below configurations. The VCC shutdown and

thermal shutdown on master device will shut down all four channels eventually by pulling down COMP bus. The

VCC shutdown and thermal shutdown on slave device shuts down the device only under fault.

•

To synchronize two devices and achieve phase shift, a 90 degree shifted clock should be applied to RT pins

of master and slave devices

•

Connect COMP pins of master and slave channels together.

Connect FB pin of slave channel to local VCC pin.

Connect RES pin to local VCC pin. This means hiccup model should be disabled.

Connect all UVLO pins of master and slave channels together. This means the UVLO hysteresis current will

be 4 times of 20-μA.

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8.2 Typical Applications

8.2.1 Dual-output Design Example

Figure 14. 10-V 4-A, 5-V 8-A Dual Output Application

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8.2.1.1 Design Requirements

The procedure for calculating the external components is illustrated with Figure 14. Only the values for the 5-V

output are calculated because the procedure is the same for the 10-V output. The circuit shown in Figure 14 is

configured for the following specifications:

•

CH1 output voltage, V_OUT1= 10 V

CH2 output voltage, V_OUT2= 5 V

CH1 maximum load current, I_OUT1= 4 A

CH2 maximum load current, I_OUT2= 8 A

Minimum input voltage, V_IN(min)= 14 V

Maximum input voltage, V_IN(max)= 55 V

Switching frequency, f_SW= 230 kHz

Some component values were chosen as a compromise between the 10-V and 5-V outputs to allow identical

components to be used on both outputs. This design can be reconfigured in a dual-channel interleaved

configuration with a single 10-V output which requires identical power channels.

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Timing Resistor

R_Tsets the switching frequency of each regulator channel. Generally, higher frequency applications are smaller

but have higher losses. Operation at 230 kHz was selected for this example as a reasonable compromise

between small size and high efficiency. The value of R_Tfor 230-kHz switching frequency can be calculated with

Equation 7.

5.2ì10⁹

R_T=

- 948 = 21.66 kW

f_SW

(7)

A standard value or 22.1 kΩ was chosen for R_T. The internal oscillator frequency is twice the switching frequency

and is approximately 460 kHz.

8.2.1.2.2 Output Inductor

The inductor value is determined based on the operating frequency, load current, ripple current, and the input

and output voltages.

T =

Figure 15. Inductor Current

Knowing the switching frequency, maximum ripple current (I_PP), maximum input voltage, and the nominal output

voltage (V_OUT), the inductor value can be calculated with Equation 8.

≈

∆

’

V_OUT

L =

ì 1-

∆

◊

I_PPì f_SW

IN(MAX)

(8)

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The maximum ripple current occurs at the maximum input voltage. Typically, I_PPis 20% to 40% of the full load

current. When operating in the diode emulation mode configuration, the maximum ripple current must be less

than twice the minimum load current. For full synchronous operation, higher ripple current is acceptable. Higher

ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth

the ripple current. For the example in Equation 9, a ripple current of 15% of 8 A was chosen as a compromise for

the 10-V output.

≈

’

◊

5 V

L =

ì 1-

= 16.5 mH

∆

0.15ì8A ì 230 kHz

55 V

(9)

The nearest standard value of 15 μH was chosen for L. Using the value of 15 µH for L in Equation 10 as the

example (Equation 11), calculate I_PPagain. This step is necessary if the chosen value of L differs significantly

from the calculated value.

≈

’

V_OUT

I_PP

ì ∆1-

◊

∆

L ì f_SW

IN(MAX)

(10)

(11)

≈

’

◊

5 V

15 mHì 230 kHz

5 V

I_PP

ì 1-

= 1.32A

∆

55 V

8.2.1.2.3 Current Sense Resistor

Before determining the value of current sense resistor (R_S), it is valuable to understand the K factor, which is the

ramp slope multiple chosen for slope compensation. The K factor can be varied from 1 to 3 in practice and is

defined with Equation 12.

K =

10ìR_SìR_RAMPìC_RAMP

(12)

The performance of the converter varies depending on the selected K value (see Table 1). For this example, 2.5

was chosen as the K factor to minimize the power loss in sense resistor R_Sand the crosstalk between channels.

Crosstalk between the two regulators under certain conditions may be observed on the output as switch jitter.

The maximum output current capability (I_OUT(MAX)) must be approximately 20% to 50% higher than the required

output current, (8 A at V_OUT2) to account for tolerances and ripple current. For this example, 120% of 8 A was

chosen (9.6 A). The current sense resistor value can be calculated with Equation 13 as the example

(Equation 14).

V_CS(TH)

R_S

V_OUTìK I_PP

I_OUT(MAX)

f_SWìL

where

•

V_CS(TH)is the current limit threshold voltage (120 mV)

(13)

(14)

0.12

5 V ì 2.5

R_S=

= 0.0096

1.32A

9.6A +

230 kHzì15 mH

A value of 10 mΩ was chosen for R_S. The sense resistor must be rated to handle the power dissipation at

maximum input voltage when current flows through the free-wheel MOSFET for the majority of the PWM cycle.

The maximum power dissipation of R_Scan be calculated with Equation 15 as the example (Equation 16).

≈

’

V_OUT

P_RS= ∆1-

÷I_OUT²R_S

∆

IN(MAX)

◊

(15)

(16)

≈

’

◊

5 V

P_RS= 1-

ì8²ì0.01= 0.58W

∆

55 V

During output short condition, the worst-case peak inductor current is limited to Equation 17 and the example

(Equation 18).

LM5119

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V_CS(TH)

V_IN(MAX)t_ON(MIN)

I_{LIM_PEAK}

R_S

where

•

t_ON(MIN)is the minimum HO ON-time which is nominally 100 ns

(17)

(18)

0.12 55 V ì100 ns

I_{LIM_PEAK}

= 12.37A

0.01W

15 mH

The chosen inductor must be evaluated for this condition, especially at elevated temperature where the

saturation current rating of the inductor may drop significantly. At the maximum input voltage with a shorted

output, the valley current must fall below V_CS(TH)/ R_Sbefore the high-side MOSFET is allowed to turn on.

8.2.1.2.4 Ramp Resistor and Ramp Capacitor

The value of ramp capacitor (C_RAMP) must be less than 2 nF to allow full discharge between cycles by the

discharge switch internal to the LM5119. A good-quality, thermally-stable ceramic capacitor with 5% or less

tolerance is recommended. For this design the value of C_RAMPwas set at the standard capacitor value of 820 pF.

With the inductor, sense resistor and the K factor selected, the value of the ramp resistor (R_RAMP) can be

calculated with Equation 19 as the example (Equation 20). The standard value of 73.2 kΩ was selected.

R_RAMP

10ìR_SìK ìC_RAMP

(19)

(20)

15 mH

R_RAMP

= 73.2 kW

10ì0.01Wì 2.5ì820 pF

8.2.1.2.5 Output Capacitors

The output capacitors smooth the inductor ripple current and provide a source of charge during transient loading

conditions. For this design example, a 470-µF electrolytic capacitor with 10-mΩ ESR was selected as the main

output capacitor. The fundamental component of the output ripple voltage is approximated with Equation 21 as

the example (Equation 22 and Equation 23).

≈

∆

’

◊

DV_OUT= I_PPì ESR²+

9ì ƒ_SWìC_OUT

(21)

≈

∆

’

◊

DV_OUT= 1.32A ì 0.01W²+

DV_OUT= 13.3 mV

9ì 230 kHz ì 470 mF

(22)

(23)

Two 22-µF low ERS or ESL ceramic capacitors are placed in parallel with the 470-µF electrolytic capacitor to

further reduce the output voltage ripple and spikes.

Table 1. Performance Variation by K Factor

K < 1

1 <— K —> 3

Higher

K > 3

Cross talk

Lower

Higher

Larger

Lower

Higher

Introduces additional

pole near crossover

frequency

Peak inductor current with short output condition

Inductor size

Lower

Smaller

Higher

Lower

Sub-harmonic

oscillation may occur

Power dissipation of Rs

Efficiency

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8.2.1.2.6 Input Capacitors

The regulator input supply voltage typically has high source impedance at the switching frequency. Good-quality

input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current

during the ON-time. When the buck switch turns on, the current into the buck switch steps to the valley of the

inductor current waveform, ramps up to the peak value, and then drops to the zero at turnoff. The input

capacitance must be selected for RMS current rating and minimum ripple voltage. A good approximation for the

required ripple current rating necessary is I_RMS> I_OUT/ 2. Seven 2.2-μF ceramic capacitors were used for each

channel. With ceramic capacitors, the input ripple voltage is triangular. The input ripple voltage with one channel

operating is approximately Equation 24 as the example (Equation 25).

I_OUT

4ì ƒ_SWìC_IN

(24)

= 0.565 V

4ì 230 kHz ì15.4 mF

(25)

The ripple voltage of the input capacitors is reduced significantly with dual-channel operation because each

channel operates 180 degrees out of phase from the other. Capacitors connected in parallel must be evaluated

for RMS current rating. The current splits between the input capacitors based on the relative impedance of the

capacitors at the switching frequency.

When the converter is connected to an input power source, a resonant circuit is formed by the line inductance

and the input capacitors. To minimize overshoot make C_IN> 10 × L_IN. The characteristic source impedance (Z_S)

and resonant frequency (f_S) are Equation 26 and the example (Equation 27).

L_IN

Z_S

C_IN

(26)

f_S=

2p L_INìC_IN

where

•

L_INis the inductance of the input wire

(27)

(28)

The converter exhibits negative input impedance which is lowest at the minimum input voltage in Equation 28.

Z_IN

P_OUT

The damping factor for the input filter is given by Equation 29.

≈

∆

’

◊

R_IN+ ESR Z_S

d =

Z_S

Z_IN

where

•

R_INis the input wiring resistance

ESR is the equivalent series resistance of the input capacitors

(29)

When δ = 1, the input filter is critically damped. This may be difficult to achieve with practical component values.

With δ < 0.2, the input filter exhibits significant ringing. If δ is zero or negative, there is not enough resistance in

the circuit and the input filter sustains an oscillation. When operating near the minimum input voltage, a bulk

aluminum electrolytic capacitor across C_INmay be needed to damp the input for a typical bench test setup.

8.2.1.2.7 VCC Capacitor

The primary purpose of the VCC capacitor (C_VCC) is to supply the peak transient currents of the LO driver and

bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes.

TI recommends the value of C_VCCbe no smaller than 0.47 µF, and be a good-quality, low-ESR, ceramic

capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused by trace

inductance. A value of 1 μF was selected for this design.

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8.2.1.2.8 Bootstrap Capacitor

The bootstrap capacitor between the HB and SW pins supplies the gate current to charge the high-side MOSFET

gate at each cycle’s turnon and recovery charge for the bootstrap diode. These current peaks can be several

amperes. TI recommends the value of the bootstrap capacitor be at least 0.1 μF, and be a good-quality, low-

ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused

by trace inductance. The absolute minimum value for the bootstrap capacitor is calculated with Equation 30. A

value of 0.47 μF was selected for this design.

Q_g

C_HB

DV_HB

where

•

Q_gis the high-side MOSFET gate charge

ΔV_HBis the tolerable voltage droop on C_HB(which is typically less than 5% of VCC)

(30)

8.2.1.2.9 Soft-Start Capacitor

The capacitor at the SS pin (C_SS) determines the soft-start time (t_SS), which is the time for the output voltage to

reach the final regulated value. The value of C_SSfor a given time is determined from Equation 31. For this

application, a value of 0.047 μF was chosen for a soft-start time of 3.8 ms.

t_SSì10 mA

C_SS

0.8 V

(31)

8.2.1.2.10 Restart Capacitor

The restart pin sources 10 µA into the external restart capacitor (C_RES). The value of the restart capacitor is given

by Equation 32. For this application, a value of 0.47 µF was chosen for a restart time of 59 ms.

10 mA ì t_RES

C_RES

1.25 V

where

•

t_RESis the time the LM5119 remains off before a restart attempt in hiccup mode current limiting

(32)

8.2.1.2.11 Output Voltage Divider

R_FB1and R_FB2set the output voltage level, the ratio of these resistors is calculated from Equation 33.

R_FB2V_OUT

-1

R_FB10.8 V

(33)

1.33 kΩ was chosen for R_FB1in this design which results in a R_FB2value of 6.98 kΩ for V_OUT2of 5 V. A

reasonable guide is to select the value of R_FB1in the range between 500 Ω and 10 kΩ. The value of R_FB1must

be large enough to keep the total divider power dissipation small.

V_OUT

0.8 V

R_FB2

COMP

R_COMPC_COMP

C_HF

R_FB1

Figure 16. Feedback Configuration

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8.2.1.2.12 UVLO Divider

The UVLO threshold is internally set to 1.25 V at the UVLO pin. The LM5119 is enabled when the system input

voltage VIN causes the UVLO pin to exceed the threshold voltage of 1.25 V. When the UVLO pin voltage is

below the threshold, the internal 20-μA current source is disabled. When the UVLO pin voltage exceeds the

1.25-V threshold, the 20-μA current source is enabled causing the UVLO pin voltage to increase, providing

hysteresis. The values of R_UV1and R_UV2can be determined from Equation 34 and the example (Equation 35).

V_HYS

R_UV2

20 mA

(34)

1.25 V ìR_UV2

R_UV1

V_IN-1.25

(35)

V_HYSis the desired UVLO hysteresis at VIN, and VIN in the second equation is the desired UVLO release

(turnon) voltage. For example, if it is desired for the LM5119 to be enabled when VIN reaches 13.5 V, and the

desired hysteresis is 1.2 V, then R_UV2must be set to 60 kΩ and R_UV1must be set to 6.12 kΩ. For this application,

R_UV2was selected to be 60.4 kΩ, R_UV1was selected to be 6.19 kΩ. The LM5119 can be remotely shutdown by

taking the UVLO pin below 0.4 V with an external open-collector or open-drain device. The outputs and the VCC

regulator are disabled in shutdown mode. Capacitor C_FTprovides filtering for the divider. A value of 100 pF was

chosen for C_FT. The voltage at the UVLO pin must never exceed 15 V when using the external set-point divider.

It may be necessary to clamp the UVLO pin at high input voltages.

V_IN

20 µA

R_UV2

UVLO

Standby

C_FT

R_UV1

Shutdown

Figure 17. UVLO Configuration

8.2.1.2.12.1 MOSFET Selection

Selection of the power MOSFETs is governed by the same tradeoffs as switching frequency. Breaking down the

losses in the high-side and low-side MOSFETs is one way to compare the relative efficiencies of different

devices. When using discrete SO-8 MOSFETs, generally the output current capability range is 2 A to 10 A.

Losses in the power MOSFETs can be broken down into conduction loss, gate charging loss, and switching loss.

Conduction loss P_DCis approximately Equation 36 and the example (Equation 37).

P_{DC(HO-MOSFET)}= Dì(I_O²ìR_DS(ON)ì1.3)

(36)

P_{DC(LO-MOSFET)}= (1-D)ì(I_O²ìR_DS(ON)ì1.3)

where

•

D is the duty cycle

The 1.3 factor accounts for the increase in MOSFET on-resistance due to heating

(37)

Alternatively, the factor of 1.3 can be eliminated and the high temperature ON-resistance of the MOSFET can be

estimated using the R_DS(ON)vs Temperature curves in the MOSFET datasheet. Gate charging loss, P_GC, results

from the current driving the gate capacitance of the power MOSFETs and is approximated with Equation 38.

P_GC= nì V_CCìQ_gì f_SW

where

•

Q_grefers to the total gate charge of an individual MOSFET

n is the number of MOSFETs

(38)

LM5119

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Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM5119

and not in the MOSFET itself. Further loss in the LM5119 is incurred if the gate driving current is supplied by the

internal linear regulator. In this example, VCC is supplied from the 10-V output through a diode to minimize the

loss of the internal linear regulator.

Switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition

period both current and voltage are present in the channel of the MOSFET. The switching loss can be

approximated with Equation 39.

P_SW= 0.5ì V ìI_Oì(t_R+ t_F)ì f_SW

where

•

t_Rand t_Fare the rise and fall times of the MOSFET

(39)

The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed with an

oscilloscope. Switching loss is calculated for the high-side MOSFET only. Switching loss in the low-side

MOSFET is negligible because the body diode of the low-side MOSFET turns on before the MOSFET itself,

minimizing the voltage from drain to source before turnon. For this example, the maximum drain-to-source

voltage applied to either MOSFET is 55 V. The selected MOSFETs must be able to withstand 55 V plus any

ringing from drain to source, and be able to handle at least the VCC voltage plus any ringing from gate to source.

A good choice of MOSFET for the 55-V input design example is the PSMN5R5. It has an R_DS(ON)of 5.2 mΩ and

total gate charge of 56 nC. In applications where a high step-down ratio is maintained in normal operation,

efficiency may be optimized by choosing a high-side MOSFET with lower Q_g, and low-side MOSFET with lower

R_DS(ON)

8.2.1.2.13 MOSFET Snubber

A resistor-capacitor snubber network across the low-side MOSFET reduces ringing and spikes at the switching

node. Excessive ringing and spikes can cause erratic operation and couple noise to the output. Selecting the

values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the

snubber connections are very short. Start with a resistor value between 5 and 50 Ω. Increasing the value of the

snubber capacitor results in more damping, but higher snubber losses. Select a minimum value for the snubber

capacitor that provides adequate damping of the spikes on the switch waveform at high load. A snubber may not

be necessary with an optimized layout.

8.2.1.2.14 Error Amplifier Compensation

R_COMP, C_COMP, and C_HFconfigure the error amplifier gain characteristics to accomplish a stable voltage loop gain.

One advantage of current mode control is the ability to close the loop with only two feedback components, R_COMP

and C_COMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For the 5-V

output design example, the modulator is treated as an ideal voltage-to-current converter. The DC modulator gain

of the LM5119 can be modeled with Equation 40.

R_LOAD

DC_GAIN_(MOD)

(A ìR_S)

(40)

NOTE

A is the gain of the current sense amplifier which is 10 in the LM5119

The dominant low frequency pole of the modulator is determined by the load resistance (R_LOAD) and output

capacitance (C_OUT). The corner frequency of this pole is calculated with Equation 41.

f_P(MOD)

(2pìR_LOADìC_OUT

)

(41)

For R_LOAD= 5 V / 8 A = 0.625 Ω and C_OUT= 514 μF (effective) then f_P(MOD)= 496 Hz.

DC Gain_(MOD)= 0.625 Ω / (10 x 10 mΩ) = 6.25 = 15.9 dB.

For the 5-V design example, the modulator gain versus frequency characteristic is shown in Figure 18.

LM5119

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Figure 18. Modulator Gain and Phase

Components R_COMPand C_COMPconfigure the error amplifier as a Type II configuration. The DC gain of the

amplifier is 80 dB with a pole at 0 Hz and a zero at f_ZEA= 1 / (2 π × R_COMP× C_COMP). The error amplifier zero

cancels the modulator pole leaving a single pole response at the crossover frequency of the voltage loop. A

single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin. For

the design example, a conservative target loop bandwidth (crossover frequency) of 11 kHz was selected. The

compensation network zero (f_ZEA) must be selected at least an order of magnitude less than the target crossover

frequency. This constrains the product of R_COMPand C_COMPfor a desired compensation network zero 1 / (2 π ×

R_COMP× C_COMP) to be approximately 1.1 kHz. Increasing R_COMP, while proportionally decreasing C_COMP

increases the error amp gain. Conversely, decreasing R_COMPwhile proportionally increasing C_COMP, decreases

the error amp gain. For the design example C_COMPwas selected as 6800 pF and R_COMPwas selected as 36.5

kΩ. These values configure the compensation network zero at 640 Hz. The error amp gain at frequencies greater

than f_ZEAis: R_COMP/ R_FB2, which is approximately 5.22 (14.3 dB).

Figure 19. Error Amplifier Gain and Phase

The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

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Figure 20. Overall Voltage Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be

configured for the desired loop transfer function. If the K factor is between 2 and 3, the stability must be checked

with the network analyzer. If a network analyzer is not available, the error amplifier compensation components

can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable

performance. The step load goal is minimum overshoot with a damped response. C_HFcan be added to the

compensation network to decrease noise susceptibility of the error amplifier. The value of C_HFmust be

sufficiently small because the addition of this capacitor adds a pole in the error amplifier transfer function. This

pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added

by C_HFis: f_P2= f_ZEA× C_COMP/ C_HF. The value of C_HFwas selected as 100 pF for the design example.

8.2.1.3 Application Curves

V_IN= 24 Vdc

I_OUTrising from 2 A to 6 A

Bottom trace: I_OUT, 2 A/div

Top trace: V_OUT= 3.3 V, 100

mV/div, AC-coupled

Horizontal resolution: 0.5

ms/div

Figure 21. Load Transient Response

Figure 22. Typical Efficiency vs Load Current

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8.2.2 Two-Phase Design Example

Figure 23. Two-Phase Design Example

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8.2.2.1 Design Requirements

Below are the design requirements for two-phase operation.

•

Output voltage, V_OUT= 10 V

Load current, I_OUT= 8 A

Minimum input voltage, V_IN(min)= 14 V

Maximum input voltage, V_IN(max)= 55 V

Switching frequency, f_SW= 230 kHz

8.2.2.2 Detailed Design Procedure

Refer to the design procedure of dual-output example to select external components. In the device evaluation

board (schematic shown in ) interleaved operation can be enabled by shorting both outputs together (with

identical components in the power train), and using zero ohm resistors for R22 and R21. This shorts VCC2 to

FB2 and COMP2 to COMP1 respectively. Also the channel2 feedback network C14, R6, and C15 must be

removed.

8.2.2.3 Application Curves

V_IN= 12 V

I_OUT= 16 A

V_OUT= 3.3 V

V_IN= 12 V

I_OUT= 1 A

V_OUT= 3.3 V

Figure 24. VIN Startup

Figure 25. VIN Shutdown

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V_IN= 12 V

I_OUT= 16 A

V_OUT= 3.3 V

Figure 26. Switching

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9 Power Supply Recommendations

LM5119 is a power management device. The power supply for the device is an DC voltage source within the

specified input range.

10 Layout

10.1 Layout Guidelines

The LM5119 consists of two integrated regulators operating almost independently. Crosstalk between the two

regulators under certain conditions may be observed as switch jitter. This effect is common for any dual-channel

regulator. Crosstalk effects are usually most severe when one channel is operating around 50% duty cycle.

Careful layout practices help to minimize this effect. The following board layout guidelines apply specifically to

the LM5119 and must be followed for best performance.

1. Keep the Loop1 and Loop2, shown in Figure 27, as small as possible

2. Keep the signal and power grounds separate

3. Place VCC capacitors (C6, C7) and VIN capacitor (C9) as closes as possible to the LM5119

4. Route CS and CSG traces together with Kelvin connection to the sense resistor

5. Connect AGND and PGND directly to the underside exposed pad

6. Ensure there are no high current paths beneath the underside exposed pad

10.1.1 Switching Jitter Root Causes and Solutions

1. Noise coupling of the high frequency switching between two channels through the input power rail

1. Keep the high current path as short as possible

2. Choose a FET with minimum lead inductance

3. Place local bypass capacitors (C_IN1, C_IN2) as close as possible to the high-side FETs to isolate one

channel from the high frequency noise of the other channel

4. Slow down the SW switching speed by increasing gate resistors R29 and R30

5. Minimize the effective ESR or ESL of the input capacitor by paralleling input capacitors

2. High frequency AC noise on FB, CS, CSG and COMP

1. Use the star ground PCB layout technique and minimize the length of the high current path

2. Keep the signal traces away from the SW, HO, HB traces and the inductor

3. Add an R-C filter between the CS and CSG pins

4. Place CS filter capacitor (C30, C31) next to the LM5119 and on the same PCB layer as the LM5119

3. Ground offset at the switching frequency

1. Use the star ground PCB layout technique and minimize the length between the grounds of C_IN1and C_IN2

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10.2 Layout Example

IN2

IN1

Loop1

Loop2

OUT2

OUT1

CSG1

CS1

CSG2

CS2

AGND

FB2A

FB1A

FB1B FB2B

The bold lines indicate a solid ground plane. Make the

traces to the widest and the shortest and use the star

ground technique.

These lines indicate the high current paths. Make the

traces as wide and short as possible

These lines indicate the small signal paths. The traces

can be narrow but keep them away from any radiated

noise and away from traces that may couple noise

capacitively

These points require the maximum bypassing of the high

frequency switching noise. Isolate each channel from the

high frequency switching noise of the other channel.

Figure 27. Recommended PCB Layout

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11 器件和文档支持

11.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

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10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM5119PSQ/NOPB

LM5119PSQE/NOPB

LM5119PSQX/NOPB

ACTIVE

WQFN

RTV

1000 RoHS & Green

250 RoHS & Green

4500 RoHS & Green

Level-3-260C-168 HR

-40 to 125

L5119P

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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10-Dec-2020

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM5119PSQ/NOPB

LM5119PSQE/NOPB

LM5119PSQX/NOPB

WQFN

RTV

1000

250

178.0

330.0

12.4

5.3

1.3

8.0

12.0

4500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM5119PSQ/NOPB

LM5119PSQE/NOPB

LM5119PSQX/NOPB

WQFN

RTV

1000

250

208.0

356.0

191.0

356.0

35.0

4500

Pack Materials-Page 2

PACKAGE OUTLINE

RTV0032A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.15

4.85

PIN 1 INDEX AREA

5.15

4.85

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

SYMM

EXPOSED

THERMAL PAD

(0.1) TYP

SYMM

2X 3.5

3.1 0.1

28X 0.5

0.30

32X

0.18

PIN 1 ID

0.1

C A B

0.5

0.3

32X

0.05

4224386/B 04/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RTV0032A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.1)

SYMM

SEE SOLDER MASK

DETAIL

32X (0.6)

32X (0.24)

28X (0.5)

(3.1)

SYMM

(4.8)

(1.3)

(R0.05) TYP

(

0.2) TYP

VIA

(1.3)

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224386/B 04/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RTV0032A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.775) TYP

32X (0.6)

32X (0.24)

28X (0.5)

(0.775) TYP

(4.8)

SYMM

(R0.05) TYP

4X (1.35)

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 33

76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4224386/B 04/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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