LM51231QRGRRQ1_技术文档

LM51231-Q1

ZHCSPC5 –OCTOBER 2022

LM51231-Q1 具有VOUT 跟踪功能的2.2MHz 宽VIN 同步升压控制器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准

LM51231-Q1 器件是一款采用峰值电流模式控制的宽

输入范围同步升压控制器。该器件的宽输入范围支持汽

车冷启动和负载突降。当 BIAS 引脚等于或大于 3.8V

时，最小输入电压可低至 0.8V。可使用跟踪功能对输

出电压进行动态编程。当V_SUPPLY> V_LOAD时，会自动

进入旁路模式运行，从而消除高侧 MOSFET 的体二极

管压降。用户可通过外部电阻器对开关频率进行动态编

程，编程范围为 100kHz 至 2.2MHz。2.2MHz 的开关

频率可更大限度地降低 AM 频带干扰，并支持实现小

解决方案尺寸和快速瞬态响应。

– 温度等级1：–40°C 至+125°C，T_A

• 功能安全型

– 可提供用于功能安全系统设计的文档

• 适用于宽工作电压范围的汽车类电池供电应用

– 3.8V 至42V 输入电压工作范围

– 5V 至20V 或15V 至57V 的动态可编程VOUT

– BIAS 引脚≥3.8V 时最小升压输入为0.8V

– V_SUPPLY> V_LOAD时进行旁路操作

• BIAS 引脚关断电流≤3μA

• 小尺寸解决方案

该器件具有内置的保护功能，例如在 V_SUPPLY范围内

具有恒定的峰值电流限制、过压保护和热关断功能。外

部时钟同步、可编程展频调制以及具有超低寄生效应的

无引线封装有助于降低 EMI 并避免串扰问题。附加功

能包括线路 UVLO、FPWM、二极管仿真、DCR 电感

器电流检测、可编程的软启动和电源正常状态指示器

– 最大开关频率：2.2MHz

– 内部自举二极管

– 具有可润湿侧翼的QFN-20 封装

• 缓解EMI，并避免AM 波段干扰和串扰

– 可选的时钟同步

– 开关频率范围为100kHz 至2.2MHz

– 可选开关模式（FPWM、二极管仿真）

– 可选可编程扩展频谱

– 无引线封装

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

LM51231-Q1

QFN (20)

3.5mm x 3.5mm

• 可编程性和灵活性

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

– 动态V_OUT跟踪

– 动态开关频率编程

– 支持DCR 电感器电流感测

– 可编程的输入电压UVLO

– 可调软启动

V_LOAD

V_SUPPLY

VOUT

HB

BIAS

VCC

RT

HO

SW

SS

V_SUPPLY

COMP

– 自适应死区时间

– PGOOD 指示器

• 集成型保护特性

LO

MODE

AGND

VDD(MCU)

PGND

CSN

CSP

UVLO

Power Good

Indicator to MCU

PGOOD

VREF

TRK

V_SUPPLY

– 在V_SUPPLY范围内具有恒定的逐周期峰值电流限

制

SYNC/DITHER

– 过压保护

– HB-SW 短路保护

– 热关断

Envelope

tracking input

from MCU

典型应用

2 应用

• 具有跟踪功能的汽车音频电源

• 汽车LED 偏置电源

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSGN5

LM51231-Q1

ZHCSPC5 –OCTOBER 2022

www.ti.com.cn

Table of Contents

7.4 Device Functional Modes..........................................26

8 Application and Implementation..................................30

8.1 Application Information............................................. 30

8.2 Typical Application.................................................... 30

8.3 System Example.......................................................32

8.4 Power Supply Recommendations.............................34

8.5 Layout....................................................................... 34

9 Device and Documentation Support............................36

9.1 接收文档更新通知..................................................... 36

9.2 支持资源....................................................................36

9.3 Trademarks...............................................................36

9.4 Electrostatic Discharge Caution................................36

9.5 术语表....................................................................... 36

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Typical Characteristics.............................................. 11

7 Detailed Description......................................................14

7.1 Overview...................................................................14

7.2 Functional Block Diagram.........................................14

7.3 Feature Description...................................................14

Information.................................................................... 36

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

October 2022

*

Initial release

2

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5 Pin Configuration and Functions

20 19

18 17 16

CSP

CSN

1

2

3

4

5

15

14 SYNC/DITHER/VH

13

RT

EP

VOUT/SENSE

PGOOD

HO

UVLO/EN

12 MODE

11 LO

6

7

8

9

10

图5-1. 20-Pin QFN with Wettable Flanks RGR Package (Top View)

表5-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NO.

1

NAME

CSP

I

Current sense amplifier input. The pin operates as the positive input pin.

Current sense amplifier input. The pin operates as the negative input pin.

2

CSN

Output voltage sensing pin. An internal feedback resistor voltage divider is connected

from the pin to AGND. Connect a 0.1-μF local VOUT capacitor from the pin to ground.

3

VOUT/SENSE

I

High-side MOSFET drain voltage sensing pin. Connect the pin to the drain of the high-

side MOSFET through a short, low inductance path.

Power-good indicator with open-drain output stage. The pin is grounded when the output

voltage is less than the undervoltage threshold. The pin can be left floating if not used.

4

5

PGOOD

HO

O

High-side gate driver output. Connect directly to the gate of the high-side N-channel

MOSFET through a short, low inductance path.

Switching node connection and the high-side MOSFET source voltage sensing pin.

Connect directly to the source of the high-side N-channel MOSFET and the drain of the

low-side N-channel MOSFET through a short, low inductance path. Connect to PGND for

non-synchronous boost configuration.

6

7

SW

HB

P

High-side driver supply for bootstrap gate drive. Boot diode is internally connected from

VCC to the pin. Connect a 0.1-μF capacitor between the pin and SW. Connect to VCC

for non-synchronous boost configuration.

Supply voltage input to the VCC regulator. Connect a 1-μF local BIAS capacitor from the

pin to ground.

8

9

BIAS

VCC

PGND

LO

P

Output of the internal VCC regulator and supply voltage input of the internal MOSFET

drivers. Connect a 4.7-μF capacitor between the pin and PGND.

Power ground pin. Connect directly to the source of the low-side N-channel MOSFET

and the power ground plane through a short, low inductance path.

10

11

G

O

Low-side gate driver output. Connect directly to the gate of the low-side N-channel

MOSFET through a short, low inductance path.

Device switching mode (FPWM or diode emulation) selection pin. The device is

configured to diode emulation if the pin is open or if a resistor that is greater than 500 kΩ

is connected from the pin to AGND or is less than 0.4 V during initial power-on. The

device is configured to FPWM mode by connecting the pin to VCC or if the pin voltage is

greater than 2.0 V during power-on. The switching mode can be dynamically

programmed between the FPWM and the DE mode during operation.

12

MODE

I

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表5-1. Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NO.

NAME

Enable pin. The pin enables/disables the device. If the pin is less than 0.35 V, the device

shuts down. The pin must be raised above 0.65 V to enable the device.

Undervoltage lockout programming pin. The converter start-up and shutdown levels can

be programmed by connecting the pin to the supply voltage through a resistor voltage

divider. The low-side UVLO resistor must be connected to AGND. Connect to BIAS if not

used.

13

UVLO/EN

I

Synchronization clock input. The internal oscillator can be synchronized to an external

clock during operation. Connect to AGND if not used.

Clock dithering/spread spectrum modulation frequency programming pin. If a capacitor is

connected between the pin and AGND, the clock dithering/spread spectrum function is

activated. During the dithering operation, the capacitor is charged and discharged with an

internal 20-μA current source/sink. As the voltage on the pin ramps up and down, the

oscillator frequency is modulated between –6% and +5% of the nominal frequency set

by the RT resistor. The clock dithering/spread spectrum can be deactivated during

operation by pulling down the pin to ground.

14

SYNC/DITHER/VH

I/O

VCC hold pin. If the pin is greater than 2.0 V, the device holds the VCC pin voltage when

the EN pin is grounded, which helps to restart fast without reconfiguration.

Switching frequency setting pin. If no external clock is applied to the SYNC pin, the

switching frequency is programmed by a single resistor between the pin and AGND.

Switching frequency is dynamically programmable during operation.

15

16

RT

I

1.0-V internal reference voltage output. Connect a 470-pF capacitor from the pin to

AGND. The V_OUTregulation target can be programmed by connecting a resistor voltage

divider from the pin to TRK. The resistance from the pin to AGND must be always greater

than 20 kΩif used. Connect the low-side resistor of the divider to AGND.

V_OUTrange selection pin. Lower V_OUTrange (5 V to 20 V) is selected if the resistance

from the pin to AGND is in the range of 75 kΩand 100 kΩduring initial power-on. Upper

VOUT range (15 V to 57 V) is selected if the resistance from the pin to AGND is in the

range of 20 kΩand 35 kΩduring initial power-on. Boost converter output voltage can be

dynamically programmed within the pre-programmed range. The accuracy of the output

voltage regulation is specified within the selected range.

VREF/RANGE

I/O

Soft-start time programming pin. An external capacitor and an internal current source set

the ramp rate of the internal error amplifier reference during soft start. The device forces

diode emulation during soft-start time.

17

18

SS

I/O

I

Output regulation target programming pin. The V_OUTregulation target can be

programmed by connecting the pin to VREF through a resistor voltage divider or by

controlling the pin voltage directly from a D/A. The recommended operating range of the

pin is from 0.25 V to 1.0 V.

TRK

19

20

AGND

COMP

G

O

Analog ground pin. Connect to the analog ground plane through a wide and short path.

Output of the internal transconductance error amplifier. Connect the loop compensation

components between the pin and AGND.

Exposed pad of the package. The EP must be soldered to a large analog ground plane to

reduce thermal resistance.

-

EP

(1) G = Ground, I = Input, O = Output, P = Power

4

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6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range (unless otherwise specified)⁽¹⁾

MIN

MAX

UNIT

BIAS to AGND

UVLO to AGND

CSP to AGND

50

–0.3

-0.3

BIAS + 0.3

50

0.3

CSP to CSN

VOUT to AGND

HB to AGND

65

Input⁽²⁾

V

HB to SW

5.8⁽³⁾

60

SW to AGND

SW to AGND (50ns)

MODE, SYNC, TRK to AGND

PGOOD to AGND

RT to AGND

–1

5.5

VOUT + 0.3

2.5

–0.3

–1

PGND to AGND

VCC to AGND

0.3

5.8⁽³⁾

HO to SW (50ns)

LO to PGND (50ns)

Output⁽²⁾

V

–1

VREF, SS, COMP to AGND⁽⁴⁾

5.5

150

–0.3

–40

–55

(5)

Operating junction temperature, T_J

Storage temperature, T_STG

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) It is not allowed to apply an external voltage directly to VREF, COMP, SS, RT, LO, HO pins.

(3) Operating lifetime is de-rated when the pin voltage is greater than 5.5V.

(4) Maximum VREF pin sourcing current is 50uA.

(5) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD Classification Level 2

±2000

Electrostatic

discharge

V_(ESD)

V

All pins

±500

±750

Charged-device model (CDM), per AEC Q100-011

CDM ESD Classification Level C4B

Corner pins

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range (unless otherwise specified)⁽¹⁾

MIN

NOM

MAX

UNIT

V_{SUPPLY(BOOST)}

V_LOAD(BOOST)

V_BIAS

0.8

5

42

57

Boost Converter Input (when BIAS ≥3.8V)

Boost Converter Output

BIAS Input

3.8

0

42

V_UVLO

UVLO Input

42

V

V_CSP, V_CSN

V_VOUT

Current Sense Input

0.8

5

42

Boost Output Sense

57

V_TRK

TRK Input

0.25

0

1⁽³⁾

5.25

2200

150

V_SYNC

Synchronization Pulse Input

Typical Switching Frequency

Synchronization Pulse Frequency

Operating Junction Temperature⁽²⁾

f_SW

100

200

–40

kHz

°C

f_SYNC

T_J

(1) Recommended Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions,

see Electrical Characteristics

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

(3) The maximum TRK pin voltage is limited to 0.95V when upper VOUT range is selected.

6.4 Thermal Information

LM5123-Q1

THERMAL METRIC⁽¹⁾

RGR(QFN)

20 PINS

43.3

UNIT

R_qJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_qJC(top)

R_qJB

39.9

17.8

y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.8

y_JB

17.8

R_qJC(bot)

5.3

(1) For more information about traditional and new thermal metrics, see the application report.

6.5 Electrical Characteristics

Typical values correspond to T_J= 25 °C. Minimum and maximum limits apply over T_J= -40 °C to 125 °C. Unless otherwise

stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, , R_VREF= 65 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT(BIAS, VCC, VOUT)

I_BIAS-SD

BIAS current in shutdown

V_UVLO= 0 V, V_OUT= 11.3 V

V_UVLO= 2.5 V, V_TRK= 0.6 V

2.5

1.22

5

µA

BIAS current in active (Non-

switching, VCC is supplied by

BIAS)

I_BIAS-ACTIVE

1.52

mA

I_BIAS-BYP

I_VOUT-SD

BIAS current in bypass mode

VOUT current in shutdown

V_UVLO= 2.5 V, V_TRK= 0.25 V

V_UVLO= 0 V, V_OUT= 11.3 V

1.52

1

mA

µA

V_UVLO= 2.5 V, V_TRK= 0.25 V, V_VOUT

12 V, MODE = GND

=

I_VOUT-BYP-DE

VOUT current in bypass mode

100

240

115

276

µA

V_UVLO= 2.5 V, V_TRK= 0.25 V, V_VOUT

12 V, MODE = VCC

I_{VOUT-BYP-FPWM}

6

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6.5 Electrical Characteristics (continued)

Typical values correspond to T_J= 25 °C. Minimum and maximum limits apply over T_J= -40 °C to 125 °C. Unless otherwise

stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, , R_VREF= 65 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOUT current in active (Non-

switching) (DE mode)

V_UVLO= 2.5 V, V_TRK= 0.6 V, MODE =

GND

90

105

µA

I_VOUT-ACTIVE

VOUT current in active (Non-

switching), (FPWM)

V_UVLO= 2.5 V, V_TRK= 0.6 V, MODE =

VCC

240

2.5

276

5

µA

I_BATTERY-SD

I_BATTERY-DE

Battery drain in shutdown

V_UVLO= 0 V, V_OUT= 11.3 V

Battery drain in bypass mode

(DE mode)

V_UVLO= 2.5 V, V_TRK= 0.25 V, MODE =

GND

1.44

1.59

mA

Battery drain in bypass mode

(FPWM)

V_UVLO= 2.5 V, V_TRK= 0.25 V, MODE =

VCC

I_BATTERY-FPWM

1.58

1.74

mA

ENABLE, UVLO

V_EN-RISING

Enable threshold

Enable hysteresis

EN rising

EN falling

0.45

0.35

55

0.55

0.45

90

0.65

0.55

130

V

V_EN-FALLING

V_EN-HYS

mV

UVLO pull-down hysteresis

current

I_UVLO-HYS

V_UVLO= 0.7 V

8

10

12

µA

V_UVLO-RISING

UVLO threshold

UVLO hysteresis

UVLO rising

UVLO falling

1.05

1.1

1.075

25

1.15

V

V_UVLO-FALLING

V_UVLO-HYS

1.025

1.125

mV

SYNC/DITHER/VH

SYNC threshold/SYNC detection

threshold

V_SYNC-RISING

V_SYNC-FALLING

SYNC rising

SYNC falling

2

V

SYNC threshold

0.4

16

Minimum SYNC pull up pulse

width

100

26

ns

µA

I_DITHER

Dither source/sink current

f_SWModulation (Upper Limit)

f_SWModulation (Lower Limit)

Dither disable threshold

21

5%

Δf_SW1

-6%

0.75

Δf_SW2

V_{DITHER-FALLING}

VCC

0.65

0.85

V

V_VCC-REG1

V_VCC-REG2

V_VCC-REG3

V_{VCC-UVLO-RISING}

VCC regulation

I_VCC= 100 mA

No load

4.75

3.45

3.55

3.2

5

5.25

V

VCC regulation

VCC regulation during dropout

VCC UVLO threshold

V_BIAS= 3.8V, I_VCC= 100 mA

VCC rising

V

3.65

3.3

3.75

3.4

V

V_{VCC-UVLO-FALLING}VCC UVLO threshold

I_VCC-CLVCC sourcing current limit

CONFIGURATION (MODE)

VCC falling

V

V_VCC= 4 V

100

mA

V_MODE-RISING

V_MODE-FALLING

RT

FPWM mode threshold

MODE rising

2.0

V

Diode emulation mode threshold MODE falling

0.4

V_RT

RT regulation

0.5

V

VREF, TRK, VOUT

V_REF

VREF regulation target

0.99

1

5

1.005

5.085

V

VOUT regulation target1 with

resistor divider (lower VOUT

range)

VREF resistor divider to make V_TRK

0.25 V, R_VREF= 65 kΩ

=

V_OUT-REG

4.915

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6.5 Electrical Characteristics (continued)

Typical values correspond to T_J= 25 °C. Minimum and maximum limits apply over T_J= -40 °C to 125 °C. Unless otherwise

stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, , R_VREF= 65 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOUT regulation target2 with

resistor divider (lower VOUT

range)

VREF resistor divider to make V_TRK

0.5 V, R_VREF= 65 kΩ

=

V_OUT-REG

9.9

10

10.1

V

VOUT regulation target3 with

resistor divider (lower VOUT

range)

VREF resistor divider to make V_TRK

1.0 V, R_VREF= 65 kΩ

19.8

14.74

29.7

20

15

30

57

20.2

15.24

30.3

V

VOUT regulation target4 with

resistor divider (upper VOUT

range)

VREF resistor divider to make V_TRK

0.25 V, R_VREF= 35 kΩ

VOUT regulation target5 with

resistor divider (upper VOUT

range)

VREF resistor divider to make V_TRK

0.5 V, R_VREF= 35 kΩ

VOUT regulation target6 with

resistor divider (upper VOUT

range)

VREF resistor divider to make V_TRK

0.95 V, R_VREF= 35 kΩ

56.43

57.57

VOUT regulation target1 using

TRK (lower VOUT range)

V_OUT-REG

4.91

9.88

5

10

20

15

30

57

5.09

10.11

20.2

V

V_TRK= 0.25 V, R_VREF= 65 kΩ

V_TRK= 0.5 V, R_VREF= 65 kΩ

V_TRK= 1.0 V, R_VREF= 65 kΩ

V_TRK= 0.25 V, R_VREF= 35 kΩ

V_TRK= 0.5 V, R_VREF= 35 kΩ

V_TRK= 0.95 V, R_VREF= 35 kΩ

VOUT regulation target2 using

TRK (lower VOUT range)

VOUT regulation target3 using

TRK (lower VOUT range)

19.8

VOUT regulation target4 using

TRK (upper VOUT range)

14.71

29.6

15.25

30.3

VOUT regulation target5 using

TRK (upper VOUT range)

VOUT regulation target6 using

TRK (upper VOUT range)

V_OUT-REG

I_TRK

56.45

57.5

1

V

TRK bias current

µA

SOFT START, DE to FPWM TRANSITION

I_SS

Soft-start current

17

20

1.5

30

50

55

23

1.7

70

75

µA

V

V_SS-DONE

R_SS

V_SS-DIS

V_SS-FB

MODE transition start

SS rising

V_FB=0V

1.3

SS pull-down switch R_DSON

SS discharge detection threshold

internal SS to FB clamp

Ω

30

mV

CURRENT SENSE (CSP, CSN, SW, SENSE)

Peak slope compensation

amplitude

V_SLOPE

45

mV

R_T= 220 kΩ, Referenced to CS input

Current sense amplifier gain

CSP=3.0V

CSP=1.5V

10

V/V

A_CS

Current sense amplifier gain

Positive peak current limit

threshold (CSP-CSN)

CSP=3.0V, MODE = GND

52

51

60

68

72

mV

V_CLTH

Positive peak current limit

threshold (CSP-CSN)

CSP=1.5V, MODE = GND

MODE = GND

60

4

mV

V_ZCD-DE

ZCD threshold (SW-SENSE)

Negative current limit threshold

(SW-SENSE)

V_I-NEG-FPWM

MODE = VCC

–150

Forward current threshold

voltage to enter bypass mode

(CSP-CSN)

V_CS-FWD

V_ULVO= 2.5 V, V_TRK= 0.25 V

2

6

10

mV

Zero cross detection in bypass

mode (DE mode) (SW-SENSE) GND

V_ULVO= 2.5 V, V_TRK= 0.25 V, MODE =

V_ZCD-BYP

-5

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6.5 Electrical Characteristics (continued)

Typical values correspond to T_J= 25 °C. Minimum and maximum limits apply over T_J= -40 °C to 125 °C. Unless otherwise

stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, , R_VREF= 65 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Negative current limit in bypass V_ULVO= 2.5 V, V_TRK= 0.25 V, MODE =

V_I-NEG-BYP

-150

mV

mode (FPWM) (SW-SENSE)

CSN bias current

VCC

I_CSN

I_CSP

1

µA

CSP bias current

110

BOOT FAULT PROTECTION (HB)

Maximum replenish pulse cycles

4

cycles

Replenish off cycles

12

Number of sets to enter hiccup

mode protection

4

sets

Off-cycle during hiccup mode off

512

cycles

ERROR AMPLIFIER (COMP)

Gm

Transconductance

1

mA/V

µA

Maximum COMP sourcing

current

I_SOURCE-MAX

V_COMP=0V

95

I_SINK-MAX

Maximum COMP sinking current V_COMP=1.8V

COMP maximum clamp voltage COMP rising

90

µA

V

V_CLAMP-MAX

V_CLAMP-MIN

PULSE WIDTH MODULATION (PWM)

2.05

2.4

2.8

COMP minimum clamp voltage

COMP falling

0.65

V

f_SW1

Switching frequency

85

1980

14

100

2200

20

115

2420

50

kHz

ns

R_T= 220 kΩ

R_T= 9.09 kΩ

R_T= 220kΩ

R_T= 9.09 kΩ

f_SW2

Switching frequency

t_ON-MIN

t_OFF-MIN

D_MAX1

Minimum controllable on-time

Minimum forced off-time

Maximum duty cycle limit

70

95

115

ns

90%

75%

94%

80%

98%

83%

D_MAX2

PGOOD, OVP

Overvoltage threshold (OVP

threshold)

V_OVTH-RISING

V_OVTH-FALLING

V_OVTH-DLY

VOUT rising (referenced to V_OUT-REG

)

108.5%

100.5%

110% 113.5%

103% 105.5%

30

Overvoltage threshold (OVP

threshold)

VOUT falling (referenced to V_OUT-REG

)

Delay before entering bypass

mode

us

Undervoltage threshold (PGOOD

threshold)

V_UVTH-RISING

V_UVTH-FALLING

VOUT rising (referenced to V_OUT-REG

)

91.5%

89.5%

94%

92%

98%

Undervoltage threshold (PGOOD

threshold)

VOUT falling (referenced to V_OUT-REG

)

95.5%

UV comparator deglitch filter

PGOOD pull-down switch R_DSON

Minimum BIAS for valid PGOOD

Rising edge

Falling edge

26

21

90

µs

R_PGOOD

180

2.5

Ω

V

MOSFET DRIVER

High-state voltage drop (HO

driver)

100mA sinking

100mA sourcing

100mA sinking

0.08

0.04

0.08

0.15

0.1

V

Low-state voltage drop (HO

driver)

High-state voltage drop (LO

driver)

0.17

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6.5 Electrical Characteristics (continued)

Typical values correspond to T_J= 25 °C. Minimum and maximum limits apply over T_J= -40 °C to 125 °C. Unless otherwise

stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, , R_VREF= 65 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.1

UNIT

Low-state voltage drop (LO

driver)

100mA sourcing

0.04

V

V_HB-UVLO

t_DHL

HB-SW UVLO threshold

HO off to LO on deadtime

LO off to HO on deadtime

HB diode resistance

HB-SW falling

2.2

2.5

20

22

1.2

55

3.0

V

ns

t_DLH

Ω

I_CP

HB charge pump current

BIAS=3.8V

30

µA

THERMAL SHUTDOWN

T_TSD-RISINGThermal shutdown threshold

T_TSD-HYSThermal shutdown hysteresis

Temperature rising

175

15

°C

10

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6.6 Typical Characteristics

2600

2400

2200

2000

1800

1600

1400

1200

1000

800

2.42

2.38

2.34

2.3

2.26

2.22

2.18

2.14

2.1

600

2.06

2.02

1.98

400

200

0

5 6 7 8 10

20

30 40 50 70 100

RT Resistor (k)

200 300

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-1. Frequency vs RT Resistance

图6-2. RT Frequency vs Temperature

(RT = 9.09 kΩ, f _SW= 2.2 MHz)

115

112

109

106

103

100

97

4

3.5

3

94

2.5

2

91

88

85

-40 -20

0

20

40

60

80 100 120 140 160

0

5

10

15

20

V_BIAS(V)

25

30

35

40

45

Temperature (°C)

图6-3. RT Frequency vs Temperature

(RT = 220 kΩ, f _SW= 100 kHz)

图6-4. V_BIASvs I_BIAS(shutdown mode)

1120

225

200

175

150

125

100

75

1100

1080

1060

1040

1020

1000

980

50

960

940

25

920

0

5

10

15

20 25

V_BIAS(V)

30

35

40

45

0

5

10

15

20 25

V_VOUT(V)

30

35

40

45

图6-5. V_BIASvs I_BIAS(active mode)

图6-6. Bypass DEM

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400

350

300

250

200

150

100

50

6

5

4

3

2

1

0

5

10

15

20 25

V_VOUT(V)

30

35

40

45

0

2

4

6

8

10

12

图6-7. V_VOUTvs I_VOUT(bypass mode)

V_BIAS(V)

图6-8. V_BIASvs V_VCC

5.5

5

66

64

62

60

58

56

54

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

20

40

60

80

100 120 140 160 180

0

5

10

15

20

V_CSP(V)

25

30

35

40

I_VCC(mA)

图6-9. V_VCCvs I_VCC

图6-10. Peak current limit threshold V_CLTHvs V_CSP

65

66

65

64

63

62

61

60

59

58

57

56

55

54

64

63

62

61

60

59

58

57

56

55

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-11. Peak current limit threshold V_CLTHvs

Temperature, V_CSP= 3 V

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (C)

图6-12. Bypass forward current threshold, V_CS-FWD

vs Temperature , V_CSP= 3 V

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120

110

100

90

120

119

118

117

116

115

114

113

112

111

110

80

70

60

50

40

30

20

10

0

5

10

15

20

V_CSP(V)

25

30

35

40

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (°C)

图6-13. I_CSPvs V_CSP(active mode)

图6-14. I_CSPvs temperature (active mode)

V_CSP= 3 V

1.01

1.008

1.006

1.004

1.002

1

3.5

Pull-up

Pull-down

3

2.5

2

0.998

0.996

0.994

0.992

0.99

1.5

1

0.5

-40 -20

0

20

40

60

80 100 120 140 160

3.8

4

4.2

4.4

4.6

4.8

5

Temperature (°C)

V_VCC(V)

图6-15. V_REFvs Temperature

图6-16. V_VCCvs Peak Driver Current

图6-17. DMAX vs Switching Frequency

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7 Detailed Description

7.1 Overview

The LM51231-Q1 device is a wide input range synchronous boost controller that employs peak current mode

control. The output voltage can be dynamically programmed by using the tracking function on the TRK pin.

Bypass mode operation is automatically entered when the supply voltage is greater than the boost output

regulation target. Bypass mode eliminates the need for an external bypass switch, by driving the high-side

MOSFET at 100% duty cycle, decreasing the power dissipation by eliminating the high-side body diode voltage

drop.

The device's wide input range supports automotive cold-crank and load dump. The minimum input voltage can

be as low as 0.8 V when BIAS is equal to or greater than 3.8 V. The switching frequency is dynamically

programmed with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes AM band

interference and allows for a small solution size and fast transient response. Controller architecture simplifies

thermal management at harsh ambient temperature conditions when compared to converter architectures.

The device has built-in protection features such as peak current limit, which is constant over input voltage,

overvoltage protection, and thermal shutdown. External clock synchronization, programmable spread spectrum

modulation, and a lead-less package with minimal parasitic, help reduce EMI and avoid cross talk. Additional

features include line UVLO, FPWM, diode emulation, DCR inductor current sensing, programmable soft start,

and a power-good indicator.

7.2 Functional Block Diagram

V_LOAD

Forward Current

Comparator

VOUT/SENSE

VREF / RANGE

1V

VCC_EN

V_CS

+

CP

HB

C_OUT

R_LOAD

V_ZCDTH

VCC

BIAS

ZCD

Comparator

VOUT

V_CS-FWD

–

C_VREF

RANGE

+

R_VREFT

R_VREFB

TRK

HO

Q

S

R

Q_H

BYP

OV

+

–

Reference

generator

–

SW

ZCD

SW

VCC

ZCD

Q

FB

V_SUPPLY

BYP

AGND

Peak

PWM

Comparator

450mV

L_M

C_IN

R_S

–

+

–

V_CS

LO

Q

S

Q_L

I_SS

PGND

Q

R

Peak C/L

Comparator

+

690 mV

SS

CLK

C_ss

CSN

–

V_CS

COMP

A_CS

V_CS

CSP

V_CLTH

+

–

25us

Delay

V_SUPPLY

UV

OV

R_COMP

V_UVTH

PGOOD

+

–

+

–

BIAS

V_EN

VCC

Regulator

VCC

C_COMP

FB

4-cycle

Delay

–

+

VCC

UVLO

CLK,

D_MAX

VCC_EN

V_OVTH

R_UVLOT

VCC_OK

–

+

MODE

Ready

EN/UVLO

I_UVLO-HYS

SYNC /

DITHER

Selector

V_UVLO

R_UVLOB

Clock

Generator

FPWM

DE

Switching Mode

Selector

TSD

SYNC/DITHER/VH

RT

7.3 Feature Description

备注

Read through 节 7.4 before reading the feature description of the device. It is recommended to

understand which device functional modes and what type of light load switching modes are supported

by the device.

The parameters or thresholds values mentioned in this section are reference values unless otherwise

specified. Refer to the 节6.5 to find the minimum, maximum, and typical values.

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7.3.1 Device Enable/Disable (EN, VH Pin)

The device shuts down when EN is less than the EN threshold (V_EN) and VH is less than the SYNC threshold

(V_SYNC). The device is enabled when EN is greater than V_ENor VH is greater than V_SYNC. The VH pin provides a

40-μs internal delay before the device shuts down.

The device provides a 33-kΩinternal EN pulldown resistor to prevent a false turnon when the pin is floating. The

EN pulldown resistor is connected to ground during the device configuration time or when the device shuts

down. If the device configuration is finished and VH is greater than V_SYNC, EN hysteresis is accomplished by

disconnecting/connecting the resistor when EN is greater/less than V_EN

.

V_SUPPLY

≥

VCC V_VCC-UVLO

R_UVLOT

R_UVLOS

EN/UVLO

œ

Ready

to start

V_UVLO

I_UVLO-HYS

R_UVLOB

+

C_UVLO

TSD

PD

Configuration

+

Enable

VCC

V_EN

œ

33 kꢀ

PD

≥

VH

V_SYNC

Configuration

图7-1. EN/UVLO Circuit

7.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)

The device features a high voltage 5-V VCC regulator which is sourced from the BIAS pin. The internal VCC

regulator turns on 50 μs after the device is enabled, and 120 μs device configuration starts when VCC is above

VCC UVLO threshold (V_VCC-UVLO). The device configuration is reset when the device shuts down or VCC falls

down below V_{VCC-UVLO-FALLING}. The preferred way to reconfigure the device is to shut down the device. During

configuration time, the VOUT range is selected.

The high voltage VCC regulator allows the connection of the BIAS pin directly to supply voltages from 3.8 V to

42 V. When BIAS is less than the 5-V VCC regulation target (V_VCC-REG), the VCC output tracks the BIAS pin

voltage with a small dropout voltage which is caused by 1.7-Ωresistance of the VCC regulator.

The recommended VCC capacitor value is 4.7 μF. The VCC capacitor should be populated between VCC and

PGND as close to the device. The recommended BIAS capacitor value is 1.0 μF. The BIAS capacitor must be

populated between BIAS and PGND close to the device.

BIAS

VCC

1.0 …F

4.7 …F

5-V VCC

Regulator

图7-2. High Voltage VCC Regulator

The VCC regulator features a VCC current limit function that prevents device damage when the VCC pin is

shorted to ground accidentally. The minimum sourcing capability of the VCC regulator is 100 mA (I_VCC-CL) during

either the device configuration time or active mode operation. The minimum sourcing capability of the VCC

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regulator is reduced to 1 mA when EN/UVLO is less than V_ENand VH is greater than V_SYNC. The VCC regulator

supplies the internal drivers and other internal circuits. The external MOSFETs must be carefully selected to

make the driver current consumption less than I_VCC-CL. The driver current consumption can be calculated in 方程

式1.

I_G= 2 × Q_G@5V× f_SW

(1)

where

• Q_G@5Vis the N-channel MOSFET gate charge at 5 V gate-source voltage

If VIN operation below 3.8 V is required, the BIAS pin can be connected to the output of the boost converter

(V_LOAD). By connecting the BIAS pin to V_LOAD, the boost converter input voltage (V_SUPPLY) can drop down to 0.8

V if the BIAS pin is greater than 3.8 V. See 节7.3.17 for more detailed information about the minimum V_SUPPLY

.

7.3.3 Light Load Switching Mode Selection (MODE Pin)

The light load switching mode is selected based on the state of the MODE pin. If the MODE pin voltage is less

than 0.4 V (V_MODE-FALLING) or floating, the device is configured to diode emulation (DE) mode. If the MODE pin

voltage is greater than 2.0 V (V_MODE-RISING) or connected to VCC, the device is configured to forced PWM

(FPWM) mode. The light load switching mode can be dynamically changed between DE and FPWM mode

during operation. If the MODE pin is left floating the default light load switching mode is DE mode.

Closed during

con gura on

MODE

FPWM

MODE

Selector

DE

Closed during

con gura on

图7-3. MODE Selection Circuit

7.3.4 VOUT Range Selection (RANGE Pin)

The programmable V_OUTrange is selected during the device configuration and it cannot be changed until you

reconfigure the device. Lower V_OUTrange (5 V to 20 V) is selected if the resistance from VREF to AGND

(R_VREFT+ R_VREFB) is in the range of 75 kΩ to 100 kΩ during the device configuration. Upper V_OUTrange (15 V

to 57 V) is selected if the resistance from VREF to AGND is in the range of 20 kΩ to 35 kΩ during the device

configuration. The accuracy of the V_OUTregulation is within the selected range.

7.3.5 Line Undervoltage Lockout (UVLO Pin)

When UVLO is greater than the UVLO threshold (V_UVLO), the device enters active mode if the device

configuration is finished. UVLO hysteresis is accomplished with an internal 25-mV voltage hysteresis (V_UVLO-HYS

)

at the UVLO pin, and an additional 10-μA current sink (I_UVLO-HYS) that is switched on or off. When the UVLO pin

voltage exceeds V_UVLO, the current sink is disabled to quickly raise the voltage at the UVLO pin. When the

UVLO pin voltage falls below V_UVLOor during the device configuration time, the current sink is enabled, causing

the voltage at the UVLO pin to fall quickly.

The external UVLO resistor voltage divider (R_UVLOT, R_UVLOB) must be designed so that the voltage at the UVLO

pin is greater than V_UVLOwhen V_SUPPLYis in the desired operating range. The values of R_UVLOTand R_UVLOBcan

be calculated as follows.

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V

UVLO_RISING

V

−

× V

SUPPLY_OFF

SUPPLY_ON

V

UVLO_FALLING

R

=

(2)

(3)

UVLOT

I

UVLO_HYS

V

× R

UVLO_FALLING

UVLOT

UVLOB

V

− V

SUPPLY_OFF

UVLO_FALLING

A UVLO capacitor (C_UVLO) is required in case V_SUPPLYdrops below V_SUPPLY-OFFmomentarily during the start-up

or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an additional

series UVLO resistor (R_UVLOS) can be used to quickly raise the voltage at the UVLO pin when I_UVLO-HYSis

disabled.

The UVLO pin can be connected to the BIAS pin if not used. Drive the UVLO pin through a minimum of a 5-kΩ

resistor if the BIAS pin voltage is less than the UVLO pin voltage in any conditions.

7.3.6 Fast Restart using VCC HOLD (VH Pin)

After the device configuration, a fast restart can be achieved without reconfiguration by toggling EN/UVLO when

VH is greater than V_SYNC. The device stops switching, but keeps the VCC regulator active when EN is less than

V_ENand VH is greater than V_SYNC(See 图7-5).

3.8 V

BIAS

V_UVLO

V_EN

UVLO/

EN

V_VCC-UVLO

120-µs (Typ.)

configuration

time

120-µs (Typ.)

configuration

time

VCC

SS

V_TRK

50-µs (Typ.)

internal start-up delay

LO

x V_TRK

V_LOAD

SS =

V_LOAD(TARGET)

V_LOAD

图7-4. Boost Start-up Waveforms Case 1: Start-up by EN/UVLO, Restart when VH < V_SYNC

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3.8 V

BIAS

V_UVLO

V_EN

UVLO/

EN

V_VCC-UVLO

120-µs (Typ.)

configuration

time

VCC

SS

V_TRK

50-µs (Typ.)

internal start-up delay

LO

V_LOADx V_TRK

SS =

V_LOAD(TARGET)

V_LOAD

图7-5. Boost Start-up Waveforms Case 2: Start-up by EN/UVLO, Restart when VH > V_SYNC

7.3.7 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)

The V_OUTregulation target (V_OUT-REG) is adjustable by programming the TRK pin voltage which is the reference

of the internal error amplifier. The accuracy of V_OUT-REGis ensured when the TRK voltage is between 0.25 V and

1.0 V. If the V_OUTregulation set point is set outside of the V_OUTrange selection, V_OUTis still regulated. The high

impedance TRK pin allows users to program the pin voltage directly by a D/A converter or by connecting to a

resistor voltage divider (R_VREFT, R_VREFB) between VREF and AGND. See 图7-6.

The device provides a 1-V voltage reference (V_REF) which can be used to program the TRK pin voltage through

a resistor voltage divider. It is not recommended to use V_REFas a reference voltage of an external circuit. For

stability reasons the VREF capacitor (C_VREF) should be between 330 pF and 1 nF, 470 pF are recommended.

When R_VREFTand R_VREFBare used to program the TRK pin voltage, V_OUT-REGcan be calculated as follows.

Lower VOUT Range

20 × R

VREFB

V

=

(4)

(5)

OUT_REG

R

+ R

VREFT

VREFB

Upper VOUT Range

60 × R

VREFB

V

=

R

OUT_REG

+ R

VREFB

VREFT

The TRK pin voltage can be dynamically programmed in active mode, which makes an envelope tracking power

supply design easy. When designing a tracking power supply, it is required to adjust the TRK pin voltage slow

enough so that the VOUT pin voltage can track the command and the internal overvoltage or undervoltage

comparator is not triggered during the transient operation. It is recommended to use an RC filter at the TRK pin

to slow down the slew rate of the command signal at the TRK pin, especially when a step input is applied. When

a trapezoidal or sinusoidal input is applied, it is recommended to limit the slew rate or the frequency of the

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command signal. Bypass mode, OVP and PGOOD functions are based on the TRK pin voltage, see 节 7.4.1.4,

节7.3.8, 节7.3.9 respectively.

VREF

C_VREF

R_VREF

R_VREFT

R_VREFB

TRK

R_FTRK

TRK

AGND

C_FTRK

(b)

(a)

图7-6. TRK Control (a) using VREF (b) by External Step Input

7.3.8 Overvoltage Protection (VOUT Pin)

The device provides an overvoltage protection (OVP) for boost converter output. The OVP comparator monitors

the VOUT pin through an internal resistor voltage resistors. If the VOUT pin voltage rises above the overvoltage

threshold (V_OVTH), OVP is activated. When OVP is triggered, the device turns off the low-side driver and turns on

the high-side driver until zero current is detected in diode emulation. In FPWM mode, the low-side driver is not

turned off when the OVP is triggered.

After at least 30 μs (V_OVTH-DLY) in OVP status, the device enters the OVP condition. The recommended

capacitor from the VOUT pin to PGND (C_VOUT) is 0.1 μF.

7.3.9 Power Good Indicator (PGOOD Pin)

The device provides a power-good indicator (PGOOD) to simplify sequencing and supervision. PGOOD is an

open-drain output and a pullup resistor between 5 kΩ and 100 kΩ can be externally connected. The PGOOD

switch opens when the VOUT pin voltage is greater than the undervoltage threshold (V_UVTH). The PGOOD pin is

pulled down to ground when the VOUT pin voltage is less than V_UVTH, UVLO is less than V_UVLO, VCC is less

than V_VCC-UVLO, or during thermal shutdown. A 26-μs rising and 21-μs falling deglitch filter prevents any false

pulldown of the PGOOD due to transients. The PGOOD pin voltage cannot be greater than V_VOUT+ 0.3 V

26 us Delay

21 us Delay

V_UVTH

PGOOD

+

–

+

–

UV

FB

4-cycle

Delay

V_OVTH

OV

图7-7. PGOOD Indicator

7.3.10 Dynamically Programmable Switching Frequency (RT)

The switching frequency of the device is set by a single RT resistor connected between RT and AGND if no

external synchronization clock is applied to the SYNC pin. The resistor value to set the RT switching frequency

(R_T) is calculated as follows.

10

2 . 21 × 10

R =

− 955

(6)

T

f

RT typical

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The RT pin is regulated to 0.5 V by an internal RT regulator when the device is in active mode or during the

device configuration. The switching frequency can be dynamically programmed during operation as shown in 图

7-8.

RT

Higher F_SW

图7-8. Frequency Hopping Example

7.3.11 External Clock Synchronization (SYNC Pin)

The switching frequency of the device can be synchronized to an external clock by directly applying an external

pulse signal to the SYNC pin. The internal clock is synchronized at the rising edge of the external

synchronization pulse using an internal PLL. Connect the SYNC pin to ground if not used.

The external synchronization pulse must be greater than V_SYNCin the high logic state and must be less than

V_SYNCin the low logic state. The duty cycle of the external synchronization pulse is not limited, but the minimum

on-pulse and the minimum off-pulse widths must be greater than 100 ns. The frequency of the external

synchronization pulse must satisfy the following two inequalities.

(7)

0.75ì f_RT(typical)Ç f_SYNCÇ 1.5ì f_RT(typical)

(8)

For example, an RT resistor is required for typical 350-kHz switching to cover from 263-kHz to 525-kHz clock

synchronization without changing the RT resistor.

R_SYNC

SYNC

SYNC rising threshold

SYNC falling threshold

SYNC

2 cycles

SYNC exit delay

7 cycles

PLL enable delay

~150us

PLL lock time

Clock

Synchronized

RT programmed

switching

RT programmed

switching

图7-9. External Clock Synchronization

Drive the SYNC pin through a minimum 1-kΩ resistor if the BIAS pin voltage is less than the SYNC pin voltage

in any conditions.

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7.3.12 Programmable Spread Spectrum (DITHER Pin)

The device provides an optional programmable spread spectrum (clock dithering) function that is activated by

connecting a capacitor between DITHER and AGND. A triangular waveform centered at 1.0 V is generated

across the dither capacitor. This triangular waveform modulates the oscillator frequency by –6% to +5% of the

frequency set by the RT resistor. The dither capacitance value sets the rate of the low frequency modulation.

DITHER

C_DITHER

I_DITHER= -20uA

1.0V +7.0%

1.0V -7.0%

I_DITHER= 20uA

Dither disable threshold

T_MOD= 1 / f_MOD

DITHER

RT programmed

switching

Clock dithering

RT programmed

switching

图7-10. Switching Frequency Dithering

For the dithering circuit to effectively reduce peak EMI, the modulation frequency must be much less than the RT

switching frequency. The dither capacitance which is required for a given modulation frequency (f_MOD), can be

calculated from 方程式9. Setting the f_MODto 9 kHz or 10 kHz is a good starting point.

20μA

C

=

(9)

DITHER

f

× 0 . 29

MOD

Connecting DITHER to AGND deactivates clock dithering, and the internal oscillator operates at a fixed

frequency set by the RT resistor. Clock dithering is also disabled when an external synchronization pulse is

applied.

DITHER

No Dither

图7-11. Dynamic Dither On/Off Example

7.3.13 Programmable Soft-start (SS Pin)

The soft-start feature helps the converter gradually reach the steady state operating point. To reduce start-up

stresses and surges, the device regulates the error amplifier reference to the SS pin voltage or the TRK pin

voltage (V_TRK), whichever is lower.

The internal 20-μA soft-start (I_SS) current turns on 120 μs after the VCC pin crosses V_VCC-UVLO. I_SSgradually

increases the voltage on an external soft-start capacitor (C_SS). This results in a gradual rise of the output

voltage.

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In FPWM mode, the device forces diode emulation while the SS pin voltage is less than 1.5 V. When the SS pin

voltage is greater than 1.5 V, the device changes the high-side negative current limit threshold from V_ZCD-DEto

V_I-HS-NEG

.

VCC

UVLO

I_SS=20uA

VCC

1.5V

V_TRK

SS

Transient period

120us

delay

Forced Diode

Emulation

图7-12. Soft Start and Smooth Transition to FPWM

In boost topology, the soft-start time (t_SS) varies with the input supply voltage because the boost output voltage is

equal to the boost input voltage at the beginning of the soft-start switching. t_SSin boost topology is calculated in

方程式10.

C

V

SUPPLY

SS

t

= V

×

× 1 −

(10)

SS

TRK

20μA

V

LOAD

In general, it is recommended to choose a soft-start time long enough so that the converter can start up without

going into an overcurrent state. If the device is used for a pre-boost in automotive application, it is recommended

to use 100-pF C_SSto reach steady state as soon as possible.

The device also features an internal SS-to-FB clamp (V_SS-FB), which clamps SS 55 mV above FB and is

activated if 256 consecutive switching cycles occur with current limit. The SS-to-FB clamp is deactivated if 32

consecutive switching cycles occur without exceeding the current limit threshold. This clamp helps to minimize

surges after output shorts or over load situations. The device can enter deep sleep mode when SS is greater

than 1.5 V. It is not recommended to pulldown SS to stop switching.

7.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)

The device includes an internal feedback resistor voltage divider. The internal feedback resistor voltage divider is

connected to the negative input of the internal transconductance error amplifier, and the TRK pin voltage

programs the positive input of the internal transconductance error amplifier after the soft start is finished. The

internal transconductance error amplifier features high output resistance (R_O= 10 MΩ) and wide bandwidth (BW

= 3 MHz) and sinks (or sources) current which is proportional to the difference between the negative and the

positive inputs of the error amplifier.

The output of the error amplifier is connected to the COMP pin, allowing the use of a Type-2 loop compensation

network. R_COMP, C_COMP, and an optional C_HFloop compensation components configure the error amplifier gain

and phase characteristics to achieve a stable loop response. This compensation network creates a pole at very

low frequency, a mid-band zero, and a high frequency pole.

The PWM comparator in 图 7-13 compares the sum of the amplified sensed inductor current and the slope

compensation ramp with the sum of the COMP pin voltage and a –690 mV internal offset, and terminates the

present cycle if the sum of the amplified sensed inductor current and the slope compensation ramp is greater

than the sum of the COMP pin voltage and the –690 mV internal offset.

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V_SUPPLY

R_S

CSN

CSP

V_SLOPE

–

+

VCC_EN

VREF

Gain=10

1V

VOUT

C_VREF

R_VREFT

R_VREFB

+

TRK

+

–

Reference

generator

–

PWM

Comparator

FB

0.65V

DC offset

AGND

Bypass

Mode

I_SS

SS

COMP

C_ss

R_COMP

C_COMP

C_HF

(optional)

图7-13. Error Amplifier, Current Sense Amplifier and PWM

7.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)

The device features a current sense amplifier with an effective gain of 10 (A_CS), and provides an internal slope

compensation ramp to the PWM comparator to prevent a subharmonic oscillation at high duty cycle. The device

generates the 45-mV peak slope compensation ramp (V_SLOPE) at the input of the current sense amplifier which is

0.45-V peak (at 100% duty cycle) slope compensation ramp at the PWM comparator input.

According to peak current mode control theory, the slope of the slope compensation ramp must be greater than

at least half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle.

Therefore, the minimum amount of the slope compensation must satisfy 方程式11.

0.5 × (V_LOAD- V_SUPPLY) / L_M× R_S× Margin < V_SLOPE× f_SW(in Boost)

(11)

where

• 1.5-1.7 is recommended as the Margin to cover non-ideal factors.

V

V_COMP

0.65V offset

Internal Slope

Compensation

0.45V x D

Sensed Inductor

Current (10 x Rs x I_LM

)

图7-14. PWM Comparator Input

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7.3.16 Constant Peak Current Limit (CSP, CSN Pin)

When the CSP-CSN voltage exceeds the 60-mV cycle-by-cycle current limit threshold (V_CLTH), the current limit

comparator immediately terminates the LO output. The device provides an constant peak current limit whose

peak inductor current limit is constant over the input and output voltage. For the case where the inductor current

can overshoot, such as inductor saturation, the current limit comparator skips pulses until the current has

decayed below the current limit threshold.

V_SUPPLY

R_S

CSN

CSP

Gain=10

CS Amplifier

+

œ

0.6V

Current Limit

Comparator

图7-15. Current Limit Comparator

Cycle-by-cycle peak current limit is calculated as follows:

0.06

R_S

I_PEAK-CL

=

(12)

V

Current Limit = 0.6V

Sensed Inductor

Current (10 x Rs x I_LM

)

图7-16. Current Limit Comparator Input

Boost converters have a natural pass-through path from the supply to the load through the high-side MOSFET

body diode. Due to this path, boost converters cannot provide the peak current limit protection when the output

voltage is close to or less than the input supply voltage, especially the peak current limit protection that does not

work during the minimum on-time (t_ON-MIN).

7.3.17 Maximum Duty Cycle and Minimum Controllable On-time Limits

The device provides the maximum duty cycle limit (D_MAX) / minimum off-time to cover the non-ideal factors

caused by resistive elements. D_MAXdecides the minimum input supply voltage (V_SUPPLY(MIN)) which can achieve

the target output voltage (V_LOAD) during CCM operation, but V_SUPPLY(MIN)which can achieve the target output

voltage during DCM operation is not limited by D_MAX. V_SUPPLY(MIN), which can achieve the target output voltage

during CCM operation, can be estimated as follows.

V

_SUPPLY(MIN)≈V_LOAD× (1 - D_MAX) + I_SUPPLY(MAX)× (R_DCR+ R_S+ R_DS(ON)

)

(13)

where

• I_SUPPLY(MAX)is the maximum input current at V_SUPPLY(MIN)

• R_DCRis the DC resistance of the inductor

• R_DS(ON)is the on resistance of the MOSFET

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90

80

75

0.1

2.2

Switching Frequency (MHz)

图7-17. Switching Frequency vs max. Duty Cycle

At very light load condition or when V_SUPPLYis close to V_OUT-REG, the device skips the low-side driver pulses if

the required on-time is less than t_ON-MIN. This pulse skipping appears as a random behavior. If V_SUPPLYis further

increased to the voltage higher than V_OUT-REG, the required on-time becomes zero and eventually the device can

start bypass operation which turns on the high-side driver 100% when the VOUT pin voltage is greater than

V_OVTH

.

7.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)

The device provides N-channel logic MOSFET drivers, which can source a peak current of 2.2 A and sink a peak

current of 3.3 A. The LO driver is powered by VCC, and is enabled when EN is greater than V_ENand VCC is

greater than V_VCC-UVLO. The HO driver is powered by HB, and is enabled when EN is greater than V_ENand HB-

SW voltage is greater than HB UVLO threshold (V_HB-UVLO).

When the SW pin voltage is approximately 0 V by turning on the low-side MOSFET, the C_HBis charged from

VCC through the internal boot diode. The recommended value of the C_HBis 0.1 μF.

The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs

are not turned on at the same time. When the device commands LO to be turned on, the adaptive dead-time

logic first turns off HO and waits for HO-SW voltage to drop. LO is then turned on after a small delay (t_DHL).

Similarly, the HO driver turn-on is delayed until the LO-PGND voltage has discharged. HO is then turned on after

a small delay (t_DLH).

If the BIAS pin voltage is below the 5-V VCC regulation target, take extra care when selecting the MOSFETs.

The gate plateau voltage of the MOSFET switch must be less than the BIAS pin voltage to completely enhance

the MOSFET, especially during start-up at low BIAS pin voltage. If the driver output voltage is lower than the

MOSFET gate plateau voltage during start-up, the converter may not start up properly and it can stick at the

maximum duty cycle in a high-power dissipation state. This condition can be avoided by selecting a lower

threshold MOSFET or by turning on the device when the BIAS pin voltage is sufficient. Care should be taken

when the converter operates in bypass at any conditions. During the bypass operation, the minimum HO-SW

voltage is 3.75 V.

VCC

D_HB

Qpump

HB

ZCD

Delay

HO

SW

Level

Shifter

Adaptive

Deadtime

VCC

PWM

Delay

LO

PGND

图7-18. Driver Structure with Internal Boot Diode

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The hiccup mode fault protection is triggered by the HB UVLO. If the HB-SW voltage is less than the HB UVLO

threshold (V_HB-UVLO), the LO turns on by force for 75 ns to replenish the boost capacitor. The device allows up to

four consecutive replenish switching. After the maximum four consecutive boot replenish switching, the device

skips switching for 12 cycles. If the device fails to replenish the boost capacitor after the four sets of the four

consecutive replenish switching, the device stops switching and enters 512 cycles of hiccup mode off-time.

During the hiccup mode off-time, PGOOD and SS are grounded.

If required, the slew rate of the switching node voltage can be adjusted by adding a gate resistor in parallel with

pulldown PNP transistor. Extra care should be taken when adding the gate resistor since it can decrease the

effective dead-time.

R_GL

LO

Q_GL

PGND

图7-19. Slew Rate Control

7.3.19 Thermal Shutdown Protection

An internal thermal shutdown (TSD) is provided to protect the device if the junction temperature (T_J) exceeds

175°C. When TSD is activated, the device is forced into a low-power thermal shutdown state with the MOSFET

drivers and the VCC regulator disabled. After the T_Jis reduced (typical hysteresis is 15⁰C), the device restarts.

7.4 Device Functional Modes

7.4.1 Device Status

7.4.1.1 Shutdown Mode

When EN is less than V_ENand VH is less than V_SYNC, the device shuts down, consuming 3 μA from BIAS. In

shutdown mode, COMP, SS, and PGOOD are grounded. The device is enabled when EN is greater than V_ENor

VH is greater than V_SYNC

.

7.4.1.2 Configuration Mode

When the device is enabled initially, the 120-μs device configuration starts if VCC is greater than V_VCC-UVLO

.

During device configuration, the VOUT range is selected. The device configuration is reset when the device

shuts down or VCC falls down below 2.2 V. The preferred way to reconfigure the device is to shut down the

device. During the configuration time, a 33-kΩinternal EN pulldown resistor is connected, the minimum sourcing

capability of the VCC regulator is 100 mA and the RT pin is regulated to 0.5 V by the internal RT regulator.

7.4.1.3 Active Mode

After the 120-μs initial device configuration is finished, the device enters active mode with all functions enabled

if UVLO is greater than V_UVLO. In active mode, a soft-start sequence starts and the error amplifier is enabled.

7.4.1.4 Bypass Mode

Boost converters have a natural pass-through path from the supply to the load through the high-side MOSFET

body diode when the supply voltage is greater than the target load voltage. During this operating condition, the

high-side MOSFET dissipates power due to the forward voltage drop of the body diode. To reduce the power

dissipation the high-side MOSFET (HO) is driven at 100% duty cycle and V_LOADis approximately equal to

V_SUPPLY. This mode of operation is called bypass mode.

The device behaves differently in bypass mode based on the selected light load switching mode operation, the

sensed inductor current, and the input voltage. To enter bypass mode; the OVP status must be triggered for at

least 30 μs (V_OVTH-DLY), see 节 7.3.8 and the voltage between CSP and CSN must be greater than 6 mV

(V_CS-FWD). To exit bypass mode either the OVP status is cleared, or V_SW-SENSEis less than bypass mode zero

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cross threshold. The bypass mode zero cross threshold is dependent on the selected light-load switching mode

operation and detailed in 节7.4.1.4.1 and 节7.4.1.4.2, for DE mode and FPWM respectively.

Bypass Mode

V_LOAD

V_SUPPLY

V_TRK

V_OVTH-falling

V_OVTH-rising

V

_HO- V_SW

V

_LO- PGND

V_CS-FWD

V

_CSP-V_CSN

0 mV

V

_SW-V_SENSE

V_ZCD

图7-20. Bypass mode operation

7.4.1.4.1 Bypass DE mode

In DE mode switching operation, bypass mode is entered when the OVP status is triggered for at least 30 μs

(V_OVTH-DLY), and V_CSP-CSNis greater than 6 mV (V_CS-FWD), indicating positive inductor current. To exit bypass

mode the either the OVP status is cleared or V_SW-SENSEis less than -5 mV (V_ZCD-BYP). V_ZCD-BYPindicates that

current is flowing from V_LOADto V_SUPPLYand the high-side FET is turned off to stop the negative current flow.

Once the high-side FET is turned-off, the device enters active mode. The proper conditions must be achieved to

enter bypass mode again. See 表7-1 for details on how the device enters and exits bypass mode.

表7-1. Bypass Mode: DE mode

Conditions ⁽¹⁾

Enter bypass mode

Exit bypass mode

V_VOUT>V_TRK*K_FB*V_{OVTH_RISING}

AND

V_CSP-CSN> V_CS-FWD

V_VOUT< V_TRK*K_FB*V_{OVTH_FALLING}

OR

V_SW-SENSE< V_ZCD-BYP

(1) K_FBis either 20 or 60 depending on the selected output voltage range. See section 节7.3.7

7.4.1.4.2 Bypass FPWM

In FPWM switching operation, the device enters bypass mode when the OVP status is triggered for at least 30

μs (V_OVTH-DLY) and V_CSP-CSNis greater than 6 mV (V_CS-FWD), indicating positive inductor current. To exit bypass

mode the either the OVP status is cleared or V_SW-SENSEis less than -150 mV (V_I-NEG-BYP). Current flow from

V_LOADto V_SUPPLYcan occur in bypass mode while operating in FPWM. Once the high-side FET is disabled, the

device enters active mode. The proper conditions must be achieved to enter bypass mode again. See 表 7-2 for

details on how the device enters and exits bypass mode.

表7-2. Bypass Mode: FPWM

Conditions ⁽¹⁾

Enter bypass mode

V_VOUT>V_TRK*K_FB*V_{OVTH_RISING}

AND

V_CSP-CSN> V_CS-FWD

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表7-2. Bypass Mode: FPWM (continued)

Conditions ⁽¹⁾

Exit bypass mode

V_VOUT< V_TRK*K_FB*V_{OVTH_FALLING}

OR

V_SW-SENSE< V_I-NEG-BYP

(1) K_FBis either 20 or 60 depending on the selected output voltage range. See section 节7.3.7

7.4.2 Light Load Switching Mode

The device provides two light load switching modes. Inductor current waveforms in each mode are different at

the light/no load condition.

Inductor

Inductor current coducts continuously.

Current

Negative current flow is allowed.

0A

(a)

Inductor

Current

Random pulse skip

when the required t_ON

is less than t_ON-MIN

Random pulse skip

when the required t_ON

is less than t_ON-MIN

0A

(b)

图7-21. Inductor Current Waveform at Light Load (a) FPWM (b) Diode Emulation

7.4.2.1 Forced PWM (FPWM) Mode

In FPWM mode, the inductor current conducts continuously at light or no load conditions, allowing a continuous

conduction mode (CCM) operation. The benefits of the FPWM mode are a fast light load to heavy load transient

response, and constant switching frequency at light or no load conditions. The maximum reverse current is

limited to 150 mV/R_DS(ON)in FPWM mode.

7.4.2.2 Diode Emulation (DE) Mode

In diode emulation (DE) mode, inductor current flow is allowed only in one direction - from the input source to the

output load. The device monitors the SW-SENSE voltage during the high-side switch on-time and turns off the

high-side switch for the remainder of the PWM cycle when the SW-SENSE voltage falls down below the 5-mV

zero current detection (ZCD) threshold (V_ZCD). The benefit of the diode emulation is a higher efficiency than

FPWM mode efficiency at light load condition.

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SENSE + 5mV

SW

ZCD

HO-SW

LO1

Dead-time

图7-22. Zero Current Detection

7.4.2.3 Forced Diode Emulation Operation in FPWM Mode

During soft start, the device forces diode emulation while the SS pin voltage is less than 1.5 V. When the SS pin

is greater than 1.5 V, the device shifts the zero current detection (ZCD) threshold down to -145 mV. The peak-to-

peak inductor current must satisfy 方程式14 for a proper FPWM operation at no load.

I

× R

DS on

2

PP

< 145mV

(14)

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The device integrates several optional features to meet system design requirements, including input UVLO,

programmable soft start, clock synchronization, spread spectrum, and selectable light load switching mode.

Each application incorporates these features as needed for a more comprehensive design. Refer to the

LM5123EVM-BST user's guide for more information.

8.2 Typical Application

图8-1 shows the typical components to design a boost controller with a variable output voltage.

V_SUPPLY

100 nF

V_LOAD

4.7 µF

BIAS

VCC

RT

VOUT

HB

+

–

SW

R_LOAD

49.9 k

C_OUT

100 nF

330 nF

HO

SW

SS

V_SUPPLY

C_HF

+

–

L_M

R_S

COMP

C_IN

LO

R_COMPC_COMP

MODE

AGND

PGND

CSN

CSP

UVLO

100 k

VCC

V_SUPPLY

100

PGOOD

VREF

100 pF

R_UVLOT

TRK

SYNC/DITHER

R_UVLOB

C_UVLO

24.9 k

470 pF

+

V_TRK

–

图8-1. Typical Synchronous Boost Converter with Optional Components

'

表8-1 provides the selected component values for the results found in 节8.2.4.

表8-1. Component Selection

L_M

R_S

R_COMP

C_COMP

C_HF

C_OUT

C_IN

6.8 nF

47 pF

2.6 μH

1.5 mΩ

54.9 kΩ

450 μF

120 μF

8.2.1 Design Requirements

表 8-2 shows the intended input, output, and performance parameters for this application example. The design

parameters reflect an application that requires a variable output voltage

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表8-2. Design Example Parameters

DESIGN PARAMETER

Minimum input supply voltage (V_SUPPLY(MIN)

Minimum output voltage (V_{LOAD_MAX}

Maximum output voltage (V_{LOAD_MAX}

Maximum output power (P_{OUT_MAX}

Typical switching frequency (f_SW

VALUE

9 V

)

24 V

)

45 V

)

200 W

440 kHz

)

8.2.2 Detailed Design Procedure

Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application.

Refer to the LM5123EVM-BST EVM user guide for recommended components and typical application curves.

8.2.3 Application Ideas

For applications requiring the lowest cost with minimum conduction loss, inductor DC resistance (DCR) can be

used to sense the inductor current rather than using a sense resistor. R_DCRCand C_DCRCmust meet 方程式 15 to

match a time constant.

L_M

R_DCR

V_SUPPLY

C_DCRC

R_DCRC

CSN

CSP

图8-2. DCR Current Sensing

L

M

= R

× C

(15)

DCRC

R

DCR

If required, an additional PGOOD delay can be programmed using an external circuit.

VDD_MCU

PGOOD : Internal 25us pull-down and pull-up delay

PGOOD

VDD_MCU

/RESET (with additional delay)

C_DELAY

图8-3. Additional PGOOD Delay

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8.2.4 Application Curves

The data presented in this section were gathered using theLM5123EVM-BST evaluation module. The LM51231-

Q1 replaced the LM5123-Q1 as the power supply controller.

100

95

90

85

80

75

70

65

60

55

50

100

80

60

40

20

0

18V_EFF

14V_EFF

12V_EFF

10V_EFF

8V_EFF

FPWM MODE

0

1

2

3

4

I_OUT(A)

5

6

7

8

0.001

0.021

0.041

0.061

0.081

0.1

I_OUT(A)

图8-4. Efficiency vs. I_OUT, V_OUT= 24 V (FPWM)

图8-5. Efficiency vs. I_OUT, V_OUT= 24-V Light Load

24.4

24.3

24.2

24.1

24

VIN = 18V

VIN = 14V

VIN = 12V

VIN = 10V

VIN = 8V

23.9

23.8

23.7

23.6

0

1

2

3

4

5

6

7

8

I_OUT(A)

图8-6. 24-V Load Regulation

8.3 System Example

Use the LM51231 in class-H audio applications. The TRK pin can be used to dynamically control the supply of

the audio amplifier.

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V_LOAD

PVDD

VOUT/SENSE

BIAS VCC

MCU VDD

High-side MOSFET can turn

on 100% when supply voltage

is in greater than V_{LOAD_traget}

HB

SYNC/DITHER/VH

PGOOD

HO

SW

Car Battery

V_SUPPLY

TAS6584-Q1

Power Good

indicator to

MCU

RT

SS

LO

GPIO

PGND

COMP

PWM signal

Dynamic headroom control

CSN

MODE

CSP

REF/ RANGE

Enable from MCU

R_VREF

TRK

UVLO/EN AGND

R_FTRK

C_FTRK

图8-7. LM51231 in class-H audio application

Use LM51231 in LED application. The TRK pin can be used to control head-room.

TPS92515 Buck

LED Driver

V_LOAD

TPS92515 Buck

LED Driver

BIAS VCC

VOUT/SENSE

MCU VDD

High-side MOSFET can turn

on 100% when car battery

voltage is in normal range

HB

SYNC/DITHER/VH/QP

PGOOD

HO

SW

Car Battery

V_SUPPLY

RT

SS

Power Good

indicator to

MCU

LO

PGND

COMP

CSN

VCC

MODE

CSP

REF/ RANGE

Enable from MCU

R_VREF

TRK

UVLO/EN AGND

R_FTRK

Dynamic

Headroom

Control

C_FTRK

图8-8. LM51231 in LED application

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To configure non-synchronous boost controller, connect SW to PGND, and connect HB to VCC.

V_LOAD

VOUT

VCC

HB

HO

V_SUPPLY

SW

LO

PGND

CSN

CSP

图8-9. Non-synchronous boost configuration

8.4 Power Supply Recommendations

The device is designed to operate from a power supply or a battery whose voltage range is from 0.8 V to 42 V.

The input power supply must be able to supply the maximum boost supply voltage and handle the maximum

input current at 0.8 V. The impedance of the power supply and battery including cables must be low enough that

an input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required

at the supply input of the converter.

8.5 Layout

8.5.1 Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. The following

guidelines will help users design a PCB with the best power conversion performance, thermal performance, and

minimize generation of unwanted EMI.

• Place C_VCC, C_BIAS, C_HB, and C_VOUTas close to the device. Make direct connections to the pins.

• Place Q_H, Q_L, and C_OUT. Make the switching loop (C_OUTto Q_Hto Q_Lto C_OUT) as small as possible. A small

size ceramic capacitor helps to minimize the loop length. Leave a copper area near the drain connection of

Q_Hfor a thermal dissipation.

• Place L_M, R_S, and C_IN. Make the loop (C_INto R_Sto L_Mto C_IN) as small as possible. A small size ceramic

capacitor helps to minimize the loop length.

• Connect R_Sto CSP-CSN. The CSP-CSN traces must be routed in parallel and surrounded by ground.

• Connect VOUT, HO, and SW. These traces must be routed in parallel using a short, low inductance path.

VOUT must be directly connected the drain connection of Q_H. SW must be directly connected to the source

connection of Q_H

• Connect LO and PGND. The LO-PGND traces must be routed in parallel using a short, low inductance path.

PGND must be directly connected the source connection of Q_L

• Place R_COMP, C_COMP, C_SS, C_VREF, R_VREFT, R_VREFB, R_T, and R_UVLOBas close to the device, and connect to a

common analog ground plane.

• Connect power ground plane (the source connection of the Q_L) to EP through PGND. Connect the common

analog ground plane to EP through AGND. PGND and AGND must be connected underneath the device.

• Add several vias under EP to help conduct heat away from the device. Connect the vias to a large analog

ground plane on the bottom layer.

• Do not connect C_OUTand C_INgrounds underneath the device and through the large analog ground plane

which is connected to EP.

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9 Device and Documentation Support

9.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RGR 20

3.5 x 3.5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4228482/A

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PACKAGE OUTLINE

RGR0020C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.65

3.35

A

B

3.65

3.35

PIN 1 INDEX AREA

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 2

(0.2) TYP

SYMM

6

10

EXPOSED

THERMAL PAD

5

11

A

(0.16)

TYP

SYMM

21

2X 2

2.05 0.1

0.30

16X 0.5

1

15

20X

0.18

PIN 1 ID

20

16

0.1

C A B

0.05

0.5

0.3

20X

4225699/B 05/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RGR0020C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.05)

SYMM

16

SEE SOLDER MASK

DETAIL

20

20X (0.6)

15

20X (0.24)

16X (0.5)

1

(2.05)

SYMM

21

(3.3)

(0.775)

5

11

(R0.05) TYP

(

0.2) TYP

VIA

6

10

(0.775)

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225699/B 05/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RGR0020C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.56) TYP

16

20

20X (0.6)

1

20X (0.24)

16X (0.5)

15

(0.56) TYP

(3.3)

21

SYMM

4X (0.92)

11

(R0.05) TYP

5

6

10

4X (0.92)

SYMM

(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 21

81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4225699/B 05/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM51231QRGRRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有输出电压跟踪功能的 2.2MHz 宽输入电压同步升压控制器 \| RGR \| 20 \| -40 to 125 控制器
文件：	总42页 (文件大小：2303K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM51231QRGRRQ1 [TI]

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