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LM5141-Q1

SNVSAJ6D –JULY 2016–REVISED DECEMBER 2017

LM5141-Q1 Wide Input Range Synchronous Buck Controller

1 Features

2 Applications

1

•

Qualified for Automotive Applications

•

Automotive Applications Including:

AEC-Q100 Qualified With the Following Results:

–

Infotainment Systems

–

Device Temperature Grade 1: –40°C to

+125°C Ambient Operating Temperature

Instrumentation Clusters

Advanced Driver Assistance Systems (ADAS)

–

Device HBM ESD Classification Level 2

Device CDM ESD Classification Level C4B

3 Description

The LM5141-Q1 is a synchronous buck controller,

intended for high voltage wide V_INstep-down

converter applications. The control method is peak

current mode control. Current mode control provides

inherent line feed-forward, cycle-by-cycle current

limiting, and ease-of-loop compensation. The

LM5141-Q1 features slew rate control to simplify the

compliance with CISPR and automotive EMI

requirements.

•

V_IN: 3.8 V to 65 V (70 V Absolute Maximum)

Output: Fixed 3.3 V, 5 V, or Adjustable From

1.5 V to 15 V with ±0.8% Accuracy

•

Fixed 2.2-MHz or 440-kHz Switching Frequency

with ±5% Accuracy

High-Side and Low-Side Gate Drive With Slew-

Rate Control

Optional Frequency Shift by Varying an Analog

Voltage or RT Resistor

The LM5141-Q1 has two selectable switching

frequencies: 2.2 MHz and 440 kHz. Gate drivers with

slew rate Control that can be adjusted to reduce EMI.

•

Optional Synchronization to an External Clock

Optional Spread Spectrum

In light or no-load conditions, the LM5141-Q1

operates in skip cycle mode for improved low power

efficiency. The LM5141-Q1 has a high voltage bias

regulator with automatic switch-over to an external

bias to reduce the I_Qcurrent from V_IN. Additional

features include frequency synchronization, cycle-by-

cycle current limit, hiccup mode fault protection for

sustained overload, and power good output.

Shutdown Mode I_Q: 10 µA Typical

Low Standby Mode I_Q: 35 µA Typical

75-mV Current Limit Threshold with ±0.9%

Accuracy

•

External Resistor or DCR Current Sensing

Output Enable Logic Input

Hiccup Mode for Sustained Overload

Power-Good Indication Output

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

Selectable Diode Emulation or Forced Pulse-

Width Modulation

LM5141-Q1

VQFN (24)

4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

24-pin VQFN Package With Wettable Flanks

Create a Custom Design Using the LM5141-Q1

With the WEBENCH^®Power Designer

Simplified Schematic

V_IN

C_IN

VIN

VCC

C_VCC

D_BST

C_BST

HB

HO

RES

SS

L_OUT

V_OUT

HOL

SW

R_SENSE

DITH

LM5141-Q1

C_OUT

LO

C_RES

C_SS

C_DITH

LOL

PGND

PG

CS

EN

DEMB

VOUT

VCCX

R_COMPC_COMP

COMP

FB

AGND

RT

OSC VDDA

R_T

C_VDDA

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5141-Q1

SNVSAJ6D –JULY 2016–REVISED DECEMBER 2017

www.ti.com

Table of Contents

7.3 Feature Description................................................. 13

Application and Implementation ........................ 22

8.1 Application Information............................................ 22

8.2 Typical Application ................................................. 22

Power Supply Recommendations...................... 35

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics.......................................... 8

6.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 12

8

9

10 Layout................................................................... 35

10.1 Layout Guidelines ................................................. 35

10.2 Layout Examples................................................... 36

11 Device and Documentation Support ................. 39

11.1 Custom Design With WEBENCH® Tools ............. 39

11.2 Receiving Notification of Documentation Updates 39

11.3 Community Resources.......................................... 39

11.4 Trademarks........................................................... 39

11.5 Electrostatic Discharge Caution............................ 39

11.6 Glossary................................................................ 39

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 39

4 Revision History

Changes from Revision C (February 2017) to Revision D

Page

•

Added top navigator icon for TI Design reference design ..................................................................................................... 1

Changed "CDS18534Q5A" to "CSD18534Q5A" to fix typo.................................................................................................. 29

Changed "+" to "×" in Equation 56 ...................................................................................................................................... 32

Changes from Revision B (January 2017) to Revision C

Page

•

Changed the FBD with updates in the CS pin area ............................................................................................................. 12

Updated I_STEPdefinition in Equation 28 ............................................................................................................................... 25

Changes from Revision A (July 2016) to Revision B

Page

•

Added 'Systems' to the ADAS bullet in Applications ............................................................................................................. 1

Changed Description text From: 'conducted EMI' To: 'EMI' ................................................................................................... 1

Changed test conditions for RT parameter from: OSC = VDD to: OSC = GND ................................................................... 8

Changed equation unit From: '0.815 Apk' To: '0.815 A' ....................................................................................................... 24

Changed equation unit From: '6.41 Apk' To: '6.41 A' ........................................................................................................... 24

Changed equation unit From: '8.81 Apk' To: ' 8.81 A'.......................................................................................................... 25

Changed equation unit From: '0.235 A_RMS' To: '0.235 A'...................................................................................................... 26

Changed text From: 'a capacitance value greater than filter capacitor C_IN' To: 'a capacitance value greater than 5

times the filter capacitor C_IN' ................................................................................................................................................ 28

•

Changed equation text From: '6²A' and '105 nc' To: '(6A)²' and '105 nC' ............................................................................ 28

Added G_CSto equation definition list .................................................................................................................................... 31

Added Ω and µS symbols to equation text........................................................................................................................... 33

Changes from Original (July 2016) to Revision A

Page

•

Changed Product Preview to Production Data Release ........................................................................................................ 1

2

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SNVSAJ6D –JULY 2016–REVISED DECEMBER 2017

5 Pin Configuration and Functions

RGE Package

24-Pin VQFN With Exposed Thermal Pad

Top View

DEMB

VDDA

AGND

RT

1

2

3

4

5

6

18

17

16

15

14

13

CS

VOUT

VCCX

VIN

Thermal

Pad

DITH

OSC

HOL

HO

Not to scale

Connect Exposed Pad on bottom to AGND and PGND on the PCB.

Pin Functions

TYPE

NAME

DESCRIPTION

NO.

Diode emulation pin. Connect the DEMB pin to AGND to enable diode emulation. If it is

connected to VDDA the LM5141-Q1 operates in forced PWM (FPWM) mode with continuous

conduction at light loads. The DEMB pin can also be used as a synchronization input, to

synchronize the internal oscillator to an external clock.

1

DEMB

I

2

3

VDDA

AGND

P

Internal analog bias regulator output. Connect a capacitor from the VDDA pin to AGND.

Analog ground connection. Ground return for the internal voltage reference and analog

circuits.

G

A resistor from the RT pin to ground shifts the oscillator frequency up or down from 2.2 MHz

(1.8 MHz to 2.53 MHz), or 440 kHz (300 kHz to 500 kHz). An analog voltage can be applied

to the RT pin (through a resistor) to shift the oscillator frequency.

4

RT

I

A capacitor connected between the DITH pin and AGND is charged and discharged with a

20 µA current source. If Dither is enabled, the voltage on the DITH pin ramps up and down

modulating the oscillator frequency between –5% and +5% of the internal oscillator.

Connecting DITH to VDDA disables the dithering feature. DITH is ignored if an external

synchronization clock is used.

5

6

DITH

OSC

O

I

Frequency selection pin. Connecting the OSC pin to VDDA sets the oscillator frequency to

2.2 MHz. Connecting the OSC pin to AGND sets the frequency to 440 kHz.

7

LOL

LO

O

G

P

Low-side gate driver turnoff output.

8

Low-side gate driver turnon output.

9

PGND

VCC

HB

Power ground connection pin for low-side NMOS gate driver.

VCC bias supply pin. Connect a capacitor from the VCC pin to PGND.

High-side driver supply for bootstrap gate drive.

10

11

Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal

of the high-side MOSFET and the drain terminal of the low-side MOSFET.

12

SW

13

14

HO

O

High-side gate driver turnon output.

High-side gate driver turnoff output.

HOL

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SNVSAJ6D –JULY 2016–REVISED DECEMBER 2017

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Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

15

VIN

P

Supply voltage input source for the VCC regulator

Optional input for an external bias supply. If VCCX > 4.5 V, VCCX is internally connected to

the VCC pin and the internal VCC regulator is disabled. If VCCX is unused, it should be

grounded.

16

VCCX

Current sense amplifier input. Connect this pin to the output side of the current sense

resistor.

17

18

VOUT

CS

I

Current sense amplifier input. Make a low current Kelvin connection between this pin and the

inductor side of the external current sense resistor.

Connect the FB pin to VDDA for a fixed 3.3-V output or connect FB to AGND for a fixed 5-V

output. Connecting the FB pin to the appropriate output divider network will set the output

voltage between 1.5 V and 15 V. The regulation threshold at the FB pin is 1.2 V.

19

FB

I

20

21

COMP

PG

I

Output of the transconductance error amplifier.

O

An open collector output which switches low if V_OUTis outside of the power good window.

Soft-start programming pin. An external capacitor and an internal 20-μA current source set

the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below

80 mV turns-off the gate driver outputs, but all the other functions remain active.

22

23

SS

EN

I

An active high logic input enables the controller.

Restart timer pin. An external capacitor configures the hiccup mode current limiting. The

capacitor at the RES pin determines the time the controller will remain off before

automatically restarting in hiccup mode. The hiccup mode commences when the controller

experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connecting

the RES pin to VDD during power up disables hiccup mode protection.

24

RES

O

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–5

MAX

70

UNIT

V

VIN

SW to PGND

70

V

SW to PGND (20 ns transient)

HB to SW

V

–0.3

–5

6.5

V

HB to SW (20 ns transient)

HO, HOL to SW

V

–0.3

–5

HB + 0.3

VCC + 0.3

V

Input voltage

HO, HOL to SW (20 ns transient)

LO, LOL to PGND

V

–0.3

–1.5

–0.3

–40

–65

V

LO, LOL to PGND (20 ns transient)

OSC, SS, COMP, RES, DEMB, RT, DITH

EN to PGND

V

VDD + 0.3

70

V

VCC, VCCX, VDD, PG, FB

VOUT, CS

6.5

V

15.5

0.3

V

PGND to AGND

Operating junction temperature⁽²⁾

V

150

°C

Storage temperature, T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

4

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SNVSAJ6D –JULY 2016–REVISED DECEMBER 2017

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

All pins except

±2000

±500

±750

V_(ESD)

Electrostatic discharge

1,6,7,12,13,18,19, and 24

V

Charged-device model (CDM), per AEC

Q100-011

Pins 1,6,7,12,13,18,19, and

24

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

3.8

NOM

MAX

65

UNIT

VIN

V

SW to PGND

HB to SW

–0.3

65

5

5.25

HO, HOL to SW

LO, LOL to PGND

HB + 0.3

5.25

V_IN

Input voltage

FB, PG, OSC, SS, RES, DEMB,

VCCX

–0.3

5

V

EN to PGND

VCC, VDD

VOUT, CS

–0.3

1.5

65

5.25

15

V

5

V

PGND to AGND

Operating junction temperature⁽²⁾

–0.3

–40

0.3

V

150

°C

(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test

conditions, see Electrical Characteristics.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.4 Thermal Information

LM5141-Q1

THERMAL METRIC⁽¹⁾

RGE (QFN)

24 PINS

34.1

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

36.8

12.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

12.2

R_θJC(bot)

2.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

T_J= –40°C to +125°C, Typical values T_J= 25°C, V_IN= 12 V, VCCX = 5 V, V_OUT= 5 V, EN = 5 V, OSC = VDD, F_SW= 2.2

MHz, no-load on the drive outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless

otherwise noted)⁽¹⁾⁽²⁾

PARAMETER

VIN SUPPLY VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_SHUTDOWN

Shutdown mode current

Standby current

V_IN= 8–18 V, EN = 0 V, VCCX = 0 V

10

35

12.5

45

µA

EN = 5 V, FB = VDD, V_OUTin

regulation, no-load, not switching,

DEMB = GND.

I_STANDBY

µA

EN = 5 V, FB = 0 V, V_OUTin

regulation, no-load, not switching,

VCCX = 5 V, DEMB = GND.

42

55

VCC REGULATOR

V_IN= 6 to 18 V, 0 to 75 mA, VCCX =

0 V

VCC_(REG)

VCC regulation voltage

4.75

3.25

5

5.25

3.55

V

VCC_(UVLO)

VCC_(HYST)

I_CC(LIM)

VCC undervoltage threshold

VCC hysteresis voltage

VCC rising, VCCX = 0 V

VCCX = 0 V

3.4

175

125

V

mV

mA

VCC sourcing current limit

VCCX = 0 V

85

VDDA

VDDA_(REG)Internal bias supply power

VDDA_(UVLO

VCCX = 0 V

4.75

3.1

5

3.2

125

55

5.25

3.3

V

)

VCC rising, VCCX = 0 V

VCCX = 0 V

VDDA_(HYST)

mV

Ω

R_VDDA

VCCX = 0 V

VCCX

VCCX_(ON)

VCC rising

4.1

2.0

4.3

80

2

4.4

V

mV

Ω

VCCX_(HYST)

R_(VCCX)

VCCX = 5 V

OSCILLATOR SELECT THRESHOLDS

Oscillator select threshold 2.2 MHz (OSC pin)

V

Oscillator select threshold 440 kHz

(OSC pin)

0.8

82

CURENT LIMIT

ILSET = VDDA, measure from CS to

V_OUT

V_(CS)

t_dly

Current limit threshold

68

75

mV

Current sense delay to output

Current sense amplifier gain

Amplifier input bias

40

12

ns

V/V

nA

11.4

12.6

10

ICS_(BIAS)

RES

I_(RES)

RES current source

RES threshold

20

1.2

512

4

µA

V

V_(RES)

T_imer

Timer hiccup mode fault

RES pulldown

cycles

Ω

R_DS(ON)

OUTPUT VOLTAGE REGULATION

3.3 V

5 V

V_IN= 3.8 to 42 V

V_IN= 5.5 to 42 V

3.273

4.96

3.3

5.0

3.327

5.04

V

FEEDBACK

V_OUTselect threshold 3.3 V

Regulated feedback voltage

VDD - 0.3

1.193

V

1.2

1.207

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and

applying statistical process control.

(2) The junction temperature (T_Jin ºC) is calculated from the ambient temperature (T_Ain ºC) and power dissipation (P_Din Watts) as follows:

T_J= T_A+ (P_D× R_θJA) where R_θJA(in °C/W) is the package thermal impedance provided in the Thermal Information section.

6

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Electrical Characteristics (continued)

T_J= –40°C to +125°C, Typical values T_J= 25°C, V_IN= 12 V, VCCX = 5 V, V_OUT= 5 V, EN = 5 V, OSC = VDD, F_SW= 2.2

MHz, no-load on the drive outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless

otherwise noted)⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resistance to ground on FB for FB

= 0 detection

FB_(LOWRES)

FB_(EXTRES)

500

Ω

Thevenin equivalent resistance at

FB for external regulation detection

FB < 2 V

5

kΩ

TRANSCONDUCTANCE AMPLIFIER

Gm

Gain

Feedback to COMP

1010

1200

µS

nA

Input bias current

15

Transconductance amplifier source

current

COMP = 1 V, FB = 1 V

COMP = 1 V, FB = 1.4 V

100

µA

Transconductance amplifier sink

current

POWER GOOD

Falling with respect to the regulation

voltage

PG_(UV)

PG undervoltage trip levels

90%

92%

94%

Rising with respect to the regulation

voltage

PG_(OVP)

PG overvoltage trip levels

108%

110%

3.4%

112%

PG_(HYST)

PG_(VOL)

PG_(rdly)

PG_(fdly)

PG

Open collector, Isink = 2 mA

V_OUTrising

0.4

V

OV filter time

UV filter time

25

30

µs

V_OUTfalling

HO GATE DRIVER

V_OLH

V_OHH

t_rHO

HO Low-state output voltage

I_HO= 100 mA

0.05

0.07

4

V

HO High-state output voltage

HO rise time (10% to 90%)

HO fall time (90% to 10%)

I_HO= –100 mA, V_OHH= V_HB- V_HO

C_LOAD= 2700 pf

ns

t_fHO

C_LOAD= 2700 pf

3

V_HO= 0 V, SW = 0 V, HB = 5 V,

VCCX = 5 V

I_OHH

I_OLH

V_(BOOT)

I_(BOOT)

HO peak source current

3.25

Apk

HO peak sink current

UVLO

VCCX = 5 V

HO falling

4.25

2.5

110

3

Apk

V

Hysteresis

mV

µA

Quiescent current

LO GATE DRIVER

V_OLL

V_OHL

t_rLO

LO Low-state output voltage

I_LO= 100 mA

0.05

0.07

4

V

LO High-state output voltage

LO rise time (10% to 90%)

LO fall time (90% to 10%)

LO peak source current

LO peak sink current

I_LO= –100 mA, V_OHL= VCC – V_LO

C_LOAD= 2700 pf

VCCX = 5 V

ns

t_fLO

3

ns

I_OHL

I_OLL

3.25

4.25

Apk

VCCX = 5 V

ADAPTIVE DEAD TIME CONTROL

V_(GS-DET)

tdly1

VGS detection threshold

HO off to LO on dead time

LO off to HO on dead time

VGS falling, no load

2.5

20

V

40

38

ns

tdly2

DIODE EMULATION

V_IL

DEMB input low threshold

0.8

V

V_IH

SW

FPWM input high threshold

Zero cross threshold

2

–5

mV

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Electrical Characteristics (continued)

T_J= –40°C to +125°C, Typical values T_J= 25°C, V_IN= 12 V, VCCX = 5 V, V_OUT= 5 V, EN = 5 V, OSC = VDD, F_SW= 2.2

MHz, no-load on the drive outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless

otherwise noted)⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ENABLE INPUT

V_IL

V_IH

I_Ikg

Enable input low threshold

Enable input high threshold

Leakage

VCCX = 0 V

0.8

V

VCCX = 0 V

2.0

EN logic input only

1

µA

SYN INPUT (DEMB pin)

V_IL

V_IH

DEMB input low threshold

0.8

V

DEMB input high threshold

2

DEMB input low frequency range

440 kHz

350

550

kHz

DEMB input high frequency range

2.2 MHz

1800

2600

DITHER

I_DITHER

Dither source/sink current

Dither high threshold

Dither low threshold

20

1.26

1.14

µA

V

V_DITHER

V

SOFT-START

I_SS

Soft-Start current

16

22

3

28

µA

R_DS(ON)

Soft-Start pull-down resistance

Ω

THERMAL

TSD Thermal Shutdown

175

15

ºC

Thermal shutdown hysteresis

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2100

420

TYP

MAX

UNIT

kHz

Oscillator Frequency 2.2 MHz

Oscillator Frequency 440 kHz

OSC = VDDA, V_IN= 8–18 V

OSC = GND, V_IN= 8–18 V

OSC = VDD, RT_MIN= 61.9 kΩ

OSC = VDD, RT_TYP= 49.9 kΩ

OSC = VDD, RT_MAX= 43.2 kΩ

OSC = GND, RT_MIN= 73.2 k

OSC = GND, RT_TYP= 49.9 kΩ

OSC = GND, RT_MAX= 44.2 kΩ

2200

440

2300

460

Minimum

1710

2100

2405

285

1800

2200

2530

300

1890

2300

2655

315

Adjustment

RT

Range

Typical

2.2 MHz

Maximum

Minimum

Typical

Adjustment

Range

420

440

460

440 kHz

Maximum

475

500

525

Response

time

RT

RT= 61.9–43.2 kΩ

RT = 43.2–61.9 kΩ

2

µs

Response

time

3.5

Response

time

16

45

t_on

t_off

Minimum on-time

Minimum off-time

66

ns

100

8

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6.7 Typical Characteristics

At T_A= 25ºC, unless otherwise noted

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

V_IN8 V

V_IN12 V

V_IN18 V

V_IN8 V

V_IN12 V

V_IN18 V

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Output Current (A)

EN = 12 V

FPWM

Output Current (A)

EN = 12 V

DEMB

D001

D002

V_IN8–18 V

V_OUT5 V

2.2 MHz

V_IN8–18 V

V_OUT5 V

2.2 MHz

Figure 1. Efficiency vs I_OUT

Figure 2. Efficiency vs I_OUT

12

10

8

70

65

60

55

50

45

40

35

30

25

125èC

25èC

-40èC

6

4

V_IN8 V

V_IN12 V

V_IN18 V

2

0

8

9

10

11

12

13

14

15

16

17

18

-50 -30 -10 10

30

50

70

90 110 130 150

V_IN(V)

Temperature (èC)

D003

D0041

EN = 12 V

V_IN8–18 V

EN = 0 V

Figure 3. I_STANDBYvs V_IN

Figure 4. I_SHUTDOWNvs Temperature

5.25

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

3.50

3.48

3.46

3.44

3.42

3.40

3.38

3.36

3.34

3.32

3.30

6

7

8

9

10

11

12

13

14

15

16

17

18

-60

-40

-20

0

20

40

60

80

100

120

140

V_IN(V)

Temperature (°C)

D005

D006

V_IN6-18 V

EN = GND

Figure 5. VCC_(REG)vs V_IN

V_IN8–18 V

EN = 12 V

Figure 6. VCC_(UVLO)vs Temperature

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Typical Characteristics (continued)

At T_A= 25ºC, unless otherwise noted

5.25

3.30

3.28

3.26

3.24

3.22

3.20

3.18

3.16

3.14

3.12

3.10

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

-60

-40

-20

0

20

40

60

80

100

120

140

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

D007

D008

VCC Rising

EN = 12 V

VCC Rising

EN = 12 V

Figure 7. VDD_(REG)vs Temperature

Figure 8. VDD_(UVLO)vs Temperature

4.50

4.45

4.40

4.35

4.30

4.25

4.20

4.15

4.10

4.05

4.00

13.00

12.80

12.60

12.40

12.20

12.00

11.80

11.60

11.40

11.20

11.00

-60

-40

-20

0

20

40

60

80

100

120

140

-60 -40 -20

0

20

40

60

80 100 120 140

Temperature (°C)

D009

Temperature (èC)

D010

VCC Rising

EN = 12 V

V_IN12 V

EN = 12 V

Figure 9. VCCX_(ON)vs Temperature

Figure 10. Current Sense Amplifier Gain vs Temperature

3.32

3.31

3.3

5.000

+125èC

+25èC

-40èC

+125èC

+25èC

-40èC

4.995

4.990

4.985

4.980

4.975

4.970

4.965

4.960

4.955

4.950

3.29

3.28

3.27

3.26

3.25

3.24

3.23

3.22

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Output Current (A)

Output Current (V)

D011

D012

V_IN12 V

FB = VDDA

EN = 12 V

V_IN12 V

EN = 12 V

FB = GND

Figure 11. 3.3-V Output Voltage Regulation vs I_OUT

Figure 12. 5-V Output Voltage Regulation vs I_OUT

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Typical Characteristics (continued)

At T_A= 25ºC, unless otherwise noted

2400

470

465

460

455

450

445

440

435

430

425

420

415

410

2340

2280

2220

2160

2100

2040

-60 -40 -20

0

20

40

60

80 100 120 140

-60 -40 -20

0

20

40

60

80 100 120 140

Temperature (èC)

D013

D014

V_IN12 V

EN = 12 V

OSC = VDDA

V_IN12 V

EN = 12 V

OSC = AGND

Figure 13. 2.2-MHz Oscillator Frequency vs Temperature

Figure 14. 440-kHz Oscillator Frequency vs Temperature

110

90

105

100

95

90

85

80

75

70

65

60

80

70

60

50

40

30

20

10

0

-60 -40 -20

0

20

40

60

80 100 120 140

-60 -40 -20

0

20

40

60

80 100 120 140

Temperature (èC)

D015

D016

V_IN18 V

V_IN3.8 V

V_OUT3.3 V

Figure 15. t_onMinimum vs Temperature

Figure 16. t_offMinimum vs Temperature

2600

2500

2400

2300

2200

2100

2000

1900

1800

1700

1600

600

560

520

480

440

400

360

320

280

240

200

RT 49.9 kΩ

-60 -40 -20 20

RT 43.2 kΩ

RT 61.9 kΩ

80 100 120 140

RT 49.9 kW

-60 -40 -20 20

RT 44.2 kW

RT 73.2 kW

0

40 60

Temperature (°C)

0

40

60

80 100 120 140

Temperature (èC)

D017

D018

V_IN12 V

Figure 17. RT Frequency vs Temperature (2.2 MHz)

V_IN12 V

Figure 18. RT Frequency vs Temperature (440 kHz)

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7 Detailed Description

7.1 Overview

The LM5141-Q1 is a switching controller that features all of the functions necessary to implement a high-

efficiency buck power supply that can operate over a wide input-voltage range. The LM5141-Q1 is configured to

provide a single fixed 3.3-V or 5-V output, or an adjustable output between 1.5 V to 15 V. This easy-to-use

controller integrates high-side and low-side MOSFET drivers capable of sourcing 3.25 A and sinking 4.25 A

peak. The control method is current mode control, which provides inherent line feed-forward, cycle-by-cycle

current limiting, and ease-of-loop compensation. With the OSC pin connected to VDD, the default oscillator

frequency is 2.2 MHz. With the OSC pin grounded, the oscillator frequency is 440 kHz. The LM5141-Q1 can be

synchronized by applying an external clock to the DEMB pin. Fault protection features include current limiting,

thermal shutdown, and remote shutdown capability.

The LM5141-Q1 incorporates features that simplify compliance with the CISPR and automotive EMI

requirements. The LM5141-Q1 has optional spread spectrum to reduce the peak EMI and gate drivers with slew-

rate control. The QFN-24 package features an exposed pad to aid in thermal dissipation.

7.2 Functional Block Diagram

VIN

VCCX

BIAS

V_REF1.2 V

VCC

VDDA

CONTROL

VDDA

RES

20 uA

CL

RESTART

LOGIC

HICCUP FAULT

TIMER 256 CYCLES

CLK

DEMB

OSC

RT

OUT

DEMB/

FPWM/

SYNIN

EN

CL

CURRENT

LIMIT

DITH

Gain = 12

75 mV

+

CS

+

SLOPE

COMPENSATION

RAMP

HB1 UVLO

HB

VOUT

3.3 V

5 V

VOUT

DECODER/

MUX

DEMB

OUT

+

HO

HOL

FB

SS

LEVEL SHIFT

ADAPTIVE

DEAD TIME

SW

+

PWM

VCC

R

S

Q

STBY

SS_COMPLETE

1200 uS

FBi

V_REF

CLK

LO

LOL

20 uA

SS

+

PGND

AGND

SS

COMP

PG

STBY

1.356 V

1.056 V

PGOV

+

PGDLY

25 us

STAND-BY

PGUV

+

V_STBY

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7.3 Feature Description

7.3.1 High Voltage Start-up Regulator

The LM5141-Q1 contains an internal high voltage VCC bias regulator that provides the bias supply for the PWM

controller and the gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an

input voltage source up to 65 V. The output of the VCC regulator is set to 5 V. When the input voltage is below

the VCC set-point level, the VCC output will track VIN with a small voltage drop. In high voltage applications

extra care should be taken to ensure the VIN pin does not exceed the absolute maximum voltage rating of 70 V

including line or load transients. Voltage ringing on the VIN pin that exceeds the absolute maximum ratings can

damage the IC. Use a high quality bypass capacitor between VIN and ground to minimize ringing.

7.3.2 VCC Regulator

The VCC regulator output current limit is 75 mA (minimum). At power-up, the regulator sources current into the

capacitors connected to the VCC pin. When the voltage on the VCC pin exceeds 3.4 V the output is enabled and

the soft-start sequence begins. The output remains active unless the voltage on the VCC pin falls below the

VCC_(UVLO)threshold of 3.2 V (typical) or the enable pin is switched to a low state. The recommended range for

the VCC capacitor is 2.2 µF to 4.7 µF

An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 100-nF or greater ceramic

capacitor to ensure a low noise internal bias rail. Normally VDDA is 5 V, but there are two operating conditions

where it regulates at 3.3 V. The first is in skip cycle mode with VOUT of 3.3 V. The second is when V_INis less

than 5 V. Under these conditions both VCC and VDD drop below 5 V. Internal power dissipation in the VCC

Regulator can be minimized by connecting the VCCX pin to a 5-V output or to an external 5-V supply. If VCCX >

4.5 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. If VCCX is unused, it

should be grounded. Never connect the VCCX pin to a voltage greater than 6.5 V.

7.3.3 Oscillator

The LM5141-Q1 has an internal trimmed oscillator with two frequency options: 2.2 MHz, or 440 kHz. With the

OSC pin connected to VDDA the oscillator frequency is 2.2 MHz. With the OSC pin grounded, the oscillator

frequency is 440 kHz. The state of the OSC pin is read and latched during VCC power-up and cannot be

changed until VCC drops below the VCC_(UVLO)threshold.

The oscillator frequency can be modulated up or down from the nominal oscillator frequency (2.2 MHz or 440

kHz) on demand by connecting a resistor from the RT pin to ground (refer to Figure 19). To disable the

frequency modulation option, the RT pin can be grounded or left open. If the RT pin is connected to ground

during power-up the frequency modulation option is latch-off and cannot be changed unless VCC is allowed to

drop below the VCC_(UVLO)threshold. If the RT pin is left open during power-up the frequency modulation option

will be disabled, but it can be enabled at a later time by switching in a valid RT resistor. When the frequency

modulation option is disabled, the LM5141-Q1 will operate at the internal oscillator frequency (2.2 MHz or 440

kHz).

On power up, after soft-start is complete and the output voltage is in regulation, a 16-µs timer is initiated. If a

valid RT resistor is connected, the LM5141-Q1 will switch to the frequency set by the RT resistor n the

completion of the 16-µs time delay.

The modulation range for 2.2 MHz is 1.8 MHz to 2.53 MHz (refer to Table 1). If an RT resistor value > 95 kΩ

(typical) is placed on the RT pin, the LM5141-Q1 controller will assume that the RT pin is open, and will use the

internal oscillator. If an RT resistor < 27 kΩ (typical) is connected, the controller will use the internal oscillator. To

calculate an RT resistor for a specific oscillator frequency, use Equation 1 for the 2.2 MHz frequency range or

Equation 2 for the 440 kHz frequency range.

1

- 0.0216

Fsw

RT_{2.2 MHz}

=

0.0086

where

•

RT is kΩ and Fsw is in MHz

(1)

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Feature Description (continued)

1

-1.38ì10^-5

Fsw

RT_{440 kHz}

=

4.5ì10^-5

where

•

RT is in kΩ and Fsw is in kHz

(2)

Table 1. RT Resistance vs Oscillator Frequency

RT RESISTANCE

(TYPICAL) 2.2 MHz

2.2 MHZ OSCILLATOR

RANGE (TYPICAL)

RT RESISTANCE

(TYPICAL) 440 kHz

440 kHz OSCILLATOR

RANGE (TYPICAL)

S1

S2

X

> 95 kΩ

61.98 kΩ total

50.18 kΩ total

43.2 kΩ

internal oscillator

1.8 MHz

> 95 kΩ

73.8 kΩ total

50.1 kΩ total

44.2 kΩ

internal oscillator

300 kHz

OFF

ON

X

OFF

ON

OFF

X

2.2 MHz

440 kHz

2.53 MHz

500 kHz

< 27 kΩ

internal oscillator

< 27 kΩ

internal oscillator

LM5141-Q1

VDDA

OSC

RT

43.2 k

6.98 k

S1

S2

11.8 k

Figure 19. RT Connection Circuit, 2.2 MHz

LM5141-Q1

OSC

RT

44.2 k

S1

S2

5.9 k

23.7 k

Figure 20. RT Connection Circuit, 440 kHz

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An alternative method to modulate the oscillator frequency is to use an analog voltage connected to the RT pin

through a resistor. See Figure 21. An analog voltage of 0.0 V to 0.6 V modulates the oscillator frequency

between 1.8 MHz to 2.53 MHz (OSC at 2.2 MHz), or 300 kHz to 500 kHz (OSC at 440 kHz). The analog voltage

source must be able to sink current.

DEM/SYNC

LM5141-Q1

OSC

RT

44.2 k

0 V œ 6 V

Figure 21. Analog Voltage Control of the Oscillator Frequency

When the LM5141-Q1 is in the low I_Qstandby mode, the controller sets the RT pin to a high impedance state

and ignores the RT resistor. After coming out of standby mode, the controller will monitor the RT pin. If a valid

resistor is connected, and there have been 16 µs of continuous switching without a zero-crossing event, the

LM5141-Q1 will switch to the frequency set by the RT resistor.

7.3.4 Synchronization

To synchronize the LM5141-Q1 to an external source, apply a logic level clock signal to the DEMB pin. The

synchronization range is 350 kHz to 550 kHz when the internal oscillator is set to 440 kHz. When the internal

oscillator is set to 2.2 MHz, the synchronization range is 1.8 MHz to 2.6 MHz. If there is a valid RT resistor and a

synchronization signal, the LM5141-Q1 with ignore the RT resistor and synchronize the controller to the external

clock. Under low V_INconditions, when the minimum toff time is reached (100ns), the synchronization clock will be

ignored to allow the frequency to drop to maintain output voltage regulation.

7.3.5 Frequency Dithering (Spread Spectrum)

The LM5141-Q1 provides a frequency dithering option that is enabled by connecting a capacitor from the DITH

pin to AGND. A triangular waveform centered at 1.2 V is generated across the C_DITHcapacitor. Refer to

Figure 22. The triangular waveform modulates the oscillator frequency by ±5% of the nominal frequency set by

the OSC pin or by an RT resistor. The C_DITHcapacitance value sets the rate of the low frequency modulation. A

lower C_DITHcapacitance will modulate the oscillator frequency at a faster rate than a higher capacitance. For the

dithering circuit to effectively reduce the peak EMI, the modulation rate must be less than the oscillator frequency

(F_SW). Equation 3 calculates the DITH pin capacitance required to set the modulation frequency, F_MOD

.

20 mA

2ìF_MODì0.12V

C_DITH

=

(3)

If the DITH pin is connected to VDDA during power-up the dither feature is latch-off and cannot be changed

unless VCC is allowed to drop below the VCC_(UVLO)threshold. If the DITH pin is connected to ground on power

up, dither will be disabled, but it can be enabled by raising the DITH pin voltage above ground and connecting it

to C_DITH. When the LM5141 is synchronized to an external clock, Dither is disabled.

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1.26 V +5%

1.2 V

1.14 V -5%

DITH

LM5141-Q1

C_DITH

Figure 22. Dither Operation

7.3.6 Enable

The LM5141-Q1 has an enable input EN for start-up and shutdown control of the output. The EN pin can be

connected to a voltage as high as 70 V. If the enable input is greater than 2 V the output is enabled. If the enable

pin is pulled below 0.8 V, the output will be in shutdown, and the LM5141-Q1 is switched to a low I_Qshutdown

mode, with a 10-µA typical current drawn from the VIN pin. It is not recommended to leave the EN pin left

floating.

7.3.7 Power Good

The LM5141-Q1 includes an output voltage monitoring function to simplify sequencing and supervision. The

power-good function can be used to enable circuits that are supplied by the output voltage rail or to turn on

sequenced supplies. The PG pin switches to a high impedance state when the output voltage is in regulation.

The PG signal switches low when the output voltage drops below the lower power good threshold (92% typical)

or rises above the upper power good threshold (110% typical). A 25-μs deglitch filter prevents any false tripping

of the power good signal due to transients. TI recommends a pullup resistor of 10 kΩ from the PG pin to the

relevant logic rail. Power good is asserted low during soft start and when the buck converter is disabled by EN.

7.3.8 Output Voltage

The LM5141-Q1 output can be configured for one of the two fixed output voltages with no external feedback

resistors, or the output can be adjusted to the desired voltage using an external resistor divider. V_OUTcan be

configured as a 3.3-V output by connecting the FB pin to VDDA, or a 5-V output by connecting the FB pin to

ground with a maximum resistance of 500 Ω. The FB connections (either VDDA or GND) are detected during

power up.

The configuration setting is latched and cannot be changed until the LM5141-Q1 is powered down with VCC

falling below VCC_(UVLO)(3.4 V typical) and then powered up again.

Alternatively the output voltage can be set using an external resistive dividers from the output to the FB pin. The

output voltage adjustment range is between 1.5 V and 15 V. The regulation threshold at the FB pin is 1.2 V

(V_REF). To calculate R_FB1and R_FB2use Equation 4. Refer to Figure 23:

≈

∆

«

’

V_OUT

V_REF

R_FB2

=

-1 ìR

÷

FB1

◊

(4)

The recommend starting point is to select R_FB1between 10 kΩ to 20 kΩ.

The Thevenin equivalent impedance of the resistive divider connected to the FB pin must be greater than 5 kΩ

for the LM5141-Q1 to detect the divider and set the controller to the adjustable output mode. Refer to Equation 5.

R_FB1ìR_FB2

R_FB1+ R_FB2

R_TH

=

> 5kW

(5)

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If a low I_Qmode is required, take care when selecting the external resistors. The extra current drawn from the

external divider is added to the LM5141-Q1 I_STANDBYcurrent (35 μA typical). The divider current reflected to VIN

is divided down by the ratio of V_OUT/V_IN. For example, if V_INis 12 V and V_OUTis set to 5.5 V with R_FB110 kΩ, and

R_FB2= 35.7 kΩ, the input current at VIN required to supply the current in the feedback resistors is:

V_OUT

5.5V

I_DIVIDER

=

ì

=

ì

= 55.16mA

R_FB1+R_FB2

V

10k + 35.7k 12V

IN

where

•

V_IN= 12 V

(6)

(7)

The total input current in this condition is:

I_VINö I_STANDBY+I_DIVIDERö 35mA + 55.16m ö 90.16mA

L_OUT

V_OUT

C_OUT

R_FB2

LM5141 Transconductance Amplifier

gm 1200 uS

_

FB

V_REF

SS

+

R_FB1

+

COMP

Figure 23. Voltage Feedback

7.3.8.1 Minimum Output Voltage Adjustment

There are two limitations to the minimum output voltage adjustment range: the LM5141-Q1 voltage reference of

1.2 V and the minimum switch node pulse width, t_SW

.

The minimum controllable on-time at the switch node (t_SW) limits the voltage conversion ratio (V_OUT/V_IN). For

fixed-frequency PWM operation, the voltage conversion ratio should meet the following condition:

V_OUT

> t_sw×Fsw

V

IN

where

•

t_SWis 70 ns (typical)

F_SWis the switching frequency

(8)

If the desired voltage conversion ratio does not meet the above condition, the controller transitions from fixed

frequency operation into a pulse skipping mode to maintain regulation of the output voltage.

For example if the desired output voltage is 3.3 V with a V_INof 20 V and operating at 2.2 MHz, the voltage

conversion ratio test is satisfied:

3.3V

> 70nsì2.2MHz

20V

(9)

0.165 > 0.154

For wide V_INapplications and lower output voltages, an alternative is to use the LM5141-Q1 with a 440-kHz

oscillator frequency. Operating at 440 kHz, the limitation of the minimum t_SWtime is less significant. For example,

if a 1.8-V output is required with a V_INof 50 V:

1.8V

> 70nsì440kHz

50V

(10)

0.036 > 0.0308

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7.3.9 Current Sense

There are two methods to sense the inductor current of the buck converter. The first is using current sense

resistor in series with the inductor and the second is to use the dc resistance of the inductor (DCR sensing).

Figure 24 shows inductor current sensing using a current-sense resistor. This configuration continuously

monitors the inductor current providing accurate current-limit protection. For the best current-sense accuracy and

overcurrent protection, use a low inductance ±1% tolerance current-sense resistor between the inductor and

output, with a Kelvin connection to the LM5141-Q1 sense amplifier.

If the peak differential current signal sensed from CS to VOUT exceeds 75 mV, the current limit comparator

immediately terminates the HO output for cycle-by-cycle current limiting.

V _CS

(

)

R_SENSE

=

DI

2

≈

’

I

+

∆

«

÷

◊

OUT MAX

(

)

where

•

V_(CS) = 75 mV

(11)

I_OUT(MAX)is the overcurrent setpoint, which is set higher than the maximum load current to avoid tripping the over

current comparator during load transients. ΔI is the peak-peak inductor ripple current.

L_OUT

V_OUT

R_SENSE

C_OUT

LM5141 Current Sense Amplifier

Gain = 12

+

CS

VOUT

_

Figure 24. Current Sense

7.3.10 DCR Current Sensing

For high-power applications which do not require high accuracy current-limit protection, DCR sensing may be

preferable. This technique provides lossless and continuous monitoring of the output current using an RC sense

network in parallel with the inductor. Using an inductor with a low DCR tolerance, the user can achieve a typical

current limit accuracy within the range of ±10% to ±15% at room temperature.

Components R_CSand C_CSin Figure 25 create a low-pass filter across the inductor to enable differential sensing

of the voltage drop across inductor DCR. When R_CS× C_CSis equal to L_OUT/R_DCR, the voltage developed across

the sense capacitor, C_CS, is a replica of the inductor DCR voltage waveform. Choose the capacitance of C_CSto

be greater than 0.1 μF to maintain a low impedance sensing network, thus reducing the susceptibility of noise

pickup from the switch node. Carefully observe the PCB layout guidelines to ensure the noise and DC errors do

not corrupt the differential current-sense signals applied across the CS and VOUT pins.

The voltage drop across C_CS

:

sL_OUT

1+

R_DCR

V_CSs =

( )

Ipk ìR_DCR

1+ sR_CSC_CS

(12)

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L_OUT

V_OUT

R_DCR

C_OUT

LM5141 Current Sense Amplifier

C_CS

R_CS

Gain = 12

+

CS

VOUT

_

Figure 25. DCR Current Sensing

R_CSC_CS= L_OUT/R_DCR→ accurate DC and AC current sensing

If the RC time constant is not equal to the L_OUT/L_DRCtime constant there will be an error

R_CSC_CS> L_OUT/R_DCR→ DC level still correct, the AC amplitude will be attenuated

R_CSC_CS< L_OUT/R_DCR→ DC level still correct, the AC amplitude will be amplified

7.3.11 Error Amplifier and PWM Comparator

The LM5141-Q1 has a high-gain transconductance amplifier that generates an error current proportional to the

difference between the feedback voltage and an internal precision reference (1.2 V). The output of the

transconductance amplifier is connected to the COMP pin allowing the user to provide external control loop

compensation. Generally for current mode control a type II network is recommended.

7.3.12 Slope Compensation

The LM5141-Q1 provides internal slope compensation to ensure stable operation with a duty cycle greater than

50%. To correctly use the internal slope compensation, the inductor value must be calculated based on the

following guidelines (Equation 12 assumes an inductor ripple current of 30%):

V_OUT

L_OUT

í

Fsw ì 0.3ìI

(

)

OUT

(13)

•

Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost and

improves transient response at the cost of reduced efficiency due to higher peak currents.

Higher inductance values decrease the peak-to-peak inductor current typically increases efficiency by

reducing the RMS current at the cost of requiring larger output capacitors to meet load-transient

specifications.

7.3.13 Hiccup Mode Current Limiting

The LM5141-Q1 includes an optional hiccup mode protection function that is enabled when a capacitor is

connected to the RES pin. In normal operation the RES capacitor is discharged to ground. If 512 consecutive

cycles of cycle-by-cycle current limiting occur, the SS pin capacitor is pulled low and the HO and LO outputs are

disabled (refer to Figure 26). A 20-μA current source begins to charge the RES capacitor.

When the RES pin charges to 1.2 V, the RES pin is pulled low, and the SS capacitor begins to charge. The 512

cycle hiccup counter is reset if 4 consecutive switching cycles occur without exceeding the current limit threshold.

The controller is in forced PWM (FPWM) continuous conduction mode when the DEMB pin is connected to

VDDA. In this mode the SS pin is clamped to a level 200 mV above the feedback voltage to the internal error

amplifier. This ensures that SS can be pulled low quickly during a brief overcurrent event and prevent overshoot

of VOUT when the overcurrent condition is removed.

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If DEMB = 0 V, the controller operates in diode emulation with light loads (discontinuous conduction mode) and

the SS pin is allowed to charge to VDDA. This reduces the quiescent current of the LM5141-Q1. If 32 or more

cycle-by-cycle current limit events occur, the SS pin is clamped to 200 mV above the feedback voltage to the

internal error amplifier until the hiccup counter is reset. Thus, if a momentary overload occurs that causes at least

32 cycles of current limiting, the SS capacitor voltage will be slightly higher than the FB voltage and will control

VOUT during overload recovery.

Current Limit

Detected

1.2V RES Threshold

I_RES= 20 µA

0 V

RES

SS

I_SS= 20 µA

1.2 V REF

HO/HOL

LO/LOL

t_RES

t_SS

Current Limit persists

during 512

consecutive cycles

Figure 26. Hiccup Mode

7.3.14 Standby Mode

The LM5141-Q1 operates with peak current mode control such that the compensation voltage is proportional to

the peak inductor current. During no-load or light load conditions, the output capacitor will discharge very slowly.

As a result the compensation voltage will not demand a driver output pulses on a cycle-by-cycle basis. When the

LM5141-Q1 controller detects that there have been 16 missing switching cycles, it enters standby mode and

switches to a low IQ state to reduce the current drawn from VIN. For the LM5141-Q1 to go into a standby mode,

the controller must be programmed for diode emulation (DEMB pin < 0.4 V). The typical IQ in standby mode is

35 μA with VOUT regulating at 3.3 V.

7.3.15 Soft Start

The soft-start feature allows the controller to gradually reach the steady state operating point, thus reducing start-

up stresses and surges. The LM5141-Q1 regulates the FB pin to the SS pin voltage or the internal 1.2-V

reference, whichever is lower. At the beginning of the soft-start sequence when SS = 0 V, the internal 20 µA soft-

start current source gradually increases the voltage on an external soft-start capacitor connected to the SS pin,

resulting in a gradual rise of the FB and output voltages. The controller is in the forced PWM (FPWM) mode

when the DEMB pin is connected to VDDA. In this mode, the SS pin is clamped at 200 mV above the feedback

voltage. This ensures that SS will be pulled low quickly when FB falls during brief over-current events to prevent

overshoot of VOUT during recovery. SS can be pulled low with an external circuit to stop switching, but this is not

recommended. Pulling SS low results in COMP being pulled down internally as well. If the controller is operating

in FPWM mode (DEMB = VDDA), LO remains on, and the low-side MOSFET discharges the VOUT capacitor

resulting in large negative inductor current. In contrast when the LM5141-Q1 pulls SS low internally due to a fault

condition, the LO gate driver is disabled.

7.3.16 Diode Emulation

A fully synchronous buck controller implemented with a free-wheel MOSFET rather than a diode has the

capability to sink negative current from the output in certain conditions such as light load, over-voltage, and pre-

bias start-up. The LM5141-Q1 provides a diode emulation feature that can be enabled to prevent reverse (drain

to source) current flow in the low-side free-wheel MOSFET. The diode emulation feature is configured with the

DEMB pin. To enable diode emulation, connect the DEMB pin to ground. When configured for diode emulation,

the low-side MOSFET is disabled when reverse current flow is detected. The benefit of this configuration is lower

power loss at no load or light load conditions and the ability to turn on into a pre-biased output without

discharging the output. The negative effect of diode emulation is degraded light load transient response times.

Enabling the diode emulation feature is recommended to allow discontinuous conduction operation. If continuous

conduction operation is desired, the DEMB pin should be tied to VDDA.

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Table 2. DEMB Pin Modes

DEMB PIN

MODE

FPWM

DEMB

FPWM

1

0

CLK

7.3.17 High- and Low-Side Drivers

The LM5141-Q1 contains N-channel MOSFET gate drivers and an associated high-side level shifter to drive the

external N-channel MOSFETs. The high-side gate driver works in conjunction with an external bootstrap diode

D_BST, and bootstrap capacitor C_BST(refer to Figure 27). During the on-time of the low-side MOSFET, the SW pin

voltage is approximately 0 V, and C_BSTis charged from VCC through the D_BST. A 0.1-μF or larger ceramic

capacitor, connected with short traces between the HB and SW pin is recommended.

The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs

(HO and LO) are never enabled at the same time, preventing cross conduction. When the controller commands

LO to be enabled, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below

2.5 V typical. LO is then enabled after a small delay (HO falling to LO rising delay). Similarly, the HO turn-on is

delayed until the LO voltage has dropped below 2.5 V. HO is then enabled after a small delay (LO falling to HO

rising delay). This technique ensures adequate dead-time for any size N-channel MOSFET device or parallel

MOSFET configurations. Caution is advised when adding series gate resistors, as this may decrease the

effective dead-time. Each of the high and low-side drivers have independent driver source and sink output pins.

This allows the user to adjust drive strength to optimize the switching losses for maximum efficiency and to

control the slew rate for reduced EMI. The selected N-channel high-side MOSFET determines the appropriate

boost capacitance values C_BSTin Figure 27 according toEquation 14.

Q_G

C_BST

=

DV_BST

where

•

Q_Gis the total gate charge of the high-side MOSFET

ΔV_BSTis the voltage variation allowed on the high-side MOSFET driver after turnon

(14)

Choose ΔV_BSTsuch that the available gate-drive voltage is not significantly degraded when determining C_BST. A

typical range of ΔV_BSTis 100 mV to 300 mV. The bootstrap capacitor should be a low-ESR ceramic capacitor. A

minimum value of 0.1 μF to 0.47 μF is best in most cases. The gate threshold of the high-side and low-side

MOSFETs should be a logic level variety appropriate for 5-V gate drive.

VCC

D_BST

HB

C_BST

R_HO

HO

HOL

R_HOL

SW

VCC

C_VCC

R_LO

LO

LOL

R_LOL

PGND

Figure 27. Drivers

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5141-Q1 is a synchronous buck controller used to convert a higher input voltage to a lower output

voltage. The following design procedure can be used to select external component values. Alternately, the

WEBENCH® software may be used to generate a complete design. The WEBENCH software uses an iterative

design procedure and accesses a comprehensive database of components when generating a design. This

section presents a simplified design process. In addition to the WEBENCH software the LM5141ADESIGN-

CALC.xls quick-start Excel calculator is available at www.ti.com.

8.2 Typical Application

V_IN

C_IN

VIN

VCC

C_VCC

D_BST

C_BST

HB

HO

RES

SS

L_OUT

V_OUT

R_SENSE

HOL

SW

DITH

LM5141-Q1

C_OUT

LO

C_RES

C_SS

C_DITH

LOL

PGND

PG

CS

EN

DEMB

VOUT

VCCX

R_COMPC_COMP

COMP

FB

AGND

RT

OSC VDDA

R_T

C_VDDA

Figure 28. Typical Application Schematic

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Typical Application (continued)

8.2.1 Design Requirements

For this design example, the intended input, output, and performance parameters are shown in Table 3.

Table 3. Design Requirements

DESIGN PARAMETER

Input voltage range (steady state)

V_INmaximum (transient)

V_INminimum (cold crank)

Output voltage

EXAMPLE VALUE

8 V to 18 V

42 V

3.8 V

3.3 V

Output current

6 A

Operating frequency

2.2 MHz

±1%

Output voltage regulation

Standby current, one output enabled, no-load

Shutdown current

< 35 µA

10 µA

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5141-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

•

Buck Inductor value

Calculate the peak inductor current

Current Sense resistor value

Output capacitor value

Input filter

MOSFET selection

Control Loop design

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8.2.2.2 Inductor Calculation

For peak current mode control, sub-harmonic oscillation occurs with a duty cycle greater than 50% and is

characterized by alternating wide and narrow pulses at the SW pin. By adding a slope compensating ramp equal

to at least one-half the inductor current down-slope, any tendency toward sub-harmonic oscillation is damped

within one switching cycle. For design simplification, the LM5141-Q1 has an internal slope compensation ramp

added to the current sense signal.

For the slope compensation ramp to dampen sub-harmonic oscillation, the inductor value should be calculated

based on the following guidelines (Equation 15 assumes an inductor ripple current 30%):

V_OUT

L_OUT

í

Fsw ì 0.3ìI

(

)

OUT

(15)

•

Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost and

improves transient response at the expense of reduced efficiency due to higher peak currents.

Higher inductance values decrease the peak-to-peak inductor current, which typically increases efficiency by

reducing the RMS current but requires larger output capacitors to meet load-transient specifications.

3.3V

L_OUT

í

2.2MHzì 0.3ì 6A

(

)

(16)

L_OUTí 0.833mH

A standard inductor value of 1.5 µH was selected

V_OUT

3.3V

8V

D_MAX

=

= 0.413

= 0.183

V

IN MIN

(

)

(17)

(18)

V_OUT

3.3V

18V

D_MIN

=

V

IN MAX

(

)

The peak-to-peak inductor current is:

V

₎- V_OUT

L_OUT

IN MAX

D_MIN

Fsw

(

DI =

ì

(19)

18V - 3.3V 0.183

ì

= 0.815A

1.5mH

2.2MHz

(20)

(21)

(22)

DI

2

Ipk = I_OUT

+

0.815

Ipk = 6A +

= 6.41A

2

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8.2.2.3 Current Sense Resistor

When calculating the current sense resistor, the maximum output current capability (I_OUT(MAX)) must be at least

20% higher than the required full load current to account for tolerances, ripple current, and load transients. For

this example, 120% of the 6.41-A peak inductor current calculated in Inductor Calculation (I_PK) is 7.69 A. The

current sense resistor value can be calculated using:

V _CS

(

)

R_SENSE

=

I_{OUT MAX}

(

)

(23)

75mV

R_SENSE

=

= 0.00975W

7.69A

where

•

V_(CS)is the 75 mV current limit threshold

(24)

The R_SENSEvalue selected is 9 mΩ.

Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the differential

current sense signals between the CS and VOUT pins. Place the sense resistor close to the devices with short,

direct traces, creating Kelvin-sense connections between the current-sense resistor and the LM5141-Q1.

The propagation delays through the current limit comparator, logic, and external MOSFET gate drivers allow the

peak current to increase above the calculated current limit threshold. For a propagation delay of t_dly, the worst-

case peak current through the inductor with the output shorted can be calculated from:

V _CS

V

₎ì t_dly

L_OUT

IN MAX

(

)

(

Ipk_SCKT

=

+

R_SENSE

(25)

From Electrical Characteristics, t_dly1is typically 40 ns.

75mV 18V ì 40ns

Ipk_SCKT

=

+

= 8.81A

0.009W

1.5mH

(26)

Once the peak current and the inductance parameters are known, the inductor can be chosen. Select an inductor

with a saturation current greater than Ipk_SCKT(8.81 Apk).

8.2.2.4 Output Capacitor

In a switch mode power supply, the minimum output capacitance is typically selected based on the capacitor

ripple current rating and the load transient requirements. The output capacitor must be large enough to absorb

the inductor energy and limit over voltage when transitioning from full-load to no-load, and to limit the output

voltage undershoot during no-load to full load transients. The worst-case load transient from zero to full load

occurs when the input voltage is at the maximum value and a current switching cycle has just finished. The total

output voltage drop ΔV_OUTis the sum of the voltage drop while the inductor is ramping up to support the full load

and the voltage drop before the next pulse can occur.

The output capacitance required to maintain the minimum output voltage drop (ΔV_OUT) can be calculated as

follows:

L_OUTìI_STEP

²

C_{OUT MIN}

=

(

)

2ì DV_OUTìD_MAXì V

- V_OUT

(

)

IN MIN

(

)

(27)

(28)

1.5mHì 4A²

C_{OUT MIN}

=

= 186µF

(

)

2ì33mVì0.413ì 8V -3.3V

(

)

where

•

I_STEP(the transient step load current for this example) = 4 A

ΔV_OUT= 1% of 3.3 V, or 33 mV

For this example a total of 211 μF of capacitance is used, two 82-μF aluminum capacitors for energy storage and

one 47-μF low ESR ceramic capacitor to reduce high frequency noise.

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Generally, when sufficient capacitance is used to satisfy the undershoot requirement, the overshoot during a full-

load to no-load transient will also be satisfactory. After the output capacitance has been selected, calculate the

output ripple current and verify that the ripple current is within the capacitor ripple current ratings.

DI

I_{OUT RMS}

=

(

)

12

(29)

0.815A

I_{OUT RMS}

=

= 0.235A

(

)

12

(30)

8.2.2.5 Input Filter

A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality

input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current

during the buck switch on-time. When the buck switch turns on, the current drawn from the input capacitor steps

from zero to the valley of the inductor current waveform, then ramps up to the peak value, and then drops to the

zero at turn-off.

Average input current can be calculated from the total input power required to support the load at V_OUT

:

V_OUTìI_OUT

P

=

IN

h

(31)

(32)

The efficiency (η) is assumed to be 83% for this design example, yielding a total input power:

3.3 V ì 6A

P

=

= 23.86W

IN

0.83

P

IN

I_avg

=

V

IN MIN

(

)

(33)

(34)

28.6W

8V

I_avg

=

= 3.58A

The input capacitors should be selected with sufficient RMS current rating and the maximum voltage rating.

»

…

²ÿ

Ÿ

2

DI

12

I

=

Ipk -I

+

xD

+ (I_avg²ì 1-D

)

(

)

(

)

avg

MAX

IN RMS

(

)

Ÿ

⁄

(35)

(36)

0.815²

12

2

I

=

6.41A - 3.58A

+

ì0.413 + 3.58A²ì 1- 0.413 = 2.93A

(

)

(

)

(

)

IN RMS

(

)

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8.2.2.5.1 EMI Filter Design

EMI Filter Design Steps:

•

Calculate the required attenuation

Capacitor C_INrepresents the existing capacitor at the input of the switching converter (10 µF was used for this

application)

•

Inductor LF is usually selected between 1 μH and 10 μH (1.8 µH was used for this application), but can be

smaller to reduce losses in a high current design

Calculate capacitor C_F

V_IN

L_F

C_IN

C_D

R_D

C_F

Figure 29. Input EMI Filter

By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it

by the input impedance (the impedance is defined by the existing input capacitor C_IN), a formula can be derived

to obtain the required attenuation:

Ipk

»

…

ÿ

Ÿ

⁄

ì sin pìD

(

)

MAX

p²ìF_SWìC_IN

Attn = 20ìlog

- V_MAX

1mV

(37)

6.41A

p²ì 2.2MHzì10mF

»

…

ÿ

ì sin pì0.413

(

)

Ÿ

…

Attn = 20log

- 45 dBmV = 44.07dB

1mV

Ÿ

⁄

(38)

V_MAXis the allowed dBμV noise level for the particular EMI standard. C_INis the existing input capacitors of the

Buck converter, for this application 10 µF was selected. D_MAXis the maximum duty cycle, Ipk is the inductor

current, the current at the input can be modeled as a square wave, F_SWis the switching frequency.

ÿ²

Attn

»

…

40

Ÿ

1

10

C_F=

Ÿ

L_F2ì pìF

…

Ÿ

SW

…

Ÿ

⁄

(39)

2

44.07

40

≈

∆

’

÷

◊

1

10

= 0.47µF

1.8mH 2ì pì 2.2MHz

∆

«

(40)

For this application, C_Fwas chosen to be 1 μF. Adding an input filter to a switching regulator modifies the control-

to output transfer function. The output impedance of the filter must be sufficiently small such that the input filter

does not significantly affect the loop gain of the buck converter. The impedance of the filter peaks at the filter

resonant frequency.

1

F_R=

2ì p L_FC_IN

(41)

1

F_R=

= 37.53kHz

2ì p 1.8mHì10mF

(42)

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Referring to Figure 29, the purpose of R_Dis to reduce the peak output impedance of the filter at the cutoff

frequency. The capacitor C_Dblocks the dc component of the input voltage, and avoids excessive power

dissipation on R_D. The capacitor C_Dshould have lower impedance than R_Dat the resonant frequency, with a

capacitance value greater than 5 times the filter capacitor C_IN. This will prevent it from interfering with the cutoff

frequency of the main filter. Added damping is needed when the output impedance is high at the resonant

frequency (Q) of filter formed by C_INand L_Fis too high):

An electrolytic cap C_Dcan be used as damping device, with value:

L_F

R_D

=

C_IN

(43)

(44)

For this design C_D= 47 µF was selected

1.8mH

R_D

=

= 0.424W

10mF

8.2.2.5.2 MOSFET Selection

The LM5141-Q1 gate drivers are powered by the internal 5-V VCC bias regulator. To reduce power dissipation in

the controller and improve efficiency, the VCCX pin should be connected to the 5-V output or an external 5 V

bias supply. The MOSFETs used with the LM5141-Q1 require a logic-level gate threshold with R_DS(ON)specified

with V_GS= 4.5 V or lower.

The MOSFETs must be chosen with a V_DSrating to withstand the maximum V_INvoltage plus supply voltage

transients and spikes (ringing). For automotive applications, the maximum V_INoccurs during a load dump and the

voltage can surge up to 42 V under some conditions. A MOSFET with a V_DSrating of 60 V would meet most

application requirements. The N-channel MOSFETs must be capable of delivering the load current plus peak

ripple current during switching.

The high-side MOSFET losses are associated with the R_DS(ON)of the MOSFET and the switching losses.

1

P_{D HS}= I

²ìR_{DS ON}ìD_MAX

+

ì V ì t + t ìI_OUTìF_SW

IN r f

(

)

(

)

OUT

(

)

(

)

2

1

(45)

P_{D HS}= (6A)²ì0.026W ì0.413 + ì12V ì 17ns +17ns ì6A ì2.2MHz = 2.69W

(

)

(

)

(

)

2

where

•

tr = ts = 17 ns

(46)

The losses in the low side MOSFET include: R_DS(ON)losses, dead time losses, and losses in the MOSFETs

internal body diode. The body diode conducts the inductor current during the dead time before the rising edge of

the switch node; minority carriers are injected into and stored in the diode PN junction when forward biased. As

the high side FET starts to turn-on, a negative current must first flow through the diode to remove the stored

charge before the diode can block a reverse voltage. During this time, the high side drain-source voltage remains

at V_INuntil all the diode minority carriers are removed. Then, the diode begins to block negative voltage and the

reverse current continues to flow to charge the body diode depletion capacitance. The total charge involved in

this period is called reverse-recovery charge Qrr.

P_{D LO}= I

²ìR_{DS ON}ì 1-D

+ I

ì t + t_dfìF ì V

+ D_QrrìF_SWì V

IN

D FET

(

)

(

)

(

)

(

)

(

)

OUT

MAX

OUT

dr

SW

(

)

(

)

(

)

(47)

P

= (6A)²ì26mWì 1-0.413 + 6A ì 20ns + 20ns ì2.2MHzì0.8V + 105nCì2.2MHzì12V = 3.744W

(

)

(

)

(

)

(

)

(

)

D LO

(

)

where

•

t_drand t_dfare the switch node voltage rise and fall times (20 ns)

V_D(FET)is the forward voltage drop across the low-side MOSFET internal body diode (0.8 V)

D_Qrris the internal body diodes reverse recovery charge (105 nC)

R_DS(ON)is the on resistance of the MOSFETs (26 mΩ at T_J= 125ºC)

(48)

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Table 4 provides parameters for several MOSFETs that have tested in the LM5141-Q1 evaluation module.

Table 4. EVM MOSFETs

PART

NUMBER

Q_g(MAX)(nC)

V_GS= 4.5 V

R_DS(ON)

V_GS= 4.5 V (Ω)

MANUFACTURER

VISHAY

V_DS(V)

I_D(A)

C_OSS(MAX)(pF)

APPLICATION

Automotive high

power

SQJ850EP

SQ7414EN

60

24

30

32

215

Automotive low

power

VISHAY

60

5.6

13

25

36

175

217

Texas Instruments CSD18534Q5A

11.1

12.4

Industrial

8.2.2.5.3 Driver Slew-Rate Control

Figure 30 shows the high current driver outputs with independent source and current sink pins for slew-rate

control. Slew-rate control enables the user to adjust the switch node rise and fall times which can reduce the

conducted EMI in the FM radio band (30 MHz to 108 MHz). Using the LM5141-Q1 EVM, conducted emissions

were measured in accordance with CISPR 25 Class 5. Figure 31 shows the measured results without slew-rate

control.

The conducted EMI results with slew-rate control are shown in Figure 32, a 10-dB reduction in conduction

emissions in the FM band is attained by using slew-rate control. This can help reduce the size and cost of the

EMI filters.

VCC

D_BST

HB

C_BST

R_HO

HO

HOL

R_HOL

SW

VCC

C_VCC

R_LO

LO

LOL

R_LOL

PGND

Figure 30. Drivers With Slew-Rate Control

Figure 31. EMI Measurements CISPR 25 Class 5, Without Slew-Rate Control

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Figure 32. EMI Measurements CISPR 25 With Slew-Rate Control

8.2.2.5.4 Frequency Dithering

Figure 33 shows the CISPR 25 Class 5 conducted emission test run on the LM5141-Q1EVM, without the dither

feature enabled. The first harmonic (peak measurement) is 48 dBµV, Figure 34 shows the conducted emissions

test results with the dither feature enabled. With the dither featured enabled, the first harmonic (peak

measurement) was lowered to 40 dBµV, an 8-dB reduction.

Figure 33. CISPR 25 Class 5 Conducted EMI, Without Dither

30

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Figure 34. CISPR 25 Class 5 With Dither

8.2.2.6 Control Loop

The open loop gain is defined as the product of modulator transfer function and feedback transfer function. When

plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain.

DC modulator gain is:

R_LOAD

AM =

R

+ R_DCRìG

CS

(

)

SENSE

(49)

The modulator gain plus power stage transfer function with an embedded current loop is show in Equation 50.

The equation includes the sample gain at F_SW/2 (ω_n), which is caused by sampling effect of current mode

control.

≈

∆

«

’

÷

s

1+

Ù

w_{Z ◊}

V_OUT

= AMì

Ù

≈

’

V_C

s

( )

≈

∆

«

’

÷

s

s²

2

1+

ì 1+

+

∆

÷

∆

«

w_{P ◊}

w_nQ

w_{n ◊}

where

•

s = 2 × π × F_SW

1

Q =

p K - 0.5

(

)

•

1

w_Z=

C_ESRìC_OUT

1

w_p=

R_LOADìC_OUT

w_n= pìF_SW

•

K = 1

G_CSis the current sense amplifier gain which is 12

(50)

31

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Because the loop crossover frequency is well below sample gain effects, Equation 50 can be simplified as one

pole and a one zero system as shown in Equation 51.

≈

∆

«

’

÷

s

1+

Ù

V_OUT

s

w_{Z ◊}

( )

= AMì

Ù

≈

’

V_C

s

( )

s

∆

«

÷

w_p

◊

(51)

R_LOADis the load resistance

R_DCRis the dc resistance on the output inductor which is 8.1 mΩ

R_SENSEis the current sense resistance which is 9 mΩ

8.2.2.6.1 Feedback Compensator

A type II compensator using an transconductance error amplifier (EA), Gm, is shown in Figure 35. The dominant

pole of the EA open-loop gain is set by the EA output resistance, R_AMP, and effective bandwidth-limiting

capacitance, C_O, as follows:

GmR_AMP

G_{EA openloop}s = -

₎( )

(

1+ sR_AMPC_O

(52)

The EA high frequency pole is neglected in the above expression. The compensator transfer function from output

voltage to COMP, including the gain contribution from the feedback resistor divider network is:

Ù

V_C

s

( )

V_REF

V_OUT

G_Cs =

( )

= -

ìGmì Z_EAOUTs

( )

Ù

V_OUT

s

( )

(53)

(54)

R_LOWER

V_REF

=

R_LOWER+ R_UPPERV_OUT

where

≈

∆

«

’

≈

∆

«

’

1

Z_EAOUTs = Gmì R

R

+

∆

÷

◊

( )

÷

AMP

COMP

sC_{COMP ◊}sC_HFsC_O

(55)

(56)

Which simplifies to:

s

1+

w_zEA

≈

Z_EAOUTs = R

( )

AMP

≈

’

s

1+

ì 1+

∆

«

÷

◊

∆

÷

◊

∆

«

w_pEA1

w_pEA2

V_OUT

R_UPPER

Gm

+

-

C_OUT

V_C

V_REF

R_LOAD

R_COMP

C_O

C_COMP

C_ESR

C_HF

R_LOWER

R_AMP

Figure 35. Transconductance Amplifier

32

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w_zEA

SNVSAJ6D –JULY 2016–REVISED DECEMBER 2017

1

=

R_COMPìC_COMP

(57)

(58)

1

w_pEA1

=

@

R

+ R_COMP

C

+ C_HF+ C_O

R_AMPìC_COMP

(

)(

)

AMP

COMP

1

w_pEA2

=

@

R_COMPìC_HF

R_COMP

C

+ C_O

(

)

(

COMP

HF

(59)

Typically R_COMP<< R_AMPand C_COMP>> (C_HF+ C_O) so the approximations are valid.

where

V_REFis the feedback voltage reference (1.2 V)

G_mis the error amplifier gain transconductance (1200 µs)

R_AMPis the error amplifier output impedance (2.5 MΩ)

The error amplifier compensation components create a pole at the origin, a zero, and a high frequency pole.

The procedure for choosing compensation components for a stable closed loop is:

•

Select the desired open loop gain crossover frequency (fc); for this application 30 kHz was chosen

Calculate the R_COMPresistor for the gain crossover frequency at 30 kHz

2ì pìC_OUTì R

+R_DCRìG

V_OUT

V_REF

(

)

SENSE

CS

R_COMP= fc

ì

Gm

(60)

(61)

2ì pì 293mFì 0.009W + 0.0081W ì12

(

)

3.3V

1.2V

R_COMP= 30KHzì

ì

= 25927W

1200ì10^-6mS

The value selected for R_COMPis 22.6 kΩ.

where

R_DCR= 0.0081 Ω

•

Calculate the C_COMPcapacitor value to create a zero that cancels the pole ω_p( ω_p= 1/R_LOAD× C_OUT

)

R_LOADìC_OUT

C_COMP

=

R_COMP

(62)

(63)

0.477Wì 290mF

22.6kW

C_COMP

=

= 6nF

The value selected for C_COMPis 10 nF.

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8.2.3 Application Curves

The Bode plots of the modulator and plus power stage are shown in refer to Figure 36. The results of the total

loop gain crossover frequency are 40 kHz with 112º of phase margin, (see Figure 37).

Figure 36. (V_OUT/V_C) Modulator Gain and Phase

Figure 37. Loop Gain and Phase

34

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9 Power Supply Recommendations

The LM5141-Q1EVM is designed to operate over an input voltage supply range between 5.5 V and 42 V. The

input supply must be well regulated. If the power source is located more than a few inches from the LM5141-Q1

EVM, additional bulk capacitance and ceramic bypass capacitors may be required at the power supply input. An

electrolytic capacitor with a value of 47 μF is typically a good choice.

10 Layout

10.1 Layout Guidelines

Careful PCB layout is critical to achieve low EMI and stable power supply operation. Make the high frequency

current loops as small as possible, and follow these guidelines of good layout practices:

1. Keep the high-current paths short. This is essential for stable, jitter-free operation.

2. Keep the power traces and load connections short. This is essential for high efficiency. Using 2 oz or thicker

copper can enhance full load efficiency.

3. Minimize current-sensing errors by routing CS and VOUT using a kelvin sensing directly across the current

sense resistor (R_SENSE).

4. Route high-speed switching nodes (HB, HO, LO, and SW) away from sensitive analog signals (FB, CS, and

VOUT).

10.1.1 Layout Procedure

Place the power components first, with ground terminals adjacent to the low-side FET.

•

Mount the controller IC as close as possible to the high and low-side MOSFETs. Make the grounds and high

and low-sided drive gate drive lines as short and wide as possible. Place the series gate drive resistor as

close to the MOSFET as possible to minimize gate ringing.

•

Locate the gate drive components (D1 and C12) together and near the controller IC; refer to Figure 38. Be

aware that peak gate drive currents can be as high as 4 A. Average current up to 75 mA can flow from the

VCC pin to the V_CCcapacitor through the bootstrap diode to the bootstrap capacitor. Size the traces

accordingly.

•

Figure 39 shows the high frequency loops of the synchronous buck converter. The high frequency current

flows through Q1 and Q2, through the power ground plane and back to V_INthrough the ceramic capacitors

C6, C7, and C8. This loop must be as small as possible to minimize EMI. Refer to Figure 41 and Figure 42

for the recommended PCB layout.

Make the PGND and AGND connections to the LM5141-Q1 controller as shown in Figure 40. Create a power

grounds directly connected to all high-power components and an analog ground plane for sensitive analog

components. The analog ground plane (AGND) and power ground plane (PGND) must be connected at a

single point directly under the IC (at the die attach pad or DAP).

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10.2 Layout Examples

Figure 38. EVM Top Side

Figure 39. EVM Bottom Layer, High Frequency Current Loop

36

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Layout Examples (continued)

Figure 40. AGND and PGND Connections

Figure 41 and Figure 42 show the top and bottom layer of the LM5141-Q1 EVM.

Figure 41. EVM Top Layer

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Layout Examples (continued)

Figure 42. EVM Bottom Layer

38

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11 Device and Documentation Support

11.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5141-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Mechanical, Packaging, and Orderable Information

Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

W

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

LM5141QRGERQ1

LM5141QRGETQ1

LM5141QURGERQ1

VQFN

RGE0024J

RGE0024B

24

3000

250

330.0

180.0

330.0

12.4

4.3

1.1

8.0

12.0

Q2

3000

–

7

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Mechanical, Packaging, and Orderable Information

TAPE AND REEL BOX DIMENSIONS

www.ti.com

Width (mm)

H

W

L

Device

Package Type

VQFN

Package Drawing Pins

SPQ

3000

250

Length (mm) Width (mm)

Height (mm)

38.0

LM5141QRGERQ1

LM5141QRGETQ1

LM5141QURGERQ1

RGE0024J

RGE0024B

24

367.0

213.0

367.0

191.0

367.0

VQFN

35.0

VQFN

3000

38.0

8

–

Submit Document Feedback

PACKAGE OUTLINE

RGE0024B

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

0.5

0.3

PIN 1 INDEX AREA

4.1

3.9

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.2) TYP

2.45 0.1

7

12

EXPOSED

SEE TERMINAL

DETAIL

THERMAL PAD

13

6

2X

SYMM

25

2.5

18

1

0.3

24X

20X 0.5

0.2

19

24

0.1

C A B

SYMM

24X

PIN 1 ID

(OPTIONAL)

0.05

0.5

0.3

4219013/A 05/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGE0024B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.45)

SYMM

24

19

24X (0.6)

1

18

24X (0.25)

(R0.05)

TYP

25

SYMM

(3.8)

20X (0.5)

13

6

(

0.2) TYP

VIA

7

12

(0.975) TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219013/A 05/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGE0024B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.08)

(0.64) TYP

19

24

24X (0.6)

1

25

18

24X (0.25)

(R0.05) TYP

SYMM

(0.64)

TYP

(3.8)

20X (0.5)

13

6

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219013/A 05/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

RGE0024J

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

0.5

0.3

A

0.3

0.2

PIN 1 INDEX AREA

DETAIL

OPTIONAL TERMINAL

TYPICAL

4.1

3.9

0.1 MIN

(0.05)

SECTION A-A

SCALE 25.000

SECTION A-A

TYPICAL

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.2) TYP

2.45 0.1

7

12

A

EXPOSED

THERMAL PAD

SEE TERMINAL

DETAIL

13

6

A

2X

SYMM

25

2.5

18

1

0.3

0.2

24X

20X 0.5

19

24

0.1

0.05

C A B

SYMM

24X

PIN 1 ID

(OPTIONAL)

0.5

0.3

4223242/A 08/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGE0024J

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.45)

SYMM

24

19

24X (0.6)

1

18

24X (0.25)

(R0.05)

TYP

25

SYMM

(3.8)

20X (0.5)

13

6

(

0.2) TYP

VIA

7

12

(0.975) TYP

(3.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223242/A 08/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGE0024J

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.08)

(0.64) TYP

19

24

24X (0.6)

1

25

18

24X (0.25)

(R0.05) TYP

SYMM

(0.64)

TYP

(3.8)

20X (0.5)

13

6

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223242/A 08/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM5141-Q1_V01
厂家：	TEXAS INSTRUMENTS
描述：	LM5141-Q1 Wide Input Range Synchronous Buck Controller
文件：	总49页 (文件大小：2866K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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