LM5141RGET [TI]
低 IQ、宽输入范围同步降压控制器 | RGE | 24 | -40 to 125;型号: | LM5141RGET |
厂家: | TEXAS INSTRUMENTS |
描述: | 低 IQ、宽输入范围同步降压控制器 | RGE | 24 | -40 to 125 控制器 开关 输出元件 |
文件: | 总53页 (文件大小:3975K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LM5141
ZHCSG18 –MARCH 2017
LM5141 宽输入范围同步降压控制器
1 特性
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2 应用
1
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–40ºC 至 +125ºC 的环境工作温度范围
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医疗设备
AEC-Q100 合格器件
工业可编程逻辑控制器
工业计算机
VIN:3.8V 到 65V(70V 最大绝对值)
输出:3.3V 或 5V 的固定电压;
1.5V - 15V 的可调电压(精度为 ±0.8%)
嵌入式计算机
•
•
•
•
•
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2.2MHz 或 440kHz 固定开关频率,精度为 ±5%
具有压摆率控制的高侧和低侧栅极驱动器
通过改变模拟电压或 RT 电阻实现可选频移
可选择与外部时钟保持同步
3 说明
LM5141 是一款同步降压转换器,适用于高电压宽输入
电压的降压转换器 。此控制方法基于峰值电流模式控
制。电流模式控制可提供内部线路前馈、逐周期电流限
制和简化的环路补偿。LM5141 具有 压摆率控制功
能,能够轻松满足 EMI 要求。
可选扩展频谱
关断模式 IQ:10µA(典型值)
低功耗待机模式 IQ:35µA(典型值)
限流阈值为 75mV,精度为 ±0.9%
外部电阻或 DCR 电流感测
LM5141 有两种开关频率可选:2.2MHz 和 440kHz。
栅极驱动器具有压摆率控制功能,可通过调整来降低
EMI。
输出使能逻辑输入
针对持续过载条件的断续模式
电源正常指示输出
在轻负载或无负载条件下,LM5141 通过在跳周期模式
下运行来提升轻载效率。LM5141 具备能够自动切换至
外部偏置电源的高电压偏置稳压器,可以降低来自 VIN
的 IQ 电流。其他特性 包括频率同步、逐周期电流限
制、针对持续过载条件的断续模式故障保护以及电源正
常输出。
可选二极管仿真或强制脉冲宽度调制
具有可湿性侧面的薄型四方扁平无引线 (QFN)-24
封装
结合使用 LM5141 和 WEBENCH® 电源设计器创建
定制设计
•
器件信息(1)
器件型号
LM5141
封装
QFN (24)
封装尺寸(标称值)
4.00mm x 4.00mm
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
简化电路原理图
VIN
CIN
VIN
VCC
CVCC
DBST
CBST
HB
HO
RES
SS
LOUT
VOUT
HOL
SW
RSENSE
DITH
LM5141-Q1
COUT
LO
CRES
CSS
CDITH
LOL
PGND
PG
CS
EN
DEMB
VOUT
VCCX
RCOMP CCOMP
COMP
FB
AGND
RT
OSC VDDA
RT
CVDDA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSAU0
LM5141
ZHCSG18 –MARCH 2017
www.ti.com.cn
目录
7.3 Feature Description................................................. 13
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 22
Power Supply Recommendations...................... 35
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 8
6.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Examples................................................... 36
11 器件和文档支持 ..................................................... 39
11.1 使用 WEBENCH® 工具创建定制设计 ................... 39
11.2 接收文档更新通知 ................................................. 39
11.3 社区资源................................................................ 39
11.4 商标....................................................................... 39
11.5 静电放电警告......................................................... 39
11.6 Glossary................................................................ 39
12 机械、封装和可订购信息....................................... 40
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2017 年 3 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
5 Pin Configuration and Functions
RGE Package
24-Pin QFN With Exposed Thermal Pad
Top View
DEMB
VDDA
AGND
RT
1
2
3
4
5
6
18
17
16
15
14
13
CS
VOUT
VCCX
VIN
Thermal
Pad
DITH
OSC
HOL
HO
Not to scale
Connect Exposed Pad on bottom to AGND and PGND on the PCB.
Pin Functions
PIN
TYPE
NAME
DESCRIPTION
NO.
Diode Emulation pin. Connect the DEMB pin to AGND to enable diode emulation. If it is
connected to VDDA the LM5141 operates in Forced PWM (FPWM) mode with continuous
conduction at light loads. The DEMB pin can also be used as a synchronization input, to
synchronize the internal oscillator to an external clock.
1
DEMB
I
2
3
VDDA
AGND
P
Internal analog bias regulator output. Connect a capacitor from the VDDA pin to AGND.
Analog ground connection. Ground return for the internal voltage reference and analog
circuits.
G
A resistor from the RT pin to ground shifts the oscillator frequency up or down from 2.2 MHz
(1.8 MHz to 2.53 MHz), or 440 kHz (300 kHz to 500 kHz). An analog voltage can be applied
to the RT pin (through a resistor) to shift the oscillator frequency.
4
RT
I
A capacitor connected between the DITH pin and AGND is charged and discharged with a
20 µA current source. If Dither is enabled, the voltage on the DITH pin ramps up and down
modulating the oscillator frequency between –5% and +5% of the internal oscillator.
Connecting DITH to VDDA will disable the dithering feature. DITH is ignored if an external
synchronization clock is used.
5
6
DITH
OSC
O
I
Frequency selection pin. Connecting the OSC pin to VDDA sets the oscillator frequency to
2.2 MHz. Connecting the OSC pin to AGND sets the frequency to 440 kHz.
7
LOL
LO
O
O
G
P
P
Low-side gate driver turn-off output.
8
Low-side gate driver turn-on output.
9
PGND
VCC
HB
Power ground connection pin for low-side NMOS gate driver.
VCC bias supply pin. Connect a capacitor from the VCC pin to PGND.
High-side driver supply for bootstrap gate drive.
10
11
Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal
of the high-side MOSFET and the drain terminal of the low-side MOSFET.
12
SW
13
14
HO
O
O
High-side gate driver turn-on output.
High-side gate driver turn-off output.
HOL
Copyright © 2017, Texas Instruments Incorporated
3
LM5141
ZHCSG18 –MARCH 2017
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
15
VIN
P
Supply voltage input source for the VCC regulator
Optional input for an external bias supply. If VCCX > 4.5 V, VCCX is internally connected to
the VCC pin and the internal VCC regulator is disabled. If VCCX is unused, it should be
grounded.
16
VCCX
P
Current sense amplifier input. Connect this pin to the output side of the current sense
resistor.
17
18
VOUT
CS
I
I
Current sense amplifier input. Make a low current Kelvin connection between this pin and the
inductor side of the external current sense resistor.
Connect the FB pin to VDDA for a fixed 3.3-V output or connect FB to AGND for a fixed 5-V
output. Connecting the FB pin to the appropriate output divider network will set the output
voltage between 1.5 V and 15 V. The regulation threshold at the FB pin is 1.2 V.
19
FB
I
20
21
COMP
PG
I
Output of the transconductance error amplifier.
O
An open collector output which switches low if VOUT is outside of the power good window.
Soft-start programming pin. An external capacitor and an internal 20-μA current source set
the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below
80 mV turns-off the gate driver outputs, but all the other functions remain active.
22
23
SS
EN
I
I
An active high logic input enables the controller.
Restart timer pin. An external capacitor configures the hiccup mode current limiting. The
capacitor at the RES pin determines the time the controller will remain off before
automatically restarting in hiccup mode. The hiccup mode commences when the controller
experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connecting
the RES pin to VDD during power up disables hiccup mode protection.
24
RES
O
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–5
MAX
70
UNIT
V
VIN
SW to PGND
70
V
SW to PGND (20 ns transient)
HB to SW
V
–0.3
–5
6.5
V
HB to SW (20 ns transient)
HO, HOL to SW
V
–0.3
–5
HB + 0.3
VCC + 0.3
V
Input voltage
HO, HOL to SW (20 ns transient)
LO, LOL to PGND
V
–0.3
–1.5
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–65
V
LO, LOL to PGND (20 ns transient)
OSC, SS, COMP, RES, DEMB, RT, DITH
EN to PGND
V
VDD + 0.3
70
V
V
VCC, VCCX, VDD, PG, FB
VOUT, CS
6.5
V
15.5
0.3
V
PGND to AGND
Operating junction temperature(2)
V
150
°C
°C
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
4
Copyright © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
3.8
NOM
MAX
65
UNIT
VIN
V
V
V
V
V
SW to PGND
HB to SW
–0.3
–0.3
–0.3
–0.3
65
5
5
5.25
HO, HOL to SW
LO, LOL to PGND
HB + 0.3
5.25
VIN
Input voltage
FB, PG, OSC, SS, RES, DEMB,
VCCX
–0.3
5
V
EN to PGND
VCC, VDD
VOUT, CS
–0.3
–0.3
1.5
65
5.25
15
V
V
5
5
V
PGND to AGND
Operating junction temperature(2)
–0.3
–40
0.3
V
125
°C
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM5141
THERMAL METRIC(1)
RGE (QFN)
24 PINS
34.1
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
36.8
12.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJB
12.2
RθJC(bot)
2.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
5
LM5141
ZHCSG18 –MARCH 2017
www.ti.com.cn
6.5 Electrical Characteristics
TJ = –40°C to +125°C, Typical values TJ = 25°C, VIN = 12 V, VCCX = 5 V, VOUT = 5 V, EN = 5 V, OSC = VDD, FSW = 2.2
MHz, no-load on the Drive Outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless
otherwise noted)(1)(2)
PARAMETER
VIN SUPPLY VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISHUTDOWN
Shutdown mode current
Standby current
VIN = 8–18 V, EN = 0 V, VCCX = 0 V
10
35
12.5
45
µA
EN = 5 V, FB = VDD, VOUT in
regulation, no-load, not switching,
DEMB = GND.
ISTANDBY
µA
EN = 5 V, FB = 0 V, VOUT in
regulation, no-load, not switching,
VCCX = 5 V, DEMB = GND.
42
55
VCC REGULATOR
VCC(REG)
VCC(UVLO)
VCC(HYST)
ICC(LIM)
VCC regulation voltage
VIN = 6–18 V, 0–75 mA, VCCX = 0 V
VCC rising, VCCX = 0 V
VCCX = 0 V
4.75
3.25
5
3.4
5.25
3.55
V
V
VCC under voltage threshold
VCC hysteresis voltage
175
125
mV
mA
VCC sourcing current limit
VCCX = 0 V
85
VDDA
VDDA(REG) Internal bias supply power
VDDA(UVLO
VCCX = 0 V
4.75
3.1
5
3.2
125
55
5.25
3.3
V
V
)
VCC rising, VCCX = 0 V
VCCX = 0 V
VDDA(HYST)
mV
Ω
RVDDA
VCCX = 0 V
VCCX
VCCX(ON)
VCC rising
4.1
2.0
4.3
80
2
4.4
V
mV
Ω
VCCX(HYST)
R(VCCX)
VCCX = 5 V
OSCILLATOR SELECT THRESHOLDS
Oscillator select threshold 2.2 MHz (OSC pin)
V
V
Oscillator select threshold 440 kHz
(OSC pin)
0.8
82
CURENT LIMIT
ILSET = VDDA, measure from CS to
VOUT
V(CS)
tdly
Current limit threshold
68
75
mV
Current sense delay to output
Current sense amplifier gain
Amplifier input bias
40
12
ns
V/V
nA
11.4
12.6
10
ICS(BIAS)
RES
I(RES)
RES current source
RES threshold
20
1.2
512
4
µA
V
V(RES)
Timer
Timer hiccup mode fault
RES pull-down
cycles
Ω
RDS(ON)
OUTPUT VOLTAGE REGULATION
3.3 V
5 V
VIN = 3.8–42 V
VIN = 5.5–42 V
3.273
4.96
3.3
5.0
3.327
5.04
V
V
FEEDBACK
VOUT select threshold 3.3 V
Regulated feedback voltage
VDD - 0.3
1.193
V
V
1.2
1.207
500
Resistance to ground on FB for FB
= 0 detection
FB(LOWRES)
Ω
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
(2) The junction temperature (TJ in ºC) is calculated from the ambient temperature (TA in ºC) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD × RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.
6
Copyright © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
Electrical Characteristics (continued)
TJ = –40°C to +125°C, Typical values TJ = 25°C, VIN = 12 V, VCCX = 5 V, VOUT = 5 V, EN = 5 V, OSC = VDD, FSW = 2.2
MHz, no-load on the Drive Outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless
otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Thevenin equivalent resistance at
FB for external regulation detection
FB(EXTRES)
FB < 2 V
5
kΩ
TRANSCONDUCTANCE AMPLIFIER
Gm
Gain
Feedback to COMP
1010
1200
µS
nA
Input bias current
15
Transconductance Amplifier source
current
COMP = 1 V, FB = 1 V
COMP = 1 V, FB = 1.4 V
100
100
µA
µA
Transconductance Amplifier sink
current
POWER GOOD
Falling with respect to the regulation
voltage
PG(UV)
PG under voltage trip levels
90%
92%
94%
Rising with respect to the regulation
voltage
PG(OVP)
PG over voltage trip levels
108%
110%
3.4%
112%
PG(HYST)
PG(VOL)
PG(rdly)
PG(fdly)
PG
Open collector, Isink = 2 mA
VOUT rising
0.4
V
OV filter time
UV filter time
25
30
µs
µs
VOUT falling
HO GATE DRIVER
VOLH
VOHH
trHO
HO Low-state output voltage
IHO = 100 mA
0.05
0.07
4
V
V
HO High-state output voltage
HO rise time (10% to 90%)
HO fall time (90% to 10%)
IHO = –100 mA, VOHH = VHB - VHO
CLOAD = 2700 pf
ns
ns
tfHO
CLOAD = 2700 pf
3
VHO = 0 V, SW = 0 V, HB = 5 V,
VCCX = 5 V
IOHH
IOLH
V(BOOT)
I(BOOT)
HO peak source current
3.25
Apk
HO peak sink current
UVLO
VCCX = 5 V
HO falling
4.25
2.5
110
3
Apk
V
Hysteresis
mV
µA
Quiescent current
LO GATE DRIVER
VOLL
VOHL
trLO
LO Low-state output voltage
ILO = 100 mA
0.05
0.07
4
V
V
LO High-state output voltage
LO rise time (10% to 90%)
LO fall time (90% to 10%)
LO peak source current
LO peak sink current
ILO = –100 mA, VOHL = VCC - VLO
CLOAD = 2700 pf
CLOAD = 2700 pf
VCCX = 5 V
ns
tfLO
3
ns
IOHL
IOLL
3.25
4.25
Apk
Apk
VCCX = 5 V
ADAPTIVE DEAD TIME CONTROL
V(GS-DET)
tdly1
VGS detection threshold
HO off to LO on dead time
LO off to HO on dead time
VGS falling, no-load
2.5
20
20
V
40
38
ns
ns
tdly2
DIODE EMULATION
VIL
DEMB input low threshold
0.8
V
V
VIH
SW
FPWM input high threshold
Zero cross threshold
2.0
–5
mV
Copyright © 2017, Texas Instruments Incorporated
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LM5141
ZHCSG18 –MARCH 2017
www.ti.com.cn
Electrical Characteristics (continued)
TJ = –40°C to +125°C, Typical values TJ = 25°C, VIN = 12 V, VCCX = 5 V, VOUT = 5 V, EN = 5 V, OSC = VDD, FSW = 2.2
MHz, no-load on the Drive Outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless
otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE INPUT
VIL
VIH
IIkg
Enable input low threshold
Enable input high threshold
Leakage
VCCX = 0 V
0.8
V
V
VCCX = 0 V
2.0
EN logic input only
1
µA
SYN INPUT (DEMB pin)
VIL
VIH
DEMB input low threshold
0.8
V
V
DEMB input high threshold
2.0
DEMB input low frequency range
440 kHz
350
550
kHz
kHz
DEMB input high frequency range
2.2 MHz
1800
2600
DITHER
IDITHER
Dither source/sink current
Dither high threshold
Dither low threshold
20
1.26
1.14
µA
V
VDITHER
V
SOFT-START
ISS
Soft-Start current
16
22
3
28
µA
RDS(ON)
Soft-Start pull-down resistance
Ω
THERMAL
TSD Thermal Shutdown
175
15
ºC
ºC
Thermal shutdown hysteresis
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2100
420
TYP
MAX
UNIT
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
Oscillator Frequency 2.2 MHz
Oscillator Frequency 440 kHz
OSC = VDDA, VIN = 8–18 V
OSC = GND, VIN = 8–18 V
OSC = VDD, RTMIN = 61.9 kΩ
OSC = VDD, RTTYP = 49.9 kΩ
OSC = VDD, RTMAX = 43.2 kΩ
OSC = GND, RTMIN = 73.2 k
OSC = GND, RTTYP = 49.9 kΩ
OSC = GND, RTMAX = 44.2 kΩ
2200
440
2300
460
Minimum
1710
2100
2405
285
1800
2200
2530
300
1890
2300
2655
315
Adjustment
RT
RT
Range
Typical
2.2 MHz
Maximum
Minimum
Typical
Adjustment
Range
420
440
460
440 kHz
Maximum
475
500
525
Response
time
RT
RT
RT
RT= 61.9–43.2 kΩ
RT = 43.2–61.9 kΩ
2
µs
µs
µs
Response
time
3.5
Response
time
16
45
ton
toff
Minimum on-time
Minimum off-time
66
ns
ns
100
8
Copyright © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
6.7 Typical Characteristics
At TA = 25ºC, unless otherwise noted
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
VIN 8 V
VIN 12 V
VIN 18 V
VIN 8 V
VIN 12 V
VIN 18 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
EN = 12 V
FPWM
Output Current (A)
EN = 12 V
DEMB
D001
D002
VIN 8–18 V
VOUT 5 V
2.2 MHz
VIN 8–18 V
VOUT 5 V
2.2 MHz
Figure 1. Efficiency vs IOUT
Figure 2. Efficiency vs IOUT
12
10
8
70
65
60
55
50
45
40
35
30
25
125èC
25èC
-40èC
6
4
VIN 8 V
VIN 12 V
VIN 18 V
2
0
8
9
10
11
12
13
14
15
16
17
18
-50 -30 -10 10
30
50
70
90 110 130 150
VIN (V)
Temperature (èC)
D003
D0041
EN = 12 V
VIN 8–18 V
EN = 0 V
Figure 3. ISTANDBY vs VIN
Figure 4. ISHUTDOWN vs Temperature
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
3.50
3.48
3.46
3.44
3.42
3.40
3.38
3.36
3.34
3.32
3.30
6
7
8
9
10
11
12
13
14
15
16
17
18
-60
-40
-20
0
20
40
60
80
100
120
140
VIN (V)
Temperature (°C)
D005
D006
VIN 6-18 V
EN = GND
Figure 5. VCC(REG) vs VIN
VIN 8–18 V
EN = 12 V
Figure 6. VCC(UVLO) vs Temperature
Copyright © 2017, Texas Instruments Incorporated
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Typical Characteristics (continued)
At TA = 25ºC, unless otherwise noted
5.25
3.30
3.28
3.26
3.24
3.22
3.20
3.18
3.16
3.14
3.12
3.10
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
-60
-40
-20
0
20
40
60
80
100
120
140
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
D007
D008
VCC Rising
EN = 12 V
VCC Rising
EN = 12 V
Figure 7. VDD(REG) vs Temperature
Figure 8. VDD(UVLO) vs Temperature
4.50
4.45
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
13.00
12.80
12.60
12.40
12.20
12.00
11.80
11.60
11.40
11.20
11.00
-60
-40
-20
0
20
40
60
80
100
120
140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (°C)
D009
Temperature (èC)
D010
VCC Rising
EN = 12 V
VIN 12 V
EN = 12 V
Figure 9. VCCX(ON) vs Temperature
Figure 10. Current Sense Amplifier Gain vs Temperature
3.32
3.31
3.3
5.000
+125èC
+25èC
-40èC
+125èC
+25èC
-40èC
4.995
4.990
4.985
4.980
4.975
4.970
4.965
4.960
4.955
4.950
3.29
3.28
3.27
3.26
3.25
3.24
3.23
3.22
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
Output Current (V)
D011
D012
VIN 12 V
FB = VDDA
EN = 12 V
VIN 12 V
EN = 12 V
FB = GND
Figure 11. 3.3-V Output Voltage Regulation vs IOUT
Figure 12. 5-V Output Voltage Regulation vs IOUT
10
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ZHCSG18 –MARCH 2017
Typical Characteristics (continued)
At TA = 25ºC, unless otherwise noted
2400
470
465
460
455
450
445
440
435
430
425
420
415
410
2340
2280
2220
2160
2100
2040
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
Temperature (èC)
D013
D014
VIN 12 V
EN = 12 V
OSC = VDDA
VIN 12 V
EN = 12 V
OSC = AGND
Figure 13. 2.2-MHz Oscillator Frequency vs Temperature
Figure 14. 440-kHz Oscillator Frequency vs Temperature
110
90
105
100
95
90
85
80
75
70
65
60
80
70
60
50
40
30
20
10
0
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
Temperature (èC)
D015
D016
VIN 18 V
VIN 3.8 V
VOUT 3.3 V
Figure 15. ton Minimum vs Temperature
Figure 16. toff Minimum vs Temperature
2600
2500
2400
2300
2200
2100
2000
1900
1800
1700
1600
600
560
520
480
440
400
360
320
280
240
200
RT 49.9 kΩ
-60 -40 -20 20
RT 43.2 kΩ
RT 61.9 kΩ
80 100 120 140
RT 49.9 kW
-60 -40 -20 20
RT 44.2 kW
RT 73.2 kW
0
40 60
Temperature (°C)
0
40
60
80 100 120 140
Temperature (èC)
D017
D018
VIN 12 V
Figure 17. RT Frequency vs Temperature (2.2 MHz)
VIN 12 V
Figure 18. RT Frequency vs Temperature (440 kHz)
Copyright © 2017, Texas Instruments Incorporated
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LM5141
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7 Detailed Description
7.1 Overview
The LM5141 is a switching controller which features all of the functions necessary to implement a high efficiency
buck power supply that can operate over a wide input voltage range. The LM5141 is configured to provide a
single fixed 3.3 V, or 5.0 V output, or an adjustable output between 1.5 V to 15 V. This easy to use controller
integrates high-side and low-side MOSFET drivers capable of sourcing 3.25 A and sinking 4.25 A peak. The
control method is current mode control which provides inherent line feed-forward, cycle-by-cycle current limiting,
and ease of loop compensation. With the OSC pin connected to VDD, the default oscillator frequency is 2.2 MHz.
With the OSC pin grounded, the oscillator frequency is 440 kHz. The LM5141 can be synchronized by applying
an external clock to the DEMB pin. Fault protection features include current limiting, thermal shutdown, and
remote shutdown capability.
The LM5141 has optional spread spectrum to reduce the peak EMI and gate drivers with slew rate control. The
QFN-24 package features an exposed pad to aid in thermal dissipation.
7.2 Functional Block Diagram
VIN
VCCX
BIAS
VREF 1.2 V
VCC
VDDA
CONTROL
VDDA
RES
20 uA
CL
RESTART
LOGIC
HICCUP FAULT
TIMER 256 CYCLES
CLK
DEMB
OSC
RT
OUT
DEMB/
FPWM/
SYNIN
EN
CL
CURRENT
LIMIT
DITH
Gain = 12
75 mV
+
CS
+
SLOPE
COMPENSATION
RAMP
HB1 UVLO
HB
VOUT
3.3 V
5 V
VOUT
DECODER/
MUX
DEMB
OUT
+
HO
HOL
FB
SS
LEVEL SHIFT
ADAPTIVE
DEAD TIME
SW
+
PWM
VCC
R
S
Q
Q
STBY
SSCOMPLETE
1200 uS
FBi
VREF
CLK
LO
LOL
20 uA
SS
+
+
PGND
AGND
SS
COMP
PG
STBY
1.356 V
1.056 V
PGOV
+
PGDLY
25 us
STAND-BY
PGUV
+
+
+
VSTBY
Copyright © 2016, Texas Instruments Incorporated
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LM5141
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ZHCSG18 –MARCH 2017
7.3 Feature Description
7.3.1 High Voltage Start-up Regulator
The LM5141 contains an internal high voltage VCC bias regulator that provides the bias supply for the PWM
controller and the gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an
input voltage source up to 65 V. The output of the VCC regulator is set to 5 V. When the input voltage is below
the VCC set-point level, the VCC output will track VIN with a small voltage drop. In high voltage applications
extra care should be taken to ensure the VIN pin does not exceed the absolute maximum voltage rating of 70 V
including line or load transients. Voltage ringing on the VIN pin that exceeds the Absolute Maximum Ratings can
damage the IC. Use a high quality bypass capacitor between VIN and ground to minimize ringing.
7.3.2 VCC Regulator
The VCC regulator output current limit is 75 mA (minimum). At power-up, the regulator sources current into the
capacitors connected to the VCC pin. When the voltage on the VCC pin exceeds 3.4 V the output is enabled and
the soft-start sequence begins. The output remains active unless the voltage on the VCC pin falls below the
VCC(UVLO) threshold of 3.2 V (typical) or the enable pin is switched to a low state. The recommended range for
the VCC capacitor is 2.2 µF to 4.7 µF
An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 100-nF or greater ceramic
capacitor to ensure a low noise internal bias rail. Normally VDDA is 5 V, but there are two operating conditions
where it regulates at 3.3 V. The first is in skip cycle mode with VOUT of 3.3 V. The second is when VIN is less
than 5 V. Under these conditions both VCC and VDD will drop below 5 V. Internal power dissipation in the VCC
Regulator can be minimized by connecting the VCCX pin to a 5 V output or to an external 5 V supply. If VCCX >
4.5 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. If VCCX is unused, it
should be grounded. Never connect the VCCX pin to a voltage greater than 6.5 V.
7.3.3 Oscillator
The LM5141 has an internal trimmed oscillator with two frequency options: 2.2 MHz, or 440 kHz. With the OSC
pin connected to VDDA the oscillator frequency is 2.2 MHz. With the OSC pin grounded, the oscillator frequency
is 440 kHz. The state of the OSC pin is read and latched during VCC power-up and cannot be changed until
VCC drops below the VCC(UVLO) threshold.
The oscillator frequency can be modulated up or down from the nominal oscillator frequency (2.2 MHz or 440
kHz) on demand by connecting a resistor from the RT pin to ground (refer to Figure 19). To disable the
frequency modulation option, the RT pin can be grounded or left open. If the RT pin is connected to ground
during power-up the frequency modulation option is latch-off and cannot be changed unless VCC is allowed to
drop below the VCC(UVLO) threshold. If the RT pin is left open during power-up the frequency modulation option
will be disabled, but it can be enabled at a later time by switching in a valid RT resistor. When the frequency
modulation option is disabled, the LM5141 will operate at the internal oscillator frequency (2.2 MHz or 440 kHz).
On power up, after soft-start is complete and the output voltage is in regulation, a 16 µs timer is initiated. If a
valid RT resistor is connected, the LM5141 will switch to the frequency set by the RT resistor n the completion of
the 16 µs time delay.
The modulation range for 2.2 MHz is 1.8 MHz to 2.53 MHz (refer to Table 1). If an RT resistor value > 95 kΩ
(typical) is placed on the RT pin, the LM5141 controller will assume that the RT pin is open, and will use the
internal oscillator. If an RT resistor < 27 kΩ (typical) is connected, the controller will use the internal oscillator. To
calculate an RT resistor for a specific oscillator frequency, use Equation 1 for the 2.2 MHz frequency range or
Equation 2 for the 440 kHz frequency range.
1
- 0.0216
Fsw
RT2.2 MHz
=
0.0086
where
•
RT is kΩ and Fsw is in MHz
(1)
13
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LM5141
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www.ti.com.cn
Feature Description (continued)
1
-1.38ì10-5
Fsw
RT440 kHz
=
4.5ì10-5
where
•
RT is in kΩ and Fsw is in kHz
(2)
Table 1. RT Resistance vs Oscillator Frequency
RT Resistance (Typical)
2.2 MHz
2.2 MHZ Oscillator
Range (Typical)
RT Resistance (Typical) 440 kHz Oscillator
S1
S2
440 kHz
Range (Typical)
X
X
> 95 kΩ
61.98 kΩTotal
50.18 kΩTotal
43.2 kΩ
Internal Oscillator
1.8 MHz
> 95 kΩ
Internal Oscillator
300 kHz
OFF
OFF
ON
X
OFF
ON
OFF
X
73.8 kΩTotal
50.1 kΩTotal
44.2 kΩ
2.2 MHz
440 kHz
2.53 MHz
500 kHz
< 27 kΩ
Internal Oscillator
< 27 kΩ
Internal Oscillator
LM5141-Q1
VDDA
OSC
RT
43.2 k
6.98 k
S1
S2
11.8 k
Copyright © 2016, Texas Instruments Incorporated
Figure 19. RT Connection Circuit, 2.2 MHz
LM5141-Q1
OSC
RT
44.2 k
S1
S2
5.9 k
23.7 k
Copyright © 2016, Texas Instruments Incorporated
Figure 20. RT Connection Circuit, 440 kHz
14
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LM5141
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ZHCSG18 –MARCH 2017
An alternative method to modulate the oscillator frequency is to use an analog voltage connected to the RT pin
through a resistor. See Figure 21. An analog voltage of 0.0 V to 0.6 V will modulate the oscillator frequency
between 1.8 MHz to 2.53 MHz (OSC at 2.2 MHz), or 300 kHz to 500 kHz (OSC at 440 kHz). The analog voltage
source must be able to sink current.
DEM/SYNC
LM5141-Q1
OSC
RT
44.2 k
0 V œ 6 V
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Analog Voltage Control of the Oscillator Frequency
When the LM5141 is in the low IQ standby mode, the controller will set the RT pin to a high impedance state and
ignore the RT resistor. After coming out of standby mode, the controller will monitor the RT pin. If a valid resistor
is connected, and there have been 16 µs of continuous switching without a zero-crossing event, the LM5141 will
switch to the frequency set by the RT resistor.
7.3.4 Synchronization
To synchronize the LM5141 to an external source, apply a logic level clock signal to the DEMB pin. The
synchronization range is 350 kHz to 550 kHz when the internal oscillator is set to 440 kHz. When the internal
oscillator is set to 2.2 MHz, the synchronization range is 1.8 MHz to 2.6 MHz. If there is a valid RT resistor and a
synchronization signal, the LM5141 with ignore the RT resistor and synchronize the controller to the external
clock. Under low VIN conditions, when the minimum toff time is reached (100ns), the synchronization clock will be
ignored to allow the frequency to drop to maintain output voltage regulation.
7.3.5 Frequency Dithering (Spread Spectrum)
The LM5141 provides a frequency dithering option that is enabled by connecting a capacitor from the DITH pin to
AGND. A triangular waveform centered at 1.2 V is generated across the CDITH capacitor. Refer to Figure 22. The
triangular waveform modulates the oscillator frequency by ±5% of the nominal frequency set by the OSC pin or
by an RT resistor. The CDITH capacitance value sets the rate of the low frequency modulation. A lower CDITH
capacitance will modulate the oscillator frequency at a faster rate than a higher capacitance. For the dithering
circuit to effectively reduce the peak EMI, the modulation rate must be less than the oscillator frequency (Fsw).
Equation 3 calculates the DITH pin capacitance required to set the modulation frequency, FMOD.
20 mA
2ìFMOD ì0.12V
CDITH
=
(3)
If the DITH pin is connected to VDDA during power-up the Dither feature is latch-off and cannot be changed
unless VCC is allowed to drop below the VCC(UVLO) threshold. If the DITH pin is connected to ground on power
up, Dither will be disabled, but it can be enabled by raising the DITH pin voltage above ground and connecting it
to CDITH. When the LM5141 is synchronized to an external clock, Dither is disabled.
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ZHCSG18 –MARCH 2017
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1.26 V +5%
1.2 V
1.14 V -5%
DITH
LM5141-Q1
CDITH
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Dither Operation
7.3.6 Enable
The LM5141 has an enable input EN for start-up and shutdown control of the output. The EN pin can be
connected to a voltage as high as 70 V. If the enable input is greater than 2.0 V the output is enabled. If the
enable pin is pulled below 0.8 V, the output will be in shutdown, and the LM5141 is switched to a low IQ
shutdown mode, with a 10-µA typical current drawn from the VIN pin. It is not recommended to leave the EN pin
left floating.
7.3.7 Power Good
The LM5141 includes an output voltage monitoring function to simplify sequencing and supervision. The power
good function can be used to enable circuits that are supplied by the output voltage rail or to turn-on sequenced
supplies. The PG pin switches to a high impedance state when the output voltage is in regulation. The PG signal
switches low when the output voltage drops below the lower power good threshold (92% typical) or rises above
the upper power good threshold (110% typical). A 25 μs deglitch filter prevents any false tripping of the power
good signal due to transients. A pull-up resistor of 10 kΩ is recommended from the PG pin to the relevant logic
rail. Power good is asserted low during soft-start and when the buck converter is disabled by EN.
7.3.8 Output Voltage
The LM5141 output can be configured for one of the two fixed output voltages with no external feedback
resistors, or the output can be adjusted to the desired voltage using an external resistor divider. VOUT can be
configured as a 3.3-V output by connecting the FB pin to VDDA, or a 5-V output by connecting the FB pin to
ground with a maximum resistance of 500 Ω. The FB connections (either VDDA or GND) are detected during
power up.
The configuration setting is latched and cannot be changed until the LM5141 is powered down with VCC falling
below VCC(UVLO) (3.4 V typical) and then powered up again.
Alternatively the output voltage can be set using an external resistive dividers from the output to the FB pin. The
output voltage adjustment range is between 1.5 V and 15 V. The regulation threshold at the FB pin is 1.2 V
(VREF). To calculate RFB1 and RFB2 use Equation 4. Refer to Figure 23:
≈
∆
«
’
VOUT
VREF
RFB2
=
-1 ìR
÷
FB1
◊
(4)
The recommend starting point is to select RFB1 between 10 kΩ to 20 kΩ.
The Thevenin equivalent impedance of the resistive divider connected to the FB pin must be greater than 5 kΩ
for the LM5141 to detect the divider and set the controller to the adjustable output mode. Refer to Equation 5.
RFB1 ìRFB2
RFB1 + RFB2
RTH
=
> 5kW
(5)
16
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LM5141
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If a low IQ mode is required, take care when selecting the external resistors. The extra current drawn from the
external divider is added to the LM5141 ISTANDBY current (35 μA typical). The divider current reflected to VIN is
divided down by the ratio of VOUT/VIN. For example, if VIN is 12V and VOUT is set to 5.5 V with RFB1 10 kΩ, and
RFB2 = 35.7 kΩ, the input current at VIN required to supply the current in the feedback resistors is:
VOUT
VOUT
5.5V
5.5V
IDIVIDER
=
ì
=
ì
= 55.16mA
RFB1 +RFB2
V
10k + 35.7k 12V
IN
where
•
VIN = 12 V
(6)
(7)
The total input current in this condition will be:
IVIN ö ISTANDBY +IDIVIDER ö 35mA + 55.16m ö 90.16mA
LOUT
VOUT
COUT
RFB2
LM5141 Transconductance Amplifier
gm 1200 uS
_
FB
VREF
SS
+
RFB1
+
COMP
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Voltage Feedback
7.3.8.1 Minimum Output Voltage Adjustment
There are two limitations to the minimum output voltage adjustment range: the LM5141 voltage reference of 1.2
V and the minimum switch node pulse width, tSW
.
The minimum controllable on-time at the switch node (tSW) limits the voltage conversion ratio (VOUT/VIN). For
fixed-frequency PWM operation, the voltage conversion ratio should meet the following condition:
VOUT
> tsw×Fsw
V
IN
(8)
Where tSW is 70 ns (typical) and Fsw is the switching frequency. If the desired voltage conversion ratio does not
meet the above condition, the controller transitions from fixed frequency operation into a pulse skipping mode to
maintain regulation of the output voltage.
For example if the desired output voltage is 3.3 V with a VIN of 20 V and operating at 2.2 MHz, the voltage
conversion ratio test is satisfied:
3.3V
> 70nsì2.2MHz
20V
(9)
0.165> 0.154
For wide VIN applications and lower output voltages, an alternative is to use the LM5141 with a 440-kHz oscillator
frequency. Operating at 440 kHz, the limitation of the minimum tSW time is less significant. For example, if a 1.8-V
output is required with a VIN of 50 V:
1.8V
> 70nsì440kHz
50V
(10)
0.036> 0.0308
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7.3.9 Current Sense
There are two methods to sense the inductor current of the buck converter. The first is using current sense
resistor in series with the inductor and the second is to use the dc resistance of the inductor (DCR sensing).
Figure 24 illustrates inductor current sensing using a current sense resistor. This configuration continuously
monitors the inductor current providing accurate current-limit protection. For the best current-sense accuracy and
over current protection, use a low inductance ±1% tolerance current-sense resistor between the inductor and
output, with a Kelvin connection to the LM5141 sense amplifier.
If the peak differential current signal sensed from CS to VOUT exceeds 75 mV, the current limit comparator
immediately terminates the HO output for cycle-by-cycle current limiting.
V CS
(
)
RSENSE
=
DI
2
≈
’
I
+
∆
«
÷
◊
OUT MAX
(
)
where
•
V(CS) = 75 mV
(11)
IOUT(MAX) is the over current set point which is set higher than the maximum load current to avoid tripping the over
current comparator during load transients. ΔI is the peak-peak inductor ripple current.
LOUT
VOUT
RSENSE
COUT
LM5141 Current Sense Amplifier
Gain = 12
+
CS
VOUT
_
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Current Sense
7.3.10 DCR Current Sensing
For high-power applications which do not require high accuracy current-limit protection, DCR sensing may be
preferable. This technique provides lossless and continuous monitoring of the output current using an RC sense
network in parallel with the inductor. Using an inductor with a low DCR tolerance, the user can achieve a typical
current limit accuracy within the range of ±10% to ±15% at room temperature.
Components RCS and CCS in Figure 25 create a low-pass filter across the inductor to enable differential sensing
of the voltage drop across inductor DCR. When RCS × CCS is equal to LOUT/RDCR, the voltage developed across
the sense capacitor, CCS, is a replica of the inductor DCR voltage waveform. Choose the capacitance of CCS to
be greater than 0.1 μF to maintain a low impedance sensing network, thus reducing the susceptibility of noise
pickup from the switch node. Carefully observe the PCB layout guidelines to ensure the noise and DC errors do
not corrupt the differential current-sense signals applied across the CS and VOUT pins.
The voltage drop across CCS
:
sLOUT
1+
RDCR
VCS s =
( )
Ipk ìRDCR
1+ sRCSCCS
(12)
18
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LM5141
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ZHCSG18 –MARCH 2017
LOUT
VOUT
RDCR
COUT
LM5141 Current Sense Amplifier
CCS
RCS
Gain = 12
+
CS
VOUT
_
Copyright © 2016, Texas Instruments Incorporated
Figure 25. DCR Current Sensing
RCSCCS = LOUT/RDCR → accurate DC and AC current sensing
If the RC time constant is not equal to the LOUT/LDRC time constant there will be an error
RCSCCS > LOUT/RDCR → DC level still correct, the AC amplitude will be attenuated
RCSCCS < LOUT/RDCR→ DC level still correct, the AC amplitude will be amplified
7.3.11 Error Amplifier and PWM Comparator
The LM5141 has a high-gain transconductance amplifier which generates an error current proportional to the
difference between the feedback voltage and an internal precision reference (1.2 V). The output of the
transconductance amplifier is connected to the COMP pin allowing the user to provide external control loop
compensation. Generally for current mode control a type II network is recommended.
7.3.12 Slope Compensation
The LM5141 provides internal slope compensation to ensure stable operation with a duty cycle greater than
50%. To correctly use the internal slope compensation, the inductor value must be calculated based on the
following guidelines (Equation 12 assumes an inductor ripple current of 30%):
VOUT
LOUT
í
Fsw ì 0.3ìI
OUT
(13)
•
•
Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost and
improves transient response at the cost of reduced efficiency due to higher peak currents.
Higher inductance values decrease the peak-to-peak inductor current typically increases efficiency by
reducing the RMS current at the cost of requiring larger output capacitors to meet load-transient
specifications.
7.3.13 Hiccup Mode Current Limiting
The LM5141 includes an optional hiccup mode protection function that is enabled when a capacitor is connected
to the RES pin. In normal operation the RES capacitor is discharged to ground. If 512 consecutive cycles of
cycle-by-cycle current limiting occur, the SS pin capacitor is pulled low and the HO and LO outputs are disabled
(refer to Figure 26). A 20-μA current source begins to charge the RES capacitor.
When the RES pin charges to 1.2 V, the RES pin is pulled low and the SS capacitor begins to charge. The 512
cycle hiccup counter is reset if 4 consecutive switching cycles occur without exceeding the current limit threshold.
The controller is in forced PWM (FPWM) continuous conduction mode when the DEMB pin is connected to
VDDA. In this mode the SS pin is clamped to a level 200 mV above the feedback voltage to the internal error
amplifier. This ensures that SS can be pulled low quickly during a brief overcurrent event and prevent overshoot
of VOUT when the overcurrent condition is removed.
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If DEMB=0 V, the controller operates in diode emulation with light loads (discontinuous conduction mode) and
the SS pin is allowed to charge to VDDA. This reduces the quiescent current of the LM5141. If 32 or more cycle-
by-cycle current limit events occur, the SS pin is clamped to 200 mV above the feedback voltage to the internal
error amplifier until the hiccup counter is reset. Thus, if a momentary overload occurs that causes at least 32
cycles of current limiting, the SS capacitor voltage will be slightly higher than the FB voltage and will control
VOUT during overload recovery.
Current Limit
Detected
1.2V RES Threshold
IRES = 20 µA
0 V
RES
SS
ISS = 20 µA
1.2 V REF
HO/HOL
LO/LOL
tRES
tSS
Current Limit persists
during 512
consecutive cycles
Figure 26. Hiccup Mode
7.3.14 Standby Mode
The LM5141 operates with peak current mode control such that the compensation voltage is proportional to the
peak inductor current. During no-load or light load conditions, the output capacitor will discharge very slowly. As
a result the compensation voltage will not demand a driver output pulses on a cycle-by-cycle basis. When the
LM5141 controller detects that there have been 16 missing switching cycles, it enters Standby Mode and
switches to a low IQ state to reduce the current drawn from VIN. For the LM5141 to go into a Standby Mode, the
controller must be programmed for diode emulation (DEMB pin < 0.4 V). The typical IQ in Standby Mode is 35
μA with VOUT regulating at 3.3 V.
7.3.15 Soft-Start
The soft-start feature allows the controller to gradually reach the steady state operating point, thus reducing
Start-up stresses and surges. The LM5141 regulates the FB pin to the SS pin voltage or the internal 1.2-V
reference, whichever is lower. At the beginning of the soft-start sequence when SS = 0 V, the internal 20 µA soft-
start current source gradually increases the voltage on an external soft-start capacitor connected to the SS pin,
resulting in a gradual rise of the FB and output voltages. The controller is in the forced PWM (FPWM) mode
when the DEMB pin is connected to VDDA. In this mode, the SS pin is clamped at 200 mV above the feedback
voltage. This ensures that SS will be pulled low quickly when FB falls during brief over-current events to prevent
overshoot of VOUT during recovery. SS can be pulled low with an external circuit to stop switching, but this is not
recommended. Pulling SS low will result in COMP being pulled down internally as well. If the controller is
operating in FPWM mode (DEMB = VDDA), LO will remain on and the low-side MOSFET will discharge the
VOUT capacitor resulting in large negative inductor current. In contrast when the LM5141 pulls SS low internally
due to a fault condition, the LO gate driver is disabled.
7.3.16 Diode Emulation
A fully synchronous buck controller implemented with a free-wheel MOSFET rather than a diode has the
capability to sink negative current from the output in certain conditions such as light load, over-voltage, and pre-
bias start-up. The LM5141 provides a diode emulation feature that can be enabled to prevent reverse (drain to
source) current flow in the low-side free-wheel MOSFET. The diode emulation feature is configured with the
DEMB pin. To enable diode emulation, connect the DEMB pin to ground. When configured for diode emulation,
the low-side MOSFET is disabled when reverse current flow is detected. The benefit of this configuration is lower
power loss at no load or light load conditions and the ability to turn on into a pre-biased output without
discharging the output. The negative effect of diode emulation is degraded light load transient response times.
Enabling the diode emulation feature is recommended to allow discontinuous conduction operation. If continuous
conduction operation is desired, the DEMB pin should be tied to VDDA.
20
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Table 2. DEMB Pin Modes
DEMB Pin
MODE
FPWM
DEMB
FPWM
1
0
CLK
7.3.17 High and Low Side Drivers
The LM5141 contains N-channel MOSFET gate drivers and an associated high-side level shifter to drive the
external N-channel MOSFETs. The high-side gate driver works in conjunction with an external bootstrap diode
DBST, and bootstrap capacitor CBST (refer to Figure 27). During the on-time of the low-side MOSFET, the SW pin
voltage is approximately 0 V and CBST is charged from VCC through the DBST. A 0.1-μF or larger ceramic
capacitor, connected with short traces between the HB and SW pin is recommended.
The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs
(HO and LO) are never enabled at the same time, preventing cross conduction. When the controller commands
LO to be enabled, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below
2.5 V typical. LO is then enabled after a small delay (HO falling to LO rising delay). Similarly, the HO turn-on is
delayed until the LO voltage has dropped below 2.5 V. HO is then enabled after a small delay (LO falling to HO
rising delay). This technique ensures adequate dead-time for any size N-channel MOSFET device or parallel
MOSFET configurations. Caution is advised when adding series gate resistors, as this may decrease the
effective dead-time. Each of the high and low-side drivers have independent driver source and sink output pins.
This allows the user to adjust drive strength to optimize the switching losses for maximum efficiency and to
control the slew rate for reduced EMI. The selected N-channel high-side MOSFET determines the appropriate
boost capacitance values CBST in the Figure 27 according to Equation 13.
QG
CBST
=
DVBST
(14)
Where QG is the total gate charge of the high-side MOSFET and ΔVBST is the voltage variation allowed on the
high-side MOSFET driver after turn-on. Choose ΔVBST such that the available gate-drive voltage is not
significantly degraded when determining CBST. A typical range of ΔVBST is 100 mV to 300 mV. The bootstrap
capacitor should be a low-ESR ceramic capacitor. A minimum value of 0.1 μF to 0.47 μF is best in most cases.
The gate threshold of the high-side and low-side MOSFETs should be a logic level variety approporiate for 5-V
gate drive.
VCC
DBST
HB
CBST
RHO
HO
HOL
RHOL
SW
VCC
CVCC
RLO
LO
LOL
RLOL
PGND
Figure 27. Drivers
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5141 is a synchronous buck controller used to convert a higher input voltage to a lower output voltage.
The following design procedure can be used to select external component values. Alternately, the WEBENCH®
software may be used to generate a complete design. The WEBENCH software uses an iterative design
procedure and accesses a comprehensive database of components when generating a design. This section
presents a simplified design process. In addition to the WEBENCH software the LM5141ADESIGN-CALC.xls
quick start Excel calculator is available at www.ti.com.
8.2 Typical Application
VIN
CIN
VIN
VCC
CVCC
DBST
CBST
HB
HO
RES
SS
LOUT
VOUT
RSENSE
HOL
SW
DITH
LM5141-Q1
COUT
LO
CRES
CSS
CDITH
LOL
PGND
PG
CS
EN
DEMB
VOUT
VCCX
RCOMP CCOMP
COMP
FB
AGND
RT
OSC VDDA
RT
CVDDA
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Typical Application Schematic
22
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, the intended input, output, and performance parameters are shown in Table 2.
Table 3. Design Requirements
DESIGN PARAMETER
Input voltage range (Steady State)
VIN maximum (Transient)
VIN minimum (Cold Crank)
Output voltage
EXAMPLE VALUE
8 V to 18 V
42 V
3.8 V
3.3 V
Output current
6 A
Operating frequency
2.2 MHz
±1%
Output voltage regulation
Standby current, one output enabled, no-
load
< 35 µA
10 µA
Shutdown Current
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5141 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
•
•
•
•
•
•
•
Buck Inductor value
Calculate the peak inductor current
Current Sense resistor value
Output capacitor value
Input filter
MOSFET selection
Control Loop design
8.2.3 Inductor Calculation
For peak current mode control, sub-harmonic oscillation occurs with a duty cycle greater than 50% and is
characterized by alternating wide and narrow pulses at the SW pin. By adding a slope compensating ramp equal
to at least one-half the inductor current down-slope, any tendency toward sub-harmonic oscillation is damped
within one switching cycle. For design simplification, the LM5141 has an internal slope compensation ramp
added to the current sense signal.
For the slope compensation ramp to dampen sub-harmonic oscillation, the inductor value should be calculated
based on the following guidelines (equation 15 assumes an inductor ripple current 30%):
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VOUT
LOUT
í
Fsw ì 0.3ìI
OUT
(15)
•
•
Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost and
improves transient response at the expense of reduced efficiency due to higher peak currents.
Higher inductance values decrease the peak-to-peak inductor current, which typically increases efficiency by
reducing the RMS current but requires larger output capacitors to meet load-transient specifications.
3.3V
LOUT
í
2.2MHzì 0.3ì 6A
(16)
LOUT í 0.833mH
A standard inductor value of 1.5 µH was selected
VOUT
3.3V
8V
DMAX
=
=
= 0.413
= 0.183
V
IN MIN
(17)
(18)
VOUT
3.3V
18V
DMIN
=
=
V
IN MAX
The peak-to-peak inductor current is:
V
) - VOUT
LOUT
IN MAX
DMIN
Fsw
(
DI =
DI =
ì
(19)
18V - 3.3V 0.183
ì
= 0.815A
1.5mH
2.2MHz
(20)
(21)
(22)
DI
2
Ipk = IOUT
+
0.815
Ipk = 6A +
= 6.41A
2
8.2.4 Current Sense Resistor
When calculating the current sense resistor, the maximum output current capability (IOUT(MAX)) should be at least
20% higher than the required full load current to account for tolerances, ripple current, and load transients. For
this example, 120% of the 6.41 A peak inductor current calculated in the previous section (Ipk) is 7.69 A. The
current sense resistor value can be calculated using:
V CS
(
)
RSENSE
=
IOUT MAX
(23)
75mV
RSENSE
=
= 0.00975W
7.69A
where
•
V(CS) is the 75 mV current limit threshold
(24)
The RSENSE value selected is 9 mΩ
Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the differential
current sense signals between the CS and VOUT pins. Place the sense resistor close to the devices with short,
direct traces, creating Kelvin-sense connections between the current-sense resistor and the LM5141.
The propagation delays through the current limit comparator, logic, and external MOSFET gate drivers allow the
peak current to increase above the calculated current limit threshold. For a propagation delay of tdly, the worst
case peak current through the inductor with the output shorted can be calculated from:
V CS
V
) ì tdly
LOUT
IN MAX
(
)
(
IpkSCKT
=
+
RSENSE
(25)
24
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From the Electrical Characterization Table, tdly is typically 40 ns.
75mV 18V ì 40ns
IpkSCKT
=
+
= 8.81A
0.009W
1.5mH
(26)
Once the peak current and the inductance parameters are known, the inductor can be chosen. An inductor with a
saturation current greater than IpkSCKT (8.81 Apk) should be selected.
8.2.5 Output Capacitor
In a switch mode power supply, the minimum output capacitance is typically selected based on the capacitor
ripple current rating and the load transient requirements. The output capacitor must be large enough to absorb
the inductor energy and limit over voltage when transitioning from full-load to no-load, and to limit the output
voltage undershoot during no-load to full load transients. The worst-case load transient from zero to full load
occurs when the input voltage is at the maximum value and a current switching cycle has just finished. The total
output voltage drop ΔVOUT is the sum of the voltage drop while the inductor is ramping up to support the full load
and the voltage drop before the next pulse can occur.
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The output capacitance required to maintain the minimum output voltage drop (ΔVOUT) can be calculated as
follows:
LOUT ìISTEP
²
COUT MIN
=
(
)
2ì DVOUT ìDMAX ì V
- VOUT
IN MIN
(
)
(27)
1.5mHì 4A2
COUT MIN
=
= 186µF
(
)
2ì33mVì0.413ì 8V -3.3V
where
•
•
ISTEP = 4 A
ΔVOUT = 1% of 3.3 V, or 33 mV
(28)
For this example a total of 211 μF of capacitance is used, two 82-μF aluminum capacitors for energy storage and
one 47 μF low ESR ceramic capacitor to reduce high frequency noise.
Generally, when sufficient capacitance is used to satisfy the undershoot requirement, the overshoot during a full-
load to no-load transient will also be satisfactory. After the output capacitance has been selected, calculate the
output ripple current and verify that the ripple current is within the capacitor ripple current ratings.
DI
IOUT RMS
=
(
)
12
(29)
0.815A
IOUT RMS
=
= 0.235A
(
)
12
(30)
8.2.6 Input Filter
A power supply input typically has a relatively high source impedance at the switching frequency. Good quality
input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current
during the buck switch on-time. When the buck switch turns on, the current drawn from the input capacitor steps
from zero to the valley of the inductor current waveform, then ramps up to the peak value, and then drops to the
zero at turn-off.
Average input current can be calculated from the total input power required to support the load at VOUT
:
VOUT ìIOUT
P
=
IN
h
(31)
(32)
The efficiency (η) is assumed to be 83% for this design example, yielding a total input power:
3.3 V ì 6A
P
=
= 23.86W
IN
0.83
P
IN
Iavg
=
V
IN MIN
(
)
(33)
(34)
28.6W
8V
Iavg
=
= 3.58A
The input capacitors should be selected with sufficient RMS current rating and the maximum voltage rating.
»
…
…
2 ÿ
Ÿ
2
DI
12
I
=
Ipk -I
+
xD
+ (Iavg²ì 1-D
)
(
)
(
)
avg
MAX
MAX
IN RMS
(
)
Ÿ
⁄
(35)
(36)
0.8152
12
2
I
=
6.41A - 3.58A
+
ì0.413 + 3.58A2ì 1- 0.413 = 2.93A
(
)
(
)
IN RMS
(
)
26
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8.2.6.1 EMI Filter Design
EMI Filter Design Steps:
•
•
Calculate the required attenuation
Capacitor CIN represents the existing capacitor at the input of the switching converter (10 µF was used for this
application)
•
•
Inductor LF is usually selected between 1 μH and 10 μH (1.8 µH was used for this application), but can be
smaller to reduce losses in a high current design
Calculate capacitor CF
VIN
LF
CIN
CD
RD
CF
Figure 29. Input EMI Filter
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it
by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula can be derived
to obtain the required attenuation:
Ipk
»
…
…
…
…
ÿ
Ÿ
Ÿ
Ÿ
Ÿ
⁄
ì sin pìD
(
)
MAX
p2 ìFSW ìCIN
Attn = 20ìlog
- VMAX
1mV
(37)
6.41A
p2 ì 2.2MHzì10mF
»
…
ÿ
ì sin pì0.413
(
)
Ÿ
Ÿ
Ÿ
…
…
…
Attn = 20log
- 45 dBmV = 44.07dB
1mV
Ÿ
⁄
(38)
VMAX is the allowed dBμV noise level for the particular EMI standard. CIN is the existing input capacitors of the
Buck converter, for this application 10 µF was selected. DMAX is the maximum duty cycle, Ipk is the inductor
current, the current at the input can be modeled as a square wave, FSW is the switching frequency.
ÿ2
Attn
»
…
…
40
Ÿ
1
10
CF =
CF =
Ÿ
LF 2ì pìF
…
Ÿ
SW
…
Ÿ
⁄
(39)
2
44.07
40
≈
∆
∆
’
÷
÷
÷
◊
1
10
= 0.47µF
1.8mH 2ì pì 2.2MHz
∆
«
(40)
For this application, CF was chosen to be 1 μF. Adding an input filter to a switching regulator modifies the control-
to output transfer function. The output impedance of the filter must be sufficiently small such that the input filter
does not significantly affect the loop gain of the buck converter. The impedance of the filter peaks at the filter
resonant frequency.
1
FR =
2ì p LFCIN
(41)
1
FR =
= 37.53kHz
2ì p 1.8mHì10mF
(42)
27
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Referring to Figure 29, the purpose of RD is to reduce the peak output impedance of the filter at the cutoff
frequency. The capacitor CD blocks the dc component of the input voltage, and avoids excessive power
dissipation on RD. The capacitor CD should have lower impedance than RD at the resonant frequency, with a
capacitance value greater than 5 times the filter capacitor CIN. This will prevent it from interfering with the cutoff
frequency of the main filter. Added damping is needed when the output impedance is high at the resonant
frequency (Q) of filter formed by CIN and LF is too high):
An electrolytic cap CD can be used as damping device, with value:
LF
RD
=
CIN
(43)
(44)
For this design CD = 47 µF was selected
1.8mH
RD
=
= 0.424W
10mF
8.2.6.2 MOSFET Selection
The LM5141 gate drivers are powered by the internal 5-V VCC bias regulator. To reduce power dissipation in the
controller and improve efficiency, the VCCX pin should be connected to the 5-V output or an external 5 V bias
supply. The MOSFETs used with the LM5141 require a logic-level gate threshold with RDS(ON) specified with VGS
= 4.5 V or lower.
The MOSFETs must be chosen with a VDS rating to withstand the maximum VIN voltage plus supply voltage
transients and spikes (ringing). In addition, the N-channel MOSFETs must be capable of delivering the load
current plus peak ripple current during switching.
The high-side MOSFET losses are associated with the RDS(ON) of the MOSFET and the switching losses.
1
PD HS = I
2 ìRDS ON ìDMAX
+
ì V ì t + t ìIOUT ìFSW
IN r f
(
)
OUT
(
)
(
)
2
1
(45)
PD HS = (6A)2 ì0.026W ì0.413 + ì12V ì 17ns +17ns ì6A ì2.2MHz = 2.69W
(
)
(
)
2
where
•
tr = ts = 17 ns
(46)
The losses in the low side MOSFET include: RDS(ON) losses, dead time losses, and losses in the MOSFETs
internal body diode. The body diode conducts the inductor current during the dead time before the rising edge of
the switch node; minority carriers are injected into and stored in the diode PN junction when forward biased. As
the high side FET starts to turn-on, a negative current must first flow through the diode to remove the stored
charge before the diode can block a reverse voltage. During this time, the high side drain-source voltage remains
at VIN until all the diode minority carriers are removed. Then, the diode begins to block negative voltage and the
reverse current continues to flow to charge the body diode depletion capacitance. The total charge involved in
this period is called reverse-recovery charge Qrr.
PD LO = I
2 ìRDS ON ì 1-D
+ I
ì t + tdf ìF ì V
+ DQrr ìFSW ì V
IN
D FET
(
)
(
)
(
)
(
)
OUT
MAX
OUT
dr
SW
(
)
(
)
(
)
(47)
P
= (6A)2 ì26mWì 1-0.413 + 6A ì 20ns + 20ns ì2.2MHzì0.8V + 105nCì2.2MHzì12V = 3.744W
(
)
(
)
(
)
D LO
(
)
where
•
•
•
•
tdr and tdf are the switch node voltage rise and fall times (20 ns)
VD(FET) is the forward voltage drop across the low-side MOSFET internal body diode (0.8 V)
DQrr is the internal body diodes reverse recovery charge (105 nC)
RDS(ON) is the on resistance of the MOSFETs (26 mΩ at TJ = 125ºC)
(48)
28
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Table 4 provides parameters for several MOSFETs that have tested in the LM5141 evaluation module.
Table 4. EVM MOSFETs
Qg(MAX)
(nC)
VGS = 4.5 V
RDS(ON)
VGS = 4.5 V (Ω)
Manufacture
Part Number
VDS (V)
ID (A)
COSS(MAX) (pF)
Application
Automotive High
Power
VISHAY
VISHAY
SQJ850EP
SQ7414EN
60
60
60
24
5.6
13
30
25
32
36
215
175
217
Automotive Low
Power
Texas
Instruments
CSD18534Q5A
11.1
12.4
Industrial
8.2.6.3 Driver Slew Rate Control
Figure 30 shows the high current driver outputs with independent source and current sink pins for slew rate
control. Slew rate control enables the user to adjust the switch node rise and fall times which can reduce the
conducted EMI in the FM radio band (30 MHz to 108 MHz). Figure 31 shows the measured results without slew
rate control.
The conducted EMI results with slew rate control are shown in Figure 32, a 10-dB reduction in conduction
emissions in the FM band is attained by using slew rate control. This can help reduce the size and cost of the
EMI filters.
VCC
DBST
HB
CBST
RHO
HO
HOL
RHOL
SW
VCC
CVCC
RLO
LO
LOL
RLOL
PGND
Figure 30. Drivers with Slew Rate Control
Figure 31. Conducted EMI Measurement, Without Slew Rate Control
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Figure 32. Conducted EMI Measurements, With Slew Rate Control
8.2.6.4 Frequency Dithering
Figure 33 shows the conducted emission test run on the LM5141EVM, without the Dither feature enabled. The
first harmonic (peak measurement) is 48 dBµV, Figure 34 shows the conducted emissions test results with the
Dither feature enabled. With the Dither featured enabled, the first harmonic (peak measurement) was lowered to
40 dBµV, an 8 dB reduction.
Figure 33. Measured Conducted EMI, Without Dither
30
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Figure 34. Measured Conducted EMI, With Dither
8.2.7 8.9 Control Loop
The open loop gain is defined as the product of modulator transfer function and feedback transfer function. When
plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain.
DC modulator gain is:
RLOAD
AM =
R
+ RDCR ìG
CS
SENSE
(49)
The modulator gain plus power stage transfer function with an embedded current loop is show in Equation 50.
The equation includes the sample gain at FSW /2 (ωn), which is caused by sampling effect of current mode
control.
≈
∆
«
’
÷
s
1+
Ù
wZ ◊
VOUT
= AMì
Ù
≈
’
VC
s
( )
≈
∆
«
’
÷
s
s
s2
2
1+
ì 1+
+
∆
÷
÷
∆
«
wP ◊
wnQ
wn ◊
where
•
s = 2 × π × FSW
1
Q =
p K - 0.5
•
•
•
1
wZ =
CESR ìCOUT
1
wp =
RLOAD ìCOUT
wn = pìFSW
•
•
K = 1
GCS is the current sense amplifier gain which is 12
(50)
31
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Because the loop cross over frequency is well below sample gain effects, Equation 50 can be simplified as one
pole and a one zero system as shown in Equation 51.
≈
∆
«
’
÷
s
1+
1+
Ù
VOUT
s
wZ ◊
( )
= AMì
Ù
≈
’
VC
s
( )
s
∆
∆
«
÷
÷
wp
◊
(51)
RLOAD is the load resistance
RDCR is the dc resistance on the output inductor which is 8.1 mΩ
RSENSE is the current sense resistance which is 9 mΩ
8.2.7.1 Feedback Compensator
A type II compensator using an transconductance error amplifier (EA), Gm, is shown in Figure 35. The dominant
pole of the EA open-loop gain is set by the EA output resistance, RAMP, and effective bandwidth-limiting
capacitance, CO, as follows:
GmRAMP
GEA openloop s = -
) ( )
(
1+ sRAMPCO
(52)
The EA high frequency pole is neglected in the above expression. The compensator transfer function from output
voltage to COMP, including the gain contribution from the feedback resistor divider network is:
Ù
VC
s
( )
VREF
VOUT
GC s =
( )
= -
ìGmì ZEAOUT s
( )
Ù
VOUT
s
(53)
(54)
RLOWER
VREF
=
RLOWER + RUPPER VOUT
where
≈
∆
«
’
≈
∆
«
’
1
1
1
ZEAOUT s = Gmì R
R
+
∆
÷
÷
◊
( )
÷
AMP
COMP
sCCOMP ◊ sCHF sCO
(55)
(56)
Which simplifies to:
s
1+
wzEA
≈
ZEAOUT s = R
( )
AMP
≈
’
’
s
s
1+
ì 1+
∆
∆
«
÷
÷
◊
∆
÷
÷
◊
∆
«
wpEA1
wpEA2
VOUT
RUPPER
Gm
+
-
COUT
VC
VREF
RLOAD
RCOMP
CO
CCOMP
CESR
CHF
RLOWER
RAMP
Figure 35. Transconductance Amplifier
32
Copyright © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
1
wzEA
=
RCOMP ìCCOMP
(57)
(58)
1
1
wpEA1
=
@
R
+ RCOMP
C
+ CHF + CO
RAMP ìCCOMP
AMP
COMP
1
1
wpEA2
=
@
RCOMP ìCHF
RCOMP
C
C
+ CO
COMP
HF
(59)
Typically RCOMP << RAMP and CCOMP >> (CHF + CO) so the approximations are valid.
where
VREF is the feedback voltage reference (1.2 V)
Gm is the error amplifier gain transconductance (1200 µS)
RAMP is the error amplifier output impedance (2.5 MΩ)
The error amplifier compensation components create a pole at the origin, a zero, and a high frequency pole.
The procedure for choosing compensation components for a stable closed loop is:
•
•
Select the desired open loop gain crossover frequency (fc); for this application 30 kHz was chosen
Calculate the RCOMP resistor for the gain crossover frequency at 30 kHz
2ì pìCOUT ì R
+RDCR ìG
VOUT
VREF
(
)
SENSE
CS
RCOMP = fc
ì
Gm
(60)
(61)
2ì pì 293mFì 0.009W + 0.0081W ì12
(
)
3.3V
1.2V
RCOMP = 30KHzì
ì
= 25927W
1200ì10-6mS
The value selected for RCOMP is 22.6 kΩ.
where
RDCR = 0.0081 Ω
•
Calculate the CCOMP capacitor value to create a zero that cancels the pole ωp ( ωp = 1/RLOAD × COUT
)
RLOAD ìCOUT
CCOMP
=
RCOMP
(62)
(63)
0.477Wì 290mF
22.6kW
CCOMP
=
= 6nF
The value selected for CCOMP is 10nF.
Copyright © 2017, Texas Instruments Incorporated
33
LM5141
ZHCSG18 –MARCH 2017
www.ti.com.cn
8.2.8 Application Curves
The Bode Plots of the modulator and plus power stage are shown in refer to Figure 36. The results of the total
loop gain crossover frequency are 40 kHz with 112º of phase margin, (see Figure 37).
Figure 36. (VOUT/VC) Modulator Gain and Phase
Figure 37. Loop Gain and Phase
34
Copyright © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
9 Power Supply Recommendations
The LM5141EVM was designed to operate over an input voltage supply range between 5.5 V and 42 V. The
input supply must be well regulated. If the power source is located more than a few inches from the LM5141
EVM, additional bulk capacitance and ceramic bypass capacitors may be required at the power supply input. An
electrolytic capacitor with a value of 47 μF is typically a good choice.
10 Layout
10.1 Layout Guidelines
Careful PCB layout is critical to achieve low EMI and stable power supply operation. Make the high frequency
current loops as small as possible, and follow these guidelines of good layout practices:
1. Keep the high-current paths short. This is essential for stable, jitter-free operation.
2. Keep the power traces and load connections short. This is essential for high efficiency. Using 2 oz or thicker
copper can enhance full load efficiency.
3. Minimize current-sensing errors by routing CS and VOUT using a kelvin sensing directly across the current
sense resistor (RSENSE).
4. Route high-speed switching nodes (HB, HO, LO, and SW) away from sensitive analog signals (FB, CS, and
VOUT).
10.1.1 Layout Procedure
Place the power components first, with ground terminals adjacent to the low-side FET.
•
Mount the controller IC as close as possible to the high and low-side MOSFETs. Make the grounds and high
and low-sided drive gate drive lines as short and wide as possible. Place the series gate drive resistor as
close to the MOSFET as possible to minimize gate ringing.
•
Locate the gate drive components (D1 and C12) together and near the controller IC; refer to Figure 38. Be
aware that peak gate drive currents can be as high as 4 A. Average current up to 75 mA can flow from the
VCC pin to the VCC capacitor through the bootstrap diode to the bootstrap capacitor. Size the traces
accordingly.
•
•
Figure 39 shows the high frequency loops of the synchronous buck converter. The high frequency current
flows through Q1 and Q2, through the power ground plane and back to VIN through the ceramic capacitors
C6, C7, and C8. This loop must be as small as possible to minimize EMI. Refer to Figure 41 and Figure 42
for the recommended PCB layout.
Make the PGND and AGND connections to the LM5141 controller as shown in Figure 40. Create a power
grounds directly connected to all high-power components and an analog ground plane for sensitive analog
components. The analog ground plane (AGND) and power ground plane (PGND) must be connected at a
single point directly under the IC (at the die attach pad or DAP).
Copyright © 2017, Texas Instruments Incorporated
35
LM5141
ZHCSG18 –MARCH 2017
www.ti.com.cn
10.2 Layout Examples
Figure 38. EVM Top Side
Figure 39. EVM Bottom Layer, High Frequency Current Loop
36
Copyright © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
Layout Examples (continued)
Figure 40. AGND and PGND Connections
Figure 41 and Figure 42 show the Top and Bottom layer of the LM5141 EVM.
Figure 41. EVM Top Layer
Copyright © 2017, Texas Instruments Incorporated
37
LM5141
ZHCSG18 –MARCH 2017
www.ti.com.cn
Layout Examples (continued)
Figure 42. EVM Bottom Layer
38
版权 © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
11 器件和文档支持
11.1 使用 WEBENCH® 工具创建定制设计
请单击此处,结合使用 LM5141 器件和 WEBENCH® 电源设计器创建定制设计。
1. 在开始阶段键入输出电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数,如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下,可执行以下操作:
•
•
•
•
运行电气仿真,观察重要波形以及电路性能
运行热性能仿真,了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息,请访问 www.ti.com/WEBENCH。
11.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我进行注册,即可收到所有的
产品更改信息每周摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2017, Texas Instruments Incorporated
39
LM5141
ZHCSG18 –MARCH 2017
www.ti.com.cn
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更,恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本,请参阅左侧的导航。
40
版权 © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
PACKAGE OUTLINE
RGE0024J
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
0.5
0.3
A
0.3
0.2
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
0.1 MIN
(0.05)
SECTION A-A
SCALE 25.000
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
THERMAL PAD
SEE TERMINAL
DETAIL
13
6
A
A
2X
SYMM
25
2.5
18
1
0.3
0.2
24X
20X 0.5
19
24
0.1
0.05
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.5
0.3
4223242/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
版权 © 2017, Texas Instruments Incorporated
41
LM5141
ZHCSG18 –MARCH 2017
www.ti.com.cn
EXAMPLE BOARD LAYOUT
RGE0024J
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223242/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
42
版权 © 2017, Texas Instruments Incorporated
LM5141
www.ti.com.cn
ZHCSG18 –MARCH 2017
EXAMPLE STENCIL DESIGN
RGE0024J
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223242/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
版权 © 2017, Texas Instruments Incorporated
43
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5141RGER
LM5141RGET
ACTIVE
VQFN
VQFN
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
LM
5141
Samples
Samples
ACTIVE
RGE
NIPDAU | SN
LM
5141
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
OTHER QUALIFIED VERSIONS OF LM5141 :
Automotive : LM5141-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RGE0024J
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
0.5
0.3
A
0.3
0.2
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
0.1 MIN
(0.05)
SECTION A-A
SCALE 25.000
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
A
EXPOSED
THERMAL PAD
SEE TERMINAL
DETAIL
13
6
A
2X
SYMM
25
2.5
18
1
0.3
0.2
24X
20X 0.5
19
24
0.1
0.05
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.5
0.3
4223242/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024J
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223242/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024J
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223242/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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