LM51501-Q1_V01
更新时间：2024-10-29 23:23:44
品牌：TI
描述：LM51501-Q1 Wide VIN Automotive Low IQ Boost Controller
概述
数据手册LM51501-Q1_V01 概述
LM51501-Q1 Wide VIN Automotive Low IQ Boost Controller
LM51501-Q1_V01 数据手册
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LM51501-Q1
SNVSAZ0B –MARCH 2018–REVISED JUNE 2020
LM51501-Q1 Wide VIN Automotive Low IQ Boost Controller
1 Features
2 Applications
1
•
AEC-Q100 qualified:
•
•
•
Automotive start-stop system
Automotive emergency call system
Battery-powered boost converters
–
Device temperature grade 1: –40°C to +125°C
ambient operating temperature range
–
–
Device HBM ESD classification level 2
Device CDM ESD Classification level C4B
3 Description
The LM51501-Q1 is a wide input range automatic
boost controller. The device can be used to maintain
a stable output voltage during automotive cranking
from a vehicle battery or from a back-up battery.
•
•
Functional Safety-Capable
–
Documentation available to aid functional
safety system design
Wide VIN input range from 1.5 V to 42 V when
VOUT ≥ 5 V (65-V absolute maximum)
The LM51501-Q1 switching frequency is programmed
by a resistor from 220 kHz to 2.3 MHz. Fast switching
(≥ 2.2-MHz) minimizes AM band interference and
allows for a small solution size and fast transient
response.
•
•
•
Low shutdown current (IQ ≤ 5 µA)
Low standby current (IQ ≤ 15 µA)
Four programmable output voltage options and
two selectable configurations
The LM51501-Q1 operates in low IQ standby mode
when the input or output voltage is above the preset
standby thresholds and automatically wakes up when
the output voltage drops below the preset wake-up
threshold.
–
–
6.0 V, 6.5 V, 9.5 V, or 11.5 V
Start-stop or e-Call configurations
•
Adjustable switching frequency from 220 kHz to
2.3 MHz
The device transitions in and out of the low IQ
standby mode to extend battery life at light load. A
single resistor programs the target output regulation
voltage as well as the configuration. Additional
features include low shutdown current, boost status
indicator, adjustable cycle-by-cycle current limit, and
thermal shutdown. Status indicator can be used to
control a circuit to bypass the diode when the part is
not boosting in order to reduce power dissipation. In
E-call mode, it can be used to control a disconnect
switch to protect the back-up-battery.
•
•
•
•
•
•
•
•
Automatic wake-up and standby mode transition
Optional clock synchronization
Boost status indicator
1.5-A Peak MOSFET gate driver
Adjustable cycle-by-cycle current limit
Thermal shutdown
16-Pin WQFN with wettable flanks
Create a custom design using the LM51501-Q1
with the WEBENCH® Power Designer
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM51501-Q1
WQFN (16)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
Efficiency (VLOAD = 9.5 V, FSW = 440 kHz)
100
VSUPPLY
VLOAD
95
90
85
LO
CS AGND
PGND VOUT
EN
VIN
80
STATUS
SYNC
RT
VSUPPLY=7.5V
VSUPPLY=6.5V
LM51501
COMP
VSUPPLY=5.5V
VSUPPLY=4.5V
VSUPPLY=3.5V
75
70
VSET
VCC
AVCC
0
0.3
0.6
0.9
1.2
1.5
Load Current (A)
1.8
2.1
2.4
D008
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM51501-Q1
SNVSAZ0B –MARCH 2018–REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application ................................................. 24
8.3 System Examples ................................................... 31
Power Supply Recommendations...................... 33
9
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 35
11.1 Device Support...................................................... 35
11.2 Receiving Notification of Documentation Updates 35
11.3 Support Resources ............................................... 35
11.4 Trademarks........................................................... 35
11.5 Electrostatic Discharge Caution............................ 35
11.6 Glossary................................................................ 35
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
Changes from Revision A (May 2018) to Revision B
Page
•
Added functional safety bullet to the Features ...................................................................................................................... 1
Changes from Original (March 2018) to Revision A
Page
•
Changed device status from Advanced Info to Production Data ........................................................................................... 1
2
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Copyright © 2018–2020, Texas Instruments Incorporated
Product Folder Links: LM51501-Q1
LM51501-Q1
www.ti.com
SNVSAZ0B –MARCH 2018–REVISED JUNE 2020
5 Pin Configuration and Functions
RUM Package
16-Pin WQFN
Top View
AP
AP
16
15
14
13
SYNC
STATUS
EN
1
2
3
4
12 CS
11 AGND
10 PGND
EP
9
LO
VOUT
5
6
7
8
AP
AP
Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
External synchronization clock input pin. The internal oscillator is synchronized to an external
clock by applying a pulse signal into the SYNC pin in the start-stop configuration. Connect
directly to ground if not used or in an emergency call configuration. Maximum duty cycle limit
can be programmed by controlling the external synchronization clock frequency.
1
SYNC
I
Status indicator with an open-drain output stage. Internal pulldown switch holds the pin low
when the device is not boosting. The pin can be left floating if not used.
2
3
4
STATUS
EN
O
I
Enable pin. If EN is below 1 V, the device is in shutdown mode. The pin must be raised
above 2 V to enable the device. Connect directly to VOUT pin for an automatic boost.
Boost output voltage-sensing pin and input to VCC regulator. Connect to the output of the
boost converter.
VOUT
I/P
Output of the VCC bias regulator. Decouple locally to PGND using a low-ESR or low-ESL
ceramic capacitor placed as close to the device as possible.
5
6
PVCC
NC
O/P
—
No internal electrical connection. Leave the pin floating or connect directly to ground.
Analog VCC supply input. Decouple locally to AGND using 0.1-µF, low-ESR or low-ESL
ceramic capacitor placed as close to the device as possible. Connect to the PVCC pin
through 10-Ω resistor.
7
AVCC
I/P
8
9
NC
LO
—
O
No internal electrical connection. Leave the pin floating or connect directly to ground.
N-channel MOSFET gate drive output. Connect to the gate of the N-channel MOSFET
through a short, low inductance path.
Power ground pin. Connect to the ground connection of the sense resistor through a wide
and short path.
10
11
12
PGND
AGND
CS
G
G
I
Analog ground pin. Connect to the analog ground plane through a wide and short path.
Current sense input pin. Connect to the positive side of the current sense resistor through a
short path.
Output of the internal transconductance error amplifier. The loop compensation components
must be connected between this pin and AGND.
13
14
COMP
RT
O
I
Switching frequency setting pin. The switching frequency is programmed by a single resistor
between RT and AGND.
(1) G = GROUND, I = INPUT, O = OUTPUT, P = POWER
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Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NO.
15
NAME
VSET
VIN
Configuration selection and VOUT regulation target programming pin. During initial power on,
a resistor between the VSET pin and AGND configures the VOUT regulation target and the
configuration.
I
I
16
Boost input voltage sensing pin. Connect to the input supply of the boost converter.
Exposed pad of the package. No internal electrical connection to silicon die. The EP is
electrically connected to anchor pads. The EP must be connected to the large ground copper
plain to reduce thermal resistance.
—
EP
—
Anchor pad of the package. No internal electrical connection to silicon die. The AP is
electrically connected to the EP. The AP can be left floating or soldered to the ground
copper.
—
AP
—
4
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LM51501-Q1
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SNVSAZ0B –MARCH 2018–REVISED JUNE 2020
6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise specified)(1)
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-1.0
-2.0
-0.3
-0.3
-1.0
-2.0
-0.3
-0.3
-0.3
-0.3
-40
MAX
UNIT
VIN to AGND
65
VOUT to AGND
65
65
EN to AGND
RT to AGND(2)
AVCC+0.3
7
SYNC to AGND
Input
V
VSET to AGND
7
CS to AGND (DC)
CS to AGND (40ns transient)
CS to AGND (20ns transient)
PGND to AGND
AVCC+0.3
AVCC+0.3
AVCC+0.3
0.3
LO to AGND (DC)
LO to AGND (40ns transient)
LO to AGND (20ns transient)
STATUS to AGND(3)
COMP to AGND(2)
AVCC to AGND
PVCC+0.3
PVCC+0.3
PVCC+0.3
65
Output
V
AVCC+0.3
7
PVCC to AVCC
Junction Temperature(4)
0.3
TJ
150
℃
TSTG
Storage Temperature
-55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The pin voltage is clamped by an internal circuit, and is not specified to have an external voltage applied.
(3) STATUS can go below ground during the STATUS low-to-high transition. The negative voltage on STATUS during this transition is
clamped by an internal diode and it does not damage the device.
(4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
MIN
–2000
–750
–500
MAX
2000
750
UNIT
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Corner pins
Other pins
V
Charged device model
(CDM), per AEC Q100-011
500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise specified)(1)
MIN
1.5
5
NOM
MAX
42
UNIT
VVIN
Boost input voltage sense
Boost output voltage sense(2)
EN input
V
V
V
V
V
V
VVOUT
VEN
42
0
42
VVCC
VSYNC
VCS
PVCC voltage(3)
4.5
0
5
5.5
5.5
0.3
SYNC input
Current sense input
0
(1) Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical
Characteristics
(2) The device requires minimum 5V at VOUT pin to start up
(3) VPVCC should be less than VVOUT + 0.3
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Recommended Operating Conditions (continued)
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise specified)(1)
MIN
220
220
-40
NOM
MAX
2300
2300
150
UNIT
FSW
FSYNC
TJ
Typical switching frequency
kHz
kHz
°C
Synchronization pulse frequency
Operating junction temperature(4)
(4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM51501-Q1
THERMAL METRIC(1)
UNIT
RUM (WQFN) 16 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44.4
33.4
19.5
0.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
19.3
2.0
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
Typical values correspond to TJ=25°C. Minimum and maximum limits apply over TJ=-40°C to 125°C. Unless otherwise stated,
VVOUT=9.5V, RT=9.09kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
ISHUTDOWN(VOUT)
VOUT shutdown current
VVOUT=12V, VEN=0V
5
12
25
µA
µA
VOUT standby current (PVCC in
regulation, STATUS is low)
ISTANDBY(VOUT)
IWAKEUP(VOUT)
VVOUT=12V, VEN=3.3V, RSET=90.9 kΩ
15
VOUT operating current (exclude the
current into RT resistor)
VVOUT=11.5V, VEN=2.5V, non-
switching, RT = 9.09 kΩ
1.2
2.0
mA
ISHUTDOWN(VIN)
ISTANDBY(VIN)
VIN shutdown current
VIN standby current
VVIN=12V, VEN=0V
0.1
0.1
0.5
0.5
µA
µA
VVIN=12V, VEN=3.3V, RSET=29.4 kΩ
VVIN=11.5V, VEN=2.5V, non-switching,
RT = 9.09 kΩ
IWAKEUP(VIN)
VIN operating current
30
45
µA
VCC REGULATOR
VVCC-REG-NOLOAD PVCC regulation
VVOUT=6.0V, No load, wake-up mode
VVOUT=5.0V, IPVCC=70mA
4.75
4.5
5
5.25
V
V
VVCC-REG-
PVCC regulation
4.8
FULLLOAD
VVCC-UVLO-RISING AVCC UVLO threshold
AVCC rising
AVCC falling
4.1
3.9
4.3
4.1
0.2
4.5
4.3
V
V
VVCC-UVLO-FALLING AVCC UVLO threshold
VVCC-UVLO-HYS
IVCC-CL
AVCC UVLO hysteresis
V
PVCC sourcing current limit
VPVCC=0V, wake-up mode
75
1
mA
ENABLE
VEN-RISING
VEN-FALLING
IEN
Enable threshold
Enable threshold
EN bias current
EN rising
EN falling
VEN=42V
1.7
1.3
2
V
V
100
nA
6.0V SETTING
VVOUT-REG
VOUT regulation target
RSET=29.4kΩ or 90.9kΩ
5.88
6.06
6.00
6.18
6.12
6.30
V
V
VOUT wake-up threshold (VVOUT-
REG+3%)
VVOUT-WAKEUP
RSET=29.4kΩ or 90.9kΩ, VOUT falling
6
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SNVSAZ0B –MARCH 2018–REVISED JUNE 2020
Electrical Characteristics (continued)
Typical values correspond to TJ=25°C. Minimum and maximum limits apply over TJ=-40°C to 125°C. Unless otherwise stated,
VVOUT=9.5V, RT=9.09kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOUT standby threshold (VVOUT-
REG+6%, EC config)
VVOUT-STANDBY1
VVOUT-STATUS-OFF
VVOUT-STANDBY2
VVIN-STANDBY
RSET=90.9kΩ, VOUT rising
6.23
6.36
6.49
6.85
7.54
7.32
V
V
V
V
VOUT status off threshold (VVOUT-REG
+12%, EC config)
RSET=90.9kΩ, VOUT rising
RSET=29.4kΩ, VOUT rising
RSET=29.4kΩ, VIN rising
6.59
7.30
7.04
6.72
7.44
7.18
VOUT standby threshold (VVOUT-
REG+24%, SS config)
VIN standby threshold (VVOUT-WAKEUP
+ 1.0V, SS config)
6.5V SETTING
VVOUT-REG
VOUT regulation target
RSET=19.1kΩ or 71.5kΩ
6.37
6.56
6.50
6.70
6.63
6.83
V
V
VOUT wake-up threshold (VVOUT-
REG+3%)
VVOUT-WAKEUP
VVOUT-STANDBY1
VVOUT-STATUS-OFF
VVOUT-STANDBY2
VVIN-STANDBY
RSET=19.1kΩ or 71.5kΩ, VOUT falling
VOUT standby threshold (VVOUT-
REG+6%, EC config)
RSET=71.5kΩ, VOUT rising
RSET=71.5kΩ, VOUT rising
RSET=19.1kΩ, VOUT rising
RSET=19.1kΩ, VIN rising
6.75
7.13
7.92
7.54
6.89
7.28
8.06
7.70
7.03
7.43
8.16
7.85
V
V
V
V
VOUT status off threshold (VVOUT-REG
+12%, EC config)
VOUT standby threshold (VVOUT-
REG+24%, SS config)
VIN standby threshold (VVOUT-WAKEUP
+ 1.0V, SS config)
9.5V SETTING
VVOUT-REG
VOUT regulation target
RSET=9.53kΩ or 54.9kΩ
9.31
9.59
9.50
9.79
9.69
9.98
V
V
VOUT wake-up threshold (VVOUT-
REG+3%)
VVOUT-WAKEUP
VVOUT-STANDBY1
VVOUT-STATUS-OFF
VVOUT-STANDBY2
VVIN-STANDBY
RSET=9.53kΩ or 54.9kΩ, VOUT falling
VOUT standby threshold (VVOUT-
REG+6%, EC config)
RSET=54.9kΩ, VOUT rising
RSET=54.9kΩ, VOUT rising
RSET=9.53kΩ, VOUT rising
RSET=9.53kΩ, VIN rising
9.87
10.43
11.55
10.57
10.07
10.64
11.78
10.79
10.27
10.85
11.95
11.00
V
V
V
V
VOUT status off threshold (VVOUT-REG
+12%, EC config)
VOUT standby threshold (VVOUT-
REG+24%, SS config)
VIN standby threshold (VVOUT-WAKEUP
+ 1.0V, SS mode)
11.5V SETTING
VVOUT-REG
VOUT regulation target
RSET=GND or 41.2kΩ
11.27
11.61
11.50
11.85
11.73
12.08
V
V
VOUT wake-up threshold (VVOUT-
REG+3%)
VVOUT-WAKEUP
VVOUT-STANDBY1
VVOUT-STATUS-OFF
VVOUT-STANDBY2
VVIN-STANDBY
RSET=GND or 41.2kΩ, VOUT falling
VOUT standby threshold (VVOUT-
REG+6%, EC config)
RSET=41.2kΩ, VOUT rising
RSET=41.2kΩ, VOUT rising
RSET=GND, VOUT rising
RSET=GND, VIN rising
11.95
12.62
13.98
12.52
12.19
12.88
14.26
12.85
12.43
13.14
14.55
13.10
V
V
V
V
VOUT status off threshold (VVOUT-REG
+12%, EC config)
VOUT standby threshold (VVOUT-
REG+24%, SS config)
VIN standby threshold (VVOUT-WAKEUP
+ 1.0V, SS config)
RT
VRT-REG
RT regulation voltage
1.2
V
CLOCK SYNCHRONIZATION
VSYNC-RISING SYNC rising threshold
VSYNC-FALLING SYNC falling threshold
PULSE WIDTH MODULATION AND OSCILLATOR
FSW1 Switching frequency
2.0
1.5
2.4
V
V
0.4
RT = 93.1 kΩ
204
239
270
kHz
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Electrical Characteristics (continued)
Typical values correspond to TJ=25°C. Minimum and maximum limits apply over TJ=-40°C to 125°C. Unless otherwise stated,
VVOUT=9.5V, RT=9.09kΩ
PARAMETER
TEST CONDITIONS
RT = 9.09 kΩ
MIN
TYP
2300
2000
50
MAX UNIT
FSW2
Switching frequency
Switching frequency
Forced minimum on-time
2100
2500
kHz
kHz
ns
FSW3
RT = 9.09 kΩ, FSYNC=2.0MHz
TON-MIN
SS config, VCOMP=0V
30
70
RT = 9.09 kΩ, VVIN=1.5V, VVOUT=6.5V,
VCOMP=0V
59
16
%
%
DMIN
Minimum duty cycle limit (EC config)
Maximum duty cycle limit
RT = 93.1 kΩ, VVIN=7.6V, VVOUT=9.5V,
VCOMP=0V
SS config, RT = 9.09 kΩ
EC config, RT = 93.1 kΩ
83
83
87
87
91
93
%
%
DMAX
CURRENT SENSE
VVIN=7.13V, VVOUT=9.5V at 25% DC
VVIN=4.75V, VVOUT=9.5V at 50% DC
VVIN=2.38V, VVOUT=9.5V at 75% DC
102
102
102
120
120
120
138
138
138
mV
mV
mV
VCLTH
Current Limit threshold (CS-AGND)(1)
ERROR AMPLIFIER
Gm
Transconductance
2
mA/V
µA
µA
V
COMP souring current
COMP sinking current
COMP clamp voltage
COMP to PWM offset
VCOMP=0 V
312
120
2.4
VCOMP=1.5V
2.6
0.3
V
STATUS
Low-state voltage drop
1-mA sinking
0.1
5
V
STATUS rise to LO delay
5-kΩ pull-up to 5V
4
6
µs
MOSFET DRIVER
High-state voltage drop
Low-state voltage drop
50-mA sinking
50mA sourcing
0.075
0.055
V
V
THERMAL SHUTDOWN (TSD)
Thermal shutdown threshold
Temperature rising
175
15
°C
°C
Thermal shutdown hysteresis
(1) VCL at the current limit comparator input is 10 × VCLTH
6.6 Typical Characteristics
126
124
122
120
118
20
19.5
19
6.0V output
6.5V output
9.5V output
11.5V output
18.5
18
17.5
17
16.5
16
15.5
6.0V output
6.5V output
9.5V output
11.5V output
15
14.5
14
116
114
2
3
4
5
Supply Voltage (V)
6
7
8
9
10
20
30
40
50
Duty Cycle (%)
60
70
80
D001
D002
Figure 1. Peak Inductor Current vs Supply Voltage
Figure 2. Current Limit Threshold at CS vs Duty Cycle
(FSW = 440 kHz, RS = 7 mΩ, RF = 100 Ω, CF = 2.2 nF)
8
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Typical Characteristics (continued)
6
6
5.5
5
5
4
3
2
1
0
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
20
40
60 80
IPVCC (mA)
100
120
140
0
0.5
1
1.5
2
2.5
3
VVOUT (V)
3.5
4
4.5
5
5.5
6
D003
D004
Figure 3. VPVCC vs IPVCC (VOUT = 6 V)
Figure 4. VPVCC vs VVOUT (EN = 3.3 V, IPVCC = 10 mA, VOUT
Rising)
2750
2500
2250
2000
1750
1500
1250
1000
750
100
VVOUT=6.0V
VVOUT=6.5V
VVOUT=9.5V
VVOUT=11.5V
90
80
70
60
50
40
30
20
10
0
500
250
0
0
10
20
30
40
50
RT (kW)
60
70
80
90 100
0
1
2
3
4
5
6
VVIN (V)
7
8
9
10 11 12
D005
Dmin
Figure 5. Frequency vs RT
Figure 6. Duty Cycle Limit in EC Configuration vs VVIN
20
18
16
14
12
10
8
100
95
90
85
80
75
70
Shutdown
Standby
6
VSUPPLY=7.5V
VSUPPLY=6.5V
VSUPPLY=5.5V
VSUPPLY=4.5V
VSUPPLY=3.5V
4
2
0
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (°C)
0
0.3
0.6
0.9
1.2
1.5
Load Current (A)
1.8
2.1
2.4
D007
D008
Figure 7. IVOUT vs Temperature
Figure 8. Efficiency vs Load Current
(VLOAD = 9.5 V, FSW = 440 kHz, SS Configuration)
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7 Detailed Description
7.1 Overview
The LM51501-Q1 device is a wide input range automotive boost controller designed for automotive start-stop or
emergency-call applications. The device can maintain the output voltage from a vehicle battery during automotive
cranking or from a backup battery during the loss of vehicle battery. The wide input range of the device covers
automotive load dump transient. The control method is based upon peak current mode control.
To extend the battery life time, the LM51501-Q1 features a low IQ standby mode with automatic wake-up and
standby control. The device stays in low IQ standby mode when the boost operation is not required, and
automatically enters the wake-up mode when the output voltage drops below the preset wake-up threshold. High
value feedback resistors are included inside the device to minimize leakage current in low IQ standby mode.
The LM51501-Q1 operates in one of two selectable configurations when waking up. In Start-Stop configuration
(SS configuration), the device runs at a fixed switching frequency without any pulse skipping until entering into
the standby mode, which helps to have a fixed EMI spectrum. In Emergency-Call configuration (EC
configuration), the device will skip pulses as it automatically alternates between low IQ standby mode and wake-
up mode to extend the battery life in light load conditions.
The LM51501-Q1 switching frequency is programmable from 220 kHz to 2.3 MHz. Fast switching (≥ 2.2 MHz)
minimizes AM band interference and allows for a small solution size and fast transient response. A single resistor
at the VSET pin programs the target output regulation voltage as well as the configuration. This eliminates the
need for an external feedback resistor divider which enables low IQ operation. The device also features clock
synchronization in the SS configuration, low quiescent current in shutdown mode, a boost status indicator,
adjustable cycle-by-cycle current will limit, and thermal shutdown protection.
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7.2 Functional Block Diagram
VSUPPLY
VLOAD
D1
LM
COUT
CIN
RLOAD
STATUS
VIN
(SS Mode)
+
StatusB
VSET
VIN_STANDBY
VOUT-STANDBY
Standby
œ
œ
Q
S
REF
REF
FB
VO_STANDBY
VO_WAKE
VOUT
+
VSET
Ready
RSET
Wakeup
StatusB
POWER
ON
œ
Q
Q
R
VOLTAGE
SELECT
+
S
R
(EC Mode)
VO_STATUS_OFF
œ
AVCC
PVCC
VOUT
REF
CAVCC
Q
+
+
VIN_STANDBY (SS Mode)
VOUT
2.0 V/1.0 V
Enable
œ
EN
Ready
LM51501
VCC_OK
VCC
Regulator
Enable
RAVCC
CPVCC
Standby
TSD
œ
VOUT
VCC
UVLO
VCC_OK
VCL + 0.3 V
C/L
S
Q
Q
+
LO
CS
VCS_OFFSET
Wakeup
PWM
+
R
Q1
C/L
DMIN/Forced_Ton
+
REF
FB
ISLOPE
œ
RSL
(optional)
30 uA peak
œ
RF
DMAX/Forced_Toff
VCS_OFFSET
CLOCK
GENERATOR
GM AMP
2 kꢀ
VCS
+
A = 10
œ
CF
TLEB
RS
PGND
AGND
COMP
RT
SYNC
0.3 V
RCOMP
RT
CCOMP
7.3 Feature Description
7.3.1 Enable (EN Pin)
When the EN pin voltage is less than 1 V, the LM51501-Q1 is in shutdown mode with all other functions
disabled. To turn on the internal VCC regulator and begin the start-up sequence, the EN pin voltage must be
greater than 2 V. If the EN pin is controlled by user input, TI recommends supplying a voltage greater than 3 V at
the EN pin. If the EN pin is not controlled by user input, connect the EN pin to the VOUT pin directly. See the
Device Functional Modes for more detailed information.
7.3.2 High Voltage VCC Regulator (PVCC, AVCC Pin)
The LM51501-Q1 contains an internal high voltage VCC regulator. The VCC regulator turns on when the EN pin
voltage is greater than 2 V. The VCC regulator is sourced from the VOUT pin and provides 5 V (typical) bias
supply for the N-channel MOSFET driver and other internal circuits.
The VCC regulator sources current into the capacitor connected to the PVCC pin with a minimum of 75-mA
capability when the LM51501-Q1 is in wake-up mode during the device configuration period. The maximum
sourcing capability is decreased to 17 mA in standby mode. The recommended PVCC capacitor is 4.7 µF to 10
µF. In normal operation, the PVCC pin voltage is either 5 V or VVOUT + 0.3 V, whichever is lower.
The AVCC pin is the analog bias supply input of the LM51501-Q1. The recommended AVCC capacitor is 0.1 μF.
Connect to the PVCC pin through a 10-Ω resistor.
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Feature Description (continued)
7.3.3 Power-On Voltage Selection (VSET Pin)
During initial power on, the VOUT regulation target and the configuration are configured by a resistor connected
between the VSET and the AGND pins. The configuration starts when the EN pin voltage is greater than 2 V and
the AVCC voltage crosses the AVCC UVLO threshold, which typically requires 50 µs to finish. To reset and
reconfigure, the EN should be toggled below 1 V or the AVCC/VOUT must be fully discharged.
EN
VCC
UVLO
AVCC
50 us
50 us
Figure 9. Power-On Voltage Selection
The VOUT regulation target can be programmed to 6.0 V, 6.5 V, 9.5 V, or 11.5 V with the appropriate resistor
with 5% tolerance. The configuration can be selected as either SS or EC configuration. The LM51501-Q1 will not
switch during the 50-µs configuration time.
Table 1. VSET Resistors(1)
CONFIGURATION
VOUT regulation target
RSET [Ω]
EMERGENCY-CALL
START-STOP
6.0 V
90.9k
6.5 V
71.5k
9.5 V
54.9k
11.5 V
41.2k
6.0 V
29.4k
6.5 V
19.1k
9.5 V
9.53k
11.5 V
Ground
(1) If other output regulation targets are required, contact the sales office or distributors for availability.
7.3.4 Switching Frequency (RT Pin)
The switching frequency of the LM51501-Q1 is set by a single RT resistor connected between the RT and the
AGND pins. The resistor value to set the switching frequency (FSW) is calculated using Equation 1.
2.233ì1010
RT =
- 619 W
FSW _RT TYPICAL
(1)
The RT pin is regulated to 1.2 V by the internal RT regulator during wake-up.
7.3.5 Clock Synchronization (SYNC Pin in SS Configuration)
In SS configuration, the switching frequency of the LM51501-Q1 can be synchronized to an external clock by
directly applying a pulse signal to the SYNC pin. The internal clock of the LM51501-Q1 is synchronized at the
rising edge of the external clock. The device ignores the rising edge input during forced off-time.
The external synchronization pulse must be greater than the 2.4 V in the high logic state and must be less than
0.4 V in the low logic state. The duty cycle of the external synchronization pulse is not limited, but the minimum
pulse width should be greater than 100 ns. Because the maximum duty cycle limit and the peak current limit
threshold are affected by synchronizing the switching frequency to an external synchronization pulse, take extra
care when using the clock synchronization function. See the Maximum Duty Cycle Limit and Minimum Input
Supply Voltage and Current Limit (CS Pin) sections for more detailed information.
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If the minimum input supply voltage of the boost converter is greater than ¼ of the VOUT regulation target
(VVOUT-REG), the frequency of the external synchronization pulse (FSYNC) should be within +15% and –15% of the
typical free-running switching frequency (FSW(TYPICAL)) as shown in Equation 2:
0.85´FSW_RT(TYPICAL) £ FSYNC £ 1.15´FSW_RT(TYPICAL)
(2)
In this range, a maximum 1:4 (VSUPPLY:VLOAD) step-up ratio is allowed.
A higher step-up ratio can be achieved by supplying a lower frequency synchronization pulse. 1:5 step-up ratio
can be achieved by selecting FSYNC within –25% and –15% of the FSW_RT(TYPICAL)
.
0.75´FSW_RT(TYPICAL) £ FSYNC £ 0.85´FSW_RT(TYPICAL)
(3)
In this range, a maximum 1:5 (VSUPPLY:VLOAD) step-up ratio is allowed.
7.3.6 Current Sense, Slope Compensation, and PWM (CS Pin)
The LM51501-Q1 features low-side current sense amplifier with a gain of 10, and provides an internal slope
compensation ramp to prevent subharmonic oscillation at high duty cycle. The device generates the slope
compensation ramp using a sawtooth current source with a slope of 30 µA × FSW (typical). This current flows
through an internal 2-kΩ resistor and out of the CS pin. The slope compensation ramp is determined by the RT
resistor and is 60 mV × FSW (typical) at the input of the current sense amplifier and 600 mV × FSW (typical) at the
output of the current sense amplifier. The slope compensation ramp can be increased by adding an external
slope resistor (RSL) between the sense resistor (RS) and the CS pin, but take extra care when using the RSL,
because the peak current limit is affected by adding RSL. See the Current Limit (CS Pin) section for more detailed
information.
Q1
Current Limit
œ
V
CL +0.3 V
ISLOPE
RSL
(optional)
30 uA peak
+
+
CS
RF
2 kꢀ
PWM
+
A = 10
œ
CF
œ
RS
0.3 V
COMP
Figure 10. Current Sensing and Slope Compensation
According to peak current mode control theory, the slope of the compensation ramp must be greater than half of
the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the
minimum amount of slope compensation should satisfy the inequality in Equation 4.
(VLOAD+ VF ) - VSUPPLY
0.5´
×RS×Margin < 30mA ´(2kΩ +RSL )×FSW
LM
(4)
VF is a forward voltage drop of D1, the external diode. 1.2 is recommended as a margin to cover non-ideal
factors.
If required, RSL can be added to increase the slope of the compensation ramp from half to 82% of the slope of
the sensed inductor current during the falling slope. The typical RSL value is calculated using Equation 5. The
maximum RSL value is 1 kΩ.
(VLOAD+ VF ) - VSUPPLY
0.82´
×RS = 30mA ´(2kΩ +RSL )×FSW
LM
(5)
The PWM comparator in Figure 10 compares the sum of the sensed inductor current, the slope compensation
ramp, and a 0.3-V (typical) internal COMP-to-PWM offset with the COMP pin voltage (VCOMP), and will terminate
the present cycle if the sum is greater than VCOMP
.
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7.3.7 Current Limit (CS Pin)
The LM51501-Q1 features cycle-by-cycle peak current limit without subharmonic oscillation at high duty cycle. If
the sum of the sensed inductor current and the slope compensation ramp exceeds the current limit threshold at
the current limit comparator input (VCL), the current limit comparator immediately terminates the present cycle. To
minimize the peak current limit variation due to changes in either the supply voltage or the output voltage, the
device features a variable current limit threshold which is calculated using Equation 6.
(VVOUT - VVIN
)
VCL = 1.2 + 0.6 ×
[V]
VVOUT-REG
(6)
The cycle-by-cycle peak inductor current limit (IPEAK-CL) in steady-state is calculated using Equation 7 and
Equation 8:
FSW_RT
VCL -10´30mA ´(2kW + RSL )´
´D
FSYNC
IPEAK-CL
=
10´RS
(7)
(8)
VSUPPLY
D = 1-
VLOAD+VF
FSYNC is included in the equation because the peak amplitude of the slope compensation varies with the
frequency of the external synchronization clock. Substitute FSW_RT for FSYNC if clock synchronization is not used.
Boost converters have a natural pass-through path from the supply to the load through the high-side power diode
(D1). Due to this path, boost converters cannot provide current limit protection when the output voltage is close
to or less than the input supply voltage.
A small external RC filter (RF, CF) at the CS pin is required to overcome the leading edge spike of the current
sense signal. Select an RF value that is greater than 30 Ω and a CF value that is greater than 1 nF. Due to the
effect of the filter, the peak current limit is not valid when the on-time is less than 2 × RF × CF.
7.3.8 Feedback and Error Amplifier (COMP Pin)
The LM51501-Q1 includes internal feedback resistors which are set based on the VSET pin resistor selection.
These feedback resistors are disconnected from the VOUT pin in the standby mode to minimize quiescent
current. The feedback resistor divider is connected to an internal transconductance error amplifier that features
high output resistance (RO = 10 MΩ) and wide bandwidth (BW = 3 MHz). The internal transconductance error
amplifier sources current which is proportional to the difference between the feedback resistor divider voltage
and the internal reference. The output of the error amplifier is connected to the COMP pin, allowing the use of a
Type-2 loop compensation network.
The RCOMP, CCOMP, and the optional CHF loop compensation components configure the error amplifier gain and
phase characteristics to achieve a stable loop response. This compensation network creates a pole at very low
frequency (FDP), a mid-band zero pole (FZ_EA), and a high-frequency pole (FP_EA). See the Loop Compensation
Component Selection and Maximum ESR section for more information.
7.3.9 Automatic Wake-Up and Standby
The LM51501-Q1 wakes up when VVOUT drops below the VOUT wake-up threshold. The device goes into
standby when VVOUT rises above the VOUT standby threshold in EC or SS configuration or when VVIN rises
above the VIN standby threshold in SS configuration. The VOUT wake-up threshold is typically 3% higher than
the VOUT regulation target. The STATUS output is released in 3 µs (with 50-kΩ pullup resistor to 5 V) after the
wake-up event. The LO driver is enabled 6 µs after the STATUS output starts rising.
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VOUT
VIN
WAKEUP
FB
VVOUT-STANDBY
+
+
REF
VO_STANDBY
VOUT
VIN_STANDBY
(SS Config)
Standby
Q
Q
S
R
VO_WAKE
REF
+
Wakeup
Figure 11. Automatic Wake-Up and Standby Control
In SS configuration, the VOUT standby threshold is typically 24% higher than the VOUT regulation target. The
VIN standby threshold is typically 1 V higher than the VOUT wake-up threshold in SS configuration. To prevent
chatter, the forward voltage drop of diode D1 must be less than 0.95 V. See Figure 15.
VSUPPLY (Fast fall)
Engine Cranking
VLOAD
VVOUT-STANDBY2 = 1.24 x VVOUT-REG
VVIN-STANDBY = VVOUT-WAKE +1.0
when FSW is low
VVOUT-WAKEUP = 1.03 x VVOUT-REG
VVOUT-REG
Wake-up/Standby
Wake-up
Wake-up
Standby
Standby
STATUS
ILOAD
Full load
Full load
Very light load
Figure 12. Automatic Wake-Up and Standby Operation in the SS Configuration
(With Fast VSUPPLY Fall and Slow Switching)
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VSUPPLY (Slow fall)
VLOAD
Engine Cranking
VVOUT-STANDBY2 = 1.24 x VVOUT-REG
VVIN-STANDBY = VVOUT-WAKE +1.0
when FSW is fast
VVOUT-WAKEUP = 1.03 x VVOUT-REG
VVOUT-REG
Wake-up
Wake-up
Wake-up/Standby
Standby
Standby
Standby
Standby
STATUS
ILOAD
Full load
Full load
Very light load /No load
Figure 13. Automatic Wake-Up and Standby Operation in the SS Configuration
(With Slow VSUPPLY Fall and Fast Switching)
In EC configuration, the VOUT standby threshold is typically 6% higher than the VOUT regulation target.
Because of the minimum duty cycle limit (see the Emergency-Call Configuration (EC Configuration) section), the
LM51501-Q1 alternates between the wake-up and the low IQ standby modes at medium or light load. See
Figure 16.
Vehicle Battery Disconnect
Vehicle Battery Reconnect
VLOAD
VVOUT_STATUS_OFF = 1.12 x VVOUT-REG
VVOUT-STANDBY1 = 1.06 x VVOUT-REG
VVOUT-WAKEUP = 1.03 x VVOUT-REG
VVOUT-REG
VSUPPLY
Wake-up
Wake-up
Standby
Standby
Standby
Standby
STATUS
ILOAD
Full load
Full load
Mid / Light load
Figure 14. Automatic Wake-Up and Standby Operation in EC Configuration
To minimize output undershoot when waking up, the LM51501-Q1 boosts the VOUT regulation target during the
first 128 cycles after the wake-up event. The regulation target becomes 3% higher than the original regulation
target for 64 cycles, 2% higher for the next 32 cycles, and 1% higher for the final 32 cycles. The VOUT pin
voltage can rise up above the VOUT standby threshold, even if switching stops at the VOUT standby threshold,
because the energy stored in the inductor transfers to the output capacitor when switching stops. See the Device
Functional Modes for more information about the automatic wake-up and standby operation.
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7.3.10 Boost Status Indicator (STATUS Pin)
STATUS is an open-drain output and requires a pullup resistor between 5 kΩ and 100 kΩ. The pin is pulled up
after VVOUT falls below the VOUT wake-up threshold, and is toggled to a low logic state when VVIN rises above
the VIN standby threshold in SS configuration or when VVOUT rises above the VOUT status off-threshold in EC
configuration. The pin is also pulled to ground when EN < 1 V and VOUT is greater than about 2 V, when AVCC
< VVCC-UVLO-FALLING or during thermal shutdown.
7.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
When designing a boost converter, the maximum duty cycle should be reviewed at the minimum supply voltage.
The minimum input supply voltage which can achieve the target output voltage is estimated from Equation 9.
FSYNC
VSUPPLY(MIN) » (VVOUT-REG + VF )´(1- DMAX )´
+ ISUPPLY(MAX)´RDCR + ISUPPLY(MAX)´(RDS(ON) + RS )´DMAX
FSW_RT
where
•
•
•
ISUPPLY(MAX) is the maximum input current.
RDCR is the DC resistance of the inductor.
and RDS(ON) is the on-resistance of the MOSFET.
(9)
Substitute FSW_RT for FSYNC if clock synchronization is not used. The minimum input supply voltage can be
decreased by supplying FSYNC because it is less than FSW_RT
.
This maximum duty cycle limit (DMAX) is 87% (typical), but may fall down below 80% if the external
synchronization clock frequency is higher than 0.85 × FSW (TYPICAL). Select an FSYNC that is within –25% and
–15% of the FSW
if 1:5 step-up ratio is required for clock synchronization. The minimum input supply
(TYPICAL)
voltage can be further decreased by supplying a lower frequency external synchronization clock. See the Clock
Synchronization (SYNC Pin in SS Configuration) section for more information.
7.3.12 MOSFET Driver (LO Pin)
The LM51501-Q1 provides an N-channel MOSFET driver that can source or sink a peak current of 1.5 A. The
driver is powered by the 5-V VCC regulator and is enabled when the EN pin voltage is greater than 2 V and the
AVCC pin voltage is greater than the AVCC UVLO threshold.
7.3.13 Thermal Shutdown
Internal thermal shutdown is provided to protect the LM51501-Q1 if the junction temperature exceeds 175°C
(typical). When thermal shutdown is activated, the device is forced into a low power thermal shutdown state with
the MOSFET driver and the VCC regulator is disabled. After the junction temperature is reduced (typical
hysteresis is 15⁰C), the device is re-enabled.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
If the EN pin voltage is below 1 V, the LM51501-Q1 is in shutdown mode with all functions disabled except the
EN. In shutdown mode, the device reduces the VOUT pin current consumption to below 5 µA (typical) and the
STATUS pin is pulled to ground. The device can be enabled by raising the EN pin above 2 V and operates in
either standby mode or the wake-up mode if VAVCC is greater than the AVCC UVLO threshold.
Table 2. State of Each Pin in Shutdown Mode
STATUS
SYNC
RT
COMP
EN
VOUT
PVCC/AVCC
LO
CS
VIN
VSET
Grounded
Disabled
Disabled
Disabled
Enabled
IQ ≤ 5 µA
Disabled
Grounded
Disabled
IQ ≈ 0.1 µA
Disabled
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7.4.2 Standby Mode
If VOUT is greater than the VOUT standby threshold or the VIN is greater than the VIN standby threshold in the
SS mode, the LM51501-Q1 enters into standby mode.
In standby mode, most functions are disabled, including the thermal shutdown, to minimize the current
consumption. The VOUT wake-up monitor is enabled in standby mode to allow wake-up if the VOUT voltage
drops below the VOUT wake-up threshold. The VCC regulator reduces the sourcing capability to 17 mA in
standby mode and the AVCC UVLO comparator is disabled.
The VOUT standby threshold fulfills effectively the overvoltage protection (OVP) function.
Table 3. State of Each Pin in Standby Mode
STATUS
SYNC
RT
COMP
EN
VOUT
PVCC/AVCC
LO
CS
VIN
VSET
I
Q ≤ 15 µA. VOUT
wake-up monitor
enabled
Enabled IPVCC
capability ≈ 17 Grounded
Released or
Grounded
Disabled Disabled
Disabled
Enabled
Disabled
IQ ≈ 0.1 µA
Disabled
mA
7.4.3 Wake-Up Mode
The LM51501-Q1 wakes up from standby mode if VOUT drops below the VOUT wake-up threshold. There are
two configurations when the device wakes up. One is start-stop configuration (SS configuration) and the other is
emergency-call configuration (EC configuration). The configuration is selectable by the VSET resistor (see
Table 1).
7.4.3.1 Start-Stop Configuration (SS Configuration)
Bypass path
D1
VLOAD
VSUPPLY
LM
œ
+
Reverse Battery
Protection Diode
Q1
COUT
RLOAD
CIN
Vehicle
Battery
RS
AGND
PGND
LO
CS
VIN
STATUS
SYNC
LM51501
EN
COMP
VOUT
AVCC
RT
VSET
PVCC
RCOMP
C VOUT
CCOMP
RT
RSET
Figure 15. Typical Start-Stop Application
The LM51501-Q1 runs at fixed switching frequency without any pulse skipping in SS configuration. The device
turns on the LO driver every cycle with TON-MIN until it enters standby mode, which helps to prevent EMI spectrum
shifts. Because the MOSFET turns on every cycle, the boost converter output may be above the regulation target
if the required on-time is less than the TON-MIN when the boost supply voltage is close to the VOUT regulation
target or the load current is very small. The output voltage will rise above the VOUT regulation target if the one of
the inequalities listed in Equation 10 or Equation 11 is true.
1
D´
< TON-MIN
FSW
(10)
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2
(VSUPPLY ´ TON-MIN
2´LM
)
FSW
´
> ILOAD
(VLOAD + VF - VSUPPLY
)
(11)
In SS configuration, the LM51501-Q1 enters into the standby mode if VOUT is greater than the VOUT standby
threshold—which is 24% higher than the VOUT regulation target—or if VIN is greater than the VIN standby
threshold.
7.4.3.2 Emergency-Call Configuration (EC Configuration)
Other
loads
œ
+
Vehicle
Battery
D1
VSUPPLY
VLOAD
LM
+
COUT
Q1
CIN
RLOAD
Back-up
battery
RS
LO
CS
AGND
PGND
VIN
STATUS
SYNC
LM51501
EN
COMP
RT
VOUT
VSET
PVCC AVCC
CVOUT
RCOMP
RT
RSET
CCOMP
Figure 16. Typical Emergency Call Application
The EC configuration achieves high efficiency at light or medium load by alternating between the wake-up and
the low IQ standby modes. In EC configuration, the LM51501-Q1 limits the minimum duty cycle programmed by
VVOUT and VVIN. The minimum duty cycle limit is calculated using Equation 12.
æ
ö
VVIN
DMIN = 0.75´ 1-
ç
÷
VVOUT-REG ø
è
(12)
Due to this minimum duty cycle limit, the boost converter sources more current than required when the load
current is relatively small. As a result, the output voltage increases and eventually crosses the VOUT standby
threshold which is typically 6% higher than the VOUT regulation target. The LM51501-Q1 then goes into the low
IQ standby mode. The LM51501-Q1 wakes up when VOUT drops below the VOUT wake-up threshold which is
typically 3% higher than the VOUT regulation target. The device alternates between these two modes when the
inequality in Equation 13 is true.
æ
ç
è
ö2
DMIN
V
´
÷
SUPPLY
FSW ø
FSW
´
> ILOAD
2´LM
(VLOAD + VF - VSUPPLY )
(13)
Assuming VLOAD = VVOUT = VVOUT-REG and VSUPPLY = VVIN, the skip cycle operation starts when the inequality in
Equation 14 is true.
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æ
ö2
æ
ç
è
ö
÷
ø
VLOAD - VSUPPLY
VLOAD
V
´ 0.75´
ç
ç
÷
÷
SUPPLY
è
ø
>ILOAD
2´LM ´FSW ´ V
+ VF - VSUPPLY
(
)
LOAD
(14)
In EC configuration, the LM51501-Q1 does not generate any pulse if VCOMP is less than the 0.3 V and the
required minimum duty cycle limit is zero.
If the peak current limit is triggered before reaching the minimum duty cycle, the device terminates the LO driver
output immediately.
If VOUT is greater than the VOUT status-off threshold (typically 12% higher than the VOUT regulation target), the
LM51501-Q1 pulls the STATUS pin low.
In EC configuration, light-load efficiency is proportional with the inductor current ripple ratio.
Table 4. State of Each Pin in Wake-Up Mode
STATUS
SYNC
RT
COMP
EN
VOUT
PVCC/AVCC
LO
CS
VIN
VSET
VOUT standby
monitor is
enabled. VOUT
status-off monitor capability ≈ 75 mA
is enabled in EC
configuration.
I
Q ≈ 30 µA.
Enabled in
VIN status-off
monitor is
enabled in SS
configuration
Release
d
SS
configuratio
n
Enabled IPVCC
Enabled Enabled
Enabled
PWM
Enabled
Disabled
Table 5. Start-Stop vs Emergency-Call Configuration
CONFIGURATION
START-STOP
EMERGENCY-CALL
6.0 V, 6.5 V, 9.5 V, 11.5 V
VOUT regulation options
VSET resistor value [Ω]
29.4k, 19.1k, 9.53k, GND
90.9k, 71.5k, 54.9k, 41.2k
Clock Synchronization
Yes
No, SYNC should be grounded
VOUT wake-up threshold [V]
VOUT standby threshold [V]
VOUT status-off threshold [V]
VIN standby threshold [V]
VVOUT-REG × 1.03
VVOUT-REG × 1.24
N/A
VVOUT-REG × 1.06
VVOUT-REG × 1.12
N/A
VVOUT-REG × 1.03 + 1.0 V
STATUS pin control (Open-drain with pullup
resistor)
Released by VOUT wake-up
Pulled down by VIN standby
Released by VOUT wake-up
Pulled down by VOUT status-off
At heavy load when VVIN « VVOUT
Pulse width modulation (PWM)
LO turns on at every cycle in wake-up configuration. Skip cycle operation by
alternating between wake-up and standby configurations.
At light or no load when VVIN « VVOUT
Minimum on-time is limited
Minimum duty cycle is limited
LO turns on at every cycle in wake-up
configuration. On-time is limited by TON-MIN
VOUT goes out of regulation.
Duty cycle can drop to 0%. No pulses if
When VVIN ≈ VVOUT or VVIN ≥ VVOUT
.
VCOMP < 0.3 V and DMIN ≤ 0%.
Maximum duty-cycle limit
Typically 87%
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM51501-Q1 is a non-synchronous boost controller. The following design procedure can be used to select
the external components for the LM51501-Q1. Alternately, the WEBENCH® software can be used to generate
complete designs. The WEBENCH software uses an iterative design procedure and accesses comprehensive
data bases of components when generating a design. This section presents a simplified discussion of the design
process.
8.1.1 Bypass Switch / Disconnection Switch Control
The STATUS pin can be used to control an external bypass switch, which turns on when the boost is in standby
mode, or to control an external disconnection switch that turns off when the boost is in standby mode. In
Figure 17, a P-channel MOSFET is used to connect the boost supply input to the load directly when the boost is
in standby mode. This bypass switch can be turned on slowly, but it must be turned off fast after the STATUS pin
is pulled up by the wake-up event. The STATUS pin is rated to the absolute maximum 65 V.
VSUPPLY
VLOAD
STATUS
Figure 17. Bypass Switch Control Example
In Figure 18, a P-channel MOSFET is used to disconnect the boost supply output from the battery when boost is
not required. This disconnection switch can be turned off slowly, but it must be turned on fast after the STATUS
pin is pulled up by the wake-up event.
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Application Information (continued)
VLOAD
VBAT
PVCC
STATUS
LM51501
Figure 18. Disconnection Switch Control Example
8.1.2 Loop Response
The open-loop transfer function of a boost regulator is defined as the product of modulator transfer function and
feedback transfer function.
The modulator transfer function of a current mode boost regulator including a power stage with an embedded
current loop can be simplified as a one load pole (FLP), one ESR zero (FZ_ESR), and one Right Half Plane (RHP)
zero (FRHP) system, which can be explained as follows.
Modulator transfer function is defined as Equation 15:
æ
ç
ç
è
ö
÷
÷
ø
æ
ö
s
s
1+
´ 1-
ç
÷
ˆ
VLOAD(s)
2p´FZ_ESR
2p´FRHP ø
è
= AM
´
ˆ
VCOMP(s)
æ
ö
s
1+
ç
÷
2p´F
LP ø
è
where
RLOAD
D'
2
AM
=
´
RS ´10
•
•
•
2
F
=
[Hz]
LP
2p´RLOAD ´ COUT
1
FZ
=
[Hz]
ESR
2p´RESR ´ COUT
R
LOAD ´(D')2
2p´LM
FRHP
=
[Hz]
•
(15)
RESR is the equivalent series resistance (ESR) of the output capacitor which is specified in the capacitor data
sheet.
RCOMP, CCOMP, and CHF (see Figure 19) configure the error amplifier gain and phase characteristics to produce a
stable voltage loop with fast response. This compensation network creates a dominant pole at low frequency
(FDP_EA), a mid-band zero pole (FZ_EA), and a high frequency pole (FP_EA).
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Application Information (continued)
The feedback transfer function is defined as Equation 16:
æ
ç
ç
è
ö
÷
÷
ø
s
1+
ˆ
VCOMP(S)
2p´FZ_EA
-
= AFB ´
ˆ
VLOAD(S)
æ
ç
ç
è
ö æ
ö
÷
÷
ø
s
s
1+
´ 1+
÷ ç
÷ ç
ø è
2p´FDP_EA
2p´F
P_EA
where
1.2
AFB
=
´RO ´ Gm
VLOAD
•
•
•
1
FDP_EA
=
[Hz]
2p´RO ´ CCOMP
1
FZ_EA
=
[Hz]
2p´RCOMP ´ CCOMP
1
1
F
=
»
[Hz]
P_EA
2p´RCOMP ´ CHF
æ
ç
è
ö
÷
CCOMP ´ CHF
2p´RCOMP
´
CCOMP + CHF ø
•
(16)
RO (≈ 10 MΩ) is the output resistance of the error amplifier and Gm (≈ 2 mA/V) is the transconductance of the
error amplifier.
Assuming FLP is canceled by FZ_EA, FRHP is much higher than crossover frequency (FCROSS), and if FZ_ESR is
either canceled by FP_EA or FZ_ESR, then that is much higher than FCROSS. The open-loop transfer function can be
simplified as Equation 17:
1
T(s) = AM ´ AFB
´
æ
ç
ç
è
ö
s
1+
÷
÷
ø
2p´FDP_EA
(17)
Because |T(s)|=1 at the crossover frequency, the crossover frequency can be simply estimated using those
assumptions.
2
A
M ´ AFB -1
[
]
2p´RO ´ CCOMP
FCROSS
»
[Hz]
(18)
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8.2 Typical Application
The LM51501 requires a minimum number of external components to work. Figure 19 includes all optional
components as an example.
CSNB
RSNB
VSUPPLY
VLOAD
D1
LM
Q1
ILOAD
COUT
CIN
RLOAD
RF
RVOUT
RG
RSL
RS
CVIN
CF
CVOUT
(leave floating
if not used)
LO
CS
AGND
& PGND
VIN
VOUT
EN
(connect to VOUT
if not used)
STATUS
SYNC
RT
LM51501
COMP
(connect to GND
if not used)
VSET
PVCC
AVCC
RAVCC
RCOMP
CCOMP
RT
RSET
CHF
CAVCC
CPVCC
Optional components are in blue
Figure 19. Typical Circuit With Optional Components
8.2.1 Design Requirements
Table 6 lists the design parameters for Figure 19.
Table 6. Design Example Parameters
DESIGN PARAMETER
Target Application
VALUE
Start-stop
2.5 V
Minimum Input Supply Voltage (VSUPPLY(MIN)
)
Target Output Voltage (VLOAD
Maximum Load Current (ILOAD
Switching Frequency (FSW
D1 Diode Forward Voltage Drop
)
9.5 V
)
2.6 A (≈ 25 Watt)
440 kHz
)
0.7 V
Maximum Inductor Current Ripple Ratio (RR)
Estimated Full Load Efficiency (Eff)
0.6 (= 60%)
0.8 (= 80%)
1.2 (= 120%)
Current Limit Margin (MCL
FLP over FCROSS (K1)
FZ_EA over FLP (K2)
)
0.18 (FLP = 0.18 × FCROSS
)
3 (FZ_EA = 3 × FLP
)
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM51501-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
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In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 RSET Resistor
Select the value of RSET. Referring to Table 1, 9.53 kΩ is chosen to target 9.5 V in SS configuration. In general,
about 5% to approximately 10% output undershoot should be considered when selecting the VOUT regulation
target.
8.2.2.3 RT Resistor
The value of RT for 440-kHz switching frequency is calculated in Equation 19:
2.233ì1010
2.233ì1010
440 k
RT =
- 619 =
- 619 = 50.1kW
FSW _RT TYPICAL
(
)
(19)
A standard value of 49.9 kΩ is chosen for RT.
In general, higher frequency boost converters are smaller and faster, but they also have higher switching losses
and lower efficiency.
8.2.2.4 Inductor Selection (LM)
When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the
inductor current, and RHP zero frequency (FRHP).
Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope of
the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle (additional RSL
resistor is required, if not). Higher FRHP (= lower inductance) allows a higher crossover frequency and is always
preferred when using a smaller value output capacitor.
The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average
inductor current as a good compromise between RR, FRHP, and inductor falling slope. In this example, 60% ripple
ratio (RR = 0.6) is selected as the maximum inductor current ripple ratio (the inductor current ripple ratio is the
biggest when D = 0.33). The target inductance value is calculated using Equation 20:
9.5
0.14 ì
0.14 ìRLOAD
RR ìFSW
2.6
LM TARGET
=
=
= 1.94 m H
[ ]
(
)
0.6 ì 440 k
(20)
V
LOAD - VSUPPLY MIN ì V
)
(
9.5 - 2.5 ì2.5
SUPPLY MIN
(
(
)
)
(
)
LM GUIDE
=
=
= 1.61m H
[ ]
440 k ì9.5ì2.6
(
)
FSW ì VLOAD ìILOAD
(21)
If the target inductance is smaller than the value calculated using Equation 20, consider adding the slope
compensation resistor (RSL), as mentioned in the Slope Compensation Ramp (RSL) section, or select a smaller
RR and recalculate the inductance using Equation 21.
A standard value of 2.2 µH is chosen for LM. The required inductor saturation current rating is estimated after
selecting RS and RSL.
8.2.2.5 Current Sense (RS)
Based on the assumptions that 20% of current limit margin (MCL = 1.2), 80% estimated efficiency (Eff = 0.8) at
full load and no RSL populated, RS is calculated using Equation 22 and Equation 23.
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FSW_RT
(VVOUT - VVIN
)
1.2 + 0.6´
-10´30μA ´(2kΩ + RSL )´
´D
VVOUT-REG
FSYNC
RS
=
[W]
1
æ
ç
ö
÷
VSUPPLY(MIN) ´D´
VLOAD ´ILOAD
SUPPLY(MIN) ´Eff
FSYNC
1
2
ç
ç
÷
÷
10´
+
´
´MCL
V
LM
ç
÷
è
ø
(22)
(23)
9.5 - 2.5
9.5
(
)
-10ì30 m ì 2 k + 0 ì1ì 1-
2.5
≈
«
’
1.2 + 0.6ì
(
)
∆
÷
◊
9.5 + 0.7
RS =
= 7.44 m W
[ ]
≈
∆
2.5
1
’
÷
≈
«
’
2.5ì 1-
ì
∆
÷
◊
9.5ì 2.6
2.5ì0.8
1
9.5 + 0.7
2.2 u
440 k
∆
∆
÷
÷
10 ì
+
ì
ì1.3
2
∆
«
÷
◊
Substitute FSW_RT for FSYNC if clock synchronization is not used.
A standard value of 7 mΩ is chosen for RS. A low-ESL resistor is recommended to minimize the error caused by
the ESL.
8.2.2.6 Slope Compensation Ramp (RSL)
The minimum inductance value, which can prevent subharmonic oscillation without RSL, is calculated using
Equation 24. If the selected inductance value is less than the minimum inductance calculated using Equation 24,
add a slope compensation resistor (RSL) externally.
V
LOAD + VF - V
(
)
9.5 + 0.7 - 2.5
SUPPLY MIN
(
(
)
)
LM MIN = 0.5ì
ìRS ìMargin = 0.5ì
ì7 mì1.2 = 1.22 m H
[ ]
(
)
60 mìFSW
1.2 is the recommended margin to cover non-ideal factors.
If needed, use Equation 25 to find the RSL value which matches the typical amount of slope compensation.
+ VF - V
60 mì440 k
(24)
V
(
)
LOAD
SUPPLY(MIN)
RSL = 0.82´
´RS - 2k[W]
LM ´FSW ´ 30mA
(25)
In this example, RSL is not populated because the selected inductance value, 2.2 µH, is greater than the
minimum required inductance from Equation 24.
After selecting RS and RSL, the peak inductor current at current limit (IPEAK-CL) can be calculated. Setting the
inductor saturation current rating higher than the IPEAK-CL is recommended.
FSW_RT
VCL -10´30mA ´(2kW + RSL )´
´D
VSUPPLY(MIN)
FSYNC
IPEAK-CL
=
+
´ TD[A]
10´RS
LM
(26)
(27)
9.5 - 2.5
9.5
(
)
2.5
≈
«
’
◊
1.2 + 0.6ì
-10ì30 m ì 2 k ì1ì 1-
∆
÷
2.5
9.5 + 0.7
IPEAK-CL
=
+
ì 20 n = 17.0 A
[ ]
2.2 u
10ì7 m
TD is the typical propagation delay of current limit.
8.2.2.7 Output Capacitor (COUT
)
There are a few ways to select the proper value of output capacitor (COUT). The output capacitor value can be
selected based on output voltage ripple, output overshoot, or output undershoot due to load transient. In this
example, COUT is selected based on output undershoot because the wake-up performance is similar with no-load
to full-load transient performance.
The output undershoot becomes smaller by increasing FCROSS or by decreasing FLP. A smaller COUT is allowed
by increasing FCROSS or by decreasing FLP.
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To increase FCROSS, FSW and FRHP must be increased because the maximum FCROSS is, in general, limited at
1/10 of FRHP at VSUPPLY(MIN) or 1/10 of FSW, whichever is lower.
FRHP is calculated using Equation 28.
2
V
≈
’
2
SUPPLY MIN
(
)
9.5
2.5
≈
∆
’
RLOAD
ì
∆
∆
«
÷
÷
◊
ì
÷
◊
VLOAD + VF
2.6 9.5 + 0.7
«
FRHP
=
=
= 15.9 k HZ
[
]
2p ìLM
2p ì 2.2 u
(28)
FCROSS is selected at 1/10 of FRHP or 1/10 of FSW, whichever is lower.
FRHP
= 1.59 k HZ
[
]
10
FSW
10
(29)
(30)
440 k
10
=
= 44 k Hz
[
]
In this example, 1.59 kHz is selected as a target FCROSS and FLP is selected to be 286 Hz (K1 = 0.18).
In general, there is about 5% or less undershoot with FLP = 0.1 × FCROSS (K1 = 0.1) and 10% or less undershoot
with FLP = 0.2 × FCROSS (K1 = 0.2) during 0% to 100% load transient. The recommended K1 factor range is from
0.02 to 0.2.
FLP is calculated using Equation 31.
2
F
=
[Hz]
LP
2p´RLOAD ´ COUT
(31)
The minimum required output capacitance value is calculated using Equation 32.
2
2
9.5
2.6
COUT
=
=
= 304 m F
[ ]
2p ìRLOAD ìF
LP
2p ì
ì 286
(32)
(33)
The maximum output ripple current is calculated at the minimum input supply voltage using Equation 33:
VLOAD ìILOAD
9.5 ì 2.6
2ì 2.5
IRIPPLE _ COUT MAX
=
=
= 4.9 A
[ ]
(
)
2ì VSUPPLY MIN
(
)
The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using
multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the
diode and the MOSFET than the bulk aluminum capacitors to absorb the majority of the ripple current.
In this example, three 100-µF capacitors are placed in parallel to ensure ripple current capability. If high-ESR
capacitors are used for the output capacitor, additional 10-µF ceramic capacitors can be placed close to the
switching components to minimize switching noise.
8.2.2.8 Loop Compensation Component Selection and Maximum ESR
Based on Equation 18, CCOMP is calculated using Equation 34 and Equation 35:
é
ê
ë
ù2
RLOAD
D'
1.2
´
´
´ R ´Gm -1
2
]
ú
O
A
´ AFB -1
RS ´10
2
VLOAD
[
M
û
CCOMP(over damping)
=
=
2p´ RO ´ FCROSS
2p´ RO ´ FCROSS
(34)
ÿ2
Ÿ
9.5
2.5
»
…
…
…
1.2
2.6
7 mì10
9.5 + 0.7
ì
ì
ì10 Mì 2 m -1
Ÿ
2
9.5
Ÿ
⁄
CCOMP over damping
=
= 162 n[F]
(
)
2p ì10 Mì1.59 k
(35)
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By selecting CCOMP following Equation 34, the typical phase margin is set to 90⁰ and the loop response is
overdamped. In this example, FZ_EA is placed at a frequency 3 times higher than the FLP to have lower phase
margin but faster settling time (K2 = 3, target FZ_EA is 860 Hz). The recommended range of FZ_EA is from 1 × FLP
to 4 × FLP (1 ≤ K2 ≤ 4). Practical crossover frequency will vary with K2 with a range of 0.5 × FCROSS to 1.0 ×
FCROSS
.
CCOMP over damping
162 n
3
(
)
CCOMP
=
=
= 54 n F
[ ]
K2
(36)
A standard value of 56 nF is chosen for CCOMP
.
RCOMP is selected to set the error amplifier zero at 860 Hz.
1
1
RCOMP
=
=
= 3.31k W
[ ]
2p ìCCOMP ìFZ _ EA 2p ì56 nì860
(37)
A standard value of 3.32 kΩ is chosen for RCOMP
.
CHF is usually used to create a pole at high frequency (FP_EA) to cancel FZ_ESR. By using a small ESR capacitor
that can place FZ_ESR greater than 10 × FCROSS, the output capacitor ESR would not affect the loop stability. The
maximum ESR which does not affect the loop response is calculated using Equation 38.
1
1
RESR MAX
=
=
= 30 m W
[ ]
(
)
2p ìCOUT ìFCROSS ì10 2p ì330 uì1.59 k ì10
(38)
8.2.2.9 PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
The PVCC capacitor supplies the peak transient current to the LO driver. The value of PVCC capacitor (CPVCC
)
must be 4.7 μF or higher and must be a high-quality, low-ESR, ceramic capacitor. CPVCC must be placed close to
the PVCC pin and the PGND pin. A value of 4.7 μF is selected for this design example. The AVCC capacitor
must be placed close to the device. The recommended AVCC capacitor value is 0.1 μF. The AVCC resistor
should be placed between PVCC and AVCC pins. The recommended AVCC resistor value is 10 Ω.
8.2.2.10 VOUT Filter (CVOUT, RVOUT
)
The VOUT pin is the input of the internal VCC regulator and also is the input of the output voltage sensing. To
minimize noise at the VOUT pin, a 1-μF capacitor must be placed at the VOUT pin in most cases. If multiple
output capacitors are used, one of them can be placed at the VOUT pin as CVOUT. The VOUT capacitor must be
a high-quality, low-ESR, ceramic capacitor and must be placed close to the device. A resistor can be added at
the VOUT pin (RVOUT) to form a RC filter (see Figure 19). In this case, the maximum resistor value should be less
than or equal to 2 Ω.
8.2.2.11 Input Capacitor
The input capacitors reduce the input voltage ripple. Assuming high-quality ceramic capacitors are used for the
input capacitors, the maximum input voltage ripple can be calculated using Equation 39.
VLOAD
VRIPPLY(CIN)
=
2 [V]
32´LM ´ CIN ´FSW
(39)
The required input capacitor value is a function of the impedance of the source power supply. More input
capacitors are required if the impedance of the source power supply is not low enough. In the example, three 10-
µF ceramic capacitors are used.
8.2.2.12 MOSFET Selection
The MOSFET gate driver of the LM51501-Q1 is powered by the internal 5-V VCC regulator. The MOSFET driven
by the LM51501-Q1 must have a logic-level gate threshold with its on-resistance specified at 4.5 V or lower and
must be rated to handle the maximum output voltage plus any switch node ringing. The maximum gate charge is
limited by the 75-mA PVCC sourcing current limit, and is calculated in Equation 40:
75m
QG(@5V)
<
[C]
FSW
(40)
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A leadless package is preferred for high switching-frequency designs. The MOSFET gate capacitance should be
small enough so that the gate voltage is fully discharged during the off-time.
8.2.2.13 Diode Selection
A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery
charge. Low reverse leakage current is an important parameter when selecting the Schottky diode. The diode
must be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to
handle the average output current. To prevent chatter between wake-up and standby, the forward voltage drop of
the D1 diode must be less than 0.95 V at full load.
8.2.2.14 Efficiency Estimation
The total loss of the boost converter (PTOTAL) can be expressed as the sum of the losses in the LM51501-Q1
(PIC), MOSFET power losses (PQ), diode power losses (PD), inductor power losses (PL), and the loss in the
sense resistor (PRS).
PTOTAL = P + PQ + PD + P + PRS[W]
IC
L
(41)
PIC can be separated into gate driving loss (PG) and the losses caused by quiescent current (PIQ) in Equation 42.
P
= PG + P [W]
IQ
IC
(42)
Each power loss is approximately calculated in Equation 43 and Equation 44:
PG = QG(@5V) ´ VVOUT ´FSW [W]
(43)
(44)
P
= VVOUT ´IVOUT + VVIN ´IVIN[W]
IQ
IVIN and IVOUT values in each mode can be found in the supply current section of the Electrical Characteristics
table.
PQ can be separated into switching loss (PQ(SW)) and conduction loss (PQ(COND)) in Equation 45.
PQ = PQ(SW) + PQ(COND)[W]
(45)
Each power loss is approximately calculated using Equation 46:
PQ(SW) = 0.5´ V
(
+ VF ´I
)
´ t + tF ´FSW [W]
( )
SUPPLY R
VOUT
(46)
tR and tF are the rise and fall times of the low-side N-channel MOSFET device. ISUPPLY is the input supply current
of the boost converter.
2
PQ(COND) = D´ISUPPLY ´RDS(ON)[W]
(47)
RDS(ON) is the on-resistance of the MOSFET and is specified in the MOSFET data sheet. Consider the RDS(ON)
increase due to self-heating.
PD can be separated into diode conduction loss (PVF) and reverse recovery loss (PRR) in Equation 48.
PD = PVF + PRR[W]
(48)
Each power loss is approximately calculated using Equation 49 and Equation 50:
PVF = (1- D)´ VF ´ISUPPLY [W]
(49)
PRR = VLOAD ´ QRR ´FSW [W]
(50)
QRR is the reverse recovery charge of the diode and is specified in the diode data sheet. Remember that reverse
recovery characteristics of the diode strongly affect efficiency, especially when the output voltage is high.
PL is the sum of DCR loss (PDCR) and AC core loss (PAC) in Equation 51. DCR is the DC resistance of inductor
and is mentioned in the inductor data sheet.
P = PDCR + PAC[W]
L
(51)
Each power loss is approximately calculated by Equation 52, Equation 53, and Equation 54:
2
PDCR = ISUPPLY ´RDCR[W]
(52)
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PAC = K ´ DIbFSWa[W]
where
•
•
∆I is the peak-to-peak inductor current ripple.
K, α, and β are core dependent factors that can be provided by the inductor manufacturer.
(53)
1
VSUPPLY ´D´
FSYNC
DI =
LM
(54)
(55)
PRS is calculated as Equation 55:
2
PRS = D´ISUPPLY ´RS[W]
Efficiency of the power converter can be estimated using Equation 56:
V
LOAD ´ILOAD
Efficiency =
´100[%]
PTOTAL + VLOAD ´ILOAD
(56)
8.2.3 Application Curves
2.6 A to 1.3 A, 0.1 V/DIV, and 2 ms/DIV
200 µs/DIV
Figure 20. Automatic Wake-Up
Figure 21. Load Transient
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8.3 System Examples
8.3.1 Lower Standby Threshold in SS Configuration
By connecting the VIN pin to the VOUT pin, the current limit threshold at the current limit comparator input (VCL
)
is set to 1.2 V. In SS configuration, the VOUT standby threshold is ignored. The device goes into the standby
mode when VOUT > VIN standby threshold.
VSUPPLY
VLOAD
VOUT
LO
CS
VIN
AGND
& PGND
VOUT
EN
STATUS
SYNC
LM51501
COMP
RT
VSET
PVCC
AVCC
Figure 22. Lower Standby Threshold in SS Configuration
8.3.2 Dithering Using Dither Enabled Device
Dithering is achieved by connecting DITH output to the RT pin through a resistor.
LM5141
LM51501
RT
DITH
Figure 23. Dithering Using the Dither-Enabled Device LM5141
8.3.3 Clock Synchronization With LM5140
Clock synchronization can be achieved by connecting LM5140's SYNCOUT to SYNC.
LM5140
LM51501
SYNOUT
SYNC
Figure 24. Clock Synchronization With LM5140
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System Examples (continued)
8.3.4 Dynamic Frequency Change
Switching frequency can be changed dynamically during operation by changing the RT resistor.
LM51501
RT
Low Fsw/ Hi Fsw
Figure 25. Dynamic Frequency Change
8.3.5 Dithering Using an External Clock
If a low-frequency clock is available, dithering can be achieved by injecting a ramp signal into RT.
LM51501
RT
Figure 26. Dithering Using an External Clock
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9 Power Supply Recommendations
The LM51501-Q1 is designed to operate from a power supply or battery with a voltage range of 1.5 V to 42 V.
The input power supply should be able to supply the maximum boost supply voltage and handle the maximum
input current at 1.5 V. The impedance of the power supply and battery, including cables, must be low enough
that an input current transient does not cause an excessive drop. Additional input ceramic capacitors can be
required at the supply input of the converter.
10 Layout
10.1 Layout Guidelines
The performance of switching converters heavily depends on the quality of the PCB layout. The following
guidelines will help users design a PCB with the best power conversion performance, thermal performance, and
minimize generation of unwanted EMI.
•
•
•
•
•
•
•
Place Q1, D1, and RS first.
Place ceramic COUT and make the switching loop (COUT-D1-Q1-RS-COUT) as small as possible.
Leave copper area next to D1 for thermal dissipation.
Place LM51501-Q1 close to RS.
Place CPVCC as close to the device as possible between PVCC and PGND.
Connect PGND directly to the center of the sense resistor using a wide and short trace.
Connect CS to the center of the sense resistor. Connect through vias if required. Connect filter capacitor
between CS pin and exposed pad.
•
•
•
•
•
•
Connect AGND directly to the analog ground plain and connect to RSET, RT, and CCOMP.
Connect the exposed pad to the analog ground plain and the power ground plain through vias.
Connect LO directly to the gate of Q1.
Make the switching signal loop (LO-Q1-RS-PGND-LO) as small as possible.
Place CVOUT as close to the device as possible.
The LM51501-Q1 has an exposed thermal pad to aid power dissipation. Adding several vias under the
exposed pad helps conduct heat away from the device. Connect the vias to a large ground plane on the
bottom layer.
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10.2 Layout Example
Figure 27. LM51501-Q1 PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM51501-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RUM0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
0.6
0.5
A
0.35
0.25
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
0.1 MIN
(0.05)
A
-
A
2
5
.
0
0
0
SECTION A-A
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.3 0.1
2X 1.95
(0.2) TYP
EXPOSED
THERMAL PAD
8X (0.525)
5
8
A3
A2
12X 0.65
4
9
8X (0.3)
A
A
SYMM
17
2X
1.95
SEE TERMINAL
DETAIL
1
12
A4
0.35
0.25
16X
A1
0.1
C A B
13
16
PIN 1 ID
(OPTIONAL)
SYMM
16X
0.05
0.6
0.5
4223544/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RUM0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.3)
SYMM
8X (0.725)
16X (0.75)
16
13
8X (0.3)
A4
A1
1
12
16X (0.3)
17
(3.65)
SYMM
(0.9)
20X (0.65)
9
4
(
0.2) TYP
VIA
A2
A3
5
8
(0.9)
(R0.05)
TYP
(3.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223544/A 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RUM0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.613) TYP
(0.61)
TYP
8X (0.725)
16X (0.75)
16
13
8X (0.275)
A4
A1
17
1
12
(1.613)
TYP
16X (0.3)
SYMM
(0.61)
TYP
(3.65)
4X
1.02)
12X (0.65)
4
(
9
EXPOSED METAL
TYP
A2
A3
5
8
SYMM
(R0.05) TYP
(3.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
THERMAL PAD 17: 79% - PADS A1, A2, A3 & A4: 94%
SCALE:20X
4223544/A 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM51501QRUMRQ1
LM51501QRUMTQ1
LM51501QURUMRQ1
ACTIVE
WQFN
WQFN
WQFN
RUM
16
16
16
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 150
LM
51501Q
ACTIVE
ACTIVE
RUM
SN
SN
LM
51501Q
RUM
LM
51501QU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM51501QRUMRQ1
LM51501QRUMTQ1
LM51501QURUMRQ1
WQFN
WQFN
WQFN
RUM
RUM
RUM
16
16
16
2000
250
330.0
180.0
330.0
12.4
12.4
12.4
4.3
4.3
4.3
4.3
4.3
4.3
1.1
1.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
2000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM51501QRUMRQ1
LM51501QRUMTQ1
LM51501QURUMRQ1
WQFN
WQFN
WQFN
RUM
RUM
RUM
16
16
16
2000
250
367.0
213.0
367.0
367.0
191.0
367.0
38.0
35.0
38.0
2000
Pack Materials-Page 2
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Copyright © 2021, Texas Instruments Incorporated
LM51501-Q1_V01 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| LM51501QRUMRQ1 | TI | 具有 6V、6.5V、9.5V、11.5V 输出选项的汽车类 1.5V 至 42V 输入电压、低 IQ 升压控制器 | RUM | 16 | -40 to 125 | 获取价格 |
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| LM51501QRUMTQ1 | TI | 具有 6V、6.5V、9.5V、11.5V 输出选项的汽车类 1.5V 至 42V 输入电压、低 IQ 升压控制器 | RUM | 16 | -40 to 125 | 获取价格 |
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| LM51501QURUMRQ1 | TI | LM51501-Q1 Wide VIN Automotive Low IQ Boost Controller | 获取价格 |
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| LM51501QWRUMRQ1 | TI | 具有 6V、6.5V、9.5V、11.5V 输出选项的汽车类 1.5V 至 42V 输入电压、低 IQ 升压控制器 | RUM | 16 | -40 to 125 | 获取价格 |
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| LM51501QWRUMTQ1 | TI | 具有 6V、6.5V、9.5V、11.5V 输出选项的汽车类 1.5V 至 42V 输入电压、低 IQ 升压控制器 | RUM | 16 | -40 to 125 | 获取价格 |
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| LM5150QRUMRQ1 | TI | 具有 6.8V、7.5V、8.5V、10.5V 输出选项的汽车类 1.5V 至 42V 输入电压、低 IQ 升压控制器 | RUM | 16 | -40 to 150 | 获取价格 |
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| LM5150QRUMTQ1 | TI | 具有 6.8V、7.5V、8.5V、10.5V 输出选项的汽车类 1.5V 至 42V 输入电压、低 IQ 升压控制器 | RUM | 16 | -40 to 150 | 获取价格 |
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| LM5150QURUMRQ1 | TI | LM5150-Q1 Wide VIN Automotive Low IQ Boost Controller | 获取价格 |
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| LM5150QWRUMRQ1 | TI | 具有 6.8V、7.5V、8.5V、10.5V 输出选项的汽车类 1.5V 至 42V 输入电压、低 IQ 升压控制器 | RUM | 16 | -40 to 125 | 获取价格 |
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| LM5150QWRUMTQ1 | TI | 具有 6.8V、7.5V、8.5V、10.5V 输出选项的汽车类 1.5V 至 42V 输入电压、低 IQ 升压控制器 | RUM | 16 | -40 to 125 | 获取价格 |
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