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LM5150-Q1

SNVSAP6B –SEPTEMBER 2017–REVISED JUNE 2020

LM5150-Q1 Wide VIN Automotive Low I_QBoost Controller

1 Features

2 Applications

1

•

AEC-Q100 qualified:

•

Automotive start-stop system

Automotive emergency call system

Battery-powered boost converters

–

Device temperature grade 1: –40°C to +125°C

ambient operating temperature range

–

Device HBM ESD classification level 2

Device CDM ESD classification level C4B

3 Description

The LM5150-Q1 device is a wide input range

automatic boost controller. The device is suitable for

use as a pre-boost converter which maintains the

•

Functional Safety-Capable

–

Documentation available to aid functional

safety system design

output voltage from

a

vehicle battery during

automotive cranking or from a back-up battery during

the loss of vehicle battery.

Wide VIN input range from 1.5 V to 42 V when

VOUT ≥ 5 V (65-V absolute maximum)

•

Low shutdown current (I_Q≤ 5 µA)

Low standby current (I_Q≤ 15 µA)

The LM5150-Q1 switching frequency is programmed

by a resistor from 220 kHz to 2.3 MHz. Fast switching

(≥ 2.2 MHz) minimizes AM band interference and

allows for a small solution size and fast transient

response.

Four programmable output voltage options and

two selectable configurations

–

6.8 V, 7.5 V, 8.5 V, or 10.5 V

The LM5150-Q1 operates in low I_Qstandby mode

when the input or output voltage is above the preset

standby thresholds and automatically wakes up when

the output voltage drops below the preset wake-up

threshold.

Start-stop or E-call configurations

•

Adjustable switching frequency from 220 kHz to

2.3 MHz

•

Automatic wake-up and standby mode transition

Optional clock synchronization

Boost status indicator

The device transients in and out of the low I_Qstandby

mode to extend battery life at light load. A single

resistor programs the target output regulation voltage

as well as the configuration. Additional features

include low shutdown current, boost status indicator,

adjustable cycle-by-cycle current limit, and thermal

shutdown.

1.5-A peak MOSFET gate driver

Adjustable cycle-by-cycle current limit

Thermal shutdown

16-Pin WQFN with wettable flanks

Device Information⁽¹⁾

Create a custom design using the LM5150-Q1

with the WEBENCH^®Power Designer

PART NUMBER

PACKAGE

BODY SIZE (NOM)

LM5150-Q1

WQFN (16)

4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application Circuit

Efficiency (V_LOAD= 6.8 V, F_SW= 440 kHz)

V_SUPPLY

V_LOAD

100

95

90

85

LO

CS AGND

PGND VOUT

EN

VIN

STATUS

SYNC

RT

80

LM5150

COMP

V_SUPPLY=5.5V

VSET

VCC

AVCC

V_SUPPLY=4.5V

V_SUPPLY=3.5V

V_SUPPLY=2.5V

75

70

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

Load Current (A)

3

D008

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5150-Q1

SNVSAP6B –SEPTEMBER 2017–REVISED JUNE 2020

www.ti.com

Table of Contents

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 8

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 17

8

Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Application ................................................. 24

8.3 System Examples ................................................... 31

Power Supply Recommendations...................... 33

9

10 Layout................................................................... 33

10.1 Layout Guidelines ................................................. 33

10.2 Layout Example .................................................... 34

11 Device and Documentation Support ................. 35

11.1 Device Support...................................................... 35

11.2 Receiving Notification of Documentation Updates 35

11.3 Support Resources ............................................... 35

11.4 Trademarks........................................................... 35

11.5 Electrostatic Discharge Caution............................ 35

11.6 Glossary................................................................ 35

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 35

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (February 2020) to Revision B

Page

•

Added functional safety bullet to the Features ...................................................................................................................... 1

Changes from Original (September 2017) to Revision A

Page

•

Changed Functional Block Diagram to correct erroneous component symbols ................................................................. 11

Changed equation term from C_COMPto C_OUTin Equation 38 and changed solution from 23 mΩ to 21 mΩ ........................ 28

2

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SNVSAP6B –SEPTEMBER 2017–REVISED JUNE 2020

5 Pin Configuration and Functions

RUM Package

16-Pin WQFN

Top View

AP

16

15

14

13

SYNC

STATUS

EN

1

2

3

4

12 CS

11 AGND

10 PGND

EP

9

LO

VOUT

5

6

7

8

AP

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NO.

NAME

External synchronization clock input pin. The internal oscillator is synchronized to an external

clock by applying a pulse signal into the SYNC pin in the start-stop configuration. Connect

directly to ground if not used or in emergency call configuration. Maximum duty cycle limit

can be programmed by controlling the external synchronization clock frequency.

1

SYNC

I

Status indicator with an open-drain output stage. Internal pulldown switch holds the pin low

when the device is not boosting. The pin can be left floating if not used.

2

3

4

STATUS

EN

O

I

Enable pin. If EN is below 1 V, the device is in shutdown mode. The pin must be raised

above 2 V to enable the device. Connect directly to VOUT pin for an automatic boost.

Boost output voltage-sensing pin and input to VCC regulator. Connect to the output of the

boost converter.

VOUT

I/P

Output of the VCC bias regulator. Decouple locally to PGND using a low-ESR or low-ESL

ceramic capacitor located as close to the device as possible.

5

6

PVCC

NC

O/P

—

No internal electrical connection. Leave the pin floating or connect directly to ground.

Analog VCC supply input. Decouple locally to AGND using 0.1-µF low-ESR or low-ESL

ceramic capacitor located as close to the device as possible. Connect to the PVCC pin

through 10-Ω resistor.

7

AVCC

I/P

8

9

NC

LO

—

O

No internal electrical connection. Leave the pin floating or connect directly to ground.

N-channel MOSFET gate drive output. Connect to the gate of the N-channel MOSFET

through a short, low inductance path.

Power ground pin. Connect to the ground connection of the sense resistor through a wide

and short path.

10

11

12

PGND

AGND

CS

G

I

Analog ground pin. Connect to the analog ground plane through a wide and short path.

Current sense input pin. Connect to the positive side of the current sense resistor through a

short path.

Output of the internal transconductance error amplifier. The loop compensation components

must be connected between this pin and AGND.

13

14

COMP

RT

O

I

Switching frequency setting pin. The switching frequency is programmed by a single resistor

between RT and AGND.

(1) G = GROUND, I = INPUT, O = OUTPUT, P = POWER

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Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NO.

15

NAME

VSET

VIN

Configuration selection and VOUT regulation target programming pin. During initial power on,

a resistor between the VSET pin and AGND configures the VOUT regulation target and the

configuration.

I

16

Boost input voltage sensing pin. Connect to the input supply of the boost converter.

Exposed pad of the package. No internal electrical connection to silicon die. The EP is

electrically connected to anchor pads. The EP must be connected to the large ground copper

plain to reduce thermal resistance.

—

EP

—

Anchor pad of the package. No internal electrical connection to silicon die. The AP is

electrically connected to the EP. The AP can be left floating or soldered to the ground

copper.

—

AP

—

6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)⁽¹⁾

MIN

-0.3

-1.0

-2.0

-0.3

-1.0

-2.0

-0.3

-40

MAX

UNIT

VIN to AGND

65

VOUT to AGND

65

EN to AGND

RT to AGND⁽²⁾

AVCC+0.3

7

SYNC to AGND

Input

V

VSET to AGND

7

CS to AGND (DC)

CS to AGND (40ns transient)

CS to AGND (20ns transient)

PGND to AGND

AVCC+0.3

0.3

LO to AGND (DC)

LO to AGND (40ns transient)

LO to AGND (20ns transient)

STATUS to AGND⁽³⁾

COMP to AGND⁽²⁾

AVCC to AGND

PVCC+0.3

65

Output

V

AVCC+0.3

7

PVCC to AVCC

JunctionTemperature⁽⁴⁾

0.3

T_J

150

℃

T_stg

Storage Temperature

-55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The pin voltage is clamped by an internal circuit, and is not specified to have an external voltage applied.

(3) STATUS can go below ground during the STATUS low-to-high transition. The negative voltage on STATUS during this transition is

clamped by an internal diode and it does not damage the device.

(4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings

MIN

–2000

–750

–500

MAX

2000

750

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

V_(ESD)

Electrostatic discharge

Corner pins

Other pins

V

Charged device model

(CDM), per AEC Q100-011

500

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

4

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6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise specified)⁽¹⁾

MIN

1.5

5

NOM

MAX

42

UNIT

V

V_VIN

Boost input voltage sense

Boost output voltage sense⁽²⁾

EN input

V_VOUT

V_EN

42

V

0

42

V

V_PVCC

V_SYNC

V_CS

PVCC Voltage⁽³⁾

4.5

0

5

5.5

V

SYNC Input

5.5

V

Current sense Input

0

0.3

V

F_SW

Typical switching srequency

Synchronization pulse frequency

Operating junction temperature⁽⁴⁾

220

–40

2300

150

kHz

°C

F_SYNC

T_J

(1) Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical

Characteristics.

(2) The device requires minimum 5V at VOUT pin to start up

(3) V_PVCCshould be less than V_VOUT+ 0.3 V

(4) High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125°C.

6.4 Thermal Information

LM5150-Q1

THERMAL METRIC⁽¹⁾

RUM (WQFN)

UNIT

16 PINS

44.4

33.4

19.5

0.5

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JB

19.3

2

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= -40°C to 125°C. Unless otherwise

stated, V_VOUT= 6.8 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SUPPLY CURRENT

I_{SHUTDOWN(VOUT)}

VOUT shutdown current

V_VOUT= 12 V, V_EN= 0 V

5

12

25

µA

VOUT standby current (PVCC in

regulation, STATUS is low)

V_VOUT= 12 V, V_EN= 3.3 V, R_SET=

90.9 kΩ

I_{STANDBY(VOUT)}

15

VOUT operating current (exclude

current into RT resistor)

V_VOUT= 10.5 V, V_EN= 2.5 V, non-

switching, R_T= 9.09 kΩ

I_WAKEUP(VOUT)

I_{SHUTDOWN(VIN)}

I_STANDBY(VIN)

1.2

0.1

2.0 mA

VIN shutdown current

V_VIN= 12 V, V_EN= 0 V

0.5

µA

V_VIN= 12 V, V_EN= 3.3 V, R_SET= 29.4

kΩ

VIN standby current

V_VIN= 10.5 V, V_EN= 2.5 V, non-

switching, R_T= 9.09 kΩ

I_WAKEUP(VIN)

VIN operating current

PVCC regulation

30

45

µA

VCC REGULATOR

V_{VCC-REG-NOLOAD}

V_VOUT= 6.0 V, No load, wake-up

mode

4.75

5

5.25

V

V_{VCC-REG-FULLLOAD}

V_{VCC-UVLO-RISING}

V_{VCC-UVLO-FALLING}

V_VCC-UVLO-HYS

PVCC regulation

V_VOUT= 5.0 V, I_PVCC= 70 mA

AVCC rising

4.5

4.1

3.9

4.8

4.3

4.1

0.2

V

AVCC UVLO threshold

AVCC UVLO hysteresis

4.5

4.3

AVCC falling

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Electrical Characteristics (continued)

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= -40°C to 125°C. Unless otherwise

stated, V_VOUT= 6.8 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

I_VCC-CL

PVCC sourcing current limit

V_PVCC= 0 V, wake-up mode

75

mA

ENABLE

V_EN-RISING

V_EN-FALLING

I_EN

Enable threshold

EN bias current

EN rising

EN falling

V_EN= 42 V

1.7

1.3

2

V

1

100

nA

6.8-V SETTING

V_VOUT-REG

VOUT regulation target

R_SET= 29.4 kΩ or 90.9 kΩ

6.66

6.83

6.80

7.00

6.98

7.14

V

VOUT wake-up threshold

(V_VOUT-REG+3%)

R_SET= 29.4 kΩ or 90.9 kΩ, VOUT

falling

V_VOUT-WAKEUP

V_{VOUT-STANDBY1}

V_{VOUT-STATUS-OFF}

V_{VOUT-STANDBY2}

V_VIN-STANDBY

VOUT standby threshold

(V_VOUT-REG+6%, EC config)

R_SET= 90.9 kΩ, VOUT rising

R_SET= 29.4 kΩ, VOUT rising

R_SET= 29.4 kΩ, VIN rising

7.02

7.42

8.22

7.82

7.21

7.62

8.43

8.00

7.35

7.81

8.60

8.19

V

VOUT status off threshold

(V_VOUT-REG+12%, EC config)

VOUT standby threshold

(V_VOUT-REG+24%, SS config)

VIN standby threshold

(V_VOUT-WAKEUP+ 1.0 V, SS config)

7.5-V SETTING

V_VOUT-REG

VOUT regulation target

R_SET= 19.1 kΩ or 71.5 kΩ

7.37

7.52

7.50

7.73

7.67

7.88

V

VOUT wake-up threshold

(V_VOUT-REG+3%)

R_SET= 19.1 kΩ or 71.5 kΩ, VOUT

falling

V_VOUT-WAKEUP

V_{VOUT-STANDBY1}

V_{VOUT-STATUS-OFF}

V_{VOUT-STANDBY2}

V_VIN-STANDBY

VOUT standby threshold

(V_VOUT-REG+6%, EC config)

R_SET= 71.5 kΩ, VOUT rising

R_SET= 19.1 kΩ, VOUT rising

R_SET= 19.1 kΩ, VIN rising

7.74

8.19

9.07

8.50

7.95

8.40

9.30

8.73

8.11

8.61

9.46

8.93

V

VOUT status off threshold

(V_VOUT-REG+12%, EC config)

VOUT standby threshold

(V_VOUT-REG+24%, SS config)

VIN standby threshold

(V_VOUT-WAKEUP+ 1.0 V, SS config)

8.5-V SETTING

V_VOUT-REG

VOUT regulation target

R_SET= 9.53 kΩ or 54.9 kΩ

8.37

8.52

8.50

8.76

8.69

8.93

V

VOUT wake-up threshold

(V_VOUT-REG+3%)

R_SET= 9.53 kΩ or 54.9 kΩ, VOUT

falling

V_VOUT-WAKEUP

V_{VOUT-STANDBY1}

V_{VOUT-STATUS-OFF}

V_{VOUT-STANDBY2}

V_VIN-STANDBY

VOUT standby threshold

(V_VOUT-REG+6%, EC config)

R_SET= 54.9 kΩ, VOUT rising

R_SET= 9.53 kΩ, VOUT rising

R_SET= 9.53 kΩ, VIN rising

8.78

9.28

9.01

9.52

9.19

9.75

V

VOUT status off threshold

(V_VOUT-REG+12%, EC config)

VOUT standby threshold

(V_VOUT-REG+24%, SS config)

10.29 10.54 10.72

9.50 9.76 9.98

VIN standby threshold

(V_VOUT-WAKEUP+ 1.0 V, SS config)

10.5-V SETTING

V_VOUT-REG

VOUT regulation target

R_SET= GND or 41.2 kΩ

10.31 10.50 10.75

10.53 10.82 11.02

V

VOUT wake-up threshold

(V_VOUT-REG+3%)

V_VOUT-WAKEUP

R_SET= GND or 41.2 kΩ, VOUT falling

VOUT standby threshold

(V_VOUT-REG+6%, EC config)

V_{VOUT-STANDBY1}

V_{VOUT-STATUS-OFF}

R_SET= 41.2 kΩ, VOUT rising

10.84 11.13 11.33

11.46 11.76 12.04

V

VOUT status off threshold

(V_VOUT-REG+12%, EC config)

6

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Electrical Characteristics (continued)

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= -40°C to 125°C. Unless otherwise

stated, V_VOUT= 6.8 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

VOUT standby threshold

(V_VOUT-REG+24%, SS config)

V_{VOUT-STANDBY2}

V_VIN-STANDBY

R_SET= GND, VOUT rising

12.70 13.02 13.24

11.47 11.82 12.11

V

VIN standby threshold

(V_VOUT-WAKEUP+ 1.0 V, SS config)

R_SET= GND, VIN rising

RT

V_RT-REG

RT regulation voltage

1.2

V

CLOCK SYNCHRONIZATION

V_SYNC-RISINGSYNC rising threshold

V_SYNC-FALLINGSYNC falling threshold

PULSE WIDTH MODULATION AND OSCILLATOR

2.0

1.5

2.4

V

0.4

F_SW1

F_SW2

Switching frequency

R_T= 93.1 kΩ

R_T= 9.09 kΩ

204

239

270 kHz

2100 2300 2500 kHz

R_T= 9.09 kΩ,

F_SYNC= 2.0 MHz

F_SW3

Switching frequency

2000

50

kHz

ns

T_ON-MIN

Forced minimum on-time

SS config, V_COMP= 0 V

30

70

R_T= 9.09 kΩ, V_VIN= 1.5 V, V_VOUT

6.8 V, V_COMP= 0 V

=

60

%

D_MIN

Minimum duty cycle limit (EC config)

Maximum duty cycle limit

R_T= 93.1 kΩ, V_VIN= 8.4 V, V_VOUT

10.5 V, V_COMP= 0 V

16

%

SS config, R_T= 9.09 kΩ

EC config, R_T= 93.1 kΩ

83

87

91.5

%

D_MAX

CURRENT SENSE

V_VIN= 5.1 V, V_VOUT= 6.8 V at 25%

DC

102

120

138 mV

V_VIN= 3.4 V, V_VOUT= 6.8 V at 50%

DC

V_CSTH

Current limit threshold (CS-AGND)⁽¹⁾

V_VIN= 1.7 V, V_VOUT= 6.8 V at 75%

DC

ERROR AMPLIFIER

Gm

Transconductance

2

mA/V

µA

V

COMP souring current

COMP sinking current

COMP clamp voltage

COMP to PWM offset

V_COMP= 0 V

312

120

2.4

V_COMP= 1.5 V

2.6

0.3

V

STATUS

Low-state voltage drop

1-mA sinking

0.1

5

V

STATUS rise to LO delay

5-kΩ pullup to 5 V

4

6

µs

MOSFET DRIVER

High-state voltage drop

Low-state voltage drop

50-mA sinking

0.075

0.055

V

50-mA sourcing

THERMAL SHUTDOWN (TSD)

Thermal shutdown threshold

Temperature rising

175

15

°C

Thermal shutdown hysteresis

(1) V_CLat the current limit comparator input is 10 x V_CSTH

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6.6 Typical Characteristics

17

16.5

16

126

124

122

120

118

116

114

6.8V output

7.5V output

8.5V output

10.5V output

6.8V output

7.5V output

8.5V output

10.5V output

15.5

15

14.5

14

13.5

13

2

3

4

5

Supply Voltage (V)

6

7

8

9

10

20

30

40

50

Duty Cycle (%)

60

70

80

D001

D002

Figure 1. Peak Inductor Current vs Supply Voltage

Figure 2. Current Limit Threshold at CS vs Duty Cycle

(F_SW= 250 kHz, R_S= 8 mΩ)

6

5

4

3

2

1

0

6

5.5

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

20

40

60 80

I_PVCC(mA)

100

120

140

0

0.5

1

1.5

2

2.5

3

V_VOUT(V)

3.5

4

4.5

5

5.5

6

D003

D004

Figure 3. V_PVCCvs I_PVCC(VOUT = 6 V)

Figure 4. V_PVCCvs V_VOUT(EN = 3.3 V, I_PVCC= 10 mA, VOUT

Rising)

2750

2500

2250

2000

1750

1500

1250

1000

750

100

V_VOUT=6.8V

V_VOUT=7.5V

V_VOUT=8.5V

V_VOUT=10.5V

90

80

70

60

50

40

30

20

10

0

500

250

0

10

20

30

40

50

RT (kW)

60

70

80

90 100

0

1

2

3

4

5

6

V_VIN(V)

7

8

9

10 11 12

D005

D006

Figure 5. Frequency vs RT

Figure 6. Duty Cycle Limit in EC Configuration vs V_VIN

8

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Typical Characteristics (continued)

20

18

16

14

12

10

8

100

95

90

85

80

75

70

Shutdown

Standby

6

V_SUPPLY=5.5V

V_SUPPLY=4.5V

V_SUPPLY=3.5V

V_SUPPLY=2.5V

4

2

0

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

Load Current (A)

3

D007

D008

Figure 7. I_VOUTvs Temperature

Figure 8. Efficiency vs Load Current

(V_LOAD= 6.8 V, F_SW= 440 kHz, SS Configuration)

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7 Detailed Description

7.1 Overview

The LM5150-Q1 device is a wide input range automotive boost controller designed for automotive start-stop or

emergency-call applications. The device can maintain the output voltage from a vehicle battery during automotive

cranking or from a back-up battery during the loss of vehicle battery. The wide input range of the device covers

automotive load dump transient. The control method is based upon peak current mode control.

To extend the battery life time, the LM5150-Q1 features a low I_Qstandby mode with automatic wake-up and

standby control. The device stays in low I_Qstandby mode when the boost operation is not required, and

automatically enters wake-up mode when the output voltage drops below the preset wake-up threshold. High

value feedback resistors are included inside the device to minimize leakage current in the low I_Qstandby mode.

The LM5150-Q1 operates in one of two selectable configurations when waking up. In Start-Stop configuration

(SS configuration), the device runs at a fixed switching frequency without any pulse skipping until it enters

standby mode, which helps to have a fixed EMI spectrum. In Emergency-Call configuration (EC configuration),

the device will skip pulses as it automatically alternates between low I_Qstandby mode and wake-up mode to

extend the battery life in light load conditions.

The LM5150-Q1 switching frequency is programmable from 220 kHz to 2.3 MHz. Fast switching (≥ 2.2 MHz)

minimizes AM band interference and allows for a small solution size and fast transient response. A single resistor

at the VSET pin programs the target output regulation voltage as well as the configuration. This eliminates the

need for an external feedback resistor divider which enables low I_Qoperation. The device also features clock

synchronization in the SS configuration, low quiescent current in shutdown mode, a boost status indicator,

adjustable cycle-by-cycle current will limit, and thermal shutdown protection.

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7.2 Functional Block Diagram

V_SUPPLY

V_LOAD

D1

L_M

C_OUT

C_IN

R_LOAD

STATUS

VIN

(SS Mode)

+

StatusB

VSET

VIN_STANDBY

VOUT-STANDBY

Standby

œ

Q

S

REF

FB

VO_STANDBY

VO_WAKE

VOUT

+

VSET

Ready

R_SET

Wakeup

StatusB

POWER

ON

œ

Q

R

VOLTAGE

SELECT

+

S

R

(EC Mode)

VO_STATUS_OFF

œ

AVCC

PVCC

VOUT

REF

C_AVCC

Q

+

VIN_STANDBY (SS Mode)

VOUT

2.0 V/1.0 V

Enable

œ

EN

Ready

VCC_OK

VCC

Regulator

LM5150

Enable

R_AVCC

C_PVCC

Standby

TSD

œ

VOUT

VCC

UVLO

VCC_OK

V_CL+ 0.3 V

C/L

S

R

Q

+

LO

CS

V_{CS_OFFSET}

Wakeup

PWM

+

Q1

C/L

D_MIN/Forced_Ton

+

REF

FB

I_SLOPE

œ

R_SL

(optional)

30 uA peak

œ

R_F

D_MAX/Forced_Toff

V_{CS_OFFSET}

CLOCK

GENERATOR

GM AMP

2 kꢀ

V_CS

+

A = 10

œ

C_F

TLEB

R_S

PGND

AGND

COMP

RT

SYNC

0.3 V

R_COMP

R_T

C_COMP

7.3 Feature Description

7.3.1 Enable (EN Pin)

When the EN pin voltage is less than 1 V, the LM5150-Q1 is in shutdown mode with all other functions disabled.

To turn on the internal VCC regulator and begin start-up sequence, the EN pin voltage must be greater than 2 V.

If the EN pin is controlled by user input, it is recommended to supply a voltage greater than 3 V at the EN pin. If

the EN pin is not controlled by user input, connect the EN pin to the VOUT pin directly. See the Device

Functional Modes for more detailed information.

7.3.2 High Voltage VCC Regulator (PVCC, AVCC Pin)

The LM5150-Q1 contains an internal high voltage VCC regulator. The VCC regulator turns on when the EN pin

voltage is greater than 2 V. The VCC regulator is sourced from the VOUT pin and provides 5 V (typical) bias

supply for the N-channel MOSFET driver and other internal circuits.

The VCC regulator sources current into the capacitor connected to the PVCC pin with a minimum of 75-mA

capability when the LM5150-Q1 is in the wake-up mode and during the device configuration period. The

maximum sourcing capability is decreased to 17 mA in standby mode. The recommended PVCC capacitor is 4.7

µF to 10 µF. In normal operation, the PVCC pin voltage is either 5 V or V_VOUT+ 0.3 V, whichever is lower.

The AVCC pin is the analog bias supply input of the LM5150-Q1. The recommended AVCC capacitor is 0.1-μF.

Connect to the PVCC pin through 10-Ω resistor.

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Feature Description (continued)

7.3.3 Power-On Voltage Selection (VSET Pin)

During initial power on, the VOUT regulation target and the configuration are configured by a resistor connected

between the VSET and the AGND pins. The configuration starts when the EN pin voltage is greater than 2 V and

the AVCC voltage crosses the AVCC UVLO threshold, and requires typically 50 µs to finish. To reset and

reconfigure, EN should be toggled below 1 V or AVCC/VOUT must be fully discharged.

EN

VCC

UVLO

AVCC

50 us

Figure 9. Power-On Voltage Selection

The VOUT regulation target can be programmed to 6.8 V, 7.5 V, 8.5 V, or 10.5 V with the appropriate resistor

with 5% tolerance. The configuration can be selected as either SS or EC configuration. The LM5150-Q1 will not

switch during the 50-µs configuration time.

Table 1. VSET Resistors⁽¹⁾

CONFIGURATION

VOUT regulation target

R_SET[Ω]

EMERGENCY-CALL

START-STOP

6.8 V

7.5 V

8.5 V

10.5 V

41.2 k

6.8 V

7.5 V

19.1 k

8.5 V

10.5 V

90.9 k

71.5 k

54.9 k

29.4 k

9.53 k

Ground

(1) If other output regulation targets are required, contact the sales office/distributors for availability.

7.3.4 Switching Frequency (RT Pin)

The switching frequency of the LM5150-Q1 is set by a single RT resistor connected between the RT and the

AGND pins. The resistor value to set the switching frequency (F_SW) is calculated using Equation 1.

2.233ì10¹⁰

R_T=

- 619 W

F_{SW _RT TYPICAL}

(

)

(1)

The RT pin is regulated to 1.2 V by the internal RT regulator during wake-up.

7.3.5 Clock Synchronization (SYNC Pin in SS Configuration)

In SS configuration, the switching frequency of the LM5150-Q1 can be synchronized to an external clock by

directly applying a pulse signal to the SYNC pin. The internal clock of the LM5150-Q1 is synchronized at the

rising edge of the external clock. The device ignores the rising edge input during forced off-time.

The external synchronization pulse must be greater than the 2.4 V in the high logic state and must be less than

0.4 V in the low logic state. The duty cycle of the external synchronization pulse is not limited, but the minimum

pulse width should be greater than 100 ns. Because the maximum duty cycle limit and the peak current limit

threshold are affected by synchronizing the switching frequency to an external synchronization pulse, take extra

care when using the clock synchronization function. See the Maximum Duty Cycle Limit, Minimum Input Supply

Voltage and Current Limit (CS Pin) sections for more detailed information.

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If the minimum input supply voltage of the boost converter is greater than ¼ of the VOUT regulation target

(V_VOUT-REG), the frequency of the external synchronization pulse (F_SYNC) should be within +15% and –15% of the

typical free-running switching frequency (F_SW(TYPICAL)

)

0.85´F_{SW_RT(TYPICAL)}£ F_SYNC£ 1.15´F_{SW_RT(TYPICAL)}

(2)

In this range, a maximum 1:4 (V_SUPPLY:V_LOAD) step-up ratio is allowed.

A higher step-up ratio can be achieved by supplying a lower frequency synchronization pulse. 1:5 step-up ratio

can be achieved by selecting F_SYNCwithin –25% and –15% of the F_{SW_RT(TYPICAL)}

.

0.75´F_{SW_RT(TYPICAL)}£ F_SYNC£ 0.85´F_{SW_RT(TYPICAL)}

(3)

In this range, a maximum 1:5 (V_SUPPLY:V_LOAD) step-up ratio is allowed.

7.3.6 Current Sense, Slope Compensation, and PWM (CS Pin)

The LM5150-Q1 features a low-side current sense amplifier with a gain of 10, and provides an internal slope

compensation ramp to prevent subharmonic oscillation at high duty cycle. The device generates the slope

compensation ramp using a sawtooth current source with a slope of 30 µA × F_SW(typical). This current flows

through an internal 2-kΩ resistor and out of the CS pin. The slope compensation ramp is determined by the RT

resistor and is 60 mV × F_SW(typical) at the input of the current sense amplifier and 600 mV × F_SW(typical) at the

output of the current sense amplifier. The slope compensation ramp can be increased by adding an external

slope resistor (R_SL) between the sense resistor (R_S) and the CS pin, but take extra care when using R_SL,

because the peak current limit is affected by adding R_SL. See the Current Limit (CS Pin) section for more detailed

information.

Q1

Current Limit

œ

V

_CL+0.3 V

I_SLOPE

R_SL

(optional)

30 uA peak

+

CS

R_F

2 kꢀ

PWM

+

A = 10

œ

C_F

œ

R_S

0.3 V

COMP

Figure 10. Current Sensing and Slope Compensation

According to peak current mode control theory, the slope of the compensation ramp must be greater than half of

the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the

minimum amount of slope compensation should satisfy the following inequality:

(V_LOAD+ V_F) - V_SUPPLY

0.5´

×R_S×Margin < 30mA ´(2kΩ +R_SL)×F_SW

L_M

(4)

V_Fis a forward voltage drop of D1, the external diode. 1.2 is recommended as a margin to cover non-ideal

factors.

If required, R_SLcan be added to increase the slope of the compensation ramp from half to 82% of the slope of

the sensed inductor current during the falling slope. The typical R_SLvalue is calculated using Equation 5. The

maximum R_SLvalue is 1 kΩ

(V_LOAD+ V_F) - V_SUPPLY

0.82´

×R_S= 30mA ´(2kΩ +R_SL)×F_SW

L_M

(5)

The PWM comparator in Figure 10 compares the sum of sensed inductor current, the slope compensation ramp,

and a 0.3-V (typical) internal COMP-to-PWM offset with the COMP pin voltage (V_COMP), and terminates the

present cycle if the sum is greater than V_COMP

.

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7.3.7 Current Limit (CS Pin)

The LM5150-Q1 features cycle-by-cycle peak current limit without subharmonic oscillation at high duty cycle. If

the sum of the sensed inductor current and the slope compensation ramp exceeds the current limit threshold at

the current limit comparator input (V_CL), the current limit comparator immediately terminates the present cycle. To

minimize the peak current limit variation due to changes in either the supply voltage or the output voltage, the

device features a variable current limit threshold which is calculated using Equation 6.

(V_VOUT- V_VIN

)

V_CL= 1.2 + 0.6 ×

[V]

V_VOUT-REG

(6)

Cycle-by-cycle peak inductor current limit (I_PEAK-CL) in steady state calculated as follows:

F_{SW_RT}

V_CL-10´30mA ´(2kW + R_SL)´

´D

F_SYNC

I_PEAK-CL

=

10´R_S

(7)

(8)

V_SUPPLY

D = 1-

V_LOAD+V_F

F_SYNCis included in the equation because the peak amplitude of the slope compensation varies with the

frequency of the external synchronization clock. Substitute F_{SW_RT}for F_SYNCif clock synchronization is not used.

Boost converters have a natural pass-through path from the supply to the load through the high-side power diode

(D1). Due to this path, boost converters cannot provide current limit protection when the output voltage is close

to or less than the input supply voltage.

A small external RC filter (R_F, C_F) at the CS pin is required to overcome the leading edge spike of the current

sense signal. Select an R_Fvalue which is greater than 30 Ω and a C_Fvalue which is greater than 1 nF. Due to

the effect of the filter, the peak current limit is not valid when the on-time is less than 2 × R_F× C_F.

7.3.8 Feedback and Error Amplifier (COMP Pin)

The LM5150-Q1 includes internal feedback resistors which are set based on the VSET pin resistor selection.

These feedback resistors are disconnected from the VOUT pin in standby mode to minimize quiescent current.

The feedback resistor divider is connected to an internal transconductance error amplifier which features high

output resistance (R_O= 10 MΩ) and wide bandwidth (BW = 3 MHz). The internal transconductance error

amplifier sources current which is proportional to the difference between the feedback resistor divider voltage

and the internal reference. The output of the error amplifier is connected to the COMP pin, allowing the use of a

Type 2 loop compensation network.

R_COMP, C_COMPand optional C_HFloop compensation components configure the error amplifier gain and phase

characteristics to achieve a stable loop response. This compensation network creates a pole at very low

frequency (F_DP), a mid-band zero (F_{Z_EA}), and a high frequency pole (F_{P_EA}). See the Loop Compensation

Component Selection and Maximum ESR section for more detailed information.

7.3.9 Automatic Wake-Up and Standby

The LM5150-Q1 wakes up when V_VOUTdrops below the VOUT wake-up threshold. The device goes into standby

when V_VOUTrises above the VOUT standby threshold in EC or SS configuration or when V_VINrises above the

VIN standby threshold in SS configuration. The VOUT wake-up threshold is typically 3% higher than the VOUT

regulation target. The STATUS output is released in 3 µs (with a 50-kΩ pullup resistor to 5 V) after the wake-up

event. The LO driver is enabled 6 µs after the STATUS output starts rising.

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VOUT

VIN

WAKEUP

FB

V_VOUT-STANDBY

+

REF

VO_STANDBY

VOUT

VIN_STANDBY

(SS Config)

Standby

Q

S

R

VO_WAKE

REF

+

Wakeup

Figure 11. Automatic Wake-Up and Standby Control

In SS configuration, the VOUT standby threshold is typically 24% higher than the VOUT regulation target. The

VIN standby threshold is typically 1 V higher than the VOUT wake-up threshold in SS configuration. To prevent

chatter, the forward voltage drop of diode D1 must be less than 0.95 V. See Figure 15.

V_SUPPLY(Fast fall)

Engine Cranking

V_LOAD

V_{VOUT-STANDBY2}= 1.24 x V_VOUT-REG

V_VIN-STANDBY= V_VOUT-WAKE+1.0

when F_SWis low

V_VOUT-WAKEUP= 1.03 x V_VOUT-REG

V_VOUT-REG

Wake-up/Standby

Wake-up

Standby

STATUS

ILOAD

Full load

Very light load

Figure 12. Automatic Wake-Up and Standby Operation in the SS Configuration

(With Fast V_SUPPLYFall and Slow Switching)

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V_SUPPLY(Slow fall)

Engine Cranking

V_LOAD

V_{VOUT-STANDBY2}= 1.24 x V_VOUT-REG

V_VIN-STANDBY= V_VOUT-WAKE+1.0

when F_SWis fast

V_VOUT-WAKEUP= 1.03 x V_VOUT-REG

V_VOUT-REG

Wake-up

Wake-up/Standby

Standby

STATUS

ILOAD

Full load

Very light load /No load

Figure 13. Automatic Wake-Up and Standby Operation in the SS Configuration

(With Slow V_SUPPLYFall and Fast Switching)

In EC configuration, the VOUT standby threshold is typically 6% higher than the VOUT regulation target.

Because of the minimum duty cycle limit (see the Emergency-Call Configuration (EC Configuration) section), the

LM5150-Q1 alternates between the wake-up and the low I_Qstandby modes at medium or light load. See

Figure 16.

Vehicle Battery Disconnect

Vehicle Battery Reconnect

V_LOAD

V_{VOUT_STATUS_OFF}= 1.12 x V_VOUT-REG

V_{VOUT-STANDBY1}= 1.06 x V_VOUT-REG

V_VOUT-WAKEUP= 1.03 x V_VOUT-REG

V_VOUT-REG

V_SUPPLY

Wake-up

Standby

STATUS

ILOAD

Full load

Mid / Light load

Figure 14. Automatic Wake-Up and Standby Operation in EC Configuration

To minimize output undershoot when waking up, the LM5150-Q1 boosts the VOUT regulation target during the

first 128 cycles after the wake-up event. The regulation target becomes 3% higher than the original regulation

target for 64 cycles, 2% higher for the next 32 cycles and 1% higher for the final 32 cycles. The VOUT pin

voltage can rise up above the VOUT standby threshold even if switching stops at the VOUT standby threshold

because the energy stored in the inductor transfers to the output capacitor when switching stops. See the Device

Functional Modes for more information about the automatic wake-up and standby operation.

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7.3.10 Boost Status Indicator (STATUS Pin)

STATUS is an open-drain output and requires a pullup resistor between 5 kΩ and 100 kΩ. The pin is pulled up

after V_VOUTfalls below the VOUT wake-up threshold, and is toggled to a low logic state when V_VINrises above

the VIN standby threshold in SS configuration or when V_VOUTrises above the VOUT status off-threshold in EC

configuration. The pin is also pulled to ground when EN < 1 V and VOUT is greater than about 2 V, when AVCC

< V_{VCC-UVLO-FALLING}or during thermal shutdown.

7.3.11 Maximum Duty Cycle Limit, Minimum Input Supply Voltage

When designing a boost converter, the maximum duty cycle should be reviewed at the minimum supply voltage.

The minimum input supply voltage which can achieve the target output voltage is estimated from Equation 9.

F_SYNC

V_SUPPLY(MIN)» (V_VOUT-REG+ V_F)´(1- D_MAX)´

+ I_SUPPLY(MAX)´R_DCR+ I_SUPPLY(MAX)´(R_DS(ON)+ R_S)´D_MAX

F_{SW_RT}

where

•

I_SUPPLY(MAX)is the maximum input current

R_DCRis the DC resistance of the inductor

R_DS(ON)is the on-resistance of the MOSFET

(9)

Substitute F_{SW_RT}for F_SYNCif the clock synchronization is not used. The minimum input supply voltage can be

decreased by supplying F_SYNCwhich is less than F_{SW_RT}

.

This maximum duty cycle limit (D_MAX) is 87% (typical), but can fall down below 80% if the external

synchronization clock frequency is higher than 0.85 × F_{SW (TYPICAL)}. Select an F_SYNCwhich is within –25% and

–15% of the F_{SW (TYPICAL)}if 1:5 step-up ratio is required with clock synchronization. The minimum input supply

voltage can be further decreased by supplying a lower frequency external synchronization clock. See the Clock

Synchronization (SYNC Pin in SS Configuration) section for more information.

7.3.12 MOSFET Driver (LO Pin)

The LM5150-Q1 provides an N-channel MOSFET driver which can source or sink a peak current of 1.5 A. The

driver is powered by the 5-V VCC regulator and is enabled when the EN pin voltage is greater than 2 V and the

AVCC pin voltage is greater than the AVCC UVLO threshold.

7.3.13 Thermal Shutdown

Internal thermal shutdown is provided to protect the LM5150-Q1 if the junction temperature exceeds 175°C

(typical). When thermal shutdown is activated, the device is forced into a low power thermal shutdown state with

the MOSFET driver and the VCC regulator disabled. After the junction temperature is reduced (typical hysteresis

is 15⁰C), the device is re-enabled.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

If the EN pin voltage is below 1 V, the LM5150-Q1 is in shutdown mode with all functions disabled except EN. In

shutdown mode, the device reduces the VOUT pin current consumption to below 5.25 µA (typical) and the

STATUS pin is pulled to ground. The device can be enabled by raising the EN pin above 2 V and operates in

either the standby mode or the wake-up mode if V_AVCCis greater than the AVCC UVLO threshold.

Table 2. State of Each Pin in Shutdown Mode

STATUS

SYNC

RT

COMP

EN

VOUT

PVCC/AVCC

LO

CS

VIN

VSET

Grounded

Disabled

Enabled

I_Q≤ 5 µA

Disabled

Grounded

Disabled

I_Q≈ 0.1 µA

Disabled

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7.4.2 Standby Mode

If VOUT is greater than the VOUT standby threshold or VIN is greater than the VIN standby threshold in the SS

mode, the LM5150-Q1 enters into standby mode.

In standby mode, most functions are disabled, including the thermal shutdown, to minimize the current

consumption. The VOUT wake-up monitor is enabled in standby mode to allow wake-up if the VOUT voltage

drops below the VOUT wake-up threshold. The VCC regulator reduces the sourcing capability to 17 mA in

standby mode and the AVCC UVLO comparator is disabled.

The VOUT standby threshold effectively fulfills the overvoltage protection (OVP) function.

Table 3. State of Each Pin in Standby Mode

STATUS

SYNC

RT

COMP

EN

VOUT

PVCC/AVCC

LO

CS

VIN

VSET

I

_Q≤ 15 µA. VOUT

wake-up monitor

enabled

Enabled I_PVCC

capability ≈ 17 Grounded

Released or

Grounded

Disabled Disabled

Disabled

Enabled

Disabled

I_Q≈ 0.1 µA

Disabled

mA

7.4.3 Wake-Up Mode

The LM5150-Q1 wakes up from standby mode if VOUT drops below the VOUT wake-up threshold. There are two

configurations when the device wakes up. One is start-stop configuration (SS configuration) and the other is

emergency-call configuration (EC configuration). The configuration is selectable by the VSET resistor (see

Table 1).

7.4.3.1 Start-Stop Configuration (SS Configuration)

Bypass path

D1

V_LOAD

V_SUPPLY

L_M

œ

+

Reverse Battery

Protection Diode

Q1

C_OUT

R_LOAD

C_IN

Vehicle

Battery

R_S

AGND

PGND

LO

CS

VIN

STATUS

SYNC

LM5150

EN

COMP

VOUT

AVCC

RT

VSET

PVCC

R_COMP

C _VOUT

C_COMP

R_T

R_SET

Figure 15. Typical Start-Stop Application

The LM5150-Q1 runs at fixed switching frequency without any pulse skipping in SS configuration. The device

turns on the LO driver every cycle with T_ON-MINuntil entering into standby mode, which helps to prevent EMI

spectrum shifts. Because the MOSFET turns on every cycle, the boost converter output can be above the

regulation target if the required on-time is less than T_ON-MINwhen the boost supply voltage is close to the VOUT

regulation target or the load current is very small. The output voltage will rise above the VOUT regulation target if

the one of the inequalities below is true.

1

D´

< T_ON-MIN

F_SW

(10)

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2

(V_SUPPLY´ T_ON-MIN

2´L_M

)

F_SW

´

> I_LOAD

(V_LOAD+ V_F- V_SUPPLY

)

(11)

In SS configuration, the LM5150-Q1 enters into the standby mode if VOUT is greater than the VOUT standby

threshold—which is 24% higher than the VOUT regulation target—or if VIN is greater than the VIN standby

threshold.

7.4.3.2 Emergency-Call Configuration (EC Configuration)

Other

loads

œ

+

Vehicle

Battery

D1

V_SUPPLY

V_LOAD

L_M

+

C_OUT

Q1

C_IN

R_LOAD

Back-up

battery

R_S

LO

CS

AGND

PGND

VIN

STATUS

SYNC

LM5150

EN

COMP

RT

VOUT

VSET

PVCC AVCC

C_VOUT

R_COMP

R_T

R_SET

C_COMP

Figure 16. Typical Emergency Call Application

The EC configuration achieves high efficiency at light/medium load by alternating between the wake-up and low

I_Qstandby modes. In EC configuration, the LM5150-Q1 limits the minimum duty cycle programmed by V_VOUTand

V_VIN. The minimum duty cycle limit is calculated using Equation 12.

æ

ö

V_VIN

D_MIN= 0.75´ 1-

ç

÷

V_{VOUT-REG ø}

è

(12)

Due to this minimum duty cycle limit, the boost converter sources more current than required when the load

current is relatively small. As a result, the output voltage increases and eventually crosses the VOUT standby

threshold which is typically 6% higher than the VOUT regulation target. The LM5150-Q1 then goes into the low I_Q

standby mode. The LM5150-Q1 wakes up when VOUT drops below the VOUT wake-up threshold which is

typically 3% higher than the VOUT regulation target. The device alternates between these two modes when the

inequality below is true.

æ

ç

è

ö²

D_MIN

V

´

÷

SUPPLY

F_{SW ø}

F_SW

´

> I_LOAD

2´L_M

(V_LOAD+ V_F- V_SUPPLY)

(13)

Assuming V_LOAD= V_VOUT= V_VOUT-REGand V_SUPPLY= V_VIN, the skip cycle operation starts when the inequality

below is true.

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æ

ö²

æ

ç

è

ö

÷

ø

V_LOAD- V_SUPPLY

V_LOAD

V

´ 0.75´

ç

÷

SUPPLY

è

ø

>I_LOAD

2´L_M´F_SW´ V

+ V_F- V_SUPPLY

(

)

LOAD

(14)

In EC configuration, the LM5150-Q1 does not generate any pulse if V_COMPis less than the 0.3 V and the required

minimum duty cycle limit is zero.

If the peak current limit is triggered before reaching the minimum duty cycle, the device terminates the LO driver

output immediately.

If VOUT is greater than the VOUT status-off threshold (typically 12% higher than the VOUT regulation target), the

LM5150-Q1 pulls the STATUS pin low.

In EC configuration, light load efficiency is proportional with the inductor current ripple ratio.

Table 4. State of Each Pin in Wake-Up Mode

STATUS

SYNC

RT

COMP

EN

VOUT

PVCC/AVCC

LO

CS

VIN

VSET

VOUT standby

monitor is

enabled. VOUT

status-off monitor capability ≈ 75 mA

is enabled in EC

configuration.

I

_Q≈ 30 µA.

Enabled in

VIN status-off

monitor is

enabled in SS

configuration

Release

d

SS

configuratio

n

Enabled I_PVCC

Enabled Enabled

Enabled

PWM

Enabled

Disabled

Table 5. Start-Stop versus Emergency-Call Configuration

CONFIGURATION

VOUT regulation options

START-STOP

EMERGENCY-CALL

6.8 V, 7.5 V, 8.5 V, 10.5 V

VSET resistor value [Ω]

Clock Synchronization

29.4 k, 19.1 k, 9.53 k, GND

Yes

90.9 k, 71.5 k, 54.9 k, 41.2 k

No, SYNC should be grounded

VOUT wake-up threshold [V]

VOUT standby threshold [V]

VOUT status-off threshold [V]

VIN standby threshold [V]

V_VOUT-REG× 1.03

V_VOUT-REG× 1.24

N/A

V_VOUT-REG× 1.06

V_VOUT-REG× 1.12

N/A

V_VOUT-REG× 1.03 + 1.0 V

STATUS pin control (Open-drain with pullup

resistor)

Released by VOUT wake-up

Pulled down by VIN standby

Released by VOUT wake-up

Pulled down by VOUT status-off

At heavy load when V_VIN« V_VOUT

Pulse width modulation (PWM)

LO turns on at every cycle in wake-up configuration. Skip cycle operation by

alternating between wake-up and standby configurations.

At light/no load when V_VIN« V_VOUT

Minimum on-time is limited

Minimum duty cycle is limited

LO turns on at every cycle in wake-up

configuration. On-time is limited by T_ON-MIN

VOUT goes out of regulation.

Duty cycle can drop to 0%. No pulses if

When V_VIN≈ V_VOUTor V_VIN≥ V_VOUT

.

V_COMP< 0.3 V and D_MIN≤ 0%.

Maximum duty-cycle limit

Typically 87%

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5150-Q1 is a non-synchronous boost controller. The following design procedure can be used to select the

external components for the LM5150-Q1. Alternately, the WEBENCH^®software can be used to generate

complete designs. The WEBENCH software uses an iterative design procedure and accesses comprehensive

data bases of components when generating a design. This section presents a simplified discussion of the design

process.

8.1.1 Bypass Switch / Disconnection Switch Control

The STATUS pin can be used to control an external bypass switch, which turns on when the boost is in standby

mode, or to control an external disconnection switch that turns off when the boost is in standby mode. In

Figure 17, a P-channel MOSFET is used to connect the boost supply input to the load directly when the boost is

in standby mode. This bypass switch can be turned on slowly, but it must be turned off fast after the STATUS pin

is pulled up by the wake-up event. The STATUS pin is rated to the absolute maximum 65 V.

V_SUPPLY

V_LOAD

STATUS

Figure 17. Bypass Switch Control Example

In Figure 18, a P-channel MOSFET is used to disconnect the boost supply output from the battery when boost is

not required. This disconnection switch can be turned off slowly, but it must be turned on fast after the STATUS

pin is pulled up by the wake-up event.

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Application Information (continued)

V_LOAD

V_BAT

PVCC

STATUS

LM5150

Figure 18. Disconnection Switch Control Example

8.1.2 Loop Response

The open-loop transfer function of a boost regulator is defined as the product of modulator transfer function and

feedback transfer function.

The modulator transfer function of a current mode boost regulator including a power stage with an embedded

current loop can be simplified as a one load pole (F_LP), one ESR zero (F_{Z_ESR}), and one Right Half Plane (RHP)

zero (F_RHP) system, which can be explained as follows.

Modulator transfer function is defined as follows:

æ

ç

è

ö

÷

ø

æ

ö

s

1+

´ 1-

ç

÷

ˆ

V_LOAD(s)

2p´F_{Z_ESR}

2p´F_{RHP ø}

è

= A_M

´

ˆ

V_COMP(s)

æ

ö

s

1+

ç

÷

2p´F

^LPø

è

where

R_LOAD

D'

2

A_M

=

´

R_S´10

•

2

F

=

[Hz]

LP

2p´R_LOAD´ C_OUT

1

F_Z

=

[Hz]

ESR

2p´R_ESR´ C_OUT

R

_LOAD´(D')²

2p´L_M

F_RHP

=

[Hz]

•

(15)

R_ESRis the equivalent series resistance (ESR) of the output capacitor which is specified in the capacitor data

sheet.

R_COMP, C_COMP, and C_HF(see Figure 19) configure the error amplifier gain and phase characteristics to produce a

stable voltage loop with fast response. This compensation network creates a dominant pole at low frequency

(F_{DP_EA}), a mid-band zero (F_{Z_EA}), and a high frequency pole (F_{P_EA}).

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Application Information (continued)

The feedback transfer function is defined as follows:

æ

ç

è

ö

÷

ø

s

1+

ˆ

V_COMP(S)

2p´F_{Z_EA}

-

= A_FB´

ˆ

V_LOAD(S)

æ

ç

è

ö æ

ö

÷

ø

s

1+

´ 1+

÷ ç

ø è

2p´F_{DP_EA}

2p´F

P_EA

where

1.2

A_FB

=

´R_O´ Gm

V_LOAD

•

1

F_{DP_EA}

=

[Hz]

2p´R_O´ C_COMP

1

F_{Z_EA}

=

[Hz]

2p´R_COMP´ C_COMP

1

F

=

»

[Hz]

P_EA

2p´R_COMP´ C_HF

æ

ç

è

ö

÷

C_COMP´ C_HF

2p´R_COMP

´

C_COMP+ C_{HF ø}

•

(16)

R_O(≈ 10 MΩ) is the output resistance of the error amplifier and Gm (≈ 2 mA/V) is the transconductance of the

error amplifier.

Assuming F_LPis canceled by F_{Z_EA}, F_RHPis much higher than crossover frequency (F_CROSS), and F_{Z_ESR}is either

canceled by F_{P_EA}or F_{Z_ESR}is much higher than F_CROSS, the open-loop transfer function can be simplified as

follows:

1

T(s) = A_M´ A_FB

´

æ

ç

è

ö

s

1+

÷

ø

2p´F_{DP_EA}

(17)

Because |T(s)| = 1 at the crossover frequency, the crossover frequency can be simply estimated using those

assumptions.

2

A

_M´ A_FB-1

[

]

2p´R_O´ C_COMP

F_CROSS

»

[Hz]

(18)

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8.2 Typical Application

The LM5150-Q1 requires a minimum number of external components to work. Figure 19 includes all optional

components as an example.

C_SNB

R_SNB

V_SUPPLY

V_LOAD

D1

LM

Q1

R_F

I_LOAD

COUT

CIN

RLOAD

RVOUT

RS

RG RSL

CVIN

C_F

CVOUT

(leave floating

AGND

& PGND

LO CS

VIN

VOUT

EN

if not used)

(connect to VOUT

if not used)

STATUS

SYNC

RT

LM5150

COMP

(connect to GND

if not used)

VSET

PVCC AVCC

RCOMP

CCOMP

RAVCC

RT

RSET

CHF

CAVCC

CPVCC

Optional components are in blue

Figure 19. Typical Circuit With Optional Components

8.2.1 Design Requirements

Table 6 lists the design parameters for Figure 19.

Table 6. Design Example Parameters

DESIGN PARAMETER

Target Application

VALUE

Start-stop

2.5 V

Minimum Input Supply Voltage (V_SUPPLY(MIN)

)

Target Output Voltage (V_LOAD

Maximum Load Current (I_LOAD

Switching Frequency (F_SW

D1 Diode Forward Voltage Drop

)

8.5 V

)

2.94 A (≈ 25 Watt)

440 kHz

)

0.7 V

Maximum Inductor Current Ripple Ratio (RR)

Estimated Full Load Efficiency (Eff)

0.6 (= 60%)

0.8 (= 80%)

1.2 (= 120%)

Current Limit Margin (M_CL

F_LPover F_CROSS(K1)

F_{Z_EA}over F_LP(K2)

)

0.15 (F_LP= 0.15 × F_CROSS

)

3 (F_{Z_EA}= 3 × F_LP

)

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5150-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

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In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 R_SETResistor

Select the value of R_SET, referring to Table 1. 9.53 kΩ is chosen to target 8.5 V in SS configuration. In general,

about 5% to approximately 10% output undershoot should be considered when selecting the VOUT regulation

target.

8.2.2.3 R_TResistor

The value of R_Tfor 440-kHz switching frequency is calculated as follows:

2.233ì10¹⁰

440 k

R_T=

- 619 =

- 619 = 50.1kW

F_{SW _RT TYPICAL}

(

)

(19)

A standard value of 49.9 kΩ is chosen for RT.

In general, higher frequency boost converters are smaller and faster, but they also have higher switching losses

and lower efficiency.

8.2.2.4 Inductor Selection (L_M)

When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the

inductor current, and RHP zero frequency (F_RHP).

Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope of

the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle (additional R_SL

resistor is required if not). Higher F_RHP(= lower inductance) allows a higher crossover frequency and is always

preferred when using a smaller value output capacitor.

The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average

inductor current as a good compromise between RR, F_RHP, and inductor falling slope. In this example, 60% ripple

ratio (RR = 0.6) is selected as the maximum inductor current ripple ratio (the inductor current ripple ratio is the

biggest when D = 0.33). The target inductance value is calculated as follows:

8.5

0.14´

2.94

0.6´ 440k

0.14´R_LOAD

L_M(TARGET)

=

= 1.53m[H]

RR´F_SW

(20)

(21)

V

- V_SUPPLY(MIN)´ V

)

F_SW´ V_LOAD´I_LOAD

(

LOAD

SUPPLY(MIN)

(8.5 - 2.5)´ 2.5

L_M(GUIDE)

=

= 1.36m[H]

440k ´ 8.5´ 2.94

If the target inductance is smaller than the value calculated using Equation 21, consider adding the slope

compensation resistor (R_SL), as mentioned in the Slope Compensation Ramp (R_SL) section, or select a smaller

RR and recalculate the inductance using Equation 20.

A standard value of 1.5 µH is chosen for L_M. The required inductor saturation current rating is estimated after

selecting R_Sand R_SL.

8.2.2.5 Current Sense (R_S)

Based on the assumptions that 20% of current limit margin (M_CL= 1.2), 80% estimated efficiency (Eff = 0.8) at

full load and no R_SLpopulated, R_Sis calculated using Equation 22 and Equation 23.

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F_{SW_RT}

(V_VOUT- V_VIN

)

1.2 + 0.6´

-10´30μA ´(2kΩ + R_SL)´

´D

V_VOUT-REG

F_SYNC

R_S

=

[W]

1

æ

ç

ö

÷

V_SUPPLY(MIN)´D´

V_LOAD´I_LOAD

_SUPPLY(MIN)´Eff

F_SYNC

1

2

ç

÷

10´

+

´

´M_CL

V

L_M

ç

÷

è

ø

(22)

(23)

(8.5 - 2.5)

2.5

æ

ö

1.2 + 0.6´

-10´30μ´(2k + 0)´1´ 1-

ç

÷

8.5

8.5 + 0.7

è

ø

R_S

=

= 7.12m[W]

æ

ç

ö

÷

2.5

8.5 + 0.7

1.5u

1

æ

ö

2.5´ 1-

´

ç

÷

8.5´ 2.94

2.5´0.8

1

2

440k

è

ø

ç

÷

10´

+

´

´1.2

ç

÷

è

ø

Substitute F_{SW_RT}for F_SYNCif the clock synchronization is not used.

A standard value of 7 mΩ is chosen for R_S. A low-ESL resistor is recommended to minimize the error caused by

the ESL.

8.2.2.6 Slope Compensation Ramp (R_SL)

The minimum inductance value which can prevent subharmonic oscillation without R_SLis calculated using

Equation 24. If the selected inductance value is less than the minimum inductance calculated using Equation 24,

add a slope compensation resistor (R_SL) externally.

V

+ V_F- V

SUPPLY(MIN)

(

)

(8.5 + 0.7) - 2.5

60m´ 440k

LOAD

L_M(MIN)= 0.5´

´R_S´Margin = 0.5´

´7m´1.2 = 1.07m[H]

60m´F_SW

1.2 is the recommended margin to cover non-ideal factors.

If needed, use Equation 25 to find the R_SLvalue which matches the typical amount of slope compensation.

+ V_F- V

(24)

V

(

)

LOAD

SUPPLY(MIN)

R_SL= 0.82´

´R_S- 2k[W]

L_M´F_SW´ 30mA

(25)

In this example, R_SLis not populated because the selected inductance value, 1.5 µH, is greater than the

minimum required inductance from Equation 24.

After selecting R_Sand R_SL, the peak inductor current at current limit (I_PEAK-CL) can be calculated. Setting the

inductor saturation current rating higher than the I_PEAK-CLis recommended.

F_{SW_RT}

V_CL-10´30mA ´(2kW + R_SL)´

´D

V_SUPPLY(MIN)

F_SYNC

I_PEAK-CL

=

+

´ T_D[A]

10´R_S

L_M

(26)

(27)

(8.5 - 2.5)

8.5

2.5

æ

ö

1.2 + 0.6´

-10´30m ´ 2k ´1´ 1-

ç

÷

ø

2.5

8.5 + 0.7

è

I_PEAK-CL

=

+

´ 20n = 16.9[A]

10´7m

1.5u

T_Dis the typical propagation delay of current limit.

8.2.2.7 Output Capacitor (C_OUT

)

There are a few ways to select the proper value of output capacitor (C_OUT). The output capacitor value can be

selected based on output voltage ripple, output overshoot, or undershoot due to load transient. In this example,

C_OUTis selected based on output undershoot because the waking up performance is similar with no-load to full-

load transient performance.

The output undershoot becomes smaller by increasing F_CROSSor by decreasing F_LP: a smaller C_OUTis allowed by

increasing F_CROSSor by decreasing F_LP.

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To increase F_CROSS, F_SW, and F_RHPmust be increased because the maximum F_CROSSis, in general, limited at

1/10 of F_RHPat V_SUPPLY(MIN)or 1/10 of F_SWwhichever is lower.

F_RHPis calculated using Equation 28.

2

ö²

V

æ

ç

è

_SUPPLY(MIN)ö

8.5

2.5

æ

R_LOAD

´

÷

´

ç

÷

V_LOAD+ V_F

2.94 8.5 + 0.7

ø

è

ø

F_RHP

=

= 22.6k[Hz]

2p´L_M

2p´1.5u

(28)

F_CROSSis selected at 1/10 of F_RHPor 1/10 of F_SW, whichever is lower.

F_RHP

= 2.27 kHz

10

(29)

(30)

F_SW

10

440 k

10

=

= 44 kHz

In this example, 2.27 kHz is selected as a target F_CROSSand F_LPis selected to be 340 Hz (K1 = 0.15).

In general, there is about 5% or less undershoot with F_LP= 0.1 × F_CROSS(K1 = 0.1) and 10% or less undershoot

with F_LP= 0.2 × F_CROSS(K1 = 0.2) during 0% to 100% load transient. The recommended K1 factor range is from

0.02 to 0.2.

F_LPis calculated using Equation 31.

2

F

=

[Hz]

LP

2p´R_LOAD´ C_OUT

(31)

The minimum required output capacitance value is calculated using Equation 32.

2

8.5

C_OUT

=

= 324 mF

2p ìR_LOADìF_LP

2p ì

ì340

2.94

(32)

(33)

The maximum output ripple current is calculated at the minimum input supply voltage as follows:

V_LOAD´I_LOAD

8.5´ 2.94

I_{RIPPLE_COUT(MAX)}

=

= 5[A]

2´ V_SUPPLY(MIN)

2´ 2.5

The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using

multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the

diode and the MOSFET than the bulk aluminum capacitors to absorb the majority of the ripple current.

In this example, three 100-µF capacitors are placed in parallel to ensure ripple current capability. If high-ESR

capacitors are used for the output capacitor, additional 10-µF ceramic capacitors can be placed close to the

switching components to minimize switching noise.

8.2.2.8 Loop Compensation Component Selection and Maximum ESR

Based on Equation 18, C_COMPis calculated as follows:

é

ê

ë

ù²

R_LOAD

D'

1.2

´

´ R ´Gm -1

2

]

ú

O

A

´ A_FB-1

R_S´10

2

V_LOAD

[

M

û

C_{COMP(over damping)}

=

2p´ R_O´ F_CROSS

(34)

»

…

ÿ²

Ÿ

8.5

2.5

1.2

2.94

7mì10

8.5 + 0.7

ì

ì10Mì 2m -1

Ÿ

⁄

2

8.5

C_{COMP over damping}

=

= 111nF

(

)

2p ì10Mì 2.27 k

(35)

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By selecting C_COMPfollowing Equation 34, the typical phase margin is set to 90⁰ and the loop response is

overdamped. In this example, F_{Z_EA}is placed at three times higher frequency than F_LPto have lower phase

margin but faster settling time (K2 = 3, target F_{Z_EA}is 1.02 kHz). Recommended range of F_{Z_EA}is from 1 × F_LPto

4 × F_LP(1 ≤ K2 ≤ 4). Practical crossover frequency will vary with K2 with a range of 0.5 × F_CROSSto 1.0 × F_CROSS

.

C_{COMP over damping}

111n

(

)

C_COMP

=

= 37 nF

K2

A standard value of 33 nF is chosen for C_COMP

R_COMPis selected to set the error amplifier zero at 1.02 kHz.

3

(36)

.

1

R_COMP

=

= 4.73 kW

2pìC_COMPìF_{Z _EA}2pì33 nì1.02 k

(37)

A standard value of 4.64 kΩ is chosen for R_COMP

.

C_HFis usually used to create a pole at high frequency (F_{P_EA}) to cancel F_{Z_ESR}. By using a small ESR capacitor,

which can place F_{Z_ESR}greater than 10 × F_CROSS, the output capacitor ESR would not affect the loop stability.

The maximum ESR, which does not affect the loop response, is calculated using Equation 38.

1

R_{ESR MAX}

;

=

= 21mW

(

)

2pìC_OUTìF_CROSSì10 2pì330 mFì 2.27 kWì10

(38)

8.2.2.9 PVCC Capacitor, AVCC Capacitor, and AVCC Resistor

The PVCC capacitor supplies the peak transient current to the LO driver. The value of PVCC capacitor (C_PVCC

)

must be 4.7 μF or higher and must be a high-quality, low-ESR, ceramic capacitor. C_PVCCmust be placed close to

the PVCC pin and the PGND pin. A value of 4.7 μF is selected for this design example. The AVCC capacitor

must be placed close to the device. The recommended AVCC capacitor value is 0.1 μF. The AVCC resistor

should be placed between PVCC and AVCC pins. The recommended AVCC resistor value is 10 Ω.

8.2.2.10 VOUT Filter (C_VOUT, R_VOUT

)

The VOUT pin is the input of the internal VCC regulator and also is the input of the output voltage sensing. To

minimize noise at the VOUT pin, a 1-μF capacitor must be placed at the VOUT pin in most cases. If multiple

output capacitors are used, one of them can be placed at the VOUT pin as C_VOUT. The VOUT capacitor must be

a high-quality, low-ESR, ceramic capacitor and must be placed close to the device. A resistor can be added at

the VOUT pin (R_VOUT) to form a RC filter (see Figure 19). In this case, the maximum resistor value should be less

than or equal to 2 Ω.

8.2.2.11 Input Capacitor

The input capacitors reduce the input voltage ripple. Assuming high-quality ceramic capacitors are used for the

input capacitors, the maximum input voltage ripple can be calculated by using Equation 39.

V_LOAD

V_RIPPLY(CIN)

=

₂[V]

32´L_M´ C_IN´F_SW

(39)

The required input capacitor value is a function of the impedance of the source power supply. More input

capacitors are required if the impedance of the source power supply is not low enough. In the example, three 10-

µF ceramic capacitors are used.

8.2.2.12 MOSFET Selection

The MOSFET gate driver of the LM5150-Q1 is powered by the internal 5-V VCC regulator. The MOSFET driven

by the LM5150-Q1 must have a logic-level gate threshold with its on-resistance specified at 4.5 V or lower and

must be rated to handle the maximum output voltage plus any switch node ringing. The maximum gate charge is

limited by the 75-mA PVCC sourcing current limit, and is calculated as follows:

75m

Q_G(@5V)

<

[C]

F_SW

(40)

A leadless package is preferred for high switching-frequency designs. The MOSFET gate capacitance should be

small enough so that the gate voltage is fully discharged during the off-time.

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8.2.2.13 Diode Selection

A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery

charge. Low reverse leakage current is important parameter when selecting the Schottky diode. The diode must

be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to handle

the average output current. To prevent chatter between wake-up and standby, the forward voltage drop of the D1

diode must be less than 0.95 V at full load.

8.2.2.14 Efficiency Estimation

The total loss of the boost converter (P_TOTAL) can be expressed as the sum of the losses in the LM5150-Q1 (P_IC),

MOSFET power losses (P_Q), diode power losses (P_D), inductor power losses (P_L), and the loss in the sense

resistor (P_RS).

P_TOTAL= P + P_Q+ P_D+ P + P_RS[W]

IC

L

(41)

P_ICcan be separated into gate driving loss (P_G) and the losses caused by quiescent current (P_IQ).

= P_G+ P [W]

P

IC

IQ

(42)

Each power loss is approximately calculated as follows:

P_G= Q_G(@5V)´ V_VOUT´F_SW[W]

(43)

(44)

P

= V_VOUT´I_VOUT+ V_VIN´I_VIN[W]

IQ

I_VINand I_VOUTvalues in each mode can be found in the supply current section of the Electrical Characteristics.

P_Qcan be separated into switching loss (P_Q(SW)) and conduction loss (P_Q(COND)).

P_Q= P_Q(SW)+ P_Q(COND)[W]

(45)

(46)

Each power loss is approximately calculated as follows:

P_Q(SW)= 0.5´ V

(

+ V_F´I

)

´ t + t_F´F_SW[W]

( )

SUPPLY R

VOUT

t_Rand t_Fare the rise and fall times of the low-side N-channel MOSFET device. I_SUPPLYis the input supply current

of the boost converter.

2

P_Q(COND)= D´I_SUPPLY´R_DS(ON)[W]

(47)

R_DS(ON)is the on-resistance of the MOSFET and is specified in the MOSFET data sheet. Consider the R_DS(ON)

increase due to self-heating.

P_Dcan be separated into diode conduction loss (P_VF) and reverse recovery loss (P_RR).

P_D= P_VF+ P_RR[W]

(48)

Each power loss is approximately calculated as follows:

P_VF= (1- D)´ V_F´I_SUPPLY[W]

(49)

P_RR= V_LOAD´ Q_RR´F_SW[W]

(50)

Q_RRis the reverse recovery charge of the diode and is specified in the diode data sheet. Reverse recovery

characteristics of the diode strongly affect efficiency, especially when the output voltage is high.

P_Lis the sum of DCR loss (P_DCR) and AC core loss (P_AC). DCR is the DC resistance of inductor which is

mentioned in the inductor data sheet.

P = P_DCR+ P_AC[W]

L

(51)

Each power loss is approximately calculated as follows:

2

P_DCR= I_SUPPLY´R_DCR[W]

(52)

(53)

P_AC= K ´ DI^bF_SW^a[W]

1

V_SUPPLY´D´

F_SYNC

DI =

L_M

(54)

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∆I is the peak-to-peak inductor current ripple. K, α, and β are core dependent factors which can be provided by

the inductor manufacturer.

P_RSis calculated as follows:

2

P_RS= D´I_SUPPLY´R_S[W]

(55)

Efficiency of the power converter can be estimated as follows:

V

_LOAD´I_LOAD

Efficiency =

´100[%]

P_TOTAL+ V_LOAD´I_LOAD

(56)

8.2.3 Application Curves

Figure 20. Automatic Wake-Up

Figure 21. Load Transient (3 A to 1.5 A, 0.1 V/DIV)

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8.3 System Examples

8.3.1 Lower Standby Threshold in SS Configuration

By connecting the VIN pin to the VOUT pin, the current limit threshold at the current limit comparator input (V_CL

)

is set to 1.2 V. In SS configuration, the VOUT standby threshold is ignored. The device goes into the standby

mode when VOUT > VIN standby threshold.

V_SUPPLY

V_LOAD

VOUT

LO

CS

VIN

AGND

& PGND

VOUT

EN

STATUS

SYNC

LM5150

COMP

RT

VSET

PVCC

AVCC

Figure 22. Lower Standby Threshold in SS Configuration

8.3.2 Dithering Using Dither Enabled Device

Dithering is achieved by connecting DITH output to the RT pin through a resistor.

LM5141

LM5150

RT

DITH

Figure 23. Dithering Using Dither Enabled Device LM5141

8.3.3 Clock Synchronization With LM5140

Clock synchronization can be achieved by connecting SYNCOUT of the LM5140 to SYNC.

LM5140

LM5150

SYNOUT

SYNC

Figure 24. Clock Synchronization With LM5140

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System Examples (continued)

8.3.4 Dynamic Frequency Change

Switching frequency can be changed dynamically during operation by changing the RT resistor.

LM5150

RT

Low Fsw/ Hi Fsw

Figure 25. Dynamic Frequency Change

8.3.5 Dithering Using an External Clock

If a low-frequency clock is available, dithering can be achieved by injecting a ramp signal into RT.

LM5150

RT

Figure 26. Dithering Using an External Clock

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9 Power Supply Recommendations

The LM5150-Q1 is designed to operate from a power supply or a battery whose voltage range is from 1.5 V to 42

V. The input power supply should be able to supply the maximum boost supply voltage and handle the maximum

input current at 1.5 V. The impedance of the power supply and battery including cables must be low enough that

an input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required

at the supply input of the converter.

10 Layout

10.1 Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. The following

guidelines will help users design a PCB with the best power conversion performance, thermal performance, and

minimize generation of unwanted EMI.

•

Place Q1, D1, and R_Sfirst.

Place ceramic C_OUTand make the switching loop (C_OUT-D1-Q1-R_S-C_OUT) as small as possible.

Leave copper area next to D1 for thermal dissipation.

Place LM5150-Q1 close to R_S.

Place C_PVCCas close to the device as possible between PVCC and PGND.

Connect PGND directly to the center of the sense resistor using a wide and short trace.

Connect CS to the center of the sense resistor. Connect through vias if required. Connect filter capacitor

between CS pin and exposed pad.

•

Connect AGND directly to the analog ground plain and connect to R_SET, R_T, and C_COMP.

Connect the exposed pad to the analog ground plain and the power ground plain through vias.

Connect LO directly to the gate of Q1.

Make the switching signal loop (LO-Q1-R_S-PGND-LO) as small as possible.

Place C_VOUTas close to the device as possible.

The LM5150-Q1 has an exposed thermal pad to aid power dissipation. Adding several vias under the

exposed pad helps conduct heat away from the device. Connect the vias to a large ground plane on the

bottom layer.

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10.2 Layout Example

Figure 27. LM5150-Q1 PCB Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5150-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RUM0016C

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

3

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

0.6

0.5

A

0.35

0.25

PIN 1 INDEX AREA

DETAIL

OPTIONAL TERMINAL

TYPICAL

4.1

3.9

0.1 MIN

(0.05)

A

-

A

2

5

.

0

SECTION A-A

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2.3 0.1

2X 1.95

(0.2) TYP

EXPOSED

THERMAL PAD

8X (0.525)

5

8

A3

A2

12X 0.65

4

9

8X (0.3)

A

SYMM

17

2X

1.95

SEE TERMINAL

DETAIL

1

12

A4

0.35

0.25

16X

A1

0.1

C A B

13

16

PIN 1 ID

(OPTIONAL)

SYMM

16X

0.05

0.6

0.5

4223544/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RUM0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.3)

SYMM

8X (0.725)

16X (0.75)

16

13

8X (0.3)

A4

A1

1

12

16X (0.3)

17

(3.65)

SYMM

(0.9)

20X (0.65)

9

4

(

0.2) TYP

VIA

A2

A3

5

8

(0.9)

(R0.05)

TYP

(3.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4223544/A 02/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RUM0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.613) TYP

(0.61)

TYP

8X (0.725)

16X (0.75)

16

13

8X (0.275)

A4

A1

17

1

12

(1.613)

TYP

16X (0.3)

SYMM

(0.61)

TYP

(3.65)

4X

1.02)

12X (0.65)

4

(

9

EXPOSED METAL

TYP

A2

A3

5

8

SYMM

(R0.05) TYP

(3.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

THERMAL PAD 17: 79% - PADS A1, A2, A3 & A4: 94%

SCALE:20X

4223544/A 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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PACKAGE MATERIALS INFORMATION

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4-Jul-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM5150QRUMRQ1

LM5150QRUMTQ1

LM5150QURUMRQ1

WQFN

RUM

16

2000

250

330.0

180.0

330.0

12.4

4.3

1.1

8.0

12.0

Q1

2000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jul-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM5150QRUMRQ1

LM5150QRUMTQ1

LM5150QURUMRQ1

WQFN

RUM

16

2000

250

367.0

213.0

367.0

191.0

367.0

38.0

35.0

38.0

2000

Pack Materials-Page 2

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM5150QWRUMRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 6.8V、7.5V、8.5V、10.5V 输出选项的汽车类 1.5V 至 42V 输入电压、低 IQ 升压控制器 \| RUM \| 16 \| -40 to 125 控制器
文件：	总43页 (文件大小：1768K)
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