LM51521QRGRRQ1 [TI]

具有禁用旁路模式的汽车类 2.2MHz 宽输入电压、低 IQ 同步升压控制器 | RGR | 20 | -40 to 150;


型号：	LM51521QRGRRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有禁用旁路模式的汽车类 2.2MHz 宽输入电压、低 IQ 同步升压控制器 \| RGR \| 20 \| -40 to 150 控制器
文件：	总48页 (文件大小：2328K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

适用于启停/备用电池电源的LM5152x-Q1 汽车低I_Q同步升压控制器

• EMI 缓解

1 特性

– 可选可编程扩展频谱

• 符合面向汽车应用的AEC-Q100 标准

– 无引线封装

• 可编程性和灵活性

– 动态V_OUT跟踪

– 动态开关频率编程

– 可编程线路UVLO

– 可调软启动

– 自适应死区时间

– 升压状态指示器

• 集成保护特性

– 逐周期峰值电流限制

– 过压保护

– 温度等级1：–40°C 至+125°C，T_A

• 提供功能安全

– 有助于进行功能安全系统设计的文档

• 适用于宽工作电压范围的汽车类电池供电应用

– 3.8V 至42V 输入电压工作范围

– 5V 至20V（提供高达57V 的保护）动态可编程

V_OUT

– BIAS ≥3.8V 时最小输入升压为0.8V

– V_SUPPLY> V_LOAD时进行旁路操作（仅限

LM5152，请参阅器件比较表）

• 最小电池消耗

– HB-SW 短路保护

– 热关断

– 关断电流≤3 μA

– 自动模式转换

– 睡眠模式下的电池消耗≤11 μA（旁路操作，

电荷泵关闭）

– 睡眠模式下的电池消耗≤33 μA（旁路操作，

电荷泵打开）

– 睡眠模式下的偏置电流I_Q≤13 μA（跳跃模

式）

2 应用

• 高功率/高电流汽车启动-停止应用（主机）

• 稳压器模块

• 紧急呼叫应用

• 由备用电池/超级电容器供电的升压转换器

• 汽车冗余电源

3 说明

– 强大的5V MOSFET 驱动器

• 解决方案尺寸小、成本低

– 最大开关频率为2.2 MHz

– 内部自举二极管

LM5152x-Q1（LM5152-Q1 和 LM51521-Q1）器件是

一款涉及峰值电流模式控制、具有宽输入范围的同步升

压控制器。

– 在V_IN范围内峰值电流限值保持恒定

– 支持DCR 电感器电流感测

– 具有可润湿侧翼的QFN-20 封装

• 避免AM 频带干扰和串扰

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

LM5152-Q1

LM51521-Q1

QFN (20)

3.5mm x 3.5mm

– 可选的时钟同步

– 100 kHz 至2.2 MHz 开关频率

– 可选开关模式（FPWM、二极管仿真和跳跃模

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

式）

V_LOAD

V_SUPPLY

VOUT

BIAS

VCC

V_SUPPLY

COMP

MODE

VDD(MCU)

AGND

PGND

CSN

Boost Status

STATUS

Indicator to MCU

CSP

VREF

TRK

V_LOAD

UVLO SYNC/DITHER

典型应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSFF2

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

Table of Contents

9.4 Device Functional Modes..........................................28

10 Application and Implementation................................32

10.1 Application Information........................................... 32

10.2 Typical Application.................................................. 32

10.3 System Example.....................................................35

11 Power Supply Recommendations..............................36

12 Layout...........................................................................37

12.1 Layout Guidelines................................................... 37

12.2 Layout Example...................................................... 38

13 Device and Documentation Support..........................39

13.1 Device Support....................................................... 39

13.2 接收文档更新通知................................................... 39

13.3 支持资源..................................................................39

13.4 Trademarks.............................................................39

13.5 Electrostatic Discharge Caution..............................39

13.6 术语表..................................................................... 39

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................3

6 Device Comparison Table...............................................3

7 Pin Configuration and Functions...................................4

8 Specifications.................................................................. 6

8.1 Absolute Maximum Ratings........................................ 6

8.2 ESD Ratings............................................................... 6

8.3 Recommended Operating Conditions.........................7

8.4 Thermal Information....................................................7

8.5 Electrical Characteristics.............................................7

8.6 Typical Characteristics.............................................. 11

9 Detailed Description......................................................14

9.1 Overview...................................................................14

9.2 Functional Block Diagram.........................................14

9.3 Feature Description...................................................15

Information.................................................................... 39

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (February 2022) to Revision A (April 2022)

Page

• 将文档状态从“预告信息”更改为“量产数据”................................................................................................ 1

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

5 说明（续）

该器件采用低关断I_Q和低I_Q睡眠模式，可尽可能减少无负载和轻负载条件下的电池消耗。该器件还支持采用旁路

操作的超低 I_Q深度睡眠模式，当电源电压大于升压输出调节目标时，无需外部旁路开关。可使用跟踪功能对此输

出电压进行动态编程。

该器件的宽输入范围支持汽车冷启动和负载突降。当BIAS 等于或大于3.8V 时，最小输入电压可低至0.8V。用户

可通过外部电阻器对开关频率进行动态编程，编程范围为 100kHz 至 2.2MHz。2.2MHz 的开关频率可更大限度地

降低 AM 频带干扰，并支持实现小解决方案尺寸和快速瞬态响应。与转换器架构相比，控制器架构简化了严苛环

境温度条件下的热管理性能。

该器件具有内置的保护功能，例如在 V_IN范围内保持恒定的峰值电流限制、过压保护和热关断功能。外部时钟同

步、可编程展频调制以及具有超低寄生效应的无引线封装有助于降低 EMI 并避免串扰问题。附加功能包括线路

UVLO、FPWM、二极管仿真、DCR 电感器电流检测、可编程的软启动和升压状态指示器。

6 Device Comparison Table

Device Option

LM5152-Q1

Bypass Operation

Enabled

LM51521-Q1

Disabled

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

7 Pin Configuration and Functions

20 19

18 17 16

CSP

CSN

14 SYNC/DITHER/VH/CP

VOUT/SENSE

STATUS

UVLO/EN

12 MODE

11 LO

图7-1. 20-Pin QFN with Wettable Flanks RGR Package (Top View)

表7-1. Pin Functions

I/O⁽¹⁾

Description

Name

CSP

NO.

Current sense amplifier input. The pin operates as the positive input pin.

Current sense amplifier input. The pin operates as the negative input pin.

CSN

Output voltage sensing pin. An internal feedback resistor voltage divider is connected

from the pin to AGND. Connect a 0.1-μF local VOUT capacitor from the pin to ground.

VOUT/SENSE

High-side MOSFET drain voltage sensing pin. Connect the pin to the drain of the high-

side MOSFET through a short, low inductance path.

Status indicator with an open-drain output stage. The internal pulldown switch opens

when the output voltage is greater than the overvoltage threshold. The pin can be left

floating if not used.

STATUS

High-side gate driver output. Connect directly to the gate of the high-side N-channel

MOSFET through a short, low inductance path.

Switching node connection and the high-side MOSFET source voltage sensing pin.

Connect directly to the source of the high-side N-channel MOSFET and the drain of the

low-side N-channel MOSFET through a short, low inductance path. Connect to PGND

for a non-synchronous boost configuration.

High-side driver supply for bootstrap gate drive. Boot diode is internally connected from

VCC to this pin. Connect a 0.1-μF capacitor between this pin and SW. Connect to VCC

for a non-synchronous boost configuration.

Supply voltage input to the VCC regulator. Connect a 1-μF local BIAS capacitor from

the pin to ground.

BIAS

VCC

PGND

Output of the internal VCC regulator and supply voltage input of the internal MOSFET

drivers. Connect a 4.7-μF capacitor between the pin and PGND.

Power-ground pin. Connect directly to the source of the low-side N-channel MOSFET

and the power ground plane through a short, low inductance path.

Low-side gate driver output. Connect directly to the gate of the low-side N-channel

MOSFET through a short, low inductance path.

Device switching mode (FPWM, diode emulation, or skip) selection pin. The device is

configured to skip mode if the pin is open or if a resistor that is greater than 500 kΩis

connected from the pin to AGND during initial power-on. The device is configured to

FPWM mode by connecting the pin to VCC or if the pin voltage is greater than 2.0 V

during power-on. The device is configured to diode emulation mode by connecting the

pin to ground or the pin voltage is less than 0.4 V during initial power-on. The switching

mode can be dynamically programmed between FPWM and the DE mode during

operation.

MODE

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

表7-1. Pin Functions (continued)

I/O⁽¹⁾

Description

Name

NO.

Enable pin. The pin enables and disables the device. If the pin is less than 0.35 V, the

device shuts down. The pin must be raised above 0.65 V to enable the device.

Undervoltage lockout programming pin. The converter start-up and shutdown levels can

be programmed by connecting the pin to the supply voltage through a resistor voltage

divider. The low-side UVLO resistor must be connected to AGND. Connect to BIAS if not

used.

UVLO/EN

Synchronization clock input. The internal oscillator can be synchronized to an external

clock during operation. Connect to AGND if not used.

Clock dithering and spread spectrum modulation frequency programming pin. If a

capacitor is connected between the pin and AGND, the clock dithering and spread

spectrum function is activated. During the dithering operation, the capacitor is charged

and discharged with an internal 20-μA current source or sink. As the voltage on the pin

ramps up and down, the oscillator frequency is modulated between –6% and +5% of

the nominal frequency set by the RT resistor. The clock dithering and spread spectrum

can be deactivated during operation by pulling down the pin to ground.

SYNC/DITHER/VH/CP

I/O

VCC hold pin. If the pin is greater than 2.0 V, the device holds the VCC pin voltage when

the EN pin is grounded, which helps to restart quickly without reconfiguration.

Charge pump enable pin. If the pin is greater than 2.0 V, the internal charge pump

maintains the HB pin voltage above its HB UVLO threshold for bypass operation, which

allows the high-side switch to turn on 100% during bypass operation (LM5152-Q1 only).

Switching frequency setting pin. If no external clock is applied to the SYNC pin, the

switching frequency is programmed by a single resistor between the pin and AGND.

Switching frequency is dynamically programmable during operation.

1.0-V internal reference voltage output. Connect a 470-pF capacitor from the pin to

AGND. The V_OUTregulation target can be programmed by connecting a resistor voltage

divider from the pin to TRK. The resistance from the pin to AGND must be always

greater than 20 kΩif used. Connect the low-side resistor of the divider to AGND.

VREF

I/O

Boost converter output voltage can be dynamically programmed in the range of 5 V to

20 V during operation. The accuracy of the output voltage regulation is specified within

the range. If the TRK pin voltage is externally controlled, the resistor voltage divider is

not required.

Soft-start time programming pin. An external capacitor and an internal current source set

the ramp rate of the internal error amplifier reference during soft start. The device forces

diode emulation during soft-start time.

I/O

Output regulation target programming pin. The V_OUTregulation target can be

programmed by connecting the pin to VREF through a resistor voltage divider or by

controlling the pin voltage directly from a D/A. The recommended operating range of the

pin is from 0.25 V to 1.0 V.

TRK

AGND

COMP

Analog ground pin. Connect to the analog ground plane through a wide and short path.

Output of the internal transconductance error amplifier. Connect the loop compensation

components between the pin and AGND.

Exposed pad of the package. The EP must be soldered to a large analog ground plane

to reduce thermal resistance.

—

(1) G = Ground, I = Input, O = Output, P = Power

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

8 Specifications

8.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range (unless otherwise specified)⁽¹⁾

MIN

MAX

UNIT

BIAS to AGND

UVLO to AGND

CSP to AGND

–0.3

–1

BIAS + 0.3

0.3

CSP to CSN

VOUT to AGND

HB to AGND

Input⁽²⁾

HB to SW

5.8⁽³⁾

SW to AGND

SW to AGND (50 ns)

MODE, SYNC, TRK to AGND

STATUS to AGND

RT to AGND

5.5

VOUT + 0.3

2.5

–0.3

–1

PGND to AGND

VCC to AGND

0.3

5.8⁽³⁾

HO to SW (50 ns)

LO to PGND (50 ns)

Output⁽²⁾

–1

VREF, SS, COMP to AGND⁽⁴⁾

5.5

150

–0.3

–40

–55

(5)

Operating junction temperature, T_J

Storage temperature, T_STG

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) It is not allowed to apply an external voltage directly to VREF, COMP, SS, RT, LO, and HO pins.

(3) Operating lifetime is de-rated when the pin voltage is greater than 5.5 V.

(4) Maximum VREF pin sourcing current is 50 μA.

(5) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

8.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD Classification Level 2

±2000

Electrostatic

discharge

V_(ESD)

All pins

±500

±750

Charged-device model (CDM), per AEC Q100-011

CDM ESD Classification Level C4B

Corner pins

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

8.3 Recommended Operating Conditions

Over the recommended operating junction temperature range (unless otherwise specified)⁽¹⁾

MIN

NOM

MAX

UNIT

V_{SUPPLY(BOOST)}

V_LOAD(BOOST)

V_BIAS

0.8

Boost converter input (when BIAS ≥3.8 V)

Boost converter output

BIAS input

57⁽³⁾

3.8

V_UVLO

UVLO input

V_CSP, V_CSN

V_VOUT

Current sense input

0.8

Boost output sense

57⁽³⁾

V_TRK

TRK input

0.25

V_SYNC

Synchronization pulse input

Typical switching frequency

Synchronization pulse frequency

Operating junction temperature⁽²⁾

5.25

2200

150

f_SW

100

200

–40

kHz

°C

f_SYNC

T_J

(1) Recommended Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions,

see Electrical Characteristics.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

(3) V_VOUTregulation target can be up to 20 V. The pin voltage should be less than or equal to 57 V.

8.4 Thermal Information

RGR (QFN)

THERMAL METRIC⁽¹⁾

UNIT

20 PINS

43.3

39.9

17.8

0.8

R_qJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_qJC(top)

R_qJB

y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

y_JB

17.8

5.3

R_qJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= –40°C to 125°C. Unless otherwise

stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, R_VREF= 65 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

2.5

MAX

UNIT

SUPPLY CURRENT (BIAS, VCC, VOUT)

I_BIAS-SD

BIAS current in shutdown

V_UVLO= 0 V, V_OUT= 11.3 V

µA

BIAS current in deep sleep (skip

or diode emulation mode, charge V_UVLO= 2.5 V, V_TRK= 0.25 V, V_SYNC

pump off, VCC is supplied by

BIAS)

I_BIAS-DS1

µA

0 V, V_OUT= 12 V

BIAS current in deep sleep

(FPWM mode, charge pump off,

VCC is supplied by BIAS)

V_UVLO= 2.5 V, V_TRK= 0.25 V, V_SYNC

0 V, V_OUT= 12 V

I_BIAS-DS2

I_BIAS-DS3

I_BIAS-DS4

µA

BIAS current in deep sleep (skip

or diode emulation mode, charge V_UVLO= 2.5 V, V_TRK= 0.25 V, V_SYNC

pump on, VCC is supplied by

BIAS)

2.5 V, V_OUT= 12 V

BIAS current in deep sleep

(FPWM mode, charge pump on,

VCC is supplied by BIAS)

V_UVLO= 2.5 V, V_TRK= 0.25 V, V_SYNC

2.5 V, V_OUT= 12 V

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

8.5 Electrical Characteristics (continued)

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= –40°C to 125°C. Unless otherwise

stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, R_VREF= 65 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BIAS current in sleep (skip

mode, VCC is supplied by BIAS) OPEN, V_OUT= 5 V

V_UVLO= 2.5 V, V_TRK= 0.25 V, MODE =

I_BIAS-SLEEP

17.5

µA

BIAS current in active

(nonswitching, VCC is supplied

by BIAS)

V_UVLO= 2.5 V, V_TRK= 0.6 V, MODE =

VCC

I_BIAS-ACTIVE

I_VOUT-SD

I_VOUT-DS

I_VOUT-ACTIVE

I_BATTERY-SD

1.2

1.5

VOUT current in shutdown

V_UVLO= 0 V, V_OUT= 11.3 V

µA

VOUT current in deep sleep

(diode emulation mode)

V_UVLO= 2.5 V, V_TRK= 0.25 V, V_OUT

12 V

1.5

VOUT current in active

(nonswitching)

V_UVLO= 2.5 V, V_TRK= 0.6 V, MODE =

VCC

µA

Battery drain in shutdown

V_UVLO= 0 V, V_OUT= 11.3 V

2.5

Battery drain in deep sleep (skip

or diode emulation mode, charge

pump off)

V_UVLO= 2.5 V, V_TRK= 0.25 V, V_SYNC

0 V

I_BATTERY-DS1

I_BATTERY-DS2

I_BATTERY-DS3

I_BATTERY-DS4

µA

Battery drain in deep

sleep (FPWM mode, charge

pump off)

V_UVLO= 2.5 V, V_TRK= 0.25 V, V_SYNC

0 V

Battery drain in deep sleep (skip

or diode emulation mode, charge

pump on)

V_UVLO= 2.5 V, V_TRK= 0.25 V, V_SYNC

2.5 V

Battery drain in deep

sleep (FPWM mode, charge

pump on)

V_UVLO= 2.5 V, V_TRK= 0.25 V, V_SYNC

2.5 V

ENABLE, UVLO

V_EN-RISING

Enable threshold

Enable hysteresis

EN rising

EN falling

0.45

0.35

0.55

0.45

0.65

0.55

130

V_EN-FALLING

V_EN-HYS

UVLO pulldown hysteresis

current

I_UVLO-HYS

V_UVLO= 0.7 V

µA

V_UVLO-RISING

V_UVLO-FALLING

V_UVLO-HYS

UVLO threshold

UVLO hysteresis

UVLO rising

UVLO falling

1.05

1.1

1.075

1.15

1.025

1.125

SYNC/DITHER/VH/CP

SYNC threshold/SYNC detection

V_SYNC-RISING

SYNC rising

SYNC falling

threshold

V_SYNC-FALLING

SYNC threshold

0.4

Minimum SYNC pullup pulse

width

100

µA

I_DITHER

Dither source and sink current

f_SWmodulation (upper limit)

f_SWmodulation (lower limit)

Dither disable threshold

Δf_SW1

Δf_SW2

–6%

V_{DITHER-FALLING}

VCC

0.65

0.75

0.85

V_VCC-REG1

V_VCC-REG2

V_VCC-REG3

V_{VCC-UVLO-RISING}

VCC regulation

I_VCC= 100 mA

No load

4.75

3.45

3.55

3.2

5.25

VCC regulation

VCC regulation during dropout

VCC UVLO threshold

V_BIAS= 3.8 V, I_VCC= 100 mA

VCC rising

3.65

3.3

3.75

3.4

V_{VCC-UVLO-FALLING}VCC UVLO threshold

VCC falling

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

8.5 Electrical Characteristics (continued)

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= –40°C to 125°C. Unless otherwise

stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, R_VREF= 65 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_VCC-CL

VCC sourcing current limit

V_VCC= 4 V

100

CONFIGURATION (MODE)

V_MODE-RISING

V_MODE-FALLING

FPWM mode threshold

MODE rising

2.0

Diode emulation mode threshold MODE falling

0.4

V_RT

RT regulation

0.5

VREF, TRK, VOUT

V_REF

VREF regulation target

0.99

1.005

5.085

VREF resistor divider to make V_TRK

0.25 V, R_VREF= 65 kΩ

VOUT regulation target1 with

resistor divider

V_OUT-REG

4.915

VREF resistor divider to make V_TRK

0.5 V, R_VREF= 65 kΩ

VOUT regulation target2 with

resistor divider

9.9

19.8

4.91

9.88

19.8

10.1

20.2

VREF resistor divider to make V_TRK

1.0 V, R_VREF= 65 kΩ

VOUT regulation target3 with

resistor divider

VOUT regulation target1 using

TRK

5.09

V_TRK= 0.25 V, R_VREF= 65 kΩ

V_TRK= 0.5 V, R_VREF= 65 kΩ

V_TRK= 1.0 V, R_VREF= 65 kΩ

VOUT regulation target2 using

TRK

10.11

VOUT regulation target3 using

TRK

V_OUT-REG

I_TRK

20.2

TRK bias current

SOFT START, DE to FPWM TRANSITION

I_SS

Soft-start current

1.5

1.7

µA

V_SS-DONE

R_SS

V_SS-DIS

V_SS-FB

MODE transition start

SS rising

1.3

SS pulldown switch R_DSON

SS discharge detection threshold

internal SS to FB clamp

V_FB= 0 V

CURRENT SENSE (CSP, CSN, SW, SENSE)

Peak slope compensation

amplitude

V_SLOPE

Referenced to CS input

A_CS

Current sense amplifier gain

CSP = 3.0 V

CSP = 1.5 V

V/V

Positive peak current limit

threshold (CSP-CSN)

V_CLTH

CSP = 3.0 V, MODE = GND

Positive peak current limit

threshold (CSP-CSN)

CSP = 1.5 V, MODE = GND

MODE = GND

V_ZCD-DE

I_CSN

ZCD threshold (SW-SENSE)

CSN bias current

µA

I_CSP

CSP bias current

115

BOOT FAULT PROTECTION (HB)

Maximum replenish pulse cycles

cycles

Replenish off cycles

Number of sets to enter hiccup

mode protection

sets

Off-cycle during hiccup mode off

512

cycles

ERROR AMPLIFIER (COMP)

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

8.5 Electrical Characteristics (continued)

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= –40°C to 125°C. Unless otherwise

stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, R_VREF= 65 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Transconductance

mA/V

Maximum COMP sourcing

current

I_SOURCE-MAX

V_COMP= 0 V

µA

I_SINK-MAX

Maximum COMP sinking current V_COMP= 1.8 V

COMP maximum clamp voltage COMP rising

COMP minimum clamp voltage,

µA

V_CLAMP-MAX

1.8

2.2

2.55

V_CLAMP-MIN

active in sleep and deep sleep

mode

COMP falling

0.25

PULSE WIDTH MODULATION (PWM)

f_SW1

Switching frequency

1980

100

2200

115

2420

kHz

R_T= 220 kΩ

R_T= 9.09 kΩ

R_T= 220kΩ

R_T= 9.09 kΩ

f_SW2

Switching frequency

t_ON-MIN

t_OFF-MIN

D_MAX1

D_MAX2

Minimum controllable on time

Minimum forced off time

Maximum duty cycle limit

115

90%

75%

94%

80%

98%

83%

LOW IQ SLEEP MODE

V_WAKE

Internal wakeup threshold

VOUT falling (referenced to V_OUT-REG

)

98.5%

Sleep to wake-up delay

R_T= 9.09 kΩ

μs

STATUS, OVP

Overvoltage threshold (OVP

threshold, bypass mode

threshold)

V_OVTH-RISING

VOUT rising (referenced to V_OUT-REG

)

104.5%

100.5%

108%

111%

109%

Overvoltage threshold (OVP

threshold, bypass mode

threshold)

V_OVTH-FALLING

R_STATUS

VOUT falling (referenced to V_OUT-REG

)

105%

STATUS pulldown switch R_DSON

Minimum BIAS for valid STATUS

180

2.5

MOSFET DRIVER

High-state voltage drop (HO

driver)

100mA sinking

100mA sourcing

100mA sinking

100mA sourcing

0.08

0.04

0.08

0.04

0.15

0.1

Low-state voltage drop (HO

driver)

High-state voltage drop (LO

driver)

0.17

0.1

Low-state voltage drop (LO

driver)

V_HB-UVLO

I_HB-SLEEP

t_DHL

HB-SW UVLO threshold

HB quiescent current in sleep

HO off to LO on dead time

LO off to HO on dead time

HB diode resistance

HB-SW falling

HB-SW = 5 V

2.2

2.5

3.5

3.0

µA

t_DLH

1.2

THERMAL SHUTDOWN

T_TSD-RISINGThermal shutdown threshold

T_TSD-HYSThermal shutdown hysteresis

Temperature rising

175

°C

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

8.6 Typical Characteristics

2400

2200

2000

1800

1600

1400

1200

1000

800

2.42

2.38

2.34

2.3

2.26

2.22

2.18

2.14

2.1

600

2.06

2.02

1.98

400

200

5 6 7 8 10

30 40 50 70 100

RT Resistor (k)

200 300

-40 -20

80 100 120 140 160

Temperature (°C)

图8-1. Frequency vs RT Resistance

图8-2. Frequency vs Temperature

(RT = 9.09 kΩ, 2.2 MHz)

115

112

109

106

103

100

1240

1220

1200

1180

1160

1140

1120

1100

V_BIAS(V)

-40 -20

80 100 120 140 160

Temperature (°C)

图8-4. V_BIASvs I_BIAS(Active Mode)

图8-3. Frequency vs Temperature

(RT = 220 kΩ, 100 kHz)

11.5

10.5

9.5

V_BIAS(V)

图8-6. V_BIASvs I_BIAS(Bypass Mode, Charge Pump Off)

图8-5. V_BIASvs I_BIAS(Bypass Mode, Charge Pump On)

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

8.6 Typical Characteristics (continued)

5.5

4.5

3.5

2.5

1.5

2.5

0.5

V_BIAS(V)

图8-7. V_BIASvs I_BIAS(Shutdown Mode)

图8-8. V_BIASvs V_VCC

5.5

4.5

3.5

2.5

1.5

0.5

100 120 140 160 180

I_VCC(mA)

图8-9. V_VCCvs I_VCC

图8-10. V_VCCvs Peak Driver Current

-40 -20

80 100 120 140 160

V_CSP(V)

Temperature (°C)

图8-12. Peak Current Limit Threshold V_CLTHvs Temperature

图8-11. Peak Current Limit Threshold vs V_CSP

(CSP = 3 V)

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

8.6 Typical Characteristics (continued)

120

119

118

117

116

115

114

113

112

111

110

4.5

3.5

2.5

1.5

0.5

-40 -20

80 100 120 140 160

V_OUT(V)

Temperature (°C)

图8-13. I_CSPvs Temperature (Active Mode)

图8-14. VOUT Sink Current vs VOUT (Deep Sleep)

1.5

1.46

1.42

1.38

1.34

1.3

1.01

1.008

1.006

1.004

1.002

0.998

0.996

0.994

0.992

0.99

1.26

1.22

1.18

1.14

1.1

-40 -20

80 100 120 140 160

-40 -20

80 100 120 140 160

Temperature (°C)

图8-16. V_REFvs Temperature

图8-15. V_OUTSink Current vs Temperature (Deep Sleep)

250 500 750 1000 1250 1500 1750 2000 2250

Frequency (kHz)

DMAX

图8-17. D_MAXvs Frequency

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

9 Detailed Description

9.1 Overview

The LM5152x-Q1 (LM5152-Q1 and LM51521-Q1) device is a wide input range synchronous boost controller that

employs peak current mode control. The device features a low shutdown I_Qand a low I_Qsleep mode, which

minimizes battery drain at no and light load condition. The device also supports an ultra-low I_Qdeep sleep mode

with bypass operation, which eliminates the need for an external bypass switch when the supply voltage is

greater than the boost output regulation target. The output voltage can be dynamically programmed using the

tracking function.

The wide input range of the device supports automotive cold-crank and load dump. The minimum input voltage

can be as low as 0.8 V when BIAS is equal to or greater than 3.8 V. The switching frequency is dynamically

programmed with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes AM band

interference and allows for a small solution size and fast transient response. Controller architecture simplifies

thermal management at harsh ambient temperature conditions when compared to converter architectures.

The device has built-in protection features such as peak current limit, which is constant over V_IN, overvoltage

protection, and thermal shutdown. External clock synchronization, programmable spread spectrum modulation,

and a lead-less package with minimal parasitic help reduce EMI and avoid cross talk. Additional features include

the following:

• Line UVLO

• FPWM

• Diode emulation

• DCR inductor current sensing

• Programmable soft start

• Boost status indicator

9.2 Functional Block Diagram

V_LOAD

VOUT/SENSE

VREF

VCC_EN

Min. Peak C/L

Comparator

C_OUT

R_LOAD

V_ZCDTH

VCC

BIAS

V_CS

SKIP

VOUT

ZCD

Comparator

C_VREF

–

10mV

R_VREFT

R_VREFB

TRK

AGND

I_SS

Q_H

DE/SKIP

–

Reference

generator

Peak

PWM

Comparator

450mV

–

V_SUPPLY

–

V_CS

Bypass

Mode

VCC

L_M

C_IN

R_S

Q_L

0.3V

Peak C/L

Comparator

V_CS

PGND

–

V_CLTH

CLK

C_ss

CSN

CSP

–

COMP

A_CS

V_CS

V_SUPPLY

BIAS

R_COMP

STATUS

VCC

Regulator

VCC

VCC _EN2

–

4-cycle

Delay

C_COMP

VCC

UVLO

V_EN

V_OVTH

–

CLK,

D_MAX

VCC_EN1

CP Enable

(Only LM5152)

R_UVLOT

VCC_OK

–

Bypass Mode

(LM5152 only)

Ready

EN/UVLO

I_UVLO-HYS

V_UVLO

SYNC /

DITHER

Selector

R_UVLOB

Clock

Generator

MODE

FPWM

Switching Mode

Selector

TSD

SKIP

SYNC/DITHER/VH/CP

R_T

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

9.3 Feature Description

备注

Read through 节 9.4 before reading the feature description of the device. It is recommended to

understand which device functional modes and what type of light load switching modes are supported

by the device.

The parameters or thresholds values mentioned in this section are reference values unless otherwise

specified. Refer to the Electrical Characteristics to find the minimum, maximum, and typical values.

9.3.1 Device Enable/Disable (EN, VH Pin)

The device shuts down when EN is less than the EN threshold (V_EN) and VH is less than the SYNC threshold

(V_SYNC). The device is enabled when EN is greater than V_ENor VH is greater than V_SYNC. The VH pin provides a

40-μs internal delay before the device shuts down.

During shutdown, a 33-kΩ internal pulldown resistor on the EN pin is connected to GND to prevent a false turn-

on when the pin is floating. Once EN goes above the EN threshold (V_EN), the 33-kΩresistor is disconnected and

the I_UVLO-HYScurrent source is enabled to provide the UVLO functionality. The I_UVLO-HYScurrent is designed to

avoid chatter around the EN threshold voltage.

V_SUPPLY

≥

VCC V_VCC-UVLO

R_UVLOT

R_UVLOS

EN/UVLO

Ready

to start

V_UVLO

I_UVLO-HYS

R_UVLOB

C_UVLO

TSD

Configuration

Enable

VCC

V_EN

33 kꢀ

≥

V_SYNC

Configuration

图9-1. EN/UVLO Circuit

9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)

The device features a high voltage 5-V VCC regulator, which is sourced from the BIAS pin. The internal VCC

regulator turns on 50 μs after the device is enabled and the 120-μs device configuration starts when VCC is

above the VCC UVLO threshold (V_VCC-UVLO). The device configuration is reset when the device shuts down or

VCC falls down below 2.2 V. The preferred way to reconfigure the device is to shut down the device. During the

configuration time, the light load switching mode is selected.

The high voltage VCC regulator allows the connection of the BIAS pin directly to supply voltages from 3.8 V to

42 V. When BIAS is less than the 5-V VCC regulation target (V_VCC-REG), the VCC output tracks the BIAS pin

voltage with a small dropout voltage, which is caused by the 1.7-Ωresistance of the VCC regulator.

The recommended VCC capacitor value is 4.7 μF. The VCC capacitor should be populated between VCC and

PGND as close to the device as possible. The recommended BIAS capacitor value is 1.0 μF. The BIAS

capacitor must be populated between BIAS and PGND close to the device.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

BIAS

VCC

1.0 …F

4.7 …F

5-V VCC

Regulator

图9-2. High Voltage VCC Regulator

The VCC regulator features a VCC current limit function that prevents device damage when the VCC pin is

shorted to ground accidentally. The minimum sourcing capability of the VCC regulator is 100 mA (I_VCC-CL) during

either the device configuration time or active mode operation. The minimum sourcing capability of the VCC

regulator is reduced to 1 mA during sleep mode or deep sleep mode, or when EN is less than V_ENand VH is

greater than V_SYNC. The VCC regulator supplies the internal drivers and other internal circuits. The external

MOSFETs must be carefully selected to make the driver current consumption less than I_VCC-CL. The driver

current consumption can be calculated in 方程式1.

I_G= 2 × Q_G@5V× f_SW

(1)

where

• Q_G@5Vis the N-channel MOSFET gate charge at 5-V gate-source voltage.

If VIN operation below 3.8 V is required, the BIAS pin must be connected to the output of the boost converter

(V_LOAD). By connecting the BIAS pin to V_LOAD, the boost converter input voltage (V_SUPPLY) can drop down to 0.8

V if BIAS is greater than 3.8 V. See 节9.3.16 for more detailed information about the minimum V_SUPPLY

9.3.3 Light Load Switching Mode Selection (MODE Pin)

The light load switching mode is selected during the device configuration. The device is configured to skip mode

when the MODE pin is floating or a resistor that is greater than 500 kΩis connected between MODE and AGND

during the device configuration. Once the device is configured to skip mode, the light load switching mode

cannot be changed until the user reconfigures the device.

If the MODE pin voltage is less than 0.4 V (V_MODE-FALLING) or grounded during the device configuration, the

device is configured to diode emulation (DE) mode. If the MODE pin voltage is greater than 2.0 V (V_MODE-RISING

)

or connected to VCC during the device configuration, the device is configured to forced PWM (FPWM) mode. If

the device is configured to DE or FPWM mode, light load switching mode can be dynamically changed between

DE and FPWM modes during operation without reconfiguration.

Closed during

configuration

MODE

FPWM or DE

SKIP

MODE

Selector

Closed during

configuration

图9-3. MODE Selection Circuit

9.3.4 Line Undervoltage Lockout (UVLO Pin)

When UVLO is greater than the UVLO threshold (V_UVLO), the device enters active mode if the device

configuration is finished. UVLO hysteresis is accomplished with an internal 25-mV voltage hysteresis (V_UVLO-HYS

)

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

at the UVLO pin, and an additional 10-μA current sink (I_UVLO-HYS) that is switched on or off. When the UVLO pin

voltage exceeds V_UVLO, the current sink is disabled to quickly raise the voltage at the UVLO pin. When the

UVLO pin voltage falls below V_UVLOor during the device configuration time, the current sink is enabled, causing

the voltage at the UVLO pin to fall quickly.

The external UVLO resistor voltage divider (R_UVLOT, R_UVLOB) must be designed so that the voltage at the UVLO

pin is greater than V_UVLOwhen V_SUPPLYis in the desired operating range. The values of R_UVLOTand R_UVLOBcan

be calculated as follows.

UVLO_RISING

−

× V

SUPPLY_OFF

SUPPLY_ON

UVLO_FALLING

(2)

(3)

UVLOT

UVLO_HYS

× R

UVLO_FALLING

UVLOT

UVLOB

− V

SUPPLY_OFF

UVLO_FALLING

A UVLO capacitor (C_UVLO) is required in case V_SUPPLYdrops below V_SUPPLY-OFFmomentarily during the start-up

or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an additional

series UVLO resistor (R_UVLOS) can be used to quickly raise the voltage at the UVLO pin when I_UVLO-HYSis

disabled.

The UVLO pin can be connected to the BIAS pin if not used. Drive the UVLO pin through a minimum of a 5-kΩ

resistor if the BIAS pin voltage is less than the UVLO pin voltage in any conditions.

9.3.5 Fast Restart Using VCC HOLD (VH Pin)

The device is prepared for a fast start or restart when VH is greater than V_SYNC. The device configuration is

completed and the VCC regulator is active. The device stops switching, but keeps the VCC regulator active

when EN is less than V_ENand VH is greater than V_SYNC(see 图9-5).

3.8 V

BIAS

V_UVLO

V_EN

UVLO/

V_VCC-UVLO

120-µs (Typ.)

configuration

time

120-µs (Typ.)

configuration

time

VCC

V_TRK

50-µs (Typ.)

internal start-up delay

x V_TRK

V_LOAD

SS =

V_LOAD(TARGET)

V_LOAD

图9-4. Boost Start-Up Waveforms Case 1: Start-Up by EN/UVLO, Restart when VH < V_SYNC

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

3.8 V

BIAS

V_UVLO

V_EN

UVLO/

V_VCC-UVLO

120-µs (Typ.)

configuration

time

VCC

V_TRK

50-µs (Typ.)

internal start-up delay

V_LOADx V_TRK

SS =

V_LOAD(TARGET)

V_LOAD

图9-5. Boost Start-Up Waveforms Case 2: Start-Up by EN/UVLO, Restart when VH > V_SYNC

9.3.6 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)

The V_OUTregulation target (V_OUT-REG) is adjustable by programming the TRK pin voltage, which is the reference

of the internal error amplifier. The accuracy of V_OUT-REGis given when the TRK voltage is between 0.25 V and

1.0 V. The high impedance TRK pin allows users to program the pin voltage directly by a D/A converter or by

connecting to a resistor voltage divider (R_VREFT, R_VREFB) between VREF and AGND.

The device provides a 1-V voltage reference (V_REF), which can be used to program the TRK pin voltage through

a resistor voltage divider. It is not recommended to use V_REFas a reference voltage of an external circuit

because the device periodically disables V_REFin sleep or deep sleep mode. For stability reasons, the VREF

capacitor (C_VREF) should be between 330 pF and 1 nF. 470 pF is recommended.

When R_VREFTand R_VREFBare used to program the TRK pin voltage, V_OUT-REGcan be calculated as follows.

20 × R

VREFB

(4)

OUT_REG

+ R

VREFT

VREFB

The TRK pin voltage can be dynamically programmed in active mode, which makes an envelope tracking power

supply design easy. When designing a tracking power supply, it is required to adjust the TRK pin voltage slow

enough so that the VOUT pin voltage can track the command and the internal overvoltage or undervoltage

comparator is not triggered during the transient operation. An RC filter must be used at the TRK pin to slow

down the slew rate of the command signal at the TRK pin, especially when a step input is applied. When a

trapezoidal or sinusoidal input is applied, the slew rate or the frequency of the command signal must be limited.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

VREF

C_VREF

R_VREF

R_VREFT

R_VREFB

TRK

R_FTRK

TRK

AGND

C_FTRK

(b)

(a)

图9-6. TRK Control (a) Using VREF (b) by External Step Input

V_OUT-REGtracks the TRK pin voltage in all operation modes (FPWM, skip or diode mode) with a maximum of a

20-ms delay during deep sleep mode to save power. Take extra care when programming TRK if V_SUPPLYis

greater than V_OUT-REGin any conditions. The device enters active mode with a 5-μs delay if V_LOADfalls below

V_OUT-REGin deep sleep mode, but the device enters active mode with maximum of a 20-ms delay if V_OUT-REGis

increased by TRK above V_LOADin deep sleep mode.

9.3.7 Overvoltage Protection (VOUT Pin)

The device provides an overvoltage protection (OVP) for boost converter output. The OVP comparator monitors

the VOUT pin through internal resistor voltage dividers. If the VOUT pin voltage rises above the overvoltage

threshold (V_OVTH), OVP is activated. When OVP is triggered, the device turns off the low-side driver and turns on

the high-side driver until zero current is detected in diode emulation or skip mode. In FPWM mode, the low-side

driver is not turned off when the OVP is triggered.

After at least 40 μs in OVP status, the device enters deep sleep mode and LM5152-Q1 turns on the high-side

driver 100% while LM51521-Q1 turns the high-side driver off. The recommended VOUT capacitor (C_VOUT) is

0.1 μF.

9.3.8 Boost Status Indicator (STATUS Pin)

The device provides a boost status indicator (STATUS) to simplify sequencing and supervision. STATUS is an

open-drain output. A pullup resistor between 5 kΩ and 100 kΩ can be externally connected to the STATUS pin.

The STATUS switch opens four cycles after the VOUT pin voltage is greater than the overvoltage voltage

(V_OVTH). The STATUS pin is pulled down to ground when the following occurs:

• VOUT pin voltage is less than V_OVTH

• UVLO is less than V_UVLO

• VCC is less than V_VCC-UVLO

• During thermal shutdown

The STATUS pin voltage cannot be greater than V_VOUT+ 0.3 V.

STATUS

4-cycle

Delay

–

V_OVTH

Bypass Mode

(LM5152 only)

图9-7. STATUS Indicator

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

9.3.9 Dynamically Programmable Switching Frequency (RT)

The switching frequency of the device is set by a single RT resistor connected between RT and AGND if no

external synchronization clock is applied to the SYNC pin. The resistor value to set the RT switching frequency

(R_T) is calculated as follows.

2 . 21 × 10

R =

− 955

(5)

RT typical

The RT pin is regulated to 0.5 V by an internal RT regulator when the device is in active mode or during the

device configuration. The switching frequency can be dynamically programmed during operation as shown in 图

9-8.

Higher F_SW

图9-8. Frequency Hopping Example

9.3.10 External Clock Synchronization (SYNC Pin)

The switching frequency of the device can be synchronized to an external clock by directly applying an external

pulse signal to the SYNC pin. The internal clock is synchronized at the rising edge of the external

synchronization pulse using an internal PLL. Connect the SYNC pin to ground if not used.

The external synchronization pulse must be greater than V_SYNCin the high logic state and must be less than

V_SYNCin the low logic state. The duty cycle of the external synchronization pulse is not limited, but the minimum

on-pulse and the minimum off-pulse widths must be greater than 100 ns. The frequency of the external

synchronization pulse must satisfy 方程式6 and 方程式7.

(6)

0.75ì f_RT(typical)Ç f_SYNCÇ 1.5ì f_RT(typical)

(7)

For example, a RT resistor is required for typical 350-kHz switching to cover 263-kHz to 525-kHz clock

synchronization without changing the RT resistor.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

R_SYNC

SYNC

SYNC rising threshold

SYNC falling threshold

SYNC

2 cycles

SYNC exit delay

7 cycles

PLL enable delay

~150us

PLL lock time

Clock

Synchronized

RT programmed

switching

RT programmed

switching

图9-9. External Clock Synchronization

Drive the SYNC pin through a minimum 1-kΩ resistor if the BIAS pin voltage is less than the SYNC pin voltage

in any conditions.

9.3.11 Programmable Spread Spectrum (DITHER Pin)

The device provides an optional programmable spread spectrum (clock dithering) function that is activated by

connecting a capacitor between DITHER and AGND. A triangular waveform centered at 1.0 V is generated

across the dither capacitor. This triangular waveform modulates the oscillator frequency by –6% to +5% of the

frequency set by the RT resistor. The dither capacitance value sets the rate of the low frequency modulation.

DITHER

C_DITHER

I_DITHER= -20uA

1.0V +7.0%

1.0V -7.0%

I_DITHER= 20uA

Dither disable threshold

T_MOD= 1 / f_MOD

DITHER

RT programmed

switching

Clock dithering

RT programmed

switching

图9-10. Switching Frequency Dithering

For the dithering circuit to effectively reduce peak EMI, the modulation frequency must be much less than the RT

switching frequency. The dither capacitance, which is required for a given modulation frequency (f_MOD), can be

calculated from 方程式8. Setting the f_MODto 9 kHz or 10 kHz is a good starting point.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

20μA

(8)

DITHER

× 0 . 29

MOD

Connecting DITHER to AGND deactivates clock dithering, and the internal oscillator operates at a fixed

frequency set by the RT resistor. Clock dithering is also disabled when an external synchronization pulse is

applied.

DITHER

No Dither

图9-11. Dynamic Dither On/Off Example

Connecting STATUS to DITHER enables the clock dithering when the STATUS pin is pulled down to ground and

also enables the internal charge pump during bypass operation when the STATUS pin is pulled up.

VDD(MCU)

R_PU

Boost Status

Indicator to MCU

STATUS

DITHER

C_DITH

图9-12. Enable Clock Dithering and Internal Charge Pump Together

9.3.12 Programmable Soft Start (SS Pin)

The soft-start feature helps the converter gradually reach the steady state operating point. To reduce start-up

stresses and surges, the device regulates the error amplifier reference to the SS pin voltage or the TRK pin

voltage (V_TRK), whichever is lower.

The internal 20-μA soft-start (I_SS) current turns on 120 μs after the VCC pin crosses V_VCC-UVLO. I_SSgradually

increases the voltage on an external soft-start capacitor (C_SS). This results in a gradual rise of the output

voltage.

In FPWM mode, the device forces diode emulation while the SS pin voltage is less than 1.5 V. When the SS pin

voltage is greater than 1.5 V, the device changes the zero current detection (ZCD) threshold gradually from 4 mV

to –145 mV to achieve a smooth transition from diode emulation to FPWM mode.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

VCC

UVLO

I_SS=20uA

VCC

1.5V

V_TRK

Transient period

120us

delay

Forced Diode

Emulation

图9-13. Soft Start and Smooth Transition to FPWM

In boost topology, the soft-start time (t_SS) varies with the input supply voltage because the boost output voltage is

equal to the boost input voltage at the beginning of the soft-start switching. t_SSin boost topology is calculated

with 方程式9.

SUPPLY

= V

× 1 −

(9)

TRK

20μA

LOAD

In general, it is recommended to choose a soft-start time long enough so that the converter can start up without

going into an overcurrent state. If the device is used for a pre-boost in automotive application, it is recommended

to use 100-pF C_SSto reach steady state as soon as possible.

The device also features an internal SS-to-FB clamp (V_SS-FB), which clamps SS 55 mV above FB and is

activated if 256 consecutive switching cycles occur with current limit. The SS-to-FB clamp is deactivated if 32

consecutive switching cycles occur without exceeding the current limit threshold. This clamp helps to minimize

surges after output shorts or over load situations. The device can enter deep sleep mode when SS is greater

than 1.5 V. It is not recommended to pulldown SS to stop switching.

9.3.13 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)

The device includes an internal feedback resistor voltage divider. The internal feedback resistor voltage divider is

connected to the negative input of the internal transconductance error amplifier, and the TRK pin voltage

programs the positive input of the internal transconductance error amplifier after the soft start is finished. The

internal transconductance error amplifier features high output resistance (R_O= 10 MΩ) and wide bandwidth (BW

= 3 MHz) and sinks (or sources) current, which is proportional to the difference between the negative and the

positive inputs of the error amplifier.

The output of the error amplifier is connected to the COMP pin, allowing the use of a Type-2 loop compensation

network. R_COMP, C_COMP, and an optional C_HFloop compensation components configure the error amplifier gain

and phase characteristics to achieve a stable loop response. This compensation network creates a pole at very

low frequency, a mid-band zero, and a high frequency pole.

The PWM comparator in 图 9-14 compares the sum of the amplified sensed inductor current and the slope

compensation ramp with the sum of the COMP pin voltage and a –0.3-V internal offset, and terminates the

present cycle if the sum of the amplified sensed inductor current and the slope compensation ramp is greater

than the sum of the COMP pin voltage and the –0.3-V internal offset.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

V_SUPPLY

R_S

CSN

CSP

V_SLOPE

VCC_EN

VREF

Gain=10

VOUT

C_VREF

R_VREFT

R_VREFB

TRK

Reference

generator

PWM

Comparator

0.3V

DC offset

AGND

Bypass

Mode

I_SS

COMP

C_ss

R_COMP

C_HF

(optional)

C_COMP

图9-14. Error Amplifier, Current Sense Amplifier, and PWM

9.3.14 Current Sensing and Slope Compensation (CSP, CSN Pin)

The device features a current sense amplifier with an effective gain of 10 (A_CS), and provides an internal slope

compensation ramp to the PWM comparator to prevent a subharmonic oscillation at high duty cycle. The device

generates the 45-mV peak slope compensation ramp (V_SLOPE) at the input of the current sense amplifier, which

is a 0.45-V peak (at 100% duty cycle) slope compensation ramp at the PWM comparator input.

According to peak current mode control theory, the slope of the slope compensation ramp must be greater than

at least half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle.

Therefore, the minimum amount of the slope compensation must satisfy 方程式10.

0.5 × (V_LOAD- V_SUPPLY) / L_M× R_S× Margin < V_SLOPE× f_SW(in Boost)

(10)

where

• 1.5-1.7 is recommended as the margin to cover non-ideal factors.

V_COMP

0.3V offset

Internal Slope

Compensation

0.45V x D

Sensed Inductor

Current (10 x Rs x I_LM

)

图9-15. PWM Comparator Input

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

9.3.15 Constant Peak Current Limit (CSP, CSN Pin)

When the CSP-CSN voltage exceeds the 60-mV cycle-by-cycle current limit threshold (V_CLTH), the current limit

comparator immediately terminates the LO output. The device provides an constant peak current limit whose

peak inductor current limit is constant over the input and output voltage. For the case where the inductor current

can overshoot, such as inductor saturation, the current limit comparator skips pulses until the current has

decayed below the current limit threshold.

V_SUPPLY

R_S

CSN

CSP

Gain=10

CS Amplifier

0.6V

Current Limit

Comparator

图9-16. Current Limit Comparator

Cycle-by-cycle peak current limit is calculated as follows:

0.06

R_S

I_PEAK-CL

(11)

Current Limit = 0.6V

Sensed Inductor

Current (10 x Rs x I_LM

)

图9-17. Current Limit Comparator Input

Boost converters have a natural pass-through path from the supply to the load through the high-side MOSFET

body diode. Due to this path, boost converters cannot provide the peak current limit protection when the output

voltage is close to or less than the input supply voltage, especially the peak current limit protection that does not

work during the minimum on time (t_ON-MIN).

9.3.16 Maximum Duty Cycle and Minimum Controllable On-Time Limits

The device provides the maximum duty cycle limit (D_MAX) and minimum off time to cover the non-ideal factors

caused by resistive elements. D_MAXdecides the minimum input supply voltage (V_SUPPLY(MIN)), which can achieve

the target output voltage (V_LOAD) during CCM operation, but V_SUPPLY(MIN), which can achieve the target output

voltage during DCM operation, is not limited by D_MAX. V_SUPPLY(MIN), which can achieve the target output voltage

during CCM operation, can be estimated as follows. See also 图8-17.

_SUPPLY(MIN)≈V_LOAD× (1 - D_MAX) + I_SUPPLY(MAX)× (R_DCR+ R_S+ R_DS(ON)

)

(12)

where

• I_SUPPLY(MAX)is the maximum input current at V_SUPPLY(MIN)

• R_DCRis the DC resistance of the inductor.

• R_DS(ON)is the turn-on resistance of the MOSFET.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

At very light-load condition or when V_SUPPLYis close to V_OUT-REG, the device skips the low-side driver pulses if

the required on time is less than t_ON-MIN. This pulse skipping appears as a random behavior. If V_SUPPLYis further

increased to the voltage higher than V_OUT-REG, the required on time becomes 0 and eventually the device can

start bypass operation (LM5152-Q1 only), which turns on the high-side driver 100% when the VOUT pin voltage

is greater than V_OVTH

9.3.17 Deep Sleep Mode and Bypass Operation (HO, CP Pin)

When SS is greater than 1.5 V, the device enters deep sleep mode after at least 40 μs in OVP status. The

device re-enters active mode if V_OUTfalls down below V_OVP. During bypass operation, the loss, which is caused

by the body diode of the high-side MOSFET, is minimized. The high-side driver of the LM51521-Q1 does not turn

on in the deep sleep mode. See 节9.4.1.5 for more information.

Boost

Output

Bypass Operation

Boost

Input

Pulse

Skipping

Pulse

Skipping

HO-SW

Pulse

Skipping

Pulse

Skipping

LO-PGND

图9-18. PWM to Bypass Transition in CCM Operation

Boost

Output

Boost

Input

Bypass Operation

Diode Emulation

Pulse

Skipping

Pulse

Skipping

HO-SW

Pulse

Skipping

Pulse

Skipping

LO-PGND

图9-19. PWM to Bypass Transition in DCM Operation

9.3.18 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)

The device provides N-channel logic MOSFET drivers, which can source a peak current of 2.2 A and sink a peak

current of 3.3 A. The LO driver is powered by VCC, and is enabled when EN is greater than V_ENand VCC is

greater than V_VCC-UVLO. The HO driver is powered by HB, and is enabled when EN is greater than V_ENand HB-

SW voltage is greater than HB UVLO threshold (V_HB-UVLO).

When the SW pin voltage is approximately 0 V by turning on the low-side MOSFET, the C_HBis charged from

VCC through the internal boot diode. The recommended value of the C_HBis 0.1 μF.

The LO and HO outputs are controlled with an adaptive dead-time methodology, which makes sure that both

outputs are not turned on at the same time. When the device commands LO to be turned on, the adaptive dead-

time logic first turns off HO and waits for HO-SW voltage to drop. LO is then turned on after a small delay (t_DHL).

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

Similarly, the HO driver turn-on is delayed until the LO-PGND voltage has discharged. HO is then turned on after

a small delay (t_DLH).

If the BIAS pin voltage is below the 5-V VCC regulation target, take extra care when selecting the MOSFETs.

The gate plateau voltage of the MOSFET switch must be less than the BIAS pin voltage to completely enhance

the MOSFET, especially during start-up at low BIAS pin voltage. If the driver output voltage is lower than the

MOSFET gate plateau voltage during start-up, the converter may not start up properly and it can stick at the

maximum duty cycle in a high-power dissipation state. This condition can be avoided by selecting a lower

threshold MOSFET or by turning on the device when the BIAS pin voltage is sufficient. Care should be taken

when the converter operates in bypass at any conditions. During the bypass operation, the minimum HO-SW

voltage is 3.75 V.

VCC

D_HB

Qpump

ZCD

Delay

Level

Shifter

Adaptive

Deadtime

VCC

PWM

Delay

PGND

图9-20. Driver Structure with Internal Boot Diode

The hiccup mode fault protection is triggered by the HB UVLO. If the HB-SW voltage is less than the HB UVLO

threshold (V_HB-UVLO), the LO turns on by force for 75 ns to replenish the boost capacitor. The device allows up to

four consecutive replenish switching. After the maximum four consecutive boot replenish switching, the device

skips switching for 12 cycles. If the device fails to replenish the boost capacitor after the four sets of the four

consecutive replenish switching, the device stops switching and enters 512 cycles of hiccup mode off time.

During the hiccup mode off time, SS is grounded.

If required, the slew rate of the switching node voltage can be adjusted by adding a gate resistor in parallel with

a pulldown PNP transistor. Extra care should be taken when adding the gate resistor because it can decrease

the effective dead time.

R_GL

Q_GL

PGND

图9-21. Slew Rate Control

9.3.19 Thermal Shutdown Protection

An internal thermal shutdown (TSD) is provided to protect the device if the junction temperature (T_J) exceeds

175°C. When TSD is activated, the device is forced into a low-power thermal shutdown state with the MOSFET

drivers and the VCC regulator disabled. After the T_Jis reduced (typical hysteresis is 15⁰C), the device restarts.

The TSD is disabled during sleep or deep sleep mode.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

9.4 Device Functional Modes

9.4.1 Device Status

9.4.1.1 Shutdown Mode

When EN is less than V_ENand VH is less than V_SYNC, the device shuts down, consuming 3 μA from BIAS. In

shutdown mode, COMP, SS, and STATUS are grounded. The device is enabled when EN is greater than V_ENor

VH is greater than V_SYNC

9.4.1.2 Configuration Mode

When the device is enabled initially, the 120-μs device configuration starts if VCC is greater than V_VCC-UVLO

During device configuration, the light load switching mode is selected. The device configuration is reset when the

device shuts down or VCC falls down below 2.2 V. The preferred way to reconfigure the device is to shut down

the device. During the configuration time, a 33-kΩ internal EN pulldown resistor is connected, the minimum

sourcing capability of the VCC regulator is 100 mA and the RT pin is regulated to 0.5 V by the internal RT

regulator.

9.4.1.3 Active Mode

After the 120-μs initial device configuration is finished, the device enters active mode with all functions enabled

if UVLO is greater than V_UVLO. In active mode, a soft-start sequence starts and the error amplifier is enabled.

9.4.1.4 Sleep Mode

When skip mode is selected as the light load switching mode and SS is greater than 1.5 V, the device enters

sleep mode if the low-side driver skips switching for 16 consecutive cycles. Once the device enters sleep mode,

the device cannot re-enter active mode during 8-μs minimum sleep time. During sleep mode, the device stops

the internal oscillator to reduce the operating current, disables UVLO comparator, disables the error amplifier,

and parks the COMP pin at 0.25 V. The device re-enters active mode if the VOUT pin voltage falls down below

the wake up threshold (V_WAKE), which is 1.1% lower than V_OUT-REG

9.4.1.5 Deep Sleep Mode

When SS is greater than 1.5 V, the device enters deep sleep mode after four cycles in OVP status. During deep

sleep mode, the device stops the internal oscillator to reduce the operating current, disables UVLO comparator,

disables the error amplifier, and parks the COMP pin at 0.25 V.

In FPWM or DE mode, the device re-enters active mode if V_OUTfalls down below V_OVTH. In skip mode, the

device re-enters active mode if VOUT falls down below V_OVTH, then immediately enters sleep mode after 16

consecutive cycles of pulse skipping.

9.4.2 Light Load Switching Mode

The device provides three light load switching modes. Inductor current waveforms in each mode are different at

the light or no load condition.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

Inductor

Current

Inductor current coducts continuously.

Negative current flow is allowed.

(a)

Inductor

Current

Random pulse skip

when the required t_ON

is less than t_ON-MIN

Random pulse skip

when the required t_ON

is less than t_ON-MIN

(b)

Inductor

Current

Minimum peak inductor

current is limited

The channel enters sleep mode after 16

consecutive pulse skipping

I_PEAK-MIN=10mV / R_S

(c)

图9-22. Inductor Current Waveform at Light Load (a) FPWM (b) Diode Emulation (c) Skip Mode

9.4.2.1 Forced PWM (FPWM) Mode

In FPWM mode, the inductor current conducts continuously at light or no load conditions, allowing a continuous

conduction mode (CCM) operation. The benefits of FPWM mode are a fast light load to heavy load transient

response and constant switching frequency at light or no load conditions. The maximum reverse current is

limited to 145 mV/R_DS(ON)in FPWM mode.

9.4.2.2 Diode Emulation (DE) Mode

In diode emulation (DE) mode, inductor current flow is allowed only in one direction – from the input source to

the output load. The device monitors the SENSE-SW voltage during the high-side switch on time and turns off

the high-side switch for the remainder of the PWM cycle when the SENSE-SW voltage falls down below the 5-

mV zero current detection (ZCD) threshold (V_ZCD). The benefit of the diode emulation is a higher efficiency than

FPWM mode efficiency at light load condition.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

SENSE + 5mV

ZCD

HO-SW

LO1

Dead-time

图9-23. Zero Current Detection

9.4.2.3 Forced Diode Emulation Operation in FPWM Mode

During soft start, the device forces diode emulation while the SS pin voltage is less than 1.5 V. When the SS pin

is greater than 1.5 V, the device reduces the zero current detection (ZCD) threshold down to –145 mV. The

peak-to-peak inductor current must satisfy 方程式13 for a proper FPWM operation at no load.

× R

DS on

< 145mV

(13)

9.4.2.4 Skip Mode

When skip mode is selected as the light load switching mode, the device enters sleep mode when the pulse skip

counter detects 16 consecutive cycles of pulse skipping in the active mode, and re-enters the active mode if

VOUT falls down below V_WAKE

The light load efficiency can be increased by entering sleep mode more frequently and staying in sleep mode

longer. In skip mode and when SS is greater than 1.5 V, the device works in the diode emulation, but the

minimum peak current is limited to 10 mV/R_Sonce the low-side driver turns on. By limiting the minimum peak

current, the boost converter is able to supply more current than what is required when switching, and enters

sleep mode more frequently and stays longer in the sleep mode.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

V_WAKE

VOUT

Active Mode

Sleep Mode

16-cycle

Pulse Skip

Counter

Pulse Skip

V_OUT-REG

VOUT

V_WAKE

COMP

0.25V

5us wake-up delay

16 consecutive

pulse skipping

Active Mode

Sleep Mode

(8 us minimum sleep time)

图9-24. Skip Mode Operation

When skip mode is selected as the light load switching mode, L_Mshould be selected for the peak inductor to

reach the 10m-V minimum peak current limit before LO turns off by D_MAXat the minimum V_SUPPLY

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

The device integrates several optional features to meet system design requirements, including input UVLO,

programmable soft start, clock synchronization, spread spectrum, and selectable light load switching mode.

Each application incorporates these features as needed for a more comprehensive design.

10.2 Typical Application

图10-1 shows all optional components to design a boost converter.

V_SUPPLY

C_BIAS

C_VOUT

V_LOAD

C_VCC

VOUT

BIAS

VCC

C_HB

R_GH

R_LOAD

C_OUT2

C_OUT1

Q_H

R_T

V_SUPPLY

C_COMP

C_SS

Q_GH

L_M

COMP

R_S

Q_L

R_COMP

R_GL

C_IN2

C_IN1

MODE

AGND

Q_GL

PGND

CSN

CSP

UVLO

R_FCS

R_PU

V_SUPPLY

STATUS

VREF

C_VREF

C_FCS

R_UVLOT

R_UVLOS

TRK

SYNC/DITHER

R_VREFT

R_VREFB

R_UVLOB

C_UVLO

C_DITHER

图10-1. Typical Synchronous Boost Converter with Optional Components

10.2.1 Design Requirements

表10-1 shows the intended input, output, and performance parameters for this application example.

表10-1. Design Example Parameters

Design Parameter

Value

2.5 V

Minimum input supply voltage (V_SUPPLY(MIN)

)

Target output voltage (V_LOAD

Maximum load current (I_LOAD

Typical switching frequency (f_SW

)

8.5 V

)

4 A (96 W)

440 kHz

)

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

10.2.2 Detailed Design Procedure

Use the LM5152-Q1 Quick Start Calculator or LM51521-Q1 Quick Start Calculator to expedite the process of

designing of a regulator for a given application.

Refer to the LM5152EVM-BST User's Guide for recommended components and typical application curves.

10.2.2.1 Application Ideas

For applications requiring the lowest cost with minimum conduction loss, inductor DC resistance (DCR) can be

used to sense the inductor current rather than using a sense resistor. R_DCRCand C_DCRCmust meet 方程式 14 to

match a time constant.

L_M

R_DCR

V_SUPPLY

C_DCRC

R_DCRC

CSN

CSP

图10-2. DCR Current Sensing

= R

× C

(14)

DCRC

DCR

Add a diode from STATUS to DITHER if the clock dithering is required in active mode and the bypass operation

is required in deep sleep mode.

VDD(MCU)

R_PU

Boost Status

Indicator to MCU

STATUS

DITHER

C_DITH

图10-3. Enable Both Clock Dithering and Bypass Operation

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

10.2.3 Application Curves

100

SKIP V_IN= 7.5 [V]

V_SUPPLY=7.5 [V]

V_SUPPLY=6.5 [V]

V_SUPPLY=5.5 [V]

SKIP V_IN= 6.5 [V]

FPWM V_IN= 7.5 [V]

FPWM V_IN= 6.5 [V]

0.5

1.5

2.5

3.5

0.001

0.002

0.005

0.01

0.02 0.03 0.050.07 0.1

I_OUT[A]

I_OUT(A)

图10-4. Efficiency vs. I_OUT, V_OUT= 8.5 V (FPWM)

图10-5. Efficiency vs. I_OUT, V_OUT= 8.5-V Light Load

8.48

8.47

8.46

8.45

8.44

8.43

V_IN= 7.5 [V]

V_IN= 6.5 [V]

V_IN= 5.5 [V]

V_IN= 4.5 [V]

0.5

1.5

2.5

3.5

I_OUT(A)

图10-6. 8.5-V Load Regulation

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

10.3 System Example

Use the LM5152-Q1 in automotive pre-boost applications. The device can turn on the high-side switch 100%

when car battery voltage is in normal range.

(Example : Regulation target 8.5V)

V_LOAD

Connect BIAS to VOUT if HO

should turn on 100% when

V_SUPPLY> VOUT_REGx 1.07

~ 10uA in deep sleep mode (High-side MOSFET off)

~ 32uA in deep sleep mode (High-side MOSFET on 100%)

High-side MOSFET can turn

on 100% when car battery

voltage is in normal range

BIAS VCC

VOUT/SENSE

MCU VDD

SYNC/DITHER/VH/QP

STATUS

Status indicator

to MCU

Car Battery

V_SUPPLY

PGND

COMP

CSN

MODE

CSP

REF/ RANGE

Enable from MCU

TRK

UVLO/EN AGND

If V_LOAD< V_OVTH-FALLINGduring cranking, the device wakes up

automatically and STATUS becomes low logic state

If V_LOAD> V_OVTH-RISINGin normal condition, the device enters deep

sleep mode automatically and STATUS becomes high logic state

图10-7. LM5152-Q1 in Automotive Pre-boost Application

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

Use the LM51521-Q1 in emergency call or backup battery booster application. The LM51521-Q1 turns off the

high-side switch when car battery voltage is in normal range.

Car Battery

V_LOAD

~ 10 uA in deep sleep mode

Connect BIAS to VOUT

(Example : Regulation target 8.5V)

BIAS VCC

SYNC

VOUT/SENSE

The body diode of high-side

MOSFET minimizes reverse

leak current when car battery

voltage is in normal range

MCU VDD

Status indicator

to MCU

STATUS

Back-up Battery /

Super-capacitor

PGND

COMP

MODE

REF

CSN

CSP

Enable from MCU

TRK

UVLO/EN AGND

If V_LOAD< V_OVTH-FALLINGbecause the car battery is

disconnected, the device wakes up automatically,

regulates VOUT and STATUS becomes low logic state

If V_LOAD> V_OVTH-RISINGin normal condition, the device enters deep

sleep mode automatically and STATUS becomes high logic state

图10-8. LM51521 in Emergency Call/Backup Battery Booster Application

To configure non-synchronous boost converter, connect SW to PGND, and connect HB to VCC.

V_LOAD

VOUT

VCC

V_SUPPLY

PGND

CSN

CSP

图10-9. Non-Synchronous Boost Configuration

11 Power Supply Recommendations

The device is designed to operate from a power supply or a battery that has a voltage range is from 0.8 V to 42

V. The input power supply must be able to supply the maximum boost supply voltage and handle the maximum

input current at 0.8 V. The impedance of the power supply and battery including cables must be low enough that

an input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required

at the supply input of the converter.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

12 Layout

12.1 Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. The following

guidelines will help users design a PCB with the best power conversion performance, thermal performance, and

minimize generation of unwanted EMI.

• Place C_VCC, C_BIAS, C_HB, and C_VOUTas close to the device. Make direct connections to the pins.

• Place Q_H, Q_L, and C_OUT. Make the switching loop (C_OUTto Q_Hto Q_Lto C_OUT) as small as possible. A small

size ceramic capacitor helps to minimize the loop length. Leave a copper area near the drain connection of

Q_Hfor a thermal dissipation.

• Place L_M, R_S, and C_IN. Make the loop (C_INto R_Sto L_Mto C_IN) as small as possible. A small size ceramic

capacitor helps to minimize the loop length.

• Connect R_Sto CSP-CSN. The CSP-CSN traces must be routed in parallel and surrounded by ground.

• Connect VOUT, HO, and SW. These traces must be routed in parallel using a short, low inductance path.

VOUT must be directly connected the drain connection of Q_H. SW must be directly connected to the source

connection of Q_H

• Connect LO and PGND. The LO-PGND traces must be routed in parallel using a short, low inductance path.

PGND must be directly connected the source connection of Q_L.

• Place R_COMP, C_COMP, C_SS, C_VREF, R_VREFT, R_VREFB, R_T, and R_UVLOBas close to the device, and connect to a

common analog ground plane.

• Connect the power ground plane (the source connection of the Q_L) to EP through PGND. Connect the

common analog ground plane to EP through AGND. PGND and AGND must be connected underneath the

device.

• Add several vias under EP to help conduct heat away from the device. Connect the vias to a large analog

ground plane on the bottom layer.

• Do not connect C_OUTand C_INgrounds underneath the device and through the large analog ground plane that

is connected to EP.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

12.2 Layout Example

Analog Ground Plane

(Connect to EP via AGND pin)

C_COMP

R_VREFB

C_VREF

C_SS

R_COMP

R_VREFT

To R_S

R_T

CSP

CSN

SYNC

Top Layer

VOUT

UVLO

C_VOUT

R_UVLOB

Bottom Layer

STATUS

MODE

Inner Layer

To MCU

To R_UVLOT

C_VCC

C_HB

V_LOAD

V_SUPPLY

C_BIAS

GND

C_OUT

Q_H

Q_L

R_S

C_IN

/}u‰}vꢀvš •]Ìꢀ• ꢁ}v[š

match with actual

L_M

CSP

GND

CSN

V_SUPPLY

图12-1. PCB Layout Example

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

LM5152-Q1, LM51521-Q1

ZHCSPX4A –FEBRUARY 2022 –REVISED APRIL 2022

www.ti.com.cn

13 Device and Documentation Support

13.1 Device Support

13.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

13.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: LM5152-Q1 LM51521-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

5-Jul-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM51521QRGRRQ1

LM5152QRGRRQ1

ACTIVE

VQFN

RGR

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 150

L51521

LM5152

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

5-Jul-2022

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM51521QRGRRQ1

LM5152QRGRRQ1

VQFN

RGR

3000

330.0

12.4

3.75

1.15

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM51521QRGRRQ1

LM5152QRGRRQ1

VQFN

RGR

3000

367.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGR 20

3.5 x 3.5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4228482/A

www.ti.com

PACKAGE OUTLINE

RGR0020C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.65

3.35

3.65

3.35

PIN 1 INDEX AREA

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

2X 2

(0.2) TYP

SYMM

EXPOSED

THERMAL PAD

(0.16)

TYP

SYMM

2X 2

2.05 0.1

0.30

16X 0.5

20X

0.18

PIN 1 ID

0.1

C A B

0.05

0.5

0.3

20X

4225699/B 05/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGR0020C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.05)

SYMM

SEE SOLDER MASK

DETAIL

20X (0.6)

20X (0.24)

16X (0.5)

(2.05)

SYMM

(3.3)

(0.775)

(R0.05) TYP

(

0.2) TYP

VIA

(0.775)

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225699/B 05/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGR0020C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.56) TYP

20X (0.6)

20X (0.24)

16X (0.5)

(0.56) TYP

(3.3)

SYMM

4X (0.92)

(R0.05) TYP

4X (0.92)

SYMM

(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 21

81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4225699/B 05/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LM51521QRGRRQ1 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E