LM5155QDSSTQ1 [TI]
符合 AEC-Q100 标准的 2.2MHz 宽输入电压、1.5A MOSFET 驱动器、非同步升压控制器 | DSS | 12 | -40 to 150;
| 型号： | LM5155QDSSTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 符合 AEC-Q100 标准的 2.2MHz 宽输入电压、1.5A MOSFET 驱动器、非同步升压控制器 | DSS | 12 | -40 to 150 驱动 控制器 驱动器 MOSFET驱动器 |
| 文件： | 总51页 (文件大小：2207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5155-Q1, LM51551-Q1
ZHCSJ61E –AUGUST 2018 –REVISED JANUARY 2021
LM5155x-Q1 2.2MHz 宽输入非同步升压、SEPIC、反激式控制器
– OVP 保护
– 热关断保护
1 特性
• 精确的±1% 精度反馈基准
• 可编程额外斜率补偿
• 可调软启动
• PGOOD 指示器
• 使用LM5155x 并借助WEBENCH® Power
• 符合面向汽车应用的AEC-Q100 标准
– 温度等级1：–40°C 至+125°C TA
• 提供功能安全
– 可帮助进行功能安全系统设计的文档
• 适用于汽车和便携式电池应用的宽输入工作范围
– 3.5V 至45V 工作范围
Designer 创建定制设计方案
– 当BIAS = VCC 时，为2.97V 至16V
– BIAS 电压大于等于3.5V 时最小升压电源电压为
1.5V
2 应用
• 汽车启停应用
• 高电压激光雷达电源
• 无光耦合器的多输出反激式应用
• 汽车尾灯LED 偏置电源
• 宽输入升压、SEPIC 和反激式电源模块
• 便携式扬声器应用
• 电池供电的升压、SEPIC 和反激式应用
– 高达50V 的输入瞬态保护
• 最小电池消耗
– 低关断电流(IQ ≤2.6µA)
– 低工作电流(IQ ≤480µA)
• 解决方案尺寸小、成本低
– 最大开关频率为2.2MHz
3 说明
– 具有可湿性侧面的12 引脚WSON 封装(3mm ×
2mm)
– 集成的误差放大器支持在没有光耦合器的情况下
LM5155x-Q1（LM5155-Q1 和 LM51551-Q1）是一款
采用峰值电流模式控制、具有宽输入范围的非同步升压
控制器。该器件可用于升压、SEPIC 和反激式拓扑。
进行初级侧稳压（反激）
– 启动期间下冲最小化（启停应用）
• 低功耗、高效率
如果 BIAS 引脚连接到 VCC 引脚，则 M5155x-Q1 可
由单节电池（最低电压为 2.97V）供电。如果 BIAS 引
脚电压高于3.5V，则该器件可使用低至 1.5V 的输入电
源电压。
– 100mV ±7% 低限流阈值
– 强大的1.5A 峰值标准MOSFET 驱动器
– 支持外部VCC 电源
• 避免AM 频带干扰和串扰
器件信息
封装(1)
– 可选的时钟同步
– 100kHz 至2.2MHz 的动态可编程开关频率
• 集成型保护特性
封装尺寸（标称值）
器件型号
LM5155x-Q1
WSON (12)
3.00mm × 2.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 在输入电压范围内具有恒定峰值电流限制
– 可选断续模式短路保护（参阅器件比较表）
– 可编程线路UVLO
VSUPPLY
VLOAD
BIAS
GATE
CS
VCC
UVLO/SYNC
PGND
FB
AGND
PGOOD
RT
SS COMP
典型升压应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSAY4
LM5155-Q1, LM51551-Q1
ZHCSJ61E –AUGUST 2018 –REVISED JANUARY 2021
www.ti.com.cn
Table of Contents
10 Application and Implementation................................25
10.1 Application Information........................................... 25
10.2 Typical Application.................................................. 25
10.3 System Examples................................................... 30
11 Power Supply Recommendations..............................34
12 Layout...........................................................................35
12.1 Layout Guidelines................................................... 35
12.2 Layout Examples.................................................... 36
13 Device and Documentation Support..........................38
13.1 Device Support....................................................... 38
13.2 Documentation Support.......................................... 38
13.3 接收文档更新通知................................................... 38
13.4 支持资源..................................................................38
13.5 Trademarks.............................................................38
13.6 静电放电警告.......................................................... 39
13.7 术语表..................................................................... 39
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 5
8.1 Absolute Maximum Ratings........................................ 5
8.2 ESD Ratings............................................................... 5
8.3 Recommended Operating Conditions.........................6
8.4 Thermal Information....................................................6
8.5 Electrical Characteristics.............................................6
8.6 Typical Characteristics................................................8
9 Detailed Description......................................................11
9.1 Overview................................................................... 11
9.2 Functional Block Diagram......................................... 11
9.3 Feature Description...................................................12
9.4 Device Functional Modes..........................................24
Information.................................................................... 39
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (June 2020) to Revision E (January 2021)
Page
• 更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
Changes from Revision C (January 2020) to Revision D (June 2020)
Page
• Removed "TBD" from the title of 图9-16 .........................................................................................................17
Changes from Revision B (July 2019) to Revision C (January 2020)
Page
• 向“特性”列表添加了“提供功能安全”...........................................................................................................1
Changes from Revision A (December 2018) to Revision B (July 2019)
Page
• 将“预告信息”更改为“量产数据”并添加了LM51551-Q1..............................................................................1
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5 Description (continued)
The internal VCC regulator also supports BIAS pin operation up to 45 V (50-V absolute maximum) for
automotive load dump. The switching frequency is dynamically programmable with an external resistor from 100
kHz to 2.2 MHz. Switching at 2.2 MHz minimizes AM band interference and allows for a small solution size and
fast transient response.
The device features a 1.5-A standard MOSFET driver and a low 100-mV current limit threshold. The device also
supports the use of an external VCC supply to improve efficiency. Low operating current and pulse-skipping
operation improve efficiency at light loads.
The device has built-in protection features such as cycle-by-cycle current limit, overvoltage protection, line
UVLO, and thermal shutdown. Hiccup mode overload protection is available in the LM51551-Q1 device option.
Additional features include low shutdown IQ, programmable soft start, programmable slope compensation,
precision reference, power-good indicator, and external clock synchronization.
6 Device Comparison Table
DEVICE OPTION
LM5155-Q1
HICCUP MODE PROTECTION
INTERNAL REFERENCE
Disabled
Enabled
1 V
1 V
LM51551-Q1
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7 Pin Configuration and Functions
BIAS
1
2
3
4
5
6
12
11
10
9
UVLO/SYNC
PGOOD
RT
VCC
GATE
EP
SS
PGND
CS
8
FB
AGND
7
COMP
图7-1. 12-Pin WSON With Wettable Flanks DSS Package (Top View)
表7-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
1
BIAS
P
P
Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.
Output of the internal VCC regulator and supply voltage input of the MOSFET driver. Connect a
ceramic bypass capacitor from this pin to PGND.
2
3
4
5
VCC
GATE
PGND
CS
N-channel MOSFET gate drive output. Connect directly to the gate of the N-channel MOSFET
through a short, low inductance path.
O
G
I
Power ground pin. Connect directly to the ground connection of the sense resistor through a low
inductance wide and short path.
Current sense input pin. Connect to the positive side of the current sense resistor through a short
path.
Output of the internal transconductance error amplifier. Connect the loop compensation components
between this pin and PGND.
6
7
8
COMP
AGND
FB
O
G
I
Analog ground pin. Connect to the analog ground plane through a wide and short path.
Inverting input of the error amplifier. Connect a voltage divider from the output to this pin to set output
voltage in boost/SEPIC topologies. Connect the low-side feedback resistor to AGND.
Soft-start time programming pin. An external capacitor and an internal current source set the ramp
rate of the internal error amplifier reference during soft start. Connect the ground connection of the
capacitor to AGND.
9
SS
RT
I
Switching frequency setting pin. The switching frequency is programmed by a single resistor
between RT and AGND.
10
11
I
Power-good indicator. An open-drain output which goes low if FB is below the under voltage
threshold. Connect a pullup resistor to the system voltage rail.
PGOOD
O
Undervoltage lockout programming pin. The converter start-up and shutdown levels can be
programmed by connecting this pin to the supply voltage through a resistor divider. The internal clock
can be synchronized to an external clock by applying a negative pulse signal into the UVLO/EN/
SYNC pin. This pin must not be left floating. Connect to BIAS pin if not used. Connect the low-side
UVLO resistor to AGND.
UVLO/EN/
SYNC
12
I
Exposed pad of the package. The exposed pad must be connected to AGND and the large ground
copper plane to decrease thermal resistance.
EP
—
—
(1) G = Ground, I = Input, O = Output, P = Power
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8 Specifications
8.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1
MAX
50
UNIT
BIAS to AGND
UVLO to AGND
SS to AGND(2)
RT to AGND(2)
VBIAS+0.3
3.8
3.8
Input
FB to AGND
3.8
V
CS to AGND(DC)
0.3
CS to AGND(100ns transient)
CS to AGND(20ns transient)
PGND to AGND
–2
0.3
–0.3
–0.3
–1
VCC to AGND
18(3)
GATE to AGND (100ns transient)
GATE to AGND (50ns transient)
PGOOD to AGND(4)
Output
V
–2
18
–0.3
–0.3
–40
–55
COMP to AGND(5)
(6)
Junction temperature, TJ
Storage temperature, Tstg
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) This pin is not specified to have an external voltage applied.
(3) 18 V or VBIAS + 0.3 V whichever is lower
(4) The maximum current sink is limited to 1 mA when VPGOOD>VBIAS
.
(5) This pin has an internal max voltage clamp which can handle up to 1.6 mA.
(6) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
8.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
Electrostatic
discharge
V(ESD)
V
All pins
±500
±750
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
Corner pins (1, 6, 7, and 12)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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8.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise specified)(1)
MIN
2.97
2.97
0
NOM
MAX
UNIT
V
VBIAS
VVCC
VUVLO
VFB
Bias input(2)
45
16
VCC voltage(3)
V
UVLO input
45
V
FB input
0
3.7
V
fSW
Typical switching frequency
Synchronization pulse frequency
Operating junction temperature(4)
100
100
–40
2200
2200
150
kHz
kHz
°C
fSYNC
TJ
(1) Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical
Characteristics.
(2) BIAS pin operating range is from 2.97 V to 16 V when VCC is directly connected to BIAS. BIAS pin operating range is from 3.5 V to 45
V when VCC is supplied from the internal VCC regulator.
(3) This pin voltage should be less than VBIAS + 0.3 V.
(4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
8.4 Thermal Information
LM5155x-Q1
THERMAL METRIC (1)
DSS(WSON)
12 PINS
37.0
UNIT
RθJA
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance (LM5155EVM-BST)
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
60.3
Junction-to-case (top) thermal resistance
60.1
Junction-to-board thermal resistance
28.8
Junction-to-top characterization parameter (LM5155EVM-BST)
Junction-to-top characterization parameter
1.2
2.0
ψJT
Junction-to-board characterization parameter (LM5155EVM-BST)
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18.7
ψJB
28.7
ψJB
RθJC(bot)
7.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = -40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISHUTDOWN(BIAS)
BIAS shutdown current
VBIAS = 12 V, VUVLO = 0 V
2.6
5
uA
uA
VBIAS = 12 V, VUVLO = 2 V, VFB = VREF
RT = 220 kΩ
,
IOPERATING(BIAS)
BIAS operating current
480
540
VCC REGULATOR
VVCC-REG
VCC regulation
VCC regulation
VBIAS = 8 V, No load
VBIAS = 8 V, IVCC = 35 mA
VCC rising
6.5
6.5
6.85
7
V
V
VVCC-UVLO(RISING) VCC UVLO threshold
VCC UVLO hysteresis
2.75
2.85
0.063
105
2.95
V
VCC falling
V
IVCC-CL
VCC sourcing current limit
VBIAS = 10 V, VVCC = 0 V
35
mA
ENABLE
VEN(RISING)
Enable threshold
EN rising
0.4
0.52
0.7
V
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = -40°C to 125°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
0.49
0.03
MAX
UNIT
V
VEN(FALLING)
VEN(HYS)
Enable threshold
Enable hysteresis
EN falling
EN falling
0.33
0.63
V
UVLO/SYNC
VUVLO(RISING)
VUVLO(FALLING)
UVLO / SYNC threshold
UVLO / SYNC threshold
UVLO rising
UVLO falling
1.425
1.370
1.5
1.575
1.520
V
V
1.45
UVLO / SYNC threshold
hysteresis
VUVLO(HYS)
UVLO falling
VUVLO = 1.6 V
0.05
5
V
IUVLO
SS
UVLO hysteresis current
4
9
6
uA
ISS
Soft-start current
10
55
11
uA
SS pull-down switch RDSON
Ω
PULSE WIDTH MODULATION
fsw1
Switching frequency
85
100
2200
50
115
kHz
kHz
ns
RT = 220 kΩ
RT = 9.09 kΩ
RT = 9.09 kΩ
RT = 9.09 kΩ
RT = 220 kΩ
fsw2
Switching frequency
Minimum on-time
1980
2420
tON(MIN)
DMAX1
Maximum duty cycle limit
Maximum duty cycle limit
80%
90%
85%
93%
90%
96%
DMAX2
CURRENT SENSE
ISLOPE
Peak slope compensation current
22.5
93
30
37.5
107
uA
RT = 220 kΩ
Current Limit threshold (CS-
PGND)
VCLTH
100
mV
HICCUP MODE PROTECTION (LM51551)
Hiccup enable cycles
64
8
Cycles
Cycles
Hiccup timer reset cycles
ERROR AMPLIFIER
VREF
Gm
FB reference
LM5155, LM51551
0.99
1
2
1.01
V
mA/V
uA
V
Transconductance
COMP sourcing current
COMP clamp voltage
COMP clamp voltage
VCOMP = 1.2 V
180
2.5
COMP rising (VUVLO = 2.0V)
COMP falling
2.8
1
1.1
V
OVP
VOVTH
Over-voltage threshold
Over-voltage threshold
FB rising (referece to VREF
)
107%
87%
110%
105%
113%
FB falling (referece to VREF
)
PGOOD
PGOOD pull-down switch RDSON 1 mA sinking
90
90%
95%
Ω
VUVTH
Undervoltage threshold
Undervoltage threshold
FB falling (referece to VREF
)
93%
FB rising (referece to VREF
)
MOSFET DRIVER
High-state voltage drop
Low-state voltage drop
100 mA sinking
100 mA sourcing
0.25
0.15
V
V
THERMAL SHUTDOWN
TTSD Thermal shutdown threshold
Thermal shutdown hysteresis
Temperature rising
175
15
°C
°C
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8.6 Typical Characteristics
110
108
106
104
102
100
98
2400
2400
2200
2000
1800
1600
1400
1200
1000
800
RT=220kW
RT=9.09kW
2360
2320
2280
2240
2200
2160
2120
2080
2040
2000
RT=220kOhm
96
RT=9.09kOhm
94
600
400
92
200
90
-40 -20
0
20
40
60
80 100 120 140 160
0
Temperature (èC)
D002
910
20
30 40 50 6070
RT Resistor (kW)
100
200250
D001
图8-2. Frequency vs Temperature
图8-1. Frequency vs RT Resistance
7
6
5
4
3
2
1
0
12
10
8
BIAS
VCC
6
4
2
0
0
20
40
60
IVCC (mA)
80
100
120
0
2
4
6
VBIAS (V)
8
10
12
D003
D004
图8-3. VVCC vs IVCC
图8-4. VVCC vs VBIAS (No Load)
20
19
18
17
16
15
14
13
12
11
10
105
104
103
102
101
100
99
RSL=0W
RSL=1kW
98
97
96
FSW=440kHz, RS=6mW, LM=1.2mH, VLOAD=10V
95
0
10
20
30
40
50
60
Duty Cycle (%)
70
80
90 100
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
D005
D006
图8-5. Peak Current Limit vs Duty Cycle
图8-6. Current Limit Threshold vs Temperature
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1.01
1.008
1.006
1.004
1.002
1
0.56
0.55
0.54
0.53
0.52
0.51
0.5
0.49
0.48
0.47
0.46
0.45
0.44
0.43
0.998
0.996
0.994
0.992
0.99
EN Falling
EN Rising
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
Temperature (èC)
D007
D008
图8-7. FB Reference vs Temperature
图8-8. EN Threshold vs Temperature
530
520
510
500
490
480
470
4
3.5
3
2.5
2
1.5
1
0.5
0
VFB=VREF, RT=221kW, VVCC=7V, COMP=1.75V
5
10
15
20
25
VBIAS (V)
30
35
40
45
0
5
10
15
20 25
VBIAS (V)
30
35
40
45
D009
D010
图8-9. IOPERATING(BIAS)including RT current vs VBIAS
图8-10. ISHUTDOWN(BIAS) vs VBIAS
4.6
4.4
4.2
4
200
180
160
140
120
100
80
3.8
3.6
3.4
BIAS=12V
BIAS=45V
3.2
3
2.8
2.6
2.4
60
40
0
250 500 750 1000 1250 1500 1750 2000 2250 2500
Frequency (kHz)
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
D012
D011
图8-12. tON(MIN) vs Frequency
图8-11. ISHUTDOWN vs Temperature
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11
10.8
10.6
10.4
10.2
10
2
1.8
1.6
1.4
1.2
1
9.8
0.8
0.6
0.4
0.2
0
9.6
9.4
Isource (A)
Isink (A)
9.2
9
-40 -20
0
20
40
60
80 100 120 140 160
2
4
6
8
10
12
14
16
Temperature (èC)
VVCC (V)
D013
D014
图8-13. ISS vs Temperature
图8-14. Peak Driver Current vs VCC
1.56
1.54
1.52
1.5
95
94
93
92
91
90
89
88
87
86
85
UVLO rising
UVLO falling
1.48
1.46
1.44
1.42
1.4
-40 -20
0
20
40
60
80 100 120 140 160
0
250 500 750 1000 1250 1500 1750 2000 2250
Frequency (kHz)
Temperature (èC)
D015
D016
图8-15. UVLO Threshold vs Temperature
图8-16. Maximum Duty Cycle vs Frequency
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9 Detailed Description
9.1 Overview
The LM5155x-Q1 device is a wide input range, non-synchronous boost controller that uses peak-current-mode
control. The device can be used in boost, SEPIC, and flyback topologies.
The LM5155x-Q1 device can start up from a 1-cell battery with a minimum of 2.97 V if the BIAS pin is connected
to the VCC pin. It can operate with the input supply voltage as low as 1.5 V if the BIAS pin is greater than 3.5 V.
The internal VCC regulator also supports BIAS pin operation up to 45 V (50-V absolute maximum) for
automotive load dump. The switching frequency is dynamically programmable with an external resistor from 100
kHz to 2.2 MHz. Switching at 2.2 MHz minimizes AM band interference and allows for a small solution size and
fast transient response.
The device features a 1.5-A standard MOSFET driver and a low 100-mV current limit threshold. The device also
supports the use of an external VCC supply to improve efficiency. Low operating current and pulse skipping
operation improve efficiency at light loads.
The device has built-in protection features such as cycle-by-cycle current limit, overvoltage protection, line
UVLO, and thermal shutdown. Hiccup mode overload protection is available in the LM51551-Q1 device option.
Additional features include low shutdown IQ, programmable soft start, programmable slope compensation,
precision reference, power good indicator, and external clock synchronization.
9.2 Functional Block Diagram
D1
VSUPPLY
LM
VLOAD
CIN
COUT
RLOAD
RFBT
FB
PGOOD
BIAS
RFBB
VUVTH
+
œ
+
œ
IUVLO
VCC_OK
TSD
FB
VSUPPLY
œ
RUN
VUVLO
OVP
BIAS
VOVTH
RUVLOT
+
SYNC
Detector
Clock_Sync
VCC
UVLO/
SYNC
VEN
VCC
Regulator
VCC_EN
TSD
RUVLOB
+
VCC_EN
œ
Optional
Hiccup Mode
VCS1
+
CVCC
VCC
UVLO
VCC_OK
VCSTH
œ
C/L
Comparator
GATE
CS
S
R
Q
Q
ISS
OVP
Q1
SS
VREF
FB
ISLOPE
VCS2
+
+
+
œ
œ
PWM
Comparator
CSS
VCS1
GCOMP
Clock
Generator
RS
VCS2
Clock_Sync
COMP
PGND
AGND
RT
RT
RCOMP
CCOMP
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9.3 Feature Description
9.3.1 Line Undervoltage Lockout (UVLO/SYNC Pin)
The device has a dual-level UVLO circuit. During power-on, if the BIAS pin voltage is greater than 2.7 V, the
UVLO pin voltage is in between the enable threshold (VEN), and the UVLO threshold (VUVLO) for more than 1.5
µs (see 节 9.3.5 for more details), the device starts up and an internal configuration starts. The device typically
requires a 65-µs internal start-up delay before entering standby mode. In standby mode, the VCC regulator and
RT regulator are operational, SS pin is grounded, and there is no switching at the GATE output.
IUVLO
VSUPPLY
œ
VUVLO
RUN
RUVLOT
+
UVLO/
SYNC
RUVLOB
+
VCC_EN
VEN
œ
图9-1. Line UVLO and Enable
When the UVLO pin voltage is above the UVLO threshold, the device enters run mode. In run mode, a soft-start
sequence starts if the VCC voltage is greater than 4.5 V, or 50 µs after the VCC voltage exceeds the 2.85-V
VCC UV threshold (VVCC-UVLO), whichever comes first. UVLO hysteresis is accomplished with an internal 50-mV
voltage hysteresis and an additional 5-μA current source that is switched on or off. When the UVLO pin voltage
exceeds the UVLO threshold, the current source is enabled to quickly raise the voltage at the UVLO pin. When
the UVLO pin voltage falls below the UVLO threshold, the current source is disabled, causing the voltage at the
UVLO pin to fall quickly. When the UVLO pin voltage is less than the enable threshold (VEN), the device enters
shutdown mode after a 35-µs (typical) delay with all functions disabled.
65-µs (typical)
50-µs
internal start-up delay
> 3 cycles
VCC UV delay
BIAS
= VSUPPLY
2.7 V
1.5 V
0.55 V
Standby
2.85 V
4.5 V
UVLO
VCC
Shutdown
1 V
1.5 µs
SS is grounded
with 2 cycles
delay
UVLO should be greater than
0.55 V more than 1.5 µs to start-up
SS
GATE
TSS
VLOAD
SS
=
1 V
VLOAD(TARGET)
VLOAD
图9-2. Boost Start-Up Waveforms Case 1: Start-Up by 2.85-V VCC UVLO, UVLO Toggle After Start-Up
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50-µs
VCC UV delay
65-µs (typical)
internal start-up delay
65-µs (typical)
internal start-up delay
> 35 µs
BIAS
2.7 V
= VSUPPLY
1.5 V
0.52 V
UVLO
Standby
2.85 V
4.5 V
Shutdown
1 V
VCC
1.5 µs
SS is grounded
with 2 cycles
delay
UVLO should be greater than
0.55 V more than 1.5µs to start-up
SS
GATE
tSS
VLOAD
=
SS
1 V
VLOAD(TARGET)
VLOAD
图9-3. Boost Start-Up Waveforms Case 2: Start-Up When VCC > 4.5 V, EN Toggle After Start-Up
The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5 V
(typical) when the input voltage is in the desired operating range. The values of RUVLOT and RUVLOB can be
calculated as shown in 方程式1 and 方程式2.
VUVLO(FALLING)
VSUPPLY(ON)
ì
- VSUPPLY(OFF)
VUVLO(RISING)
IUVLO
RUVLOT
=
(1)
where
• VSUPPLY(ON) is the desired start-up voltage of the converter.
• VSUPPLY(OFF) is the desired turnoff voltage of the converter.
VUVLO(RISING) ìRUVLOT
RUVLOB
=
VSUPPLY(ON) - VUVLO(RISING)
(2)
A UVLO capacitor (CUVLO) is required in case the input voltage drops below the VSUPPLY(OFF) momentarily during
the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an
additional series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when the 5-
μA hysteresis current turns on.
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IUVLO
VSUPPLY
VUVLO
œ
RUVLOT
RUVLOS
RUN
+
RUVLOB
UVLO/SYNC
CUVLO
图9-4. Line UVLO using Three UVLO Resistors
Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.
9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
The device has an internal wide input VCC regulator which is sourced from the BIAS pin. The wide input VCC
regulator allows the BIAS pin to be connected directly to supply voltages from 3.5 V to 45 V.
The VCC regulator turns on when the device is in the standby or run mode. When the BIAS pin voltage is below
the VCC regulation target, the VCC output tracks the BIAS with a small dropout voltage. When the BIAS pin
voltage is greater than the VCC regulation target, the VCC regulator provides a 6.85-V supply for the N-channel
MOSFET driver.
The VCC regulator sources current into the capacitor connected to the VCC pin with a minimum of 35-mA
capability. The recommended VCC capacitor value is from 1 µF to 4.7 µF.
The device supports a wide input range from 3.5 V to 45 V in normal configuration. By connecting the BIAS pin
directly to the VCC pin, the device supports inputs from 2.97 V to 16 V. This configuration is recommended when
the device starts up from a 1-cell battery.
V
SUPPLY (2.97V ꢀ 16V)
VLOAD
BIAS
GATE
CS
VCC
UVLO/SYNC
PGND
FB
AGND
PGOOD
RT
SS COMP
图9-5. 2.97-V Start-Up (BIAS = VCC)
The minimum supply voltage after start-up can be further decreased by supplying the BIAS pin from the boost
converter output or from an external power supply as shown in 图9-6.
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VSUPPLY
VLOAD
VLOAD
BIAS
GATE
CS
VCC
UVLO > VUVLO(RISING)
UVLO/SYNC
PGND
FB
AGND
PGOOD
RT
SS COMP
图9-6. Decrease the Minimum Operating Voltage After Start-Up
In flyback topology, the internal power dissipation of the device can be decreased by supplying the VCC using an
additional transformer winding. In this configuration, the external VCC supply voltage must be greater than the
VCC regulation target (VVCC-REG), and the BIAS pin voltage must be greater the VCC voltage because the VCC
regulator includes a diode between VCC and BIAS.
VSUPPLY
BIAS
GATE
CS
VCC
UVLO/SYNC
PGND
FB
AGND
PGOOD
RT
SS COMP
图9-7. External VCC Supply (BIAS ≥VCC)
If the voltage of the external VCC bias supply is greater than the BIAS pin voltage, use an external blocking
diode from the input power supply to the BIAS pin to prevent the external bias supply from passing current to the
boost input supply through VCC.
9.3.3 Soft Start (SS Pin)
The soft-start feature helps the converter gradually reach the steady state operating point, thus reducing start-up
stresses and surges. The device regulates the FB pin to the SS pin voltage or the internal reference, whichever
is lower.
At start-up, the internal 10-μA soft-start current source (ISS) turns on 50 µs after the VCC voltage exceeds the
2.85-VCC UV threshold, or if the VCC voltage is greater than 4.5 V, whichever comes first. The soft-start current
gradually increases the voltage on an external soft-start capacitor connected to the SS pin. This results in a
gradual rise of the output voltage. The SS pin is pulled down to ground by an internal switch when the VCC is
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less than VCC UVLO threshold, the UVLO is less than the UVLO threshold, during hiccup mode off-time or
thermal shutdown.
In boost topology, soft-start time (tSS) varies with the input supply voltage. The soft-start time in boost topology is
calculated as shown in 方程式3.
≈
’
÷
◊
CSS
VSUPPLY
tSS
=
ì 1-
∆
ISS
VLOAD
«
(3)
In SEPIC topology, the soft-start time (tSS) is calculated as follows.
CSS
tSS
=
ISS
(4)
TI recommends choosing a soft-start time long enough so that the converter can start up without going into an
overcurrent state. See 节9.3.10 for more detailed information.
图9-8 shows an implementation of primary side soft start in flyback topology.
COMP
FB SS
图9-8. Primary-Side Soft-Start in Flyback
图9-9 shows an implementation of secondary side soft start in flyback topology.
VLOAD
Secondary Side
Soft-start
图9-9. Secondary-Side Soft Start in Flyback
9.3.4 Switching Frequency (RT Pin)
The switching frequency of the device can be set by a single RT resistor connected between the RT and the
AGND pins. The resistor value to set the RT switching frequency (fRT) is calculated as shown in 方程式5.
2.21ì1010
fRT(TYPICAL)
RT =
- 955
(5)
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The RT pin is regulated to 0.5 V by the internal RT regulator when the device is enabled.
9.3.5 Clock Synchronization (UVLO/SYNC Pin)
The switching frequency of the device can be synchronized to an external clock by pulling down the UVLO/
SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input
during the forced off-time which is determined by the maximum duty cycle limit. The external synchronization
clock must pull down the UVLO/SYNC pin voltage below 1.45 V (typical). The duty cycle of the pulldown pulse is
not limited, but the minimum pulldown pulse width must be greater than 150 ns, and the minimum pullup pulse
width must be greater than 250 ns. 图 9-10 shows an implementation of the remote shutdown function. The
UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In this configuration,
the device stops switching immediately after the UVLO pin is grounded, and the device shuts down 35 µs
(typical) after the UVLO pin is grounded.
VSUPPLY
MCU
UVLO/SYNC
SHUTDOWN
图9-10. UVLO and Shutdown
图9-11 shows an implementation of shutdown and clock synchronization functions together. In this configuration,
the device stops switching immediately when the UVLO pin is grounded, and the device shuts down if the fSYNC
stays in high logic state for longer than 35 µs (typical) (UVLO is in low logic state for more than 35 µs (typical)).
The device runs at fSYNC if clock pulses are provided after the device is enabled.
VSUPPLY
MCU
UVLO/SYNC
FSYNC
图9-11. UVLO, Shutdown, and Clock Synchronization
图 9-13 and 图 9-14 show implementations of standby and clock synchronization functions together. In this
configuration, the device stops switching immediately if fSYNC stays in high logic state and enters standby mode
if fSYNC stays in high logic state for longer than two switching cycles. The device runs at the fSYNC if clock pulses
are provided. Because the device can be enabled when the UVLO pin voltage is greater than the enable
threshold for more than 1.5 µs, the configurations in 图 9-13 and 图 9-14 are recommended if the external clock
synchronization pulses are provided from the start before the device is enabled. This 1.5-µs requirement can be
relaxed when the duty cycle of the synchronization pulse is greater than 50%. 图 9-12 shows the required
minimum duty cycle to start up by synchronization pulses. When the switching frequency is greater than 1.1
MHz, the UVLO pin voltage should be greater than the enable threshold for more than 1.5 µs before applying the
external synchronization pulse.
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80
75
70
65
60
55
50
45
40
35
30
25
20
15
100 200 300 400 500 600 700 800 900 1000 1100
fSW [kHz]
SUby
图9-12. Required Duty Cycle to Start up by SYNC
VSUPPLY
MCU
UVLO/SYNC
>0.7V
FSYNC
图9-13. UVLO, Standby, and Clock Synchronization (a)
VSUPPLY
UVLO/SYNC
MCU
FSYNC
图9-14. UVLO, Standby, and Clock Synchronization (b)
If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented
together by using one push-pull output of the MCU. In this configuration, the device shuts down if fSYNC stays in
low logic state for longer than 35 µs (typical). The device is enabled if fSYNC stays in high logic state for longer
than 1.5 µs. The device runs at the fSYNC if clock pulses are provided after the device is enabled. Also, in this
configuration, it is recommended to apply the external clock pulses after the BIAS is supplied. By limiting the
current flowing into the UVLO pin below 1 mA using a current limiting resistor, the external clock pulses can be
supplied before the BIAS is supplied (see 图9-15).
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MCU
10 ꢀ
UVLO/SYNC
FSYNC
图9-15. Shutdown and Clock Synchronization
图9-16 shows an implementation of inverted enable using external circuit.
VSUPPLY
UVLO/SYNC
LMV431
图9-16. Inverted UVLO
The external clock frequency (fSYNC) must be within +25% and –30% of fRT(TYPICAL). Because the maximum
duty cycle limit and the peak current limit with slope resistor (RSL) are affected by the clock synchronization, take
extra care when using the clock synchronization function. See 节 9.3.6, 节 9.3.7, and 节 9.3.11 for more
information.
9.3.6 Current Sense and Slope Compensation (CS Pin)
The device has a low-side current sense and provides both fixed and optional programmable slope
compensation ramps, which help to prevent subharmonic oscillation at high duty cycle. Both fixed and
programmable slope compensation ramps are added to the sensed inductor current input for the PWM
operation, but only the programmable slope compensation ramp is added to the sensed inductor current input
(see 图 9-17). For an accurate peak current limit operation over the input supply voltage, TI recommends using
only the fixed slope compensation (see 图8-5).
The device can generate the programmable slope compensation ramp using an external slope resistor (RSL) and
a sawtooth current source with a slope of 30 μA × fRT. This current flows out of the CS pin.
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Current Limit
Comparator
ISLOPE
VCSTH
œ
RSL
(optional)
CS
RF
(optional)
VCS1
+
RS
VCS2
+
CF
(optional)
G
COMP =0.142
V
SLOPE + offset
œ
PWM
Comparator
COMP
RCOMP
CHF
(optional)
CCOMP
图9-17. Current Sensing and Slope Compensation
Programmable Slope
Compensation Ramp
V
V
ISLOPE × RSL × D
Fixed Slope
Compensation
Ramp
Programmable Slope
Compensation Ramp
VSLOPE × D + 0.17V
ISLOPE × RSL × D
Sensed Inductor
Current (RS × ILM
Sensed Inductor
Current (RS × ILM
)
)
图9-18. Slope Compensation Ramp (a) at PWM
图9-19. Slope Compensation Ramp (b) at Current
Comparator Input
Limit Comparator Input
Use 方程式 6 to calculate the value of the peak slope current (ISLOPE) and use 方程式 7 to calculate the value of
the peak slope voltage (VSLOPE).
fRT
ISLOPE = 30mA ì
fSYNC
(6)
fRT
VSLOPE = 40mV ì
fSYNC
(7)
where
• fSYNC = fRT if clock synchronization is not used.
According to peak current mode control theory, the slope of the compensation ramp must be greater than half of
the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the
minimum amount of slope compensation in boost topology should satisfy the following inequality:
V
+ VF - V
(
)
LM
LOAD
SUPPLY
0.5ì
ìRS ìMargin < 40mV ì fSW
(8)
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where
• VF is a forward voltage drop of D1, the external diode.
The recommended value for margin to cover non-ideal factors is 1.2. If required, RSL can be added to further
increase the slope of the compensation ramp. Typically 82% of the sensed inductor current falling slope is known
as an optimal amount of the slope compensation. The RSL value to achieve 82% of the sensed inductor current
falling slope is calculated as shown in 方程式9.
V
LOAD + VF - V
(
)
LM
SUPPLY
0.82ì
ìR = 30uA ìR + 40mV ì f
(
)
S
SL
SW
(9)
If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used,
the fSW frequency equals the fSYNC frequency. The maximum value for the RSL resistance is 2 kΩ.
9.3.7 Current Limit and Minimum On-time (CS Pin)
The device provides cycle-by-cycle peak current limit protection that turns off the MOSFET when the sum of the
inductor current and the programmable slope compensation ramp reaches the current limit threshold (VCLTH).
Peak inductor current limit (IPEAK-CL) in steady state is calculated as shown in 方程式10.
fRT
VCLTH - 30mA ìRSL
ì
ìD
fSYNC
IPEAK-CL
=
RS
(10)
The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense
resistor. The estimated duty cycle is calculated as shown in 方程式11.
VSUPPLY
D = 1-
VLOAD + VF
(11)
Boost converters have a natural pass-through path from the supply to the load through the high-side power
diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot
provide current limit protection when the output voltage is close to or less than the input supply voltage. The
minimum on-time is shown in 图8-12 and is calculated as 方程式12.
800ì10-15
tON(MIN)
ö
1
+ 4ì10-6
8ìRT
(12)
If required, a small external RC filter (RF, CF) at the CS pin can be added to overcome the large leading edge
spike of the current sense signal. Select an RF value in the range of 10 Ωto 200 Ωand a CF value in the range
of 100 pF to 2 nF. Because of the effect of this RC filter, the peak current limit is not valid when the on-time is
less than 2 × RF × CF. To fully discharge the CF during the off-time, the RC time constant should satisfy the
following inequality.
1-D
fSW
3ìRF ìCF <
(13)
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9.3.8 Feedback and Error Amplifier (FB, COMP Pin)
The feedback resistor divider is connected to an internal transconductance error amplifier which features high
output resistance (RO = 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error
amplifier sources current which is proportional to the difference between the FB pin and the SS pin voltage or the
internal reference, whichever is lower. The internal transconductance error amplifier provides symmetrical
sourcing and sinking capability during normal operation and reduces its sinking capability when the FB is greater
than OVP threshold.
To set the output regulation target, select the feedback resistor values as shown in 方程式14.
≈
∆
«
’
RFBT
RFBB
VLOAD = VREF
ì
+1
÷
◊
(14)
The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation
network. RCOMP, CCOMP, and optional CHF loop compensation components configure the error amplifier gain and
phase characteristics to achieve a stable loop response. The absolute maximum voltage rating of the FB pin is
3.8 V. If necessary, especially during automotive load dump transient, the feedback resistor divider input can be
clamped with an external zener diode.
The COMP pin features internal clamps. The maximum COMP clamp limits the maximum COMP pin voltage
below its absolute maximum rating even in shutdown. The minimum COMP clamp limits the minimum COMP pin
voltage in order to start switching as soon as possible during no load to heavy load transition. The minimum
COMP clamp is disabled when FB is connected to ground in flyback topology.
9.3.9 Power-Good Indicator (PGOOD Pin)
The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches
to a high impedance open-drain state when the FB pin voltage is greater than the feedback undervoltage
threshold (VUVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than the EN
threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The
recommended minimum pullup resistor value is 10 kΩ.
Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater
than VBIAS + 0.3 V.
9.3.10 Hiccup Mode Overload Protection (LM51551 Only)
To further protect the converter during prolonged current limit conditions, the LM51551 device option provides a
hiccup mode overload protection. The internal hiccup mode fault timer of the LM51551 counts the PWM clock
cycles when the cycle-by-cycle current limiting occurs. When the hiccup mode fault timer detects 64 cycles of
current limiting, an internal hiccup mode off timer forces the device to stop switching and pulls down SS. Then,
the device will restart after 32 768 cycles of hiccup mode off-time. The 64 cycle hiccup mode fault timer is reset if
eight consecutive switching cycles occur without exceeding the current limit threshold. The soft-start time must
be long enough not to trigger the hiccup mode protection during soft-start time because the hiccup mode fault
timer is enabled during the soft start.
4 cycles of
current limit
7 normal
switching
cycles
32768 hiccup
mode off cycles
64 cycles of
current limit
60 cycles of
current limit
32768 hiccup
mode off cycles
Inductor Current
Time
图9-20. Hiccup Mode Overload Protection
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To avoid an unexpected hiccup mode operation during a harsh load transient condition, it is recommended to
have more margin when programming the peak-current limit.
9.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
When designing boost converters, the maximum duty cycle should be reviewed at the minimum supply voltage.
The minimum input supply voltage that can achieve the target output voltage is limited by the maximum duty
cycle limit, and it can be estimated as follows.
VSUPPLY(MIN) ö V
+ V ì 1-D
F ) (
+ISUPPLY(MAX) ìRDCR +ISUPPLY(MAX) ì RDS(ON) +RS ìD
(
)
LOAD
MAX
MAX
(15)
where
• ISUPPLY(MAX) = the maximum input current.
• RDCR = the DC resistance of the inductor.
• RDS(ON) = the on-resistance of the MOSFET.
fSYNC
DMAX1 = 1- 0.1ì
fRT
(16)
DMAX2 = 1-100nsì fSW
(17)
The minimum input supply voltage can be further decreased by supplying fSYNC which is less than fRT. DMAX is
DMAX1 or DMAX2, whichever is lower.
9.3.12 MOSFET Driver (GATE Pin)
The device provides an N-channel MOSFET driver that can source or sink a peak current of 1.5 A. The peak
sourcing current is larger when supplying an external VCC that is higher than the 6.75-V VCC regulation target.
During start-up, especially when the input voltage range is below the VCC regulation target, the VCC voltage
must be sufficient to completely enhance the MOSFET. If the MOSFET drive voltage is lower than the MOSFET
gate plateau voltage during start-up, the boost converter may not start up properly and it can stick at the
maximum duty cycle in a high power dissipation state. This condition can be avoided by selecting a lower
threshold N-channel MOSFET switch and setting the VSUPPLY(ON) greater than 6 to 7 V. Since the internal VCC
regulator has a limited sourcing capability, the MOSFET gate charge should satisfy the following inequality.
QG@VCC ì fSW < 35mA
(18)
An internal 1-MΩ resistor is connected between GATE and PGND to prevent a false turnon during shutdown. In
boost topology, a switch node dV/dT must be limited during the 65-µs internal start-up delay to avoid a false
turnon, which is caused by the coupling through CDG parasitic capacitance of the MOSFET.
9.3.13 Overvoltage Protection (OVP)
The device has OVP for the output voltage. OVP is sensed at the FB pin. If the voltage at the FB pin rises above
the overvoltage threshold (VOVTH), OVP is triggered and switching stops. During OVP, the internal error amplifier
is operational, but the maximum source and sink capability is decreased to 40 µA.
9.3.14 Thermal Shutdown (TSD)
An internal thermal shutdown turns off the VCC regulator, disables switching, and pulls down the SS when the
junction temperature exceeds the thermal shutdown threshold (TTSD). After the temperature is decreased by
15°C, the VCC regulator is enabled again and the device performs a soft start.
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9.4 Device Functional Modes
9.4.1 Shutdown Mode
If the UVLO pin voltage is below the enable threshold for longer than 35 µs (typical), the device goes to the
shutdown mode with all functions disabled. In shutdown mode, the device decreases the BIAS pin current
consumption to below 2.6 μA (typical).
9.4.2 Standby Mode
If the UVLO pin voltage is greater than the enable threshold and below the UVLO threshold for longer than 1.5
µs, the device is in standby mode with the VCC regulator operational, RT regulator operational, SS pin
grounded, and no switching at the GATE output. The PGOOD is activated when the VCC voltage is greater than
the VCC UV threshold.
9.4.3 Run Mode
If the UVLO pin voltage is above the UVLO threshold and the VCC voltage is sufficient, the device enters RUN
mode. In this mode, soft start starts 50 µs after the VCC voltage exceeds the 2.85 VCC UV threshold, or if the
VCC voltage is greater than 4.5 V, whichever comes first.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
See the How to Design a Boost Converter Using LM5155-Q1 application note for information on loop response
and component selections for the boost converter.
10.2 Typical Application
图10-1 shows all optional components to design a boost converter.
RSNB CSNB
VSUPPLY
LM
VLOAD
RBIAS
DG
RG
CBIAS
COUT1 COUT2
RLOAD
CVCC
D1
CIN
+
œ
RUVLOT
Q1
RFBT
BIAS
GATE
VCC
RUVLOS
CS
UVLO/SYNC
RF
RSL
RFBB
RS
RF
RUVLOB
CUVLO
CF
PGND
FB
AGND
PGOOD
MCU_VCC
RPG
RT
SS COMP
RCOMP
CCOMP
RT
CSS
CHF
图10-1. Typical Boost Converter Circuit With Optional Components
10.2.1 Design Requirements
表10-1 shows the intended input, output, and performance parameters for this application example.
表10-1. Design Example Parameters
DESIGN PARAMETER
VALUE
6 V
Minimum input supply voltage (VSUPPLY(MIN)
)
Target output voltage (VLOAD
Maximum load current (ILOAD
Typical switching frequency (fSW
)
24 V
)
2 A (≈48 Watt)
440 kHz
)
10.2.2 Detailed Design Procedure
Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application based
on the LM5155-Q1 device. Download the LM5155 Boost Controller Quick Start Calculator.
10.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5155x-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
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3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2.2.2 Recommended Components
表10-2 shows a recommended list of materials for this typical application.
表10-2. List of Materials
REFERENCE
DESIGNATOR
QTY.
SPECIFICATION
MANUFACTURER
PART NUMBER(1)
RT
1
1
1
RES, 49.9 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
RES, 47.0 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
RES, 2.0 k, 5%, 0.1 W, AEC-Q200 Grade 0, 0603
Vishay-Dale
Vishay-Dale
Vishay-Dale
CRCW060349K9FKEA
CRCW060347K0FKEA
CRCW06032K00JNEA
RFBT
RFBB
Inductor, Shielded, Composite, 6.8 µH, 18.5 A, 0.01 Ω,
LM
1
Coilcraft
XAL1010-682MEB
SMD
RS
RSL
1
1
3
RES, 0.008, 1%, 3 W, AEC-Q200 Grade 0, 2512 WIDE
RES, 0, 5%, 0.1 W, 0603
Susumu
Yageo America
TDK
KRL6432E-M-R008-F-T1
RC0603JR-070RL
COUT1
CAP, CERM, 4.7 µF, 50 V, ±10%, X7R, 1210
C3225X7R1H475K250AB
CAP, Aluminum Polymer, 100 µF, 50 V, ±20%, 0.025 Ω,
COUT2 (Bulk)
CIN1
2
6
1
Chemi-Con
MuRata
HHXB500ARA101MJA0G
GRM32ER71H106KA12L
EEHZC1H101P
AEC-Q200 Grade 2, D10xL10mm SMD
CAP, CERM, 10 µF, 50 V, ±10%, X7R, 1210
CAP, Polymer Hybrid, 100 µF, 50 V, ±20%, 28 Ω, 10x10
CIN2 (Bulk)
Panasonic
SMD
Q1
D1
1
1
1
MOSFET, N-CH, 40 V, 50 A, AEC-Q101, SON-8
Schottky, 60 V, 10 A, AEC-Q101, CFP15
Infineon
Nexperia
IPC50N04S5L5R5ATMA1
PMEG060V100EPDZ
CRCW060311K3FKEA
RCOMP
RES, 11.3 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
Vishay-Dale
CAP, CERM, 0.022 µF, 100 V, ±10%, X7R, AEC-Q200
Grade 1, 0603
CCOMP
CHF
1
1
TDK
TDK
CGA3E2X7R2A223K080AA
CGA3E2C0G1H221J080AA
CAP, CERM, 220 pF, 20 V, ±5%, C0G/NP0, AEC-Q200
Grade 1, 0603
RUVLOT
RUVLOB
RUVLOS
1
1
0
RES, 21.0 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
RES, 7.32 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
N/A
Vishay-Dale
Vishay-Dale
N/A
CRCW060321K0FKEA
CRCW06037K32FKEA
N/A
CAP, CERM, 0.22 µF, 50 V, ±10%, X7R, AEC-Q200
Grade 1, 0603
CSS
1
TDK
CGA3E3X7R1H224K080AB
DG
RG
0
1
1
1
0
0
1
N/A
RES, 0, 5%, 0.1 W, 0603
CAP, CERM, 100 pF, 50 V, ±1%, C0G/NP0, 0603
RES, 100, 1%, 0.1 W, 0603
N/A
N/A
Yageo America
Kemet
N/A
RC0603JR-070RL
C0603C101F5GACTU
RC0603FR-07100RL
N/A
CF
RF
Yageo America
N/A
RSNB
CSNB
RBIAS
N/A
N/A
N/A
RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0603
Panasonic
ERJ-3GEY0R00V
Samsung Electro-
Mechanics
CBIAS
1
CAP, CERM, 0.01 µF, 50 V, ±10%, X7R, 0603
CL10B103KB8NCNC
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表10-2. List of Materials (continued)
REFERENCE
DESIGNATOR
QTY.
SPECIFICATION
MANUFACTURER
PART NUMBER(1)
CAP, CERM, 1 µF, 16 V, ±20%, X7R, AEC-Q200 Grade
1, 0603
CVCC
RPG
1
1
MuRata
GCM188R71C105MA64D
RC0603FR-0724K9L
RES, 24.9 k, 1%, 0.1 W, 0603
Yageo America
(1) See the Third-party Products Disclaimer.
10.2.2.3 Inductor Selection (LM)
When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the
inductor current, and RHP zero frequency (fRHP).
Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope of
the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle (additional RSL
resistor is required if not). Higher fRHP (= lower inductance) allows a higher crossover frequency and is always
preferred when using a small value output capacitor.
The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average
inductor current as a good compromise between RR, FRHP, and inductor falling slope.
10.2.2.4 Output Capacitor (COUT
)
There are a few ways to select the proper value of output capacitor (COUT). The output capacitor value can be
selected based on output voltage ripple, output overshoot, or undershoot due to load transient.
The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using
multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the
diode and the MOSFET than the bulk aluminum capacitors in order to absorb the majority of the ripple current.
10.2.2.5 Input Capacitor
The input capacitors decrease the input voltage ripple. The required input capacitor value is a function of the
impedance of the source power supply. More input capacitors are required if the impedance of the source power
supply is not low enough.
10.2.2.6 MOSFET Selection
The MOSFET gate driver of the device is sourced from the VCC. The maximum gate charge is limited by the 35-
mA VCC sourcing current limit.
A leadless package is preferred for high switching-frequency designs. The MOSFET gate capacitance should be
small enough so that the gate voltage is fully discharged during the off-time.
10.2.2.7 Diode Selection
A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery
charge. Low reverse leakage current is important parameter when selecting the Schottky diode. The diode must
be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to handle
the average output current.
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10.2.2.8 Efficiency Estimation
The total loss of the boost converter (PTOTAL) can be expressed as the sum of the losses in the device (PIC),
MOSFET power losses (PQ), diode power losses (PD), inductor power losses (PL), and the loss in the sense
resistor (PRS).
PTOTAL = P +PQ +PD +P +PRS
IC
L
(19)
PIC can be separated into gate driving loss (PG) and the losses caused by quiescent current (PIQ).
= PG + P
P
IC
IQ
(20)
Each power loss is approximately calculated as follows:
PG = QG(@VCC) ì VBIAS ì fSW
(21)
(22)
P
= VBIAS ìIBIAS
IQ
IVIN and IVOUT values in each mode can be found in the supply current section of 节8.5.
PQ can be separated into switching loss (PQ(SW)) and conduction loss (PQ(COND)).
PQ = PQ(SW) + PQ(COND)
(23)
(24)
Each power loss is approximately calculated as follows:
PQ(SW) = 0.5ì(VLOAD + VF )ìISUPPLY ì(tR + tF )ì fSW
tR and tF are the rise and fall times of the low-side N-channel MOSFET device. ISUPPLY is the input supply current
of the boost converter.
PQ(COND) = DìISUPPLY2 ìRDS(ON)
(25)
RDS(ON) is the on-resistance of the MOSFET and is specified in the MOSFET data sheet. Consider the RDS(ON)
increase due to self-heating.
PD can be separated into diode conduction loss (PVF) and reverse recovery loss (PRR).
PD = PVF + PRR
(26)
Each power loss is approximately calculated as follows:
PVF = (1-D)ì VF ìISUPPLY
(27)
PRR = VLOAD ìQRR ì fSW
(28)
QRR is the reverse recovery charge of the diode and is specified in the diode data sheet. Reverse recovery
characteristics of the diode strongly affect efficiency, especially when the output voltage is high.
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PL is the sum of DCR loss (PDCR) and AC core loss (PAC). DCR is the DC resistance of inductor which is
mentioned in the inductor data sheet.
P = PDCR + PAC
L
(29)
Each power loss is approximately calculated as follows:
PDCR = ISUPPLY2 ìRDCR
(30)
a
PAC = K ì DIb ì fSW
(31)
1
VSUPPLY ìDì
fSW
DI =
LM
(32)
∆I is the peak-to-peak inductor current ripple. K, α, and βare core dependent factors which can be provided by
the inductor manufacturer.
PRS is calculated as follows:
PRS = DìISUPPLY2 ìRS
(33)
Efficiency of the power converter can be estimated as follows:
VLOAD ìILOAD
Efficiency =
PTOTAL + VLOAD ìILOAD
(34)
10.2.3 Application Curve
98
96
94
92
90
88
86
84
82
VSUPPLY=18V
80
78
76
VSUPPLY=12V
VSUPPLY=9V
VSUPPLY=6V
0
0.2 0.4 0.6 0.8
1
ILOAD [A]
1.2 1.4 1.6 1.8
2
BSTE
图10-2. Efficiency
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10.3 System Examples
VSUPPLY
VLOAD
BIAS
GATE
CS
VCC
UVLO/SYNC
PGND
FB
AGND
PGOOD
RT
SS COMP
图10-3. Typical Boost Application
VSUPPLY = 3.5V - 45V
VLOAD
-
+
Car
Battery
BIAS
GATE
CS
VCC
To MCU
From MCU
PGOOD
PGND
FB
UVLO/SYNC
AGND
RT
SS COMP
图10-4. Typical Start-Stop Application
VSUPPLY = 2.97V - 16V
= 12V / 24V
VLOAD
+
1-cell or
2-cell
Battery
BIAS
GATE
CS
VCC
-
PGOOD
From MCU
PGND
FB
UVLO/SYNC
AGND
RT
SS COMP
图10-5. Emergency-call / Boost On-Demand / Portable Speaker
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VSUPPLY
VLOAD
BIAS
GATE
CS
VCC
UVLO/SYNC
PGND
FB
AGND
PGOOD
RT
SS COMP
图10-6. Typical SEPIC Application
Inductance should be small enough
to operate in DCM at full load
VSUPPLY
= 30V-150V
VLOAD
BIAS
GATE
CS
VCC
UVLO/SYNC
From MCU
PGND
FB
AGND
PGOOD
RT
SS COMP
图10-7. LIDAR Bias Supply 1
> 150V-200V
VLOAD
Voltage
Tripler
Inductance should be big enough
to operate in CCM
VSUPPLY
BIAS
GATE
CS
VCC
UVLO/SYNC
PGND
FB
AGND
PGOOD
RT
SS COMP
图10-8. LIDAR Bias Supply 2
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VSUPPLY
VLOAD
BIAS
GATE
CS
VCC
UVLO/SYNC
To MCU
(Fault Indicator)
PGND
FB
AGND
System Power
PGOOD
RT
SS COMP
图10-9. Low-Cost LED Driver
VSUPPLY
V
LOAD = 5V/12V
BIAS
UVLO/SYNC
GATE
CS
PGND
VCC
AGND
PGOOD
RT
FB
SS
COMP
Optional Primary-Side
Soft-Start
图10-10. Secondary-Side Regulated Isolated Flyback
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VLOAD2 = +12V
VSUPPLY
VLOAD3 = -8.5V
BIAS
GATE
CS
UVLO/SYNC
PGND
VCC
AGND
To MCU
System Power
PGOOD
RT
SS
COMP
FB
VLOAD1 = 3.3V/5V +/- 2%
图10-11. Primary-Side Regulated Multiple-Output Isolated Flyback
VSUPPLY
VLOAD
BIAS
GATE
CS
UVLO/SYNC
PGND
VCC
AGND
To MCU
System Power
PGOOD
RT
SS
COMP
FB
图10-12. Typical Non-Isolated Flyback
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ILED
VSUPPLY
BIAS
GATE
CS
VCC
UVLO/SYNC
PGND
FB
AGND
PGOOD
RT
SS COMP
图10-13. LED Driver with High-Side Current Sensing
= 3.5 ꢀ 45V
VSUPPLY
BIAS
GATE
CS
VCC
UVLO/SYNC
PGND
FB
To MCU
(Fault Indicator)
AGND
System Power
PGOOD
RT
SS COMP
VLOAD
= 13V
TAIL
BRAKE
TURN
BACKUP
TPS9261x
TPS9261x
TPS9261x
TPS9261x
图10-14. Dual-Stage Automotive Rear-Lights LED Driver
11 Power Supply Recommendations
The device is designed to operate from a power supply or a battery whose voltage range is from 1.5 V to 45 V.
The input power supply must be able to supply the maximum boost supply voltage and handle the maximum
input current at 1.5 V. The impedance of the power supply and battery including cables must be low enough that
an input current transient does not cause an excessive drop. Additional input ceramic capacitors may be
required at the supply input of the converter.
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12 Layout
12.1 Layout Guidelines
The performance of switching converters heavily depends on the quality of the PCB layout. The following
guidelines will help users design a PCB with the best power conversion performance, thermal performance, and
minimize generation of unwanted EMI.
• Put the Q1, D1, and RS components on the board first.
• Use a small size ceramic capacitor for COUT
.
• Make the switching loop (COUT to D1 to Q1 to RS to COUT) as small as possible.
• Leave a copper area near the D1 diode for thermal dissipation.
• Put the device near the RS resistor.
• Put the CVCC capacitor as near the device as possible between the VCC and PGND pins.
• Use a wide and short trace to connect the PGND pin directly to the center of the sense resistor.
• Connect the CS pin to the center of the sense resistor. If necessary, use vias.
• Connect a filter capacitor between CS pin and power ground trace.
• Connect the COMP pin to the compensation components (RCOMP and CCOMP).
• Connect the CCOMP capacitor to the power ground trace.
• Connect the AGND pin directly to the analog ground plane. Connect the AGND pin to the RUVLOB, RT, CSS
and RFBB components.
,
• Connect the exposed pad to the AGND and PGND pins under the device.
• Connect the GATE pin to the gate of the Q1 FET. If necessary, use vias.
• Make the switching signal loop (GATE to Q1 to RS to PGND to GATE) as small as possible.
• Add several vias under the exposed pad to help conduct heat away from the device. Connect the vias to a
large ground plane on the bottom layer.
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12.2 Layout Examples
VSUPPLY
GND
LM
CVIN
Connect
to VSUPPLY
Do not connect input and
output capacitor grounds
underneath the device
CVIN
Connect
to VSUPPLY
RUVLOB
BIAS
1
2
3
4
5
6
12
11 PGOOD
UVLO
EP
VCC
RS
GATE
10
9
RT
SS
CVCC
RT
Q1
CSS
PGND
CS
CF
8
FB
RFBB
RF
7
AGND
COMP
CCOMP
RCOMP
Connect
to VLOAD
RFBT
Do not connect input and
output capacitor grounds
underneath the device
COUT1
D1
COUT2
Thermal Dissipation
Area
VLOAD
GND
图12-1. PCB Layout Example 1
Copyright © 2021 Texas Instruments Incorporated
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LM5155-Q1, LM51551-Q1
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www.ti.com.cn
LM
VSUPPLY
CVIN
GND
Q1
VLOAD
Connect
to VSUPPLY
Do not connect input and
output capacitor grounds
underneath the device
D1
Connect
to VSUPPLY
RUVLOB
BIAS
1
2
3
4
5
6
12
11
10
9
UVLO
PGOOD
RT
EP
RS
VCC
GND
GATE
CVCC
RT
COUT1
SS
CSS
PGND
CS
COUT2
CF
8
FB
RFBB
Power Ground Plane
(Connect to EP via PGND pin)
AGND
7
COMP
RCOMP
Conne
ct to
VLOAD
RFBT
RF
Do not connect input and
output capacitor grounds
underneath the device
图12-2. PCB Layout Example 2
Copyright © 2021 Texas Instruments Incorporated
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37
Product Folder Links: LM5155-Q1 LM51551-Q1
LM5155-Q1, LM51551-Q1
ZHCSJ61E –AUGUST 2018 –REVISED JANUARY 2021
www.ti.com.cn
13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.1.2 Development Support
For development support see the following:
• LM5155 Boost Controller Quick Start Calculator
13.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5155x-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, LM5155EVM-BST User's Guide
• Texas Instruments, How to Design a Boost Converter Using LM5155-Q1
• Texas Instruments, LM5155EVM-FLY User's Guide
• Texas Instruments, How to Design an Isolated Flyback Converter Using LM5155-Q1
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
Copyright © 2021 Texas Instruments Incorporated
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LM5155-Q1, LM51551-Q1
ZHCSJ61E –AUGUST 2018 –REVISED JANUARY 2021
www.ti.com.cn
13.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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39
Product Folder Links: LM5155-Q1 LM51551-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM51551QDSSRQ1
LM51551QDSSTQ1
LM51551QUDSSRQ1
LM51551QUDSSTQ1
LM5155QDSSRQ1
LM5155QDSSTQ1
LM5155QUDSSRQ1
LM5155QUDSSTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSS
DSS
DSS
DSS
DSS
DSS
DSS
DSS
12
12
12
12
12
12
12
12
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 150
-40 to 125
-40 to 125
-40 to 150
-40 to 150
-40 to 125
-40 to 125
1CW
1CW
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
SN
NIPDAU
NIPDAU
SN
1551QU
1551QU
CVR
SN
CVR
NIPDAU
NIPDAU
5155QU
5155QU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5155-Q1, LM51551-Q1 :
Catalog : LM5155, LM51551
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM51551QDSSRQ1
LM51551QDSSTQ1
LM51551QUDSSRQ1
LM51551QUDSSTQ1
LM5155QDSSRQ1
LM5155QDSSTQ1
LM5155QUDSSRQ1
LM5155QUDSSTQ1
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSS
DSS
DSS
DSS
DSS
DSS
DSS
DSS
12
12
12
12
12
12
12
12
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
3.2
3.2
1.0
1.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
3000
250
2.25
2.25
2.3
3.25
3.25
3.2
1.05
1.05
1.0
3000
250
2.3
3.2
1.0
3000
250
2.25
2.25
3.25
3.25
1.05
1.05
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM51551QDSSRQ1
LM51551QDSSTQ1
LM51551QUDSSRQ1
LM51551QUDSSTQ1
LM5155QDSSRQ1
LM5155QDSSTQ1
LM5155QUDSSRQ1
LM5155QUDSSTQ1
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSS
DSS
DSS
DSS
DSS
DSS
DSS
DSS
12
12
12
12
12
12
12
12
3000
250
213.0
213.0
210.0
210.0
213.0
213.0
210.0
210.0
191.0
191.0
185.0
185.0
191.0
191.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DSS0012B
WSON - 0.8 mm max height
SCALE 4.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
0.35
0.25
PIN 1 INDEX AREA
0.3
0.2
3.1
2.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
1
0.1
(0.2) TYP
SYMM
0.05
0.00
EXPOSED
THERMAL PAD
6
7
SEE TERMINAL
DETAIL
2X
13
SYMM
2.5
2.65 0.1
1
12
10X 0.5
0.3
12X
0.2
0.1
0.05
0.35
0.25
12X
PIN 1 ID
(OPTIONAL)
C A B
C
4218908/A 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSS0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1)
12X (0.5)
SYMM
1
12
12X (0.25)
13
SYMM
(2.65)
10X (0.5)
(R0.05) TYP
(1.075)
(
0.2) VIA
TYP
7
6
(1.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.05 MIN
ALL AROUND
EXPOSDE METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218908/A 01/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSS0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
EXPOSED METAL
TYP
12X (0.5)
SYMM
1
13
12
12X (0.25)
(0.685)
SYMM
10X (0.5)
2X (1.17)
(R0.05) TYP
7
6
2X (0.95)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 13:
83% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218908/A 01/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DSS0012C
WSON - 0.8 mm max height
SCALE 4.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
0.1 MIN
3.1
2.9
(0.05)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
0.8
0.7
C
SEATING PLANE
0.08 C
1
0.1
(0.2) TYP
SYMM
EXPOSED
THERMAL PAD
0.05
0.00
6
7
2X
2.5
13
A
A SYMM
2.65 0.1
1
12
10X 0.5
0.3
0.2
12X
0.35
0.25
12X
PIN 1 ID
0.1
C A B
0.05
C
4224220/A 02/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSS0012C
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1)
12X (0.5)
SYMM
1
12
12X (0.25)
13
SYMM
(2.65)
10X (0.5)
(R0.05) TYP
(1.075)
(
0.2) VIA
TYP
7
6
(1.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.05 MIN
ALL AROUND
EXPOSDE METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224220/A 02/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSS0012C
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
EXPOSED METAL
TYP
12X (0.5)
SYMM
1
13
12
12X (0.25)
(0.685)
SYMM
10X (0.5)
2X (1.17)
(R0.05) TYP
7
6
2X (0.95)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 13:
83% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4224220/A 02/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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