LM5156HPWPR [TI]

LM5156xH 2.2-MHz Wide VIN 65-V Non-synchronous Boost/SEPIC/Flyback Controller with 150Â°C Maximum Junction Temperature;


型号：	LM5156HPWPR
厂家：	TEXAS INSTRUMENTS
描述：	LM5156xH 2.2-MHz Wide VIN 65-V Non-synchronous Boost/SEPIC/Flyback Controller with 150Â°C Maximum Junction Temperature
文件：	总49页 (文件大小：2261K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM5156H, LM51561H

www.ti.com

SNVSBV2 – SEPTEMBER 2020

LM5156xH 2.2-MHz Wide VIN 65-V Non-synchronous Boost/SEPIC/Flyback Controller

with 150°C Maximum Junction Temperature

1 Features

2 Applications

•

Functional Safety-Capable

– Documentation available to aid functional safety

system design

Suited for wide input operating range battery

applications

– 3.5-V to 60-V Operating range (65-V abs max)

– 2.97-V to 16-V when BIAS = VCC

– Minimum boost supply voltage 1.5 V when

BIAS ≥ 3.5 V

•

Multiple-output flyback without optocoupler

LED bias supply

Wide input boost, SEPIC, flyback power module

Portable speaker application

Flyback POE power supply application

Battery-powered boost, SEPIC, flyback

3 Description

The LM5156xH (LM5156H and LM51561H) device is

a wide input range, non-synchronous boost controller

that uses peak current mode control. The device can

be used in boost, SEPIC, and flyback topologies.

– Input transient protection up to 65 V

– Minimized battery drain

•

Low shutdown current ( I_Q≤ 2.6 µA )

Low operating current ( I_Q≤ 490 µA )

The device can start up from a 1-cell battery with a

minimum of 2.97 V if the BIAS pin is connected to the

VCC pin. It can operate with the input supply voltage

as low as 1.5 V if the BIAS pin is greater than 3.5 V.

•

Small solution size and low cost

– Maximum switching frequency of 2.2 MHz

– Integrated error amplifier allows primary-side

regulation without optocoupler (flyback)

EMI mitigation

– Selectable dual random spread spectrum

Higher efficiency with low-power dissipation

– 100-mV ±7% accurate current limit threshold

– Strong 1.5-A peak standard MOSFET driver

– Supports external VCC supply

Avoid AM band interference and crosstalk

– Optional clock synchronization

– Dynamically programmable switching frequency

from 100 kHz to 2.2 MHz

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

•

LM5156xH

HTSSOP (14)

5.0 mm × 4.4 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

V_SUPPLY

V_LOAD

•

BIAS

GATE

VCC

UVLO/SYNC

DITHOFF

AGND

PGND

Integrated protection features

PGOOD

– Constant peak current limiting over input

voltage

SS COMP

– Optional hiccup mode overload protection (see

the Device Comparison Table)

– Programmable line UVLO

Typical Boost Application

– OVP protection

– Thermal shutdown

•

Accurate ±1% accuracy feedback reference

Programmable extra slope compensation

Adjustable soft start

PGOOD indicator

14-Pin HTSSOP package (5.0 mm × 4.4 mm)

Create a custom design using the LM5156xH with

the WEBENCH^®power designer

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 2

6 Device Comparison Table...............................................2

7 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

8 Specifications.................................................................. 4

8.1 Absolute Maximum Ratings ....................................... 4

8.2 ESD Ratings .............................................................. 4

8.3 Recommended Operating Conditions ........................5

8.4 Thermal Information ...................................................5

8.5 Electrical Characteristics ............................................5

8.6 Typical Characteristics................................................8

9 Detailed Description......................................................11

9.1 Overview................................................................... 11

9.2 Functional Block Diagram......................................... 11

9.3 Feature Description...................................................12

9.4 Device Functional Modes..........................................24

10 Application and Implementation................................25

10.1 Power-On Hours (POH)..........................................25

10.2 Application Information........................................... 25

10.3 Typical Application.................................................. 25

10.4 System Examples................................................... 30

11 Power Supply Recommendations..............................35

12 Layout...........................................................................36

12.1 Layout Guidelines................................................... 36

12.2 Layout Examples.................................................... 37

13 Device and Documentation Support..........................39

13.1 Device Support....................................................... 39

13.2 Receiving Notification of Documentation Updates..39

13.3 Support Resources................................................. 39

13.4 Trademarks.............................................................39

13.5 Electrostatic Discharge Caution..............................40

13.6 Glossary..................................................................40

14 Mechanical, Packaging, and Orderable

Information.................................................................... 41

4 Revision History

DATE

REVISION

NOTES

September 2020

Initial release.

5 Description (continued)

The internal VCC regulator also supports BIAS pin operation up to 60 V (65-V absolute maximum). The

switching frequency is dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching

at 2.2 MHz minimizes AM band interference and allows for a small solution size and fast transient response. To

reduce the EMI of the power supply, the device provides a selectable dual random spread spectrum which

reduces the EMI over the wide frequency range.

The device features a 1.5-A standard MOSFET driver and a low 100-mV current limit threshold. The device also

supports the use of an external VCC supply to improve efficiency. Low operating current and pulse-skipping

operation improve efficiency at light loads.

The device has built-in protection features such as cycle-by-cycle current limit, overvoltage protection, line

UVLO, and thermal shutdown. Hiccup mode overload protection is available in the LM51561H device option.

Additional features include low shutdown I_Q, programmable soft start, programmable slope compensation,

precision reference, power-good indicator, and external clock synchronization.

6 Device Comparison Table

DEVICE OPTION

LM5156H

HICCUP MODE PROTECTION

Disabled

Enabled

LM51561H

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7 Pin Configuration and Functions

EN/UVLO/SYNC

BIAS

PGOOD

VCC

GATE

PGND

AGND

DITHOFF

COMP

Figure 7-1. 14-Pin HTSSOP PWP Package (Transparent Top View)

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

BIAS

Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.

No electrical contact

Output of the internal VCC regulator and supply voltage input of the MOSFET driver. Connect a

ceramic bypass capacitor from this pin to PGND.

VCC

N-channel MOSFET gate drive output. Connect directly to the gate of the N-channel MOSFET

through a short, low inductance path.

GATE

Power ground pin. Connect directly to the ground connection of the sense resistor through a low

inductance wide and short path.

PGND

AGND

Analog ground pin. Connect directly to the analog ground plane through a wide and short path.

Current sense input pin. Connect to the positive side of the current sense resistor through a short

path.

Output of the internal transconductance error amplifier. Connect the loop compensation components

between this pin and ground plane.

COMP

Spread spectrum selection pin. Internal spread spectrum (Clock dithering) is disabled when the pin is

connected to the VCC pin. Connecting the pin to AGND enables the internal spread spectrum.

DITHOFF

Inverting input of the error amplifier. Connect a voltage divider from the output to this pin to set output

voltage in boost/SEPIC/non-isolated flyback topologies. Connect the low-side feedback resistor to

AGND.

Soft-start time programming pin. An external capacitor and an internal current source set the ramp

rate of the internal error amplifier reference during soft start. Connect the ground connection of the

capacitor to AGND.

Switching frequency setting pin. The switching frequency is programmed by a single resistor

between RT and AGND.

Power-good indicator. An open-drain output which goes low if FB is below the undervoltage

threshold. Connect a pullup resistor to the system voltage rail. If not used, leave the pin floating.

PGOOD

Undervoltage lockout programming pin. The converter start-up and shutdown levels can be

programmed by connecting this pin to the supply voltage through a resistor divider. The internal clock

can be synchronized to an external clock by applying a negative pulse signal into the EN/UVLO/

SYNC pin. This pin must not be left floating. Connect to BIAS pin if not used. Connect the low-side

UVLO resistor to AGND.

EN/UVLO/

SYNC

—

Exposed pad of the package. The exposed pad must be connected to AGND and the large ground

copper plane to decrease thermal resistance.

—

(1) G = Ground, I = Input, O = Output, P = Power

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8 Specifications

8.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range⁽¹⁾

MIN

–0.3

–1

MAX

UNIT

BIAS to AGND

UVLO to AGND

SS to AGND⁽²⁾

RT to AGND⁽²⁾

V_BIAS+0.3

3.8

Input

FB to AGND

4.0

CS to AGND(DC)

0.3

CS to AGND(50ns transient)

PGND to AGND

-0.3

–0.3

–1

0.3

DITHOFF to AGND

VCC to AGND

18⁽³⁾

GATE to AGND (50ns transient)

PGOOD to AGND⁽⁴⁾

Output

–0.3

–40

–55

COMP to AGND⁽⁵⁾

(6)

Junction temperature, T_J

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) This pin is not specified to have an external voltage applied.

(3) 18 V or V_BIAS+ 0.3 V whichever is lower

(4) The maximum current sink is limited to 1 mA when V_PGOOD>V_BIAS

(5) This pin has an internal max voltage clamp which can handle up to 1.6 mA.

(6) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Electrostatic

discharge

V_(ESD)

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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8.3 Recommended Operating Conditions

Over the recommended operating junction temperature range⁽¹⁾

MIN

2.97

NOM

MAX

UNIT

V_BIAS

V_VCC

V_DITHOFF

V_UVLO

V_FB

Bias input⁽²⁾

VCC voltage⁽³⁾

DITHOFF input

UVLO input

FB input

4.0

f_SW

Typical switching frequency

Synchronization pulse frequency

Operating junction temperature⁽⁴⁾

100

–40

2200

150

kHz

°C

f_SYNC

T_J

(1) Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical

Characteristics.

(2) BIAS pin operating range is from 2.97 V to 16 V when VCC is directly connected to BIAS. BIAS pin operating range is from 3.5V to 60V

when VCC is supplied from the internal VCC regulator.

(3) This pin voltage should be less than V_BIAS+ 0.3 V.

(4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

8.4 Thermal Information

LM5156xH

THERMAL METRIC⁽¹⁾

PWP(HTSSOP)

UNIT

14 PINS

54.7

44.1

49.1

20.7

2.0

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance (LM5156HEVM-FLY)

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter (LM5156HEVM-FLY)

Junction-to-top characterization parameter

ψ_JT

2.3

ψ_JB

Junction-to-board characterization parameter (LM5156HEVM-FLY)

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

17.3

20.7

7.9

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= -40°C to 150°C. Unless

otherwise stated, V_BIAS= 12 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

I_{SHUTDOWN(BIAS)}

BIAS shutdown current

BIAS operating current

V_BIAS= 12 V, V_UVLO= 0 V

2.6

µA

V_BIAS= 12 V, V_UVLO= 2.0 V, V_FB

V_REF, R_T= 220 kΩ

I_{OPERATING(BIAS)}

490

580

VCC REGULATOR

V_VCC-REG

VCC regulation

V_BIAS= 8 V, No load

V_BIAS= 8 V, I_VCC= 35 mA

VCC rising

6.5

6.85

V_{VCC-UVLO(RISING)}VCC UVLO threshold

VCC UVLO hysteresis

2.75

2.85

0.063

110

2.95

VCC falling

I_VCC-CL

VCC sourcing current limit

V_BIAS= 10 V, V_VCC= 0 V

ENABLE

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Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= -40°C to 150°C. Unless

otherwise stated, V_BIAS= 12 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

0.52

0.49

0.03

MAX

UNIT

V_EN(RISING)

Enable threshold

Enable hysteresis

EN rising

EN falling

0.4

0.7

V_EN(FALLING)

V_EN(HYS)

0.33

0.63

UVLO/SYNC

V_UVLO(RISING)

V_{UVLO(FALLING)}

UVLO / SYNC threshold

UVLO rising

UVLO falling

1.425

1.370

1.5

1.575

1.520

1.45

UVLO / SYNC threshold

hysteresis

V_UVLO(HYS)

I_UVLO

UVLO falling

0.05

UVLO hysteresis current

V_UVLO= 1.6 V

µA

SPREAD SPECTRUM

V_{DITHOFF(RISING)}

Clock dithering threshold

DITHOFF rising, V_BIAS= 4 V

DITHOFF falling, V_BIAS= 4 V

1.1

0.6

1.7

1.2

2.1

1.8

V_{DITHOFF(FALLING)}Clock dithering threshold

Clock dithering threshold

V_DITHOFF(HYS)

hysteresis

DITHOFF falling, V_BIAS= 4 V

0.5

I_SS

Soft-start current

µA

SS pull-down switch r_DS(on)

PULSE WIDTH MODULATION

fsw1

Switching frequency

R_T= 220 kΩ, V_BIAS= 4 V

R_T= 9.09 kΩ, V_BIAS= 4 V

R_T= 9.09 kΩ

100

2200

115

kHz

fsw2

Switching frequency

Minimum on-time

1980

2420

t_ON(MIN)

D_MAX1

Maximum duty cycle limit

R_T= 9.09 kΩ, V_BIAS= 4 V

R_T= 220 kΩ, V_BIAS= 4 V

D_MAX2

CURRENT SENSE

I_SLOPE

Peak slope compensation current R_T= 220 kΩ

22.5

37.5

107

µA

Current Limit threshold (CS-

PGND)

V_CLTH

100

HICCUP MODE PROTECTION (LM51561)

Hiccup enable cycles

Cycles

Hiccup timer reset cycles

ERROR AMPLIFIER

V_REF

FB reference

0.99

1.01

mA/V

µA

Transconductance

COMP sourcing current

COMP clamp voltage

V_COMP= 1.2V

180

2.5

COMP rising (V_UVLO= 2.0 V)

COMP falling

2.8

1.15

113

OVP

V_OVTH

Over-voltage threshold

FB rising (in reference to V_REF

)

107

110

105

FB falling (in reference to V_REF

)

PGOOD

PGOOD pull-down switch r_DS(on)1 mA sinking

V_UVTH

Under-voltage threshold

FB falling (in reference to V_REF

)

FB rising (in reference to V_REF

)

MOSFET DRIVER

High-state voltage drop

Low-state voltage drop

100 mA sinking

100 mA sourcing

0.25

0.15

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Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= -40°C to 150°C. Unless

otherwise stated, V_BIAS= 12 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

THERMAL SHUTDOWN

T_TSD

Thermal shutdown threshold

Thermal shutdown hysteresis

Temperature rising

175

°C

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8.6 Typical Characteristics

110

108

106

104

102

100

2400

2360

2320

2280

2240

2200

2160

2120

2080

2040

2000

2400

2200

2000

1800

1600

1400

1200

1000

800

RT=220kW

RT=9.09kW

RT=220kOhm

RT=9.09kOhm

600

400

200

-40 -20

80 100 120 140 160

Temperature (èC)

D002

910

30 40 50 6070

RT Resistor (kW)

100

200250

D001

Figure 8-2. Frequency vs Temperature

Figure 8-1. Frequency vs RT Resistance

BIAS

VCC

I_VCC(mA)

100

120

V_BIAS(V)

D003

D004

Figure 8-3. V_VCCvs I_VCC

Figure 8-4. V_VCCvs V_BIAS(No Load)

105

104

103

102

101

100

R_SL=0W

R_SL=1kW

F_SW=440kHz, R_S=6mW, L_M=1.2mH, V_LOAD=10V

Duty Cycle (%)

90 100

-40 -20

80 100 120 140 160

Temperature (èC)

D005

D006

Figure 8-5. Peak Current Limit vs Duty Cycle

Figure 8-6. Current Limit Threshold vs

Temperature

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1.01

1.008

1.006

1.004

1.002

0.56

0.55

0.54

0.53

0.52

0.51

0.5

0.49

0.48

0.47

0.46

0.45

0.44

0.43

0.998

0.996

0.994

0.992

0.99

EN Falling

EN Rising

-40 -20

80 100 120 140 160

-40 -20

80 100 120 140 160

Temperature (èC)

D007

D008

Figure 8-7. FB Reference vs Temperature

Figure 8-8. EN Threshold vs Temperature

530

4.5

3.5

520

510

500

490

480

470

2.5

1.5

0.5

V_FB=V_REF, RT=221kW, V_VCC=7V, COMP=1.75V

10 15 20 25 30 35 40 45 50 55 60

V_BIAS(V)

10 15 20 25 30 35 40 45 50 55 60

VBIAS (V)

D009

D010

Figure 8-9. I_{OPERATING(BIAS)}Including RT Current vs

V_BIAS

Figure 8-10. I_{SHUTDOWN(BIAS)}vs V_BIAS

4.6

4.4

4.2

200

180

160

140

120

100

3.8

3.6

3.4

BIAS=12V

BIAS=45V

3.2

2.8

2.6

2.4

250 500 750 1000 1250 1500 1750 2000 2250 2500

Frequency (kHz)

-40 -20

80 100 120 140 160

Temperature (èC)

D012

D011

Figure 8-12. t_ON(MIN)vs Frequency

Figure 8-11. I_SHUTDOWNvs Temperature

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10.8

10.6

10.4

10.2

1.8

1.6

1.4

1.2

9.8

0.8

0.6

0.4

0.2

9.6

9.4

Isource (A)

Isink (A)

9.2

-40 -20

80 100 120 140 160

Temperature (èC)

V_VCC(V)

D013

D014

Figure 8-13. I_SSvs Temperature

Figure 8-14. Peak Driver Current vs VCC

1.56

1.54

1.52

1.5

UVLO rising

UVLO falling

1.48

1.46

1.44

1.42

1.4

-40 -20

80 100 120 140 160

250 500 750 1000 1250 1500 1750 2000 2250

Frequency (kHz)

Temperature (èC)

D015

D016

Figure 8-15. UVLO Threshold vs Temperature

Figure 8-16. Maximum Duty Cycle vs Frequency

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9 Detailed Description

9.1 Overview

The LM5156xH device is a wide input range, non-synchronous boost controller that uses peak-current-mode

control. The device can be used in boost, SEPIC, and flyback topologies.

The device can start up from a 1-cell battery with a minimum of 2.97 V if the BIAS pin is connected to the VCC

pin. It can operate with the input supply voltage as low as 1.5 V if the BIAS pin is greater than 3.5 V. The internal

VCC regulator also supports BIAS pin operation up to 60 V (65-V absolute maximum). The switching frequency

is dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes

AM band interference and allows for a small solution size and fast transient response. To reduce the EMI of the

power supply, the device provides an optional dual random spread spectrum which reduces the EMI over the

wide frequency span.

The device features a 1.5-A standard MOSFET driver and a low 100-mV current limit threshold. The device also

supports the use of an external VCC supply to improve efficiency. Low operating current and pulse skipping

operation improve efficiency at light loads.

The device has built-in protection features such as cycle-by-cycle current limit, overvoltage protection, line

UVLO, and thermal shutdown. Hiccup mode overload protection is available in the LM51561H device option.

Additional features include low shutdown I_Q, programmable soft start, programmable slope compensation,

precision reference, power good indicator, and external clock synchronization.

9.2 Functional Block Diagram

V_SUPPLY

L_M

V_LOAD

C_IN

C_OUT

R_LOAD

R_FBT

PGOOD

BIAS

R_FBB

V_UVTH

I_UVLO

VCC_OK

TSD

V_SUPPLY

RUN

V_UVLO

OVP

BIAS

V_OVTH

R_UVLOT

SYNC

Detector

Clock_Sync

VCC

UVLO/

SYNC

V_EN

VCC

Regulator

VCC_EN

TSD

R_UVLOB

VCC_EN

Optional

Hiccup Mode

V_CS1

C_VCC

VCC

UVLO

VCC_OK

V_CSTH

GATE

C/L Comparator

I_SS

OVP

V_REF

I_SLOPE

V_CS2

C_SS

PWM Comparator

V_CS1

G_COMP

Clock

Generator

Clock_Sync

R_S

V_CS2

PGND

AGND

COMP

DITHOFF

R_T

R_COMP

C_COMP

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9.3 Feature Description

9.3.1 Line Undervoltage Lockout (UVLO/SYNC/EN Pin)

The device has a dual-level UVLO circuit. During power-on, if the BIAS pin voltage is greater than 2.7 V, and the

UVLO pin voltage is in between the enable threshold (V_EN) and the UVLO threshold (V_UVLO) for more than 1.5 µs

(see Section 9.3.6 for more details), the device starts up and an internal configuration starts. The device typically

requires a 65-µs internal start-up delay before entering standby mode. In standby mode, VCC regulator and RT

regulator are operational, SS pin is grounded, and no switching at the GATE output.

I_UVLO

V_SUPPLY

V_UVLO

RUN

R_UVLOT

UVLO/

SYNC

R_UVLOB

VCC_EN

V_EN

Figure 9-1. Line UVLO and Enable

When the UVLO pin voltage is above the UVLO threshold, the device enters run mode. In run mode, a soft-start

sequence starts if the VCC voltage is greater than 4.5 V, or 50 µs after the VCC voltage exceeds the 2.85-V

VCC UV threshold (V_VCC-UVLO), whichever comes first. UVLO hysteresis is accomplished with an internal 50-mV

voltage hysteresis and an additional 5-μA current source that is switched on or off. When the UVLO pin voltage

exceeds the UVLO threshold, the current source is enabled to quickly raise the voltage at the UVLO pin. When

the UVLO pin voltage falls below the UVLO threshold, the current source is disabled causing the voltage at the

UVLO pin to fall quickly. When the UVLO pin voltage is less than the enable threshold (V_EN), the device enters

shutdown mode after a 35-µs (typical) delay with all functions disabled.

65-µs (typical)

50-µs

internal start-up delay

> 3 cycles

VCC UV delay

BIAS

= V_SUPPLY

2.7 V

1.5 V

0.55 V

Standby

2.85 V

4.5 V

UVLO

VCC

Shutdown

1 V

1.5 µs

SS is grounded

with 2 cycles

delay

UVLO should be greater than

0.55 V more than 1.5 µs to start-up

GATE

T_SS

V_LOAD

1 V

V_LOAD(TARGET)

V_LOAD

Figure 9-2. Boost Start-Up Waveforms Case 1: Start-Up by 2.85-V VCC UVLO, UVLO Toggle After Start-Up

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50-µs

VCC UV delay

65-µs (typical)

internal start-up delay

65-µs (typical)

internal start-up delay

> 35 µs

BIAS

= V_SUPPLY

2.7 V

1.5 V

0.52 V

Standby

2.85 V

4.5 V

UVLO

VCC

Shutdown

1.5 µs

1 V

SS is grounded

with 2 cycles

delay

UVLO should be greater than

0.55 V more than 1.5µs to start-up

GATE

t_SS

V_LOAD

1 V

V_LOAD(TARGET)

V_LOAD

Figure 9-3. Boost Start-Up Waveforms Case2: Start-Up When VCC > 4.5 V, EN Toggle After Start-Up

The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5 V

(typical) when the input voltage is in the desired operating range. The values of R_UVLOTand R_UVLOBcan be

calculated as shown in Equation 1 and Equation 2.

V_{UVLO(FALLING)}

V_SUPPLY(ON)

- V_SUPPLY(OFF)

V_UVLO(RISING)

I_UVLO

R_UVLOT

(1)

where

•

V_SUPPLY(ON)is the desired start-up voltage of the converter.

V_SUPPLY(OFF)is the desired turnoff voltage of the converter.

V_UVLO(RISING)ìR_UVLOT

R_UVLOB

V_SUPPLY(ON)- V_UVLO(RISING)

(2)

A UVLO capacitor (C_UVLO) is required in case the input voltage drops below the V_SUPPLY(OFF)momentarily during

the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an

additional series UVLO resistor (R_UVLOS) can be used to quickly raise the voltage at the UVLO pin when the 5-

μA hysteresis current turns on.

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I_UVLO

V_SUPPLY

V_UVLO

R_UVLOT

R_UVLOS

RUN

R_UVLOB

UVLO/SYNC

C_UVLO

Figure 9-4. Line UVLO using Three UVLO Resistors

Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.

9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)

The device has an internal wide input VCC regulator which is sourced from the BIAS pin. The wide input VCC

regulator allows the BIAS pin to be connected directly to supply voltages from 3.5 V to 60 V.

The VCC regulator turns on when the device is in standby or run mode. When the BIAS pin voltage is below the

VCC regulation target, the VCC output tracks the BIAS with a small dropout voltage. When the BIAS pin voltage

is greater than the VCC regulation target, the VCC regulator provides 6.85-V supply for the N-channel MOSFET

driver.

The VCC regulator sources current into the capacitor connected to the VCC pin with a minimum of 35-mA

capability. The recommended VCC capacitor value is from 1 µF to 4.7 µF.

The device supports a wide input range from 3.5 V to 60 V in normal configuration. By connecting the BIAS pin

directly to the VCC pin, the device supports inputs from 2.97 V to 16 V. This configuration is recommended when

the device starts up from a 1-cell battery.

_SUPPLY(2.97V ꢀ 16V)

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

DITHOFF

AGND

PGND

PGOOD

SS COMP

Figure 9-5. 2.97-V Start-Up (BIAS = VCC)

The minimum supply voltage after start-up can be further decreased by supplying the BIAS pin from the boost

converter output or from an external power supply as shown in Figure 9-6.

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V_SUPPLY

V_LOAD

BIAS

GATE

VCC

UVLO > V_UVLO(RISING)

UVLO/SYNC

DITHOFF

AGND

PGND

PGOOD

SS COMP

Figure 9-6. Decrease the Minimum Operating Voltage After Start-Up

In flyback topology, the internal power dissipation of the device can be decreased by supplying the VCC using an

additional transformer winding. In this configuration, the external VCC supply voltage must be greater than the

VCC regulation target (V_VCC-REG), and the BIAS pin voltage must be greater the VCC voltage because the VCC

regulator includes a diode between VCC and BIAS.

V_SUPPLY

BIAS

GATE

VCC

UVLO/SYNC

DITHOFF

AGND

PGND

PGOOD

SS COMP

Figure 9-7. External VCC Supply (BIAS ≥ VCC)

If the voltage of the external VCC bias supply is greater than the BIAS pin voltage, use an external blocking

diode from the input power supply to the BIAS pin to prevent the external bias supply from passing current to the

boost input supply through VCC.

9.3.3 Soft Start (SS Pin)

The soft-start feature helps the converter gradually reach the steady state operating point, thus reducing start-up

stresses and surges. The device regulates the FB pin to the SS pin voltage or the internal reference, whichever

is lower.

At start-up, the internal 10-μA soft-start current source (I_SS) turns on 50 µs after the VCC voltage exceeds the

2.85-VCC UV threshold, or if the VCC voltage is greater than 4.5 V, whichever comes first. The soft-start current

gradually increases the voltage on an external soft-start capacitor connected to the SS pin. This results in a

gradual rise of the output voltage. The SS pin is pulled down to ground by an internal switch when the VCC is

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less than VCC UVLO threshold, the UVLO is less than the UVLO threshold, during hiccup mode off-time or

thermal shutdown.

In boost topology, soft-start time (t_SS) varies with the input supply voltage. The soft-start time in boost topology is

calculated as shown in Equation 3.

≈

’

◊

C_SS

V_SUPPLY

t_SS

ì 1-

∆

I_SS

V_LOAD

(3)

In SEPIC topology, the soft-start time (t_SS) is calculated as follows.

C_SS

t_SS

I_SS

(4)

TI recommends choosing the soft-start time long enough so that the converter can start up without going into an

overcurrent state. See Section 9.3.11 for more detailed information.

Figure 9-8 shows an implementation of primary side soft-start in flyback topology.

COMP

FB SS

Figure 9-8. Primary-Side Soft Start in Flyback

Figure 9-9 shows an implementation of secondary side soft start in flyback topology.

V_LOAD

Secondary Side

Soft-start

Figure 9-9. Secondary-Side Soft Start in Flyback

9.3.4 Switching Frequency (RT Pin)

The switching frequency of the device can be set by a single RT resistor connected between the RT and the

AGND pins. The resistor value to set the RT switching frequency (f_RT) is calculated as shown in Equation 5.

2.21ì10¹⁰

f_RT(TYPICAL)

R_T=

- 955

(5)

The RT pin is regulated to 0.5 V by the internal RT regulator when the device is enabled.

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9.3.5 Dual Random Spread Spectrum (DRSS)

The device provides a digital spread spectrum which reduces the EMI of the power supply over a wide frequency

range. This function is dynamically selectable during operation. The internal modulator dithers the internal clock

when the DITHOFF pin is less than 1.0 V or the pin is grounded, and it stops clock dithering when the DITHOFF

pin is greater than 2.0 V or the pin is connected to VCC. When an external synchronization clock is applied to

the SYNC pin, the internal spread spectrum is disabled. DRSS (a) combines a low frequency triangular

modulation profile (b) with a high frequency cycle-by-cycle random modulation profile (c). The low frequency

triangular modulation improves performance in lower radio frequency bands (for example. AM band), while the

high frequency random modulation improves performance in higher radio frequency bands (for example, FM

band). In addition, the frequency of the triangular modulation is further modulated randomly to reduce the

likelihood of any audible tones. To minimize output voltage ripple caused by spread spectrum, duty cycle is

modified on a cycle-by-cycle basis to maintain a nearly constant duty cycle when dithering is enabled (see

Figure 9-10).

Frequency

0.156 x f_SW

(a) Low + High Frequency

Random Modulation

f_SW

(b) Low Frequency

Random Modulation

DITHER ON

(DITHOFF=GND)

DITHER OFF

(DITHOFF=VCC)

Figure 9-10. Dual Random Spread Spectrum

9.3.6 Clock Synchronization (UVLO/SYNC/EN Pin)

The switching frequency of the device can be synchronized to an external clock by pulling down the UVLO/

SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input

during the forced off-time which is determined by the maximum duty cycle limit. The external synchronization

clock must pull down the UVLO/SYNC pin voltage below 1.45 V (typical). The duty cycle of the pulldown pulse is

not limited, but the minimum pulldown pulse width must be greater than 150 ns, and the minimum pullup pulse

width must be greater than 250 ns. Figure 9-11 shows an implementation of the remote shutdown function. The

UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In this configuration,

the device stops switching immediately after the UVLO pin is grounded, and the device shuts down 35 µs

(typical) after the UVLO pin is grounded.

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V_SUPPLY

MCU

UVLO/SYNC

SHUTDOWN

Figure 9-11. UVLO and Shutdown

Figure 9-12 shows an implementation of shutdown and clock synchronization functions together. In this

configuration, the device stops switching immediately when the UVLO pin is grounded, and the device shuts

down if f_SYNCstays in high logic state for longer than 35 µs (typical) (UVLO is in low logic state for more than 35

µs (typical)). The device runs at the f_SYNCif clock pulses are provided after the device is enabled.

V_SUPPLY

MCU

UVLO/SYNC

F_SYNC

Figure 9-12. UVLO, Shutdown, and Clock Synchronization

Figure 9-14 and Figure 9-15 show implementations of standby and clock synchronization functions together. In

this configuration, the device stops switching immediately if f_SYNCstays in high logic state and enters standby

mode if f_SYNCstays in high logic state for longer than two switching cycles. The device runs at the f_SYNCif clock

pulses are provided. Because the device can be enabled when the UVLO pin voltage is greater than the enable

threshold for more than 1.5 µs, the configurations in Figure 9-14 and Figure 9-15 are recommended if the

external clock synchronization pulses are provided from the start before the device is enabled. This 1.5-µs

requirement can be relaxed when the duty cycle of the synchronization pulse is greater than 50%. Figure 9-13

shows the required minimum duty cycle to start up by synchronization pulses. When the switching frequency is

greater than 1.1 MHz, the UVLO pin voltage should be greater than the enable threshold for more than 1.5 µs

before applying the external synchronization pulse.

100 200 300 400 500 600 700 800 900 1000 1100

f_SW[kHz]

SUby

Figure 9-13. Required Duty Cycle to Start Up by SYNC

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V_SUPPLY

MCU

UVLO/SYNC

>0.7V

F_SYNC

Figure 9-14. UVLO, Standby, and Clock Synchronization (a)

V_SUPPLY

UVLO/SYNC

MCU

F_SYNC

Figure 9-15. UVLO, Standby, and Clock Synchronization (b)

If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented

together by using one push-pull output of the MCU. In this configuration, the device shuts down if f_SYNCstays in

low logic state for longer than 35 µs (typical). The device is enabled if f_SYNCstays in high logic state for longer

than 1.5 µs. The device runs at the f_SYNCif clock pulses are provided after the device is enabled. Also, in this

configuration, it is recommended to apply the external clock pulses after the BIAS is supplied. By limiting the

current flowing into the UVLO pin below 1 mA using a current limiting resistor, the external clock pulses can be

supplied before the BIAS is supplied (see Figure 9-16).

MCU

10 ꢀ

UVLO/SYNC

F_SYNC

Figure 9-16. Shutdown and Clock Synchronization

Figure 9-17 shows an implementation of inverted enable using external circuit.

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V_SUPPLY

UVLO/SYNC

LMV431

Figure 9-17. Inverted UVLO

The external clock frequency (f_SYNC) must be within +25% and –30% of f_RT(TYPICAL). Because the maximum duty

cycle limit and the peak current limit with slope resistor (R_SL) are affected by the clock synchronization, take

extra care when using the clock synchronization function. See Section 9.3.7, Section 9.3.8, and Section 9.3.12

for more information.

9.3.7 Current Sense and Slope Compensation (CS Pin)

The device has a low-side current sense and provides both fixed and optional programmable slope

compensation ramps, which help to prevent subharmonic oscillation at high duty cycle. Both fixed and

programmable slope compensation ramps are added to the sensed inductor current input for the PWM

operation. But, only the programmable slope compensation ramp is added to the sensed inductor current input

(see Figure 9-18). For an accurate peak current limit operation over the input supply voltage, TI recommends

using only the fixed slope compensation (see Figure 8-5).

The device can generate the programmable slope compensation ramp using an external slope resistor (R_SL) and

a sawtooth current source with a slope of 30 μA × f_RT. This current flows out of the CS pin.

Current Limit

Comparator

I_SLOPE

V_CSTH

R_SL

(optional)

R_F

(optional)

V_CS1

R_S

V_CS2

_COMP=0.142

C_F

(optional)

_SLOPE+ offset

PWM

Comparator

COMP

R_COMP

C_HF

(optional)

C_COMP

Figure 9-18. Current Sensing and Slope Compensation

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Programmable Slope

Compensation Ramp

I_SLOPE× R_SL× D

Fixed Slope

Compensation

Ramp

Programmable Slope

Compensation Ramp

V_SLOPE× D + 0.17V

I_SLOPE× R_SL× D

Sensed Inductor

Current (R_S× I_LM

Sensed Inductor

Current (R_S× I_LM

)

Figure 9-19. Slope Compensation Ramp (a) at PWM

Comparator Input

Figure 9-20. Slope Compensation Ramp (b) at

Current Limit Comparator Input

Use Equation 6 to calculate the value of the peak slope current (I_SLOPE) and use Equation 7 to calculate the

value of the peak slope voltage (V_SLOPE).

f_RT

I_SLOPE= 30mA ì

f_SYNC

(6)

f_RT

V_SLOPE= 40mV ì

f_SYNC

(7)

where

•

f_SYNC= f_RTif clock synchronization is not used.

According to peak current mode control theory, the slope of the compensation ramp must be greater than half of

the sensed inductor current falling slope to prevent sub-harmonic oscillation at high duty cycle. Therefore, the

minimum amount of slope compensation in boost topology should satisfy the following inequality:

+ V_F- V

(

)

L_M

LOAD

SUPPLY

0.5ì

ìR_SìMargin < 40mV ì f_SW

(8)

where

V_Fis a forward voltage drop of D1, the external diode.

•

The recommended margin to cover non-ideal factors is 1.2. If required, R_SLcan be added to further increase the

slope of the compensation ramp. Typically 82% of the sensed inductor current falling slope is known as an

optimal amount of the slope compensation. The R_SLvalue to achieve 82% of the sensed inductor current falling

slope is calculated as shown in Equation 9.

_LOAD+ V_F- V

(

)

L_M

SUPPLY

0.82ì

ìR = 30uA ìR + 40mV ì f

(

)

(9)

If clock synchronization is not used, the f_SWfrequency equals the f_RTfrequency. If clock synchronization is used,

the f_SWfrequency equals the f_SYNCfrequency. The maximum value for the R_SLresistance is 2 kΩ.

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9.3.8 Current Limit and Minimum On-time (CS Pin)

The device provides cycle-by-cycle peak current limit protection that turns off the MOSFET when the sum of the

inductor current and the programmable slope compensation ramp reaches the current limit threshold (V_CLTH).

Peak inductor current limit (I_PEAK-CL) in steady state is calculated as shown in Equation 10.

f_RT

V_CLTH- 30mA ìR_SL

ìD

f_SYNC

I_PEAK-CL

R_S

(10)

The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense

resistor. The estimated duty cycle is calculated as shown in Equation 11.

V_SUPPLY

D = 1-

V_LOAD+ V_F

(11)

Boost converters have a natural pass-through path from the supply to the load through the high-side power

diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot

provide current limit protection when the output voltage is close to or less than the input supply voltage. The

minimum on-time is shown in Figure 8-12 and is calculated as Equation 12.

800ì10^-15

t_ON(MIN)

+ 4ì10^-6

8ìR_T

(12)

If required, a small external RC filter (R_F, C_F) at the CS pin can be added to overcome the large leading edge

spike of the current sense signal. Select an R_Fvalue which is in the range of 10 Ω to 200 Ω and a C_Fvalue in the

rage of 100 pF to 2 nF. Because of the effect of this RC filter, the peak current limit is not valid when the on-time

is less than 2 × R_F× C_F. To fully discharge the C_Fduring the off-time, the RC time constant should satisfy the

following inequality.

1-D

f_SW

3ìR_FìC_F<

(13)

9.3.9 Feedback and Error Amplifier (FB, COMP Pin)

The feedback resistor divider is connected to an internal transconductance error amplifier which features high

output resistance (R_O= 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error

amplifier sources current, which is proportional to the difference between the FB pin and the SS pin voltage or

the internal reference, whichever is lower. The internal transconductance error amplifier provides symmetrical

sourcing and sinking capability during normal operation and reduces its sinking capability when the FB is greater

than OVP threshold.

To set the output regulation target, select the feedback resistor values as shown in Equation 14.

≈

∆

’

R_FBT

R_FBB

V_LOAD= V_REF

◊

(14)

The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation

network. R_COMP, C_COMP, and optional C_HFloop compensation components configure the error amplifier gain and

phase characteristics to achieve a stable loop response. The absolute maximum voltage rating of the FB pin is

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4.0 V. If necessary, especially during automotive load dump transient, the feedback resistor divider input can be

clamped with an external Zener diode.

The COMP pin features internal clamps. The maximum COMP clamp limits the maximum COMP pin voltage

below its absolute maximum rating even in shutdown. The minimum COMP clamp limits the minimum COMP pin

voltage in order to start switching as soon as possible during no load to heavy load transition. The minimum

COMP clamp is disabled when FB is connected to ground in flyback topology.

9.3.10 Power-Good Indicator (PGOOD Pin)

The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches

to a high impedance open-drain state when the FB pin voltage is greater than the feedback undervoltage

threshold (V_UVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than the EN

threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The

recommended minimum pullup resistor value is 10 kΩ.

Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater

than V_BIAS+ 0.3 V.

9.3.11 Hiccup Mode Overload Protection (LM51561H Only)

To further protect the converter during prolonged current limit conditions, the LM51561H device option provides a

hiccup mode overload protection. The internal hiccup mode fault timer of the device counts the PWM clock

cycles when the cycle-by-cycle current limiting occurs after soft-start is finished. When the hiccup mode fault

timer detects 64 cycles of current limiting, an internal hiccup mode off timer forces the device to stop switching

and pulls down SS. Then, the device will restart after 32,768 cycles of hiccup mode off-time. The 64 cycle hiccup

mode fault timer is reset if eight consecutive switching cycles occur without exceeding the current limit threshold.

The soft-start time must be long enough not to trigger the hiccup mode protection after the soft-start is finished.

4 cycles of

current limit

7 normal

switching

cycles

32768 hiccup

mode off cycles

64 cycles of

current limit

60 cycles of

current limit

32768 hiccup

mode off cycles

Inductor Current

Time

Figure 9-21. Hiccup Mode Overload Protection

To avoid an unexpected hiccup mode operation during a harsh load transient condition, it is recommended to

have more margin when programming the peak-current limit.

9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage

When designing boost converters, the maximum duty cycle should be reviewed at the minimum supply voltage.

The minimum input supply voltage that can achieve the target output voltage is limited by the maximum duty

cycle limit, and it can be estimated as follows.

V_SUPPLY(MIN)ö V

+ V ì 1-D

_F) (

+I_SUPPLY(MAX)ìR_DCR+I_SUPPLY(MAX)ì R_DS(ON)+R_SìD

(

)

(

)

LOAD

MAX

(15)

where

•

I_SUPPLY(MAX)is the maximum input current.

R_DCRis the DC resistance of the inductor.

R_DS(ON)is the on-resistance of the MOSFET.

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f_SYNC

D_MAX1= 1- 0.1ì

f_RT

(16)

(17)

D_MAX2= 1-100nsì f_SW

The minimum input supply voltage can be further decreased by supplying f_SYNCwhich is less than f_RT. D_MAXis

D_MAX1or D_MAX2, whichever is lower.

9.3.13 MOSFET Driver (GATE Pin)

The device provides an N-channel MOSFET driver that can source or sink a peak current of 1.5 A. The peak

sourcing current is larger when supplying an external VCC that is higher than 6.75-V VCC regulation target.

During start-up especially when the input voltage range is below the VCC regulation target , the VCC voltage

must be sufficient to completely enhance the MOSFET. If the MOSFET drive voltage is lower than the MOSFET

gate plateau voltage during start-up, the boost converter may not start up properly and it can stick at the

maximum duty cycle in a high power dissipation state. This condition can be avoided by selecting a lower

threshold N-channel MOSFET switch and setting the V_SUPPLY(ON)greater than 6 to 7 V. Because the internal

VCC regulator has a limited sourcing capability, the MOSFET gate charge should satisfy the following inequality.

Q_G@VCCì f_SW< 35mA

(18)

An internal 1-MΩ resistor is connected between GATE and PGND to prevent a false turnon during shutdown. In

boost topology, switch node dV/dT must be limited during the 65-µs internal start-up delay to avoid a false

turnon, which is caused by the coupling through C_DGparasitic capacitance of the MOSFET.

9.3.14 Overvoltage Protection (OVP)

The device has OVP for the output voltage. OVP is sensed at the FB pin. If the voltage at the FB pin rises above

the overvoltage threshold (V_OVTH), OVP is triggered and switching stops. During OVP, the internal error amplifier

is operational, but the maximum source and sink capability is decreased to 40 µA.

9.3.15 Thermal Shutdown (TSD)

An internal thermal shutdown turns off the VCC regulator, disables switching and pulls down the SS when the

junction temperature exceeds the thermal shutdown threshold (T_TSD). After the temperature is decreased by

15°C, the VCC regulator is enabled again and the device performs a soft start.

9.4 Device Functional Modes

9.4.1 Shutdown Mode

If the UVLO pin voltage is below the enable threshold for longer than 35 µs (typical), the device goes to

shutdown mode with all functions disabled. In shutdown mode, the device decreases the BIAS pin current

consumption to below 2.6 μA (typical).

9.4.2 Standby Mode

If the UVLO pin voltage is greater than the enable threshold and below the UVLO threshold for longer than 1.5

µs, the device is in standby mode with the VCC regulator operational, RT regulator operational, SS pin

grounded, and no switching at the GATE output. The PGOOD is activated when the VCC voltage is greater than

the VCC UV threshold.

9.4.3 Run Mode

If the UVLO pin voltage is above the UVLO threshold and the VCC voltage is sufficient, the device enters RUN

mode. In this mode, soft start starts 50 µs after the VCC voltage exceeds the 2.85 VCC UV threshold, or if the

VCC voltage is greater than 4.5 V, whichever comes first.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Power-On Hours (POH)

The device is capable of operating at a wide temperature range including high junction temperature up to 150°C.

It is designed to meet or exceed AEC-Q100 grade 1 specifications by accommodating additional IC junction

temperature rise while operating at 125°C ambient temperature. The electrical specifications of the device is fully

characterized between T_Jof -40°C to 150°C to support automotive and other high junction temperature

applications. Extended reliability test data beyond AEC-Q100 grade 1 specification is also available upon

request.

The device is capable of supporting product lifetime operation temperature profiles typical to many automotive

applications. Table 10-1 shows an example of an application with 19340 POH at an input bias voltage of 60 V.

The life span of a semiconductor device is a function of bias conditions, operating temperatures, and power-on

time. Extended operation at high junction temperature degrades the product total power-on hours.

Table 10-1. POH Breakdown

JUNCTION TEMPERATURE

POWER-ON HOURS

DISTRIBUTION

OPERATING CONDITIONS

-15°C

48°C

720 Hours

3.7 %

6300 Hours

32.6 %

BIAS = 60V

E_a= 0.7eV

101°C

145°C

150°C

11000 Hours

1200 Hours

56.9 %

6.2 %

120 Hours

0.6%

10.2 Application Information

How to Design a Boost Converter Using LM5156x explains how to design boost converter using the device. This

comprehensive application note includes component selections and loop response optimization.

10.3 Typical Application

Figure 10-1 shows all optional components to design a boost converter.

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R_SNBC_SNB

V_SUPPLY

L_M

V_LOAD

R_BIAS

D_G

R_G

C_BIAS

C_OUT1C_OUT2

R_LOAD

C_VCC

C_IN

R_UVLOT

R_FBT

BIAS

GATE

VCC

R_UVLOS

UVLO/SYNC

R_F

R_SL

R_FBB

R_S

R_UVLOB

C_UVLO

DITHOFF

AGND

C_F

PGND

PGOOD

MCU_VCC

R_PG

SS COMP

R_COMP

C_COMP

R_T

C_SS

C_HF

Figure 10-1. Typical Boost Converter Circuit With Optional Components

10.3.1 Design Requirements

Table 10-2 shows the intended input, output, and performance parameters for this application example.

Table 10-2. Design Example Parameters

DESIGN PARAMETER

VALUE

6 V

Minimum input supply voltage (V_SUPPLY(MIN)

)

Target output voltage (V_LOAD

Maximum load current (I_LOAD

Typical switching frequency (f_SW

)

24 V

)

2 A (≈ 48 Watt)

440 kHz

)

10.3.2 Detailed Design Procedure

Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application based

on the device. Download the Quick Start Calculator for more information on loop response and component

selection

•

LM5155x / LM5156x Boost Quick Start Calculator

The device is also WEBENCH® Designer enabled. The WEBENCH software uses an iterative design procedure

and accesses comprehensive data bases of components when generating a design.

10.3.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

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10.3.2.2 Recommended Components

Table 10-3 shows a recommended list of materials for this typical application.

Table 10-3. List of Materials

REFERENCE

DESIGNATOR

MANUFACTURER

QTY.

SPECIFICATION

PART NUMBER

(1)

R_T

RES, 49.9 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 47.0 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 2.0 k, 5%, 0.1 W, AEC-Q200 Grade 0, 0603

Vishay-Dale

CRCW060349K9FKEA

CRCW060347K0FKEA

CRCW06032K00JNEA

R_FBT

R_FBB

Inductor, Shielded, Composite, 6.8 uH, 18.5 A, 0.01 ohm,

SMD

L_M

Coilcraft

XAL1010-682MEB

R_S

R_SL

RES, 0.008, 1%, 3 W, AEC-Q200 Grade 0, 2512 WIDE

RES, 0, 5%, 0.1 W, 0603

Susumu

Yageo America

TDK

KRL6432E-M-R008-F-T1

RC0603JR-070RL

C_OUT1

CAP, CERM, 4.7 μF, 50 V, ±10%, X7R, 1210

C3225X7R1H475K250AB

CAP, Aluminum Polymer, 100 μF, 50 V, ±20%, 0.025 Ω,

AEC-Q200 Grade 2, D10xL10mm SMD

C_OUT2(Bulk)

C_IN1

Chemi-Con

MuRata

HHXB500ARA101MJA0G

GRM32ER71H106KA12L

EEHZC1H101P

CAP, CERM, 10 μF, 50 V, ±10%, X7R, 1210

CAP, Polymer Hybrid, 100 μF, 50 V, ±20%, 28 Ω, 10x10

SMD

C_IN2(Bulk)

Panasonic

MOSFET, N-CH, 40 V, 50 A, AEC-Q101, SON-8

Schottky, 60 V, 10 A, AEC-Q101, CFP15

Infineon

Nexperia

IPC50N04S5L5R5ATMA1

PMEG060V100EPDZ

CRCW060311K3FKEA

R_COMP

RES, 11.3 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

Vishay-Dale

CAP, CERM, 0.022 μF, 100 V, ±10%, X7R, AEC-Q200

Grade 1, 0603

C_COMP

C_HF

TDK

CGA3E2X7R2A223K080AA

CGA3E2C0G1H221J080AA

CAP, CERM, 220 pF, 20 V, ±5%, C0G/NP0, AEC-Q200

Grade 1, 0603

R_UVLOT

R_UVLOB

R_UVLOS

RES, 21.0 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 7.32 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

N/A

Vishay-Dale

N/A

CRCW060321K0FKEA

CRCW06037K32FKEA

N/A

CAP, CERM, 0.22 μF, 50 V, ±10%, X7R, AEC-Q200

Grade 1, 0603

C_SS

TDK

CGA3E3X7R1H224K080AB

D_G

R_G

N/A

RES, 0, 5%, 0.1 W, 0603

CAP, CERM, 100 pF, 50 V,±1%, C0G/NP0, 0603

RES, 100, 1%, 0.1 W, 0603

N/A

Yageo America

Kemet

N/A

RC0603JR-070RL

C0603C101F5GACTU

RC0603FR-07100RL

N/A

C_F

R_F

Yageo America

N/A

R_SNB

C_SNB

R_BIAS

N/A

RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0603

Panasonic

ERJ-3GEY0R00V

Samsung Electro-

Mechanics

C_BIAS

CAP, CERM, 0.01 μF, 50 V, ±10%, X7R, 0603

CL10B103KB8NCNC

CAP, CERM, 1 μF, 16 V, ±20%, X7R, AEC-Q200 Grade

1, 0603

C_VCC

R_PG

MuRata

GCM188R71C105MA64D

RC0603FR-0724K9L

RES, 24.9 k, 1%, 0.1 W, 0603

Yageo America

(1) See Section 13.1.1

10.3.2.3 Inductor Selection (L_M)

When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the

inductor current, and RHP zero frequency (f_RHP).

Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope of

the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle (additional R_SL

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resistor is required if not). Higher f_RHP(= lower inductance) allows a higher crossover frequency and is always

preferred when using a small value output capacitor.

The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average

inductor current as a good compromise between RR, F_RHPand inductor falling slope.

10.3.2.4 Output Capacitor (C_OUT

)

There are a few ways to select the proper value of output capacitor (C_OUT). The output capacitor value can be

selected based on output voltage ripple, output overshoot, or undershoot due to load transient.

The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using

multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the

diode and the MOSFET than the bulk aluminum capacitors in order to absorb the majority of the ripple current.

10.3.2.5 Input Capacitor

The input capacitors decrease the input voltage ripple. The required input capacitor value is a function of the

impedance of the source power supply. More input capacitors are required if the impedance of the source power

supply is not low enough.

10.3.2.6 MOSFET Selection

The MOSFET gate driver of the device is sourced from the VCC. The maximum gate charge is limited by the 35-

mA VCC sourcing current limit.

A leadless package is preferred for high switching-frequency designs. The MOSFET gate capacitance should be

small enough so that the gate voltage is fully discharged during the off-time.

10.3.2.7 Diode Selection

A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery

charge. Low reverse leakage current is important parameter when selecting the Schottky diode. The diode must

be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to handle

the average output current.

10.3.2.8 Efficiency Estimation

The total loss of the boost converter (P_TOTAL) can be expressed as the sum of the losses in the device (P_IC),

MOSFET power losses (P_Q), diode power losses (P_D), inductor power losses (P_L), and the loss in the sense

resistor (P_RS).

P_TOTAL= P +P_Q+P_D+P +P_RS

(19)

P_ICcan be separated into gate driving loss (P_G) and the losses caused by quiescent current (P_IQ).

= P_G+ P

(20)

Each power loss is approximately calculated as follows:

P_G= Q_G(@VCC)ì V_BIASì f_SW

(21)

(22)

= V_BIASìI_BIAS

I_VINand I_VOUTvalues in each mode can be found in the supply current section of Section 8.5.

P_Qcan be separated into switching loss (P_Q(SW)) and conduction loss (P_Q(COND)).

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P_Q= P_Q(SW)+ P_Q(COND)

(23)

Each power loss is approximately calculated as follows:

P_Q(SW)= 0.5ì(V_LOAD+ V_F)ìI_SUPPLYì(t_R+ t_F)ì f_SW

(24)

t_Rand t_Fare the rise and fall times of the low-side N-channel MOSFET device. I_SUPPLYis the input supply current

of the boost converter.

P_Q(COND)= DìI_SUPPLY²ìR_DS(ON)

(25)

R_DS(ON)is the on-resistance of the MOSFET and is specified in the MOSFET data sheet. Consider the R_DS(ON)

increase due to self-heating.

P_Dcan be separated into diode conduction loss (P_VF) and reverse recovery loss (P_RR).

P_D= P_VF+ P_RR

(26)

Each power loss is approximately calculated as follows:

P_VF= (1-D)ì V_FìI_SUPPLY

(27)

P_RR= V_LOADìQ_RRì f_SW

(28)

Q_RRis the reverse recovery charge of the diode and is specified in the diode data sheet. Reverse recovery

characteristics of the diode strongly affect efficiency, especially when the output voltage is high.

P_Lis the sum of DCR loss (P_DCR) and AC core loss (P_AC). DCR is the DC resistance of inductor which is

mentioned in the inductor data sheet.

P = P_DCR+ P_AC

(29)

Each power loss is approximately calculated as follows:

P_DCR= I_SUPPLY²ìR_DCR

(30)

P_AC= K ì DI^bì f_SW

(31)

V_SUPPLYìDì

f_SW

DI =

L_M

(32)

∆I is the peak-to-peak inductor current ripple. K, α, and β are core dependent factors which can be provided by

the inductor manufacturer.

P_RSis calculated as follows:

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P_RS= DìI_SUPPLY²ìR_S

(33)

Efficiency of the power converter can be estimated as follows:

V_LOADìI_LOAD

Efficiency =

P_TOTAL+ V_LOADìI_LOAD

(34)

10.3.3 Application Curve

V_SUPPLY=18V

V_SUPPLY=12V

V_SUPPLY=9V

V_SUPPLY=6V

0.2 0.4 0.6 0.8

I_LOAD[A]

1.2 1.4 1.6 1.8

BSTE

Figure 10-2. Efficiency

10.4 System Examples

V_SUPPLY

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

DITHOFF

AGND

PGND

PGOOD

SS COMP

Figure 10-3. Typical Boost Application

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V_SUPPLY= 3.5V - 60V

V_LOAD

Car

Battery

BIAS

GATE

VCC

To MCU

PGOOD

From MCU

PGND

UVLO/SYNC

DITHOFF

AGND

SS COMP

Figure 10-4. Typical Start-Stop Application

V_SUPPLY= 2.97V - 16V

= 12V / 24V

V_LOAD

1-cell or

2-cell

Battery

BIAS

GATE

VCC

PGOOD

From MCU

PGND

UVLO/SYNC

DITHOFF

AGND

SS COMP

Figure 10-5. Emergency-call / Boost On-Demand / Portable Speaker

V_SUPPLY

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

DITHOFF

AGND

PGND

PGOOD

SS COMP

Figure 10-6. Typical SEPIC Application

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Inductance should be small enough

to operate in DCM at full load

V_SUPPLY

= 30V-150V

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

From MCU

DITHOFF

AGND

PGND

PGOOD

SS COMP

Figure 10-7. LIDAR Bias Supply 1

> 150V-200V

V_LOAD

Voltage

Tripler

Inductance should be big enough

to operate in CCM

V_SUPPLY

BIAS

GATE

VCC

UVLO/SYNC

DITHOFF

AGND

PGND

PGOOD

SS COMP

Figure 10-8. LIDAR Bias Supply 2

V_SUPPLY

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

DITHOFF

AGND

To MCU

(Fault Indicator)

System Power

PGND

PGOOD

SS COMP

Figure 10-9. Low-Cost LED Driver

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V_SUPPLY

_LOAD= 5V/12V

BIAS

GATE

UVLO/SYNC

DITHOFF

AGND

PGND

VCC

PGOOD

COMP

Optional Primary-Side

Soft-Start

Figure 10-10. Secondary-Side Regulated Isolated Flyback

V_LOAD2= +12V

V_SUPPLY

V_LOAD3= -8.5V

BIAS

GATE

UVLO/SYNC

DITHOFF

AGND

PGND

VCC

To MCU

System Power

PGOOD

COMP

V_LOAD1= 3.3V/5V +/- 2%

Figure 10-11. Primary-Side Regulated Multiple-Output Isolated Flyback

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V_SUPPLY

V_LOAD

BIAS

GATE

UVLO/SYNC

DITHOFF

AGND

PGND

VCC

To MCU

System Power

PGOOD

COMP

Figure 10-12. Typical Non-Isolated Flyback

I_LED

V_SUPPLY

BIAS

GATE

VCC

UVLO/SYNC

DITHOFF

AGND

PGND

PGOOD

SS COMP

Figure 10-13. LED Driver with High-Side Current Sensing

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BIAS

GATE

VCC

UVLO/SYNC

DITHOFF

AGND

PGND

To MCU

(Fault Indicator)

System Power

PGOOD

SS COMP

TAIL

BRAKE

TURN

BACKUP

TPS9261x

Figure 10-14. Dual-Stage Automotive Rear-Lights LED Driver

11 Power Supply Recommendations

The device is designed to operate from a power supply or a battery whose voltage range is from 1.5 V to 60 V.

The input power supply must be able to supply the maximum boost supply voltage and handle the maximum

input current at 1.5 V. The impedance of the power supply and battery including cables must be low enough that

an input current transient does not cause an excessive drop. Additional input ceramic capacitors may be

required at the supply input of the converter.

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12 Layout

12.1 Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. The following

guidelines will help users design a PCB with the best power conversion performance, thermal performance, and

minimize generation of unwanted EMI.

•

Put the Q1, D1, and R_Scomponents on the board first.

Use a small size ceramic capacitor for C_OUT

Make the switching loop (C_OUTto D1 to Q1 to R_Sto C_OUT) as small as possible.

Leave a copper area near the D1 diode for thermal dissipation.

Put the device near the R_Sresistor.

Put the C_VCCcapacitor as near the device as possible between the VCC and PGND pins.

Use a wide and short trace to connect the PGND pin directly to the center of the sense resistor.

Connect the CS pin to the center of the sense resistor. If necessary, use vias.

Connect a filter capacitor between CS pin and power ground trace.

Connect the COMP pin to the compensation components (R_COMPand C_COMP).

Connect the C_COMPcapacitor to the power ground trace.

Connect the AGND pin directly to the analog ground plane. Connect the AGND pin to the R_UVLOB, R_T, C_SS

and R_FBBcomponents.

•

Connect the exposed pad to the AGND pin under the device.

Connect the GATE pin to the gate of the Q1 FET. If necessary, use vias.

Make the switching signal loop (GATE to Q1 to R_Sto PGND to GATE) as small as possible.

Add several vias under the exposed pad to help conduct heat away from the device. Connect the vias to a

large ground plane on the bottom layer.

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12.2 Layout Examples

V_SUPPLY

GND

L_M

C_VIN

Do not connect input and

output capacitor grounds

underneath the device

Connect

to V_SUPPLY

Connect

to V_SUPPLY

C_VIN

UVLO

PGOOD

BIAS

R_UVLOB

VCC

GATE

PGND

AGND

R_T

R_S

C_SS

C_VCC

R_FBB

DITHOFF

COMP

C_F

R_F

C_COMP

R_COMP

Do not connect input and

output capacitor grounds

underneath the device

C_OUT1

C_OUT2

Thermal Dissipation

Area

V_LOAD

GND

Figure 12-1. PCB Layout Example 1

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L_M

V_SUPPLY

C_VIN

GND

Do not connect input and

output capacitor grounds

underneath the device

Connect

to V_SUPPLY

V_LOAD

Connect to V_SUPPLY

UVLO

PGOOD

BIAS

R_UVLOB

VCC

R_S

R_T

GND

C_VCC

GATE

C_SS

C_OUT1

R_FBB

PGND

AGND

DITHOFF

COMP

C_OUT2

C_F

Power Ground Plane

(Connect to EP via GND pin)

C_COMP

R_COMP

R_F

Do not connect input and

output capacitor grounds

underneath the device

Figure 12-2. PCB Layout Example 2

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.1.2 Development Support

For development support see the following:

•

LM5155x / LM5156x Boost Quick Start Calculator

LM5155x / LM5156x Flyback Quick Start Calculator

LM5155x / LM5156x SEPIC Quick Start Calculator

How to Design a Boost Converter Using LM5156x

How to Design an Isolated Flyback Converter Using LM5156x

How to Design a SEPIC Converter Using LM5156x

13.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

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13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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2-Oct-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2000

(1)

(2)

(3)

(4/5)

(6)

LM51561HPWPR

LM5156HPWPR

ACTIVE

HTSSOP

PWP

Green (RoHS

& no Sb/Br)

Call TI | NIPDAU

Level-3-260C-168 HR

-40 to 125

51561H

5156H

ACTIVE

PWP

Green (RoHS

& no Sb/Br)

Call TI | NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

2-Oct-2020

OTHER QUALIFIED VERSIONS OF LM51561H, LM5156H :

Automotive: LM51561H-Q1, LM5156H-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Oct-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM51561HPWPR

LM5156HPWPR

HTSSOP PWP

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Oct-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM51561HPWPR

LM5156HPWPR

HTSSOP

PWP

2000

350.0

43.0

Pack Materials-Page 2

PACKAGE OUTLINE

PWP0014H

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

6.6

6.2

TYP

SEATING PLANE

PIN 1 ID

AREA

0.1 C

12X 0.65

5.1

4.9

3.9

NOTE 3

0.30

14X

0.19

4.5

4.3

0.1

C A B

SEE DETAIL A

(0.15) TYP

4X (0.28)

NOTE 5

4X (0.1)

NOTE 5

THERMAL

PAD

0.25

GAGE PLANE

2.86

2.02

1.2 MAX

0.15

0.05

0 - 8

0.75

0.50

DETAIL A

(1)

TYPICAL

1.82

0.98

4224353/A 07/2018

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ and may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0014H

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

SOLDER MASK

DEFINED PAD

(1.82)

SYMM

SEE DETAILS

14X (1.5)

14X (0.45)

(1.1)

TYP

SYMM

(2.86)

(5)

NOTE 9

12X (0.65)

(

0.2) TYP

VIA

(R0.05) TYP

(1.1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-14

/A 07/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0014H

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(1.82)

BASED ON

0.125 THICK

STENCIL

14X (1.5)

(R0.05) TYP

14X (0.45)

(2.86)

SYMM

BASED ON

0.125 THICK

STENCIL

12X (0.65)

SEE TABLE FOR

METAL COVERED

BY SOLDER MASK

SYMM

(5.8)

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.03 X 3.20

1.86 X 2.86 (SHOWN)

1.66 X 2.61

0.125

0.15

0.175

1.54 X 2.42

4224353/A 07/2018

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LM5156HPWPR [TI]

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