LM5156 [TI]

采用双随机展频技术的 2.2MHz 宽输入电压非同步升压、反激式和 SEPIC 控制器;


型号：	LM5156
厂家：	TEXAS INSTRUMENTS
描述：	采用双随机展频技术的 2.2MHz 宽输入电压非同步升压、反激式和 SEPIC 控制器控制器
文件：	总50页 (文件大小：2475K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM5156, LM51561

ZHCSN85 –JANUARY 2021

采用双随机展频技术的LM5156x 2.2MHz 宽输入电压65V 非同步升压/SEPIC/反

激式控制器

1 特性

2 应用

• 提供功能安全

• 无光耦合器的多输出反激式应用

• LED 偏置电源

• 宽输入升压、SEPIC 和反激式电源模块

• 便携式扬声器应用

• 反激式POE 电源应用

• 电池供电的升压、SEPIC 和反激式应用

– 可帮助进行功能安全系统设计的文档

• 适用于具有宽输入工作电压范围的电池应用

– 3.5V 至60V 工作电压范围（绝对最大值65V）

– 当BIAS = VCC 时，为2.97V 至16V

– BIAS 电压大于等于3.5V 时最小升压电源电压为

1.5V

3 说明

– 高达65V 的输入瞬态保护

– 最小电池消耗

LM5156x（LM5156 和 LM51561）器件是一款采用峰

值电流模式控制、具有宽输入范围的非同步升压控制

器。该器件可用于升压、SEPIC 和反激式拓扑。

• 低关断电流(I_Q≤2.6µA)

• 低工作电流(I_Q≤490µA)

• 解决方案尺寸小、成本低

如果 BIAS 引脚连接到 VCC 引脚，则 LM5156x 器件

可由单节电池（最低电压 2.97V）供电。如果 BIAS 引

脚电压高于 3.5V，则该器件可使用低至 1.5V 的输入电

源电压。

– 最大开关频率为2.2MHz

– 12 引脚WSON 封装(3mm × 2mm)

– 集成的误差放大器支持在没有光耦合器的情况下

进行初级侧稳压（反激）

器件信息

封装⁽¹⁾

• 缓减EMI

封装尺寸（标称值）

器件型号

LM5156

LM51561

– 可选双随机展频

– 无引线封装

• 低功耗、高效率

WSON (12)

3.00mm × 2.00mm

– 100mV ±7% 精确限流阈值

– 强大的1.5A 峰值标准MOSFET 驱动器

– 支持外部VCC 电源

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

V_SUPPLY

V_LOAD

• 避免AM 频带干扰和串扰

– 可选的时钟同步

– 100kHz 至2.2MHz 的动态可编程开关频率

• 集成型保护特性

BIAS

GATE

VCC

UVLO/SYNC

– 在输入电压范围内具有恒定峰值电流限制

– 可选断续模式过载保护（参阅器件比较表）

– 可编程线路UVLO

GND

DITHOFF

PGOOD

SS COMP

– OVP 保护

– 热关断保护

• ±1% 精度反馈基准

• 支持附加斜坡补偿

典型升压应用

• 可编程软启动

• PGOOD 指示器

• 使用LM5156x 并借助WEBENCH^®Power

Designer 创建定制设计方案

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSBI6

LM5156, LM51561

ZHCSN85 –JANUARY 2021

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Table of Contents

10 Application and Implementation................................26

10.1 Application Information........................................... 26

10.2 Typical Application.................................................. 26

10.3 System Examples................................................... 31

11 Power Supply Recommendations..............................35

12 Layout...........................................................................36

12.1 Layout Guidelines................................................... 36

12.2 Layout Examples.................................................... 37

13 Device and Documentation Support..........................39

13.1 Device Support....................................................... 39

13.2 Documentation Support.......................................... 39

13.3 接收文档更新通知................................................... 39

13.4 支持资源..................................................................39

13.5 Trademarks.............................................................39

13.6 静电放电警告.......................................................... 40

13.7 术语表..................................................................... 40

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Device Comparison Table...............................................3

7 Pin Configuration and Functions...................................4

8 Specifications.................................................................. 5

8.1 Absolute Maximum Ratings ....................................... 5

8.2 ESD Ratings .............................................................. 5

8.3 Recommended Operating Conditions ........................6

8.4 Thermal Information ...................................................6

8.5 Electrical Characteristics ............................................6

8.6 Typical Characteristics................................................9

9 Detailed Description......................................................12

9.1 Overview...................................................................12

9.2 Functional Block Diagram.........................................12

9.3 Feature Description...................................................13

9.4 Device Functional Modes..........................................25

Information.................................................................... 41

4 Revision History

DATE

REVISION

NOTES

January 2021

Initial release.

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5 Description (continued)

The internal VCC regulator also supports BIAS pin operation up to 60 V (65-V absolute maximum) . The

switching frequency is dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching

at 2.2 MHz minimizes AM band interference and allows for a small solution size and fast transient response. To

reduce the EMI of the power supply, the device provides a selectable dual random spread spectrum which

reduces the EMI over the wide frequency range.

The device features a 1.5-A standard MOSFET driver and a low 100-mV current limit threshold. The device also

supports the use of an external VCC supply to improve efficiency. Low operating current and pulse-skipping

operation improve efficiency at light loads.

The device has built-in protection features such as cycle-by-cycle current limit, overvoltage protection, line

UVLO, and thermal shutdown. Hiccup mode overload protection is available in the LM51561 device option.

Additional features include low shutdown I_Q, programmable soft start, programmable slope compensation,

precision reference, power-good indicator, and external clock synchronization.

6 Device Comparison Table

DEVICE OPTION

LM5156

HICCUP MODE PROTECTION

INTERNAL REFERENCE

Disabled

Enabled

1 V

LM51561

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7 Pin Configuration and Functions

BIAS

UVLO/SYNC

PGOOD

VCC

GATE

GND

DITHOFF

COMP

图7-1. 12-Pin WSON DSS Package (Transparent Top View)

表7-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

BIAS

Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to GND.

Output of the internal VCC regulator and supply voltage input of the MOSFET driver. Connect a

ceramic bypass capacitor from this pin to GND.

VCC

GATE

GND

N-channel MOSFET gate drive output. Connect directly to the gate of the N-channel MOSFET

through a short, low inductance path.

Ground pin. Connect directly to the ground connection of the sense resistor through a low inductance

wide and short path.

Current sense input pin. Connect to the positive side of the current sense resistor through a short

path.

Output of the internal transconductance error amplifier. Connect the loop compensation components

between this pin and GND.

COMP

Spread spectrum selection pin. Internal spread spectrum (Clock dithering) is disabled when the pin is

connected to the VCC pin. Connecting the pin to GND enables the internal spread spectrum.

DITHOFF

Inverting input of the error amplifier. Connect a voltage divider from the output to this pin to set output

voltage in boost/SEPIC topologies. Connect the low-side feedback resistor to GND.

Soft-start time programming pin. An external capacitor and an internal current source set the ramp

rate of the internal error amplifier reference during soft start. Connect the ground connection of the

capacitor to GND.

Switching frequency setting pin. The switching frequency is programmed by a single resistor

between RT and GND.

Power-good indicator. An open-drain output which goes low if FB is below the under voltage

threshold. Connect a pullup resistor to the system voltage rail.

PGOOD

Undervoltage lockout programming pin. The converter start-up and shutdown levels can be

programmed by connecting this pin to the supply voltage through a resistor divider. The internal clock

can be synchronized to an external clock by applying a negative pulse signal into the UVLO/

SYNC/EN pin. This pin must not be left floating. Connect to BIAS pin if not used. Connect the low-

side UVLO resistor to GND.

UVLO/

SYNC/EN

Exposed pad of the package. The exposed pad must be connected to GND and the large ground

copper plane to decrease thermal resistance.

—

(1) G = Ground, I = Input, O = Output, P = Power

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8 Specifications

8.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range⁽¹⁾

MIN

–0.3

–1

MAX

UNIT

BIAS to GND

UVLO to GND

SS to GND⁽²⁾

V_BIAS+0.3

3.8

RT to GND⁽²⁾

3.8

Input

FB to GND

4.0

CS to GND(DC)

0.3

CS to GND(50ns transient)

DITHOFF to GND

VCC to GND

-0.3

18⁽³⁾

–0.3

–1

GATE to GND (50ns transient)

Output

PGOOD to GND⁽⁴⁾

–0.3

–40

–55

COMP to GND⁽⁵⁾

(6)

Junction temperature, T_J

150

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) This pin is not specified to have an external voltage applied.

(3) 18 V or V_BIAS+ 0.3 V whichever is lower

(4) The maximum current sink is limited to 1 mA when V_PGOOD>V_BIAS

(5) This pin has an internal max voltage clamp which can handle up to 1.6 mA.

(6) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Electrostatic

discharge

V_(ESD)

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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8.3 Recommended Operating Conditions

Over the recommended operating junction temperature range⁽¹⁾

MIN

2.97

NOM

MAX

UNIT

V_BIAS

V_VCC

V_DITHOFF

V_UVLO

V_FB

Bias input⁽²⁾

VCC voltage⁽³⁾

DITHOFF input

UVLO input

FB input

4.0

f_SW

Typical switching frequency

Synchronization pulse frequency

Operating junction temperature

100

–40

2200

125

kHz

°C

f_SYNC

T_J

(1) Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical

Characteristics.

(2) BIAS pin operating range is from 2.97 V to 16 V when VCC is directly connected to BIAS. BIAS pin operating range is from 3.5 V to 60

V when VCC is supplied from the internal VCC regulator.

(3) This pin voltage should be less than V_BIAS+ 0.3 V.

8.4 Thermal Information

LM5156x

THERMAL METRIC⁽¹⁾

DSS(WSON)

12 PINS

41.5

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance (LM5156EVM-BST)

Junction-to-ambient thermal resistance

°C/W

63.1

Junction-to-case (top) thermal resistance

62.4

Junction-to-board thermal resistance

31.6

Junction-to-top characterization parameter (LM5156EVM-BST)

Junction-to-top characterization parameter

1.5

2.2

ψ_JT

Junction-to-board characterization parameter (LM5156EVM-BST)

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

21.8

ψ_JB

31.5

ψ_JB

R_θJC(bot)

10.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= -40°C to 125°C. Unless otherwise

stated, V_BIAS= 12 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

I_{SHUTDOWN(BIAS)}

BIAS shutdown current

V_BIAS= 12 V, V_UVLO= 0 V

2.6

V_BIAS= 12 V, V_UVLO= 2.0 V, V_FB

V_REF, R_T= 220 kΩ

I_{OPERATING(BIAS)}

BIAS operating current

490

550

VCC REGULATOR

V_VCC-REG

VCC regulation

V_BIAS= 8 V, No load

V_BIAS= 8 V, I_VCC= 35 mA

VCC rising

6.5

6.85

V_{VCC-UVLO(RISING)}VCC UVLO threshold

VCC UVLO hysteresis

2.75

2.85

0.063

110

2.95

VCC falling

I_VCC-CL

VCC sourcing current limit

V_BIAS= 10 V, V_VCC= 0 V

ENABLE

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Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= -40°C to 125°C. Unless otherwise

stated, V_BIAS= 12 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

0.4

TYP

0.52

0.49

0.03

MAX

0.7

UNIT

V_EN(RISING)

Enable threshold

Enable hysteresis

EN rising

EN falling

V_EN(FALLING)

V_EN(HYS)

0.33

0.63

UVLO/SYNC

V_UVLO(RISING)

V_{UVLO(FALLING)}

UVLO / SYNC threshold

UVLO rising

UVLO falling

1.425

1.370

1.5

1.575

1.520

1.45

UVLO / SYNC threshold

hysteresis

V_UVLO(HYS)

I_UVLO

UVLO falling

0.05

UVLO hysteresis current

V_UVLO= 1.6 V

SPREAD SPECTRUM

V_{DITHOFF(RISING)}

Clock dithering threshold

DITHOFF rising, V_BIAS= 4 V

DITHOFF falling, V_BIAS= 4 V

1.1

0.6

1.7

1.2

2.1

1.8

V_{DITHOFF(FALLING)}Clock dithering threshold

Clock dithering threshold

V_DITHOFF(HYS)

hysteresis

DITHOFF falling, V_BIAS= 4 V

0.5

I_SS

Soft-start current

SS pull-down switch R_DSON

PULSE WIDTH MODULATION

fsw1

Switching frequency

100

2200

115

kHz

R_T= 220 kΩ, V_BIAS= 4 V

R_T= 9.09 kΩ, V_BIAS= 4 V

R_T= 9.09 kΩ

fsw2

Switching frequency

Minimum on-time

1980

2420

t_ON(MIN)

D_MAX1

Maximum duty cycle limit

R_T= 9.09 kΩ, V_BIAS= 4 V

R_T= 220 kΩ, V_BIAS= 4 V

D_MAX2

CURRENT SENSE

I_SLOPE

Peak slope compensation current

Current Limit threshold (CS-GND)

22.5

37.5

107

R_T= 220 kΩ

V_CLTH

100

HICCUP MODE PROTECTION (LM51561)

Hiccup enable cycles

Cycles

Hiccup timer reset cycles

ERROR AMPLIFIER

V_REF

FB reference

LM5156, LM51561

0.99

1.01

mA/V

Transconductance

COMP sourcing current

COMP clamp voltage

V_COMP= 1.2 V

180

2.5

COMP rising (V_UVLO= 2.0 V)

COMP falling

2.8

1.1

OVP

V_OVTH

Over-voltage threshold

FB rising (referece to V_REF

)

107

110

105

113

FB falling (referece to V_REF

)

PGOOD

PGOOD pulldown switch R_DSON1 mA sinking

V_UVTH

Under-voltage threshold

FB falling (referece to V_REF

)

FB rising (referece to V_REF

)

MOSFET DRIVER

High-state voltage drop

Low-state voltage drop

100 mA sinking

100 mA sourcing

0.25

0.15

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Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= -40°C to 125°C. Unless otherwise

stated, V_BIAS= 12 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

THERMAL SHUTDOWN

T_TSD

Thermal shutdown threshold

Thermal shutdown hysteresis

Temperature rising

175

°C

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8.6 Typical Characteristics

110

108

106

104

102

100

2400

2200

2000

1800

1600

1400

1200

1000

800

RT=220kW

RT=9.09kW

2360

2320

2280

2240

2200

2160

2120

2080

2040

2000

RT=220kOhm

RT=9.09kOhm

600

400

200

-40 -20

80 100 120 140 160

Temperature (èC)

D002

910

30 40 50 6070

RT Resistor (kW)

100

200250

D001

图8-2. Frequency vs Temperature

图8-1. Frequency vs RT Resistance

BIAS

VCC

I_VCC(mA)

100

120

V_BIAS(V)

D003

D004

图8-3. V_VCCvs I_VCC

图8-4. V_VCCvs V_BIAS(No Load)

105

104

103

102

101

100

R_SL=0W

R_SL=1kW

F_SW=440kHz, R_S=6mW, L_M=1.2mH, V_LOAD=10V

Duty Cycle (%)

90 100

-40 -20

80 100 120 140 160

Temperature (èC)

D005

D006

图8-5. Peak Current Limit vs Duty Cycle

图8-6. Current Limit Threshold vs Temperature

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1.01

1.008

1.006

1.004

1.002

0.56

0.55

0.54

0.53

0.52

0.51

0.5

0.49

0.48

0.47

0.46

0.45

0.44

0.43

0.998

0.996

0.994

0.992

0.99

EN Falling

EN Rising

-40 -20

80 100 120 140 160

-40 -20

80 100 120 140 160

Temperature (èC)

D007

D008

图8-7. FB Reference vs Temperature

图8-8. EN Threshold vs Temperature

530

520

510

500

490

480

470

4.5

3.5

2.5

1.5

0.5

V_FB=V_REF, RT=221kW, V_VCC=7V, COMP=1.75V

10 15 20 25 30 35 40 45 50 55 60

V_BIAS(V)

10 15 20 25 30 35 40 45 50 55 60

VBIAS (V)

D009

D010

图8-9. I_{OPERATING(BIAS)}Including RT Current vs

图8-10. I_{SHUTDOWN(BIAS)}vs V_BIAS

V_BIAS

4.6

4.4

4.2

200

180

160

140

120

100

3.8

3.6

3.4

BIAS=12V

BIAS=45V

3.2

2.8

2.6

2.4

250 500 750 1000 1250 1500 1750 2000 2250 2500

Frequency (kHz)

-40 -20

80 100 120 140 160

Temperature (èC)

D012

D011

图8-12. t_ON(MIN)vs Frequency

图8-11. I_SHUTDOWNvs Temperature

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10.8

10.6

10.4

10.2

1.8

1.6

1.4

1.2

9.8

0.8

0.6

0.4

0.2

9.6

9.4

Isource (A)

Isink (A)

9.2

-40 -20

80 100 120 140 160

Temperature (èC)

V_VCC(V)

D013

D014

图8-13. I_SSvs Temperature

图8-14. Peak Driver Current vs VCC

1.56

1.54

1.52

1.5

UVLO rising

UVLO falling

1.48

1.46

1.44

1.42

1.4

-40 -20

80 100 120 140 160

250 500 750 1000 1250 1500 1750 2000 2250

Frequency (kHz)

Temperature (èC)

D015

D016

图8-15. UVLO Threshold vs Temperature

图8-16. Maximum Duty Cycle vs Frequency

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9 Detailed Description

9.1 Overview

The LM5156x device is a wide input range, non-synchronous boost controller that uses peak-current-mode

control. The device can be used in boost, SEPIC, and flyback topologies.

The device can start up from a 1-cell battery with a minimum of 2.97 V if the BIAS pin is connected to the VCC

pin. It can operate with the input supply voltage as low as 1.5 V if the BIAS pin is greater than 3.5 V. The internal

VCC regulator also supports BIAS pin operation up to 60 V (65-V absolute maximum) . The switching frequency

is dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes

AM band interference and allows for a small solution size and fast transient response. To reduce the EMI of the

power supply, the device provides an optional dual random spread spectrum, which reduces the EMI over the

wide frequency span.

The device features a 1.5-A standard MOSFET driver and a low 100-mV current limit threshold. The device also

supports the use of an external VCC supply to improve efficiency. Low operating current and pulse skipping

operation improve efficiency at light loads.

The device has built-in protection features such as cycle-by-cycle current limit, overvoltage protection, line

UVLO, and thermal shutdown. Hiccup mode overload protection is available in the LM51561 device option.

Additional features include low shutdown I_Q, programmable soft start, programmable slope compensation,

precision reference, power good indicator, and external clock synchronization.

9.2 Functional Block Diagram

V_SUPPLY

L_M

V_LOAD

C_IN

C_OUT

R_LOAD

R_FBT

PGOOD

BIAS

R_FBB

V_UVTH

I_UVLO

VCC_OK

TSD

V_SUPPLY

RUN

V_UVLO

OVP

BIAS

V_OVTH

R_UVLOT

SYNC

Detector

Clock_Sync

VCC

UVLO/

SYNC

V_EN

VCC

Regulator

VCC_EN

TSD

R_UVLOB

VCC_EN

Optional

Hiccup Mode

V_CS1

C_VCC

VCC

UVLO

VCC_OK

V_CSTH

GATE

C/L Comparator

I_SS

OVP

V_REF

I_SLOPE

V_CS2

C_SS

PWM Comparator

V_CS1

G_COMP

Clock

Generator

Clock_Sync

R_S

V_CS2

COMP

GND

DITHOFF

R_T

R_COMP

C_COMP

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9.3 Feature Description

9.3.1 Line Undervoltage Lockout (UVLO/SYNC/EN Pin)

The device has a dual-level UVLO circuit. During power-on, if the BIAS pin voltage is greater than 2.7 V, and the

UVLO pin voltage is in between the enable threshold (V_EN) and the UVLO threshold (V_UVLO) for more than 1.5 µs

(see 节 9.3.6 for more details), the device starts up and an internal configuration starts. The device typically

requires a 65-µs internal start-up delay before entering standby mode. In standby mode, the VCC regulator and

RT regulator are operational, SS pin is grounded, and there is no switching at the GATE output.

I_UVLO

V_SUPPLY

V_UVLO

RUN

R_UVLOT

UVLO/

SYNC

R_UVLOB

VCC_EN

V_EN

图9-1. Line UVLO and Enable

When the UVLO pin voltage is above the UVLO threshold, the device enters run mode. In the run mode, a soft-

start sequence starts if the VCC voltage is greater than 4.5 V, or 50 µs after the VCC voltage exceeds the 2.85-V

VCC UV threshold (V_VCC-UVLO), whichever comes first. UVLO hysteresis is accomplished with an internal 50-mV

voltage hysteresis and an additional 5-μA current source that is switched on or off. When the UVLO pin voltage

exceeds the UVLO threshold, the current source is enabled to quickly raise the voltage at the UVLO pin. When

the UVLO pin voltage falls below the UVLO threshold, the current source is disabled, causing the voltage at the

UVLO pin to fall quickly. When the UVLO pin voltage is less than the enable threshold (V_EN), the device enters

shutdown mode after a 35-µs (typical) delay with all functions disabled.

65-µs (typical)

50-µs

internal start-up delay

> 3 cycles

VCC UV delay

BIAS

= V_SUPPLY

2.7 V

1.5 V

0.55 V

Standby

2.85 V

4.5 V

UVLO

VCC

Shutdown

1 V

1.5 µs

SS is grounded

with 2 cycles

delay

UVLO should be greater than

0.55 V more than 1.5 µs to start-up

GATE

T_SS

V_LOAD

1 V

V_LOAD(TARGET)

V_LOAD

图9-2. Boost Start-Up Waveforms Case 1: Start-Up by 2.85-V VCC UVLO, UVLO Toggle After Start-Up

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50-µs

VCC UV delay

65-µs (typical)

internal start-up delay

65-µs (typical)

internal start-up delay

> 35 µs

BIAS

= V_SUPPLY

2.7 V

1.5 V

0.52 V

Standby

2.85 V

4.5 V

UVLO

VCC

Shutdown

1.5 µs

1 V

SS is grounded

with 2 cycles

delay

UVLO should be greater than

0.55 V more than 1.5µs to start-up

GATE

t_SS

V_LOAD

1 V

V_LOAD(TARGET)

V_LOAD

图9-3. Boost Start-Up Waveforms Case 2: Start-Up When VCC > 4.5 V, EN Toggle After Start-Up

The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5 V

(typical) when the input voltage is in the desired operating range. The values of R_UVLOTand R_UVLOBcan be

calculated as shown in 方程式1 and 方程式2.

V_{UVLO(FALLING)}

V_SUPPLY(ON)

- V_SUPPLY(OFF)

V_UVLO(RISING)

I_UVLO

R_UVLOT

(1)

where

• V_SUPPLY(ON)is the desired start-up voltage of the converter.

• V_SUPPLY(OFF)is the desired turnoff voltage of the converter.

V_UVLO(RISING)ìR_UVLOT

R_UVLOB

V_SUPPLY(ON)- V_UVLO(RISING)

(2)

UVLO capacitor (C_UVLO) is required in case the input voltage drops below V_SUPPLY(OFF)momentarily during start-

up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an

additional series UVLO resistor (R_UVLOS) can be used to quickly raise the voltage at the UVLO pin when the 5-

μA hysteresis current turns on.

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I_UVLO

V_SUPPLY

V_UVLO

R_UVLOT

R_UVLOS

RUN

R_UVLOB

UVLO/SYNC

C_UVLO

图9-4. Line UVLO Using Three UVLO Resistors

Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.

9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)

The device has an internal wide input VCC regulator which is sourced from the BIAS pin. The wide input VCC

regulator allows the BIAS pin to be connected directly to supply voltages from 3.5 V to 60 V.

The VCC regulator turns on when the device is in the standby or run mode. When the BIAS pin voltage is below

the VCC regulation target, the VCC output tracks the BIAS with a small dropout voltage. When the BIAS pin

voltage is greater than the VCC regulation target, the VCC regulator provides 6.85-V supply for the N-channel

MOSFET driver.

The VCC regulator sources current into the capacitor connected to the VCC pin with a minimum of 35-mA

capability. The recommended VCC capacitor value is from 1 µF to 4.7 µF.

The device supports a wide input range from 3.5 V to 60 V in normal configuration. By connecting the BIAS pin

directly to the VCC pin, the device supports inputs from 2.97 V to 16 V. This configuration is recommended when

the device starts up from a 1-cell battery.

_SUPPLY(2.97V ꢀ 16V)

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

GND

DITHOFF

PGOOD

SS COMP

图9-5. 2.97-V Start-Up (BIAS = VCC)

The minimum supply voltage after start-up can be further decreased by supplying the BIAS pin from the boost

converter output or from an external power supply as shown in 图9-6.

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V_SUPPLY

V_LOAD

BIAS

GATE

VCC

UVLO > V_UVLO(RISING)

UVLO/SYNC

GND

DITHOFF

PGOOD

SS COMP

图9-6. Decrease the Minimum Operating Voltage After Start-Up

In flyback topology, the internal power dissipation of the device can be decreased by supplying the VCC using an

additional transformer winding. In this configuration, the external VCC supply voltage must be greater than the

VCC regulation target (V_VCC-REG), and the BIAS pin voltage must be greater the VCC voltage because the VCC

regulator includes a diode between VCC and BIAS.

V_SUPPLY

BIAS

GATE

VCC

UVLO/SYNC

GND

DITHOFF

PGOOD

SS COMP

图9-7. External VCC Supply (BIAS ≥VCC)

If the voltage of the external VCC bias supply is greater than the BIAS pin voltage, use an external blocking

diode from the input power supply to the BIAS pin to prevent the external bias supply from passing current to the

boost input supply through VCC.

9.3.3 Soft Start (SS Pin)

The soft-start feature helps the converter gradually reach the steady state operating point, thus reducing start-up

stresses and surges. The device regulates the FB pin to the SS pin voltage or the internal reference, whichever

is lower.

At start-up, the internal 10-μA soft-start current source (I_SS) turns on 50 µs after the VCC voltage exceeds the

2.85-VCC UV threshold, or if the VCC voltage is greater than 4.5 V, whichever comes first. The soft-start current

gradually increases the voltage on an external soft-start capacitor connected to the SS pin. This results in a

gradual rise of the output voltage. The SS pin is pulled down to ground by an internal switch when the VCC is

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less than VCC UVLO threshold, the UVLO is less than the UVLO threshold, during hiccup mode off-time or

thermal shutdown.

In boost topology, soft-start time (t_SS) varies with the input supply voltage. The soft-start time in boost topology is

calculated as shown in 方程式3.

≈

’

◊

C_SS

V_SUPPLY

t_SS

ì 1-

∆

I_SS

V_LOAD

(3)

In SEPIC topology, the soft-start time (t_SS) is calculated as follows.

C_SS

t_SS

I_SS

(4)

TI recommends choosing soft-start time long enough so that the converter can start up without going into an

overcurrent state. See 节9.3.11 for more detailed information.

图9-8 shows an implementation of primary side soft start in flyback topology.

COMP

FB SS

图9-8. Primary-Side Soft Start in Flyback

图9-9 shows an implementation of secondary side soft start in flyback topology.

V_LOAD

Secondary Side

Soft-start

图9-9. Secondary-Side Soft Start in Flyback

9.3.4 Switching Frequency (RT Pin)

The switching frequency of the device can be set by a single RT resistor connected between the RT and the

GND pins. The resistor value to set the RT switching frequency (f_RT) is calculated as shown in 方程式5.

2.21ì10¹⁰

f_RT(TYPICAL)

R_T=

- 955

(5)

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The RT pin is regulated to 0.5 V by the internal RT regulator when the device is enabled.

9.3.5 Dual Random Spread Spectrum (DRSS)

The device provides a digital spread spectrum which reduces the EMI of the power supply over a wide frequency

range. This function is dynamically selectable during operation. The internal modulator dithers the internal clock

when the DITHOFF pin is less than 1.0 V or the pin is grounded, and it stops clock dithering when the DITHOFF

pin is greater than 2.0 V or the pin is connected to VCC. When an external synchronization clock is applied to

the SYNC pin, the internal spread spectrum is disabled. DRSS (a) combines a low-frequency triangular

modulation profile (b) with a high frequency cycle-by-cycle random modulation profile (c). The low frequency

triangular modulation improves performance in lower radio frequency bands (for example, the AM band), while

the high frequency random modulation improves performance in higher radio frequency bands (for example, the

FM band). In addition, the frequency of the triangular modulation is further modulated randomly to reduce the

likelihood of any audible tones. To minimize output voltage ripple caused by spread spectrum, duty cycle is

modified on a cycle-by-cycle basis to maintain a nearly constant duty cycle when dithering is enabled (see 图

9-10).

Frequency

0.156 x f_SW

(a) Low + High Frequency

Random Modulation

f_SW

(b) Low Frequency

Random Modulation

DITHER ON

(DITHOFF=GND)

DITHER OFF

(DITHOFF=VCC)

图9-10. Dual Random Spread Spectrum

9.3.6 Clock Synchronization (UVLO/SYNC/EN Pin)

The switching frequency of the device can be synchronized to an external clock by pulling down the UVLO/

SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input

during the forced off-time which is determined by the maximum duty cycle limit. The external synchronization

clock must pull down the UVLO/SYNC pin voltage below 1.45 V (typical). The duty cycle of the pulldown pulse is

not limited, but the minimum pulldown pulse width must be greater than 150 ns, and the minimum pullup pulse

width must be greater than 250 ns. 图 9-11 shows an implementation of the remote shutdown function. The

UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In this configuration,

the device stops switching immediately after the UVLO pin is grounded, and the device shuts down 35 µs

(typical) after the UVLO pin is grounded.

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V_SUPPLY

MCU

UVLO/SYNC

SHUTDOWN

图9-11. UVLO and Shutdown

图 9-12 shows an implementation of shutdown and clock synchronization functions together. In this

configuration, the device stops switching immediately when the UVLO pin is grounded, and the device shuts

down if f_SYNCstays in high logic state for longer than 35 µs (typical) (UVLO is in low logic state for more than 35

µs (typical)). The device runs at the f_SYNCif clock pulses are provided after the device is enabled.

V_SUPPLY

MCU

UVLO/SYNC

F_SYNC

图9-12. UVLO, Shutdown, and Clock Synchronization

图 9-14 and 图 9-15 show implementations of standby and clock synchronization functions together. In this

configuration, the device stops switching immediately if f_SYNCstays in high logic state and enters standby mode

if f_SYNCstays in high logic state for longer than two switching cycles. The device runs at f_SYNCif clock pulses are

provided. Since the device can be enabled when the UVLO pin voltage is greater than the enable threshold for

more than 1.5 µs, the configurations in 图 9-14 and 图 9-15 are recommended if the external clock

synchronization pulses are provided from the start before the device is enabled. This 1.5-µs requirement can be

relaxed when the duty cycle of the synchronization pulse is greater than 50%. 图 9-13 shows the required

minimum duty cycle to start up by synchronization pulses. When the switching frequency is greater than 1.1

MHz, the UVLO pin voltage should be greater than the enable threshold for more than 1.5 µs before applying the

external synchronization pulse.

100 200 300 400 500 600 700 800 900 1000 1100

f_SW[kHz]

SUby

图9-13. Required Duty Cycle to Start Up by SYNC

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V_SUPPLY

MCU

UVLO/SYNC

>0.7V

F_SYNC

图9-14. UVLO, Standby, and Clock Synchronization (a)

V_SUPPLY

UVLO/SYNC

MCU

F_SYNC

图9-15. UVLO, Standby, and Clock Synchronization (b)

If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented

together by using one push-pull output of the MCU. In this configuration, the device shuts down if f_SYNCstays in

low logic state for longer than 35 µs (typical). The device is enabled if f_SYNCstays in high logic state for longer

than 1.5 µs. The device runs at the f_SYNCif clock pulses are provided after the device is enabled. Also, in this

configuration, it is recommended to apply the external clock pulses after the BIAS is supplied. By limiting the

current flowing into the UVLO pin below 1 mA using a current limiting resistor, the external clock pulses can be

supplied before the BIAS is supplied (see 图9-16).

MCU

10 ꢀ

UVLO/SYNC

F_SYNC

图9-16. Shutdown and Clock Synchronization

图9-17 shows an implementation of inverted enable using external circuit.

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V_SUPPLY

UVLO/SYNC

LMV431

图9-17. Inverted UVLO

The external clock frequency (f_SYNC) must be within +25% and –30% of f_RT(TYPICAL). Because the maximum

duty cycle limit and the peak current limit with slope resistor (R_SL) are affected by the clock synchronization, take

extra care when using the clock synchronization function. See 节 9.3.7, 节 9.3.8, and 节 9.3.12 for more

information.

9.3.7 Current Sense and Slope Compensation (CS Pin)

The device has a low-side current sense and provides both fixed and optional programmable slope

compensation ramps, which help prevent subharmonic oscillation at high duty cycle. Both fixed and

programmable slope compensation ramps are added to the sensed inductor current input for the PWM

operation, but only the programmable slope compensation ramp is added to the sensed inductor current input

(see 图 9-18). For an accurate peak current limit operation over the input supply voltage, TI recommends using

only the fixed slope compensation (see 图8-5).

The device can generate the programmable slope compensation ramp using an external slope resistor (R_SL) and

a sawtooth current source with a slope of 30 μA × f_RT. This current flows out of the CS pin.

Current Limit

Comparator

I_SLOPE

V_CSTH

R_SL

(optional)

R_F

(optional)

V_CS1

R_S

V_CS2

_COMP=0.142

C_F

(optional)

_SLOPE+ offset

PWM

Comparator

COMP

R_COMP

C_HF

(optional)

C_COMP

图9-18. Current Sensing and Slope Compensation

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Programmable Slope

Compensation Ramp

I_SLOPE× R_SL× D

Fixed Slope

Compensation

Ramp

Programmable Slope

Compensation Ramp

V_SLOPE× D + 0.17V

I_SLOPE× R_SL× D

Sensed Inductor

Current (R_S× I_LM

Sensed Inductor

Current (R_S× I_LM

)

图9-19. Slope Compensation Ramp (a) at PWM

图9-20. Slope Compensation Ramp (b) at Current

Comparator Input

Limit Comparator Input

Use 方程式 6 to calculate the value of the peak slope current (I_SLOPE) and use 方程式 7 to calculate the value of

the peak slope voltage (V_SLOPE).

f_RT

I_SLOPE= 30mA ì

f_SYNC

(6)

f_RT

V_SLOPE= 40mV ì

f_SYNC

(7)

where

• f_SYNC= f_RTif clock synchronization is not used.

According to peak current mode control theory, the slope of the compensation ramp must be greater than half of

the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the

minimum amount of slope compensation in boost topology should satisfy the following inequality:

+ V_F- V

(

)

L_M

LOAD

SUPPLY

0.5ì

ìR_SìMargin < 40mV ì f_SW

(8)

where

• V_Fis a forward voltage drop of D1, the external diode

The recommended margin to cover non-ideal factors is 1.2. If required, R_SLcan be added to further increase the

slope of the compensation ramp. Typically 82% of the sensed inductor current falling slope is known as an

optimal amount of the slope compensation. The R_SLvalue to achieve 82% of the sensed inductor current falling

slope is calculated as shown in 方程式9.

_LOAD+ V_F- V

(

)

L_M

SUPPLY

0.82ì

ìR = 30uA ìR + 40mV ì f

(

)

(9)

If clock synchronization is not used, the f_SWfrequency equals the f_RTfrequency. If clock synchronization is used,

the f_SWfrequency equals the f_SYNCfrequency. The maximum value for the R_SLresistance is 2 kΩ.

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9.3.8 Current Limit and Minimum On-time (CS Pin)

The device provides cycle-by-cycle peak current limit protection that turns off the MOSFET when the sum of the

inductor current and the programmable slope compensation ramp reaches the current limit threshold (V_CLTH).

Peak inductor current limit (I_PEAK-CL) in steady state is calculated as shown in 方程式10.

f_RT

V_CLTH- 30mA ìR_SL

ìD

f_SYNC

I_PEAK-CL

R_S

(10)

The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense

resistor. The estimated duty cycle is calculated as shown in 方程式11.

V_SUPPLY

D = 1-

V_LOAD+ V_F

(11)

Boost converters have a natural pass-through path from the supply to the load through the high-side power

diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot

provide current limit protection when the output voltage is close to or less than the input supply voltage. The

minimum on-time is shown in 图8-12 and is calculated as 方程式12.

800ì10^-15

t_ON(MIN)

+ 4ì10^-6

8ìR_T

(12)

If required, a small external RC filter (R_F, C_F) at the CS pin can be added to overcome the large leading edge

spike of the current sense signal. Select an R_Fvalue in the range of 10 Ωto 200 Ωand a C_Fvalue in the range

of 100 pF to 2 nF. Because of the effect of this RC filter, the peak current limit is not valid when the on-time is

less than 2 × R_F× C_F. To fully discharge the C_Fduring the off-time, the RC time constant should satisfy the

following inequality.

1-D

f_SW

3ìR_FìC_F<

(13)

9.3.9 Feedback and Error Amplifier (FB, COMP Pin)

The feedback resistor divider is connected to an internal transconductance error amplifier which features high

output resistance (R_O= 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error

amplifier sources current, which is proportional to the difference between the FB pin and the SS pin voltage or

the internal reference, whichever is lower. The internal transconductance error amplifier provides symmetrical

sourcing and sinking capability during normal operation and reduces its sinking capability when the FB is greater

than OVP threshold.

To set the output regulation target, select the feedback resistor values as shown in 方程式14.

≈

∆

’

R_FBT

R_FBB

V_LOAD= V_REF

◊

(14)

The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation

network. R_COMP, C_COMP, and optional C_HFloop compensation components configure the error amplifier gain and

phase characteristics to achieve a stable loop response. The absolute maximum voltage rating of the FB pin is

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3.8 V. If necessary, especially during automotive load dump transient, the feedback resistor divider input can be

clamped with an external zener diode.

The COMP pin features internal clamps. The maximum COMP clamp limits the maximum COMP pin voltage

below its absolute maximum rating even in shutdown. The minimum COMP clamp limits the minimum COMP pin

voltage in order to start switching as soon as possible during no load to heavy load transition. The minimum

COMP clamp is disabled when FB is connected to ground in flyback topology.

9.3.10 Power-Good Indicator (PGOOD pin)

The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches

to a high impedance open-drain state when the FB pin voltage is greater than the feedback under voltage

threshold (V_UVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than the EN

threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The

recommended minimum pullup resistor value is 10 kΩ.

Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater

than V_BIAS+ 0.3 V.

9.3.11 Hiccup Mode Overload Protection (LM51561 Only)

To further protect the converter during prolonged current limit conditions, the LM51561 device option provides a

hiccup mode overload protection. The internal hiccup mode fault timer of the device counts the PWM clock

cycles when the cycle-by-cycle current limiting occurs after soft start is finished. When the hiccup mode fault

timer detects 64 cycles of current limiting, an internal hiccup mode off-timer forces the device to stop switching

and pulls down SS. Then, the device will restart after 32 768 cycles of hiccup mode off-time. The 64-cycle hiccup

mode fault timer is reset if eight consecutive switching cycles occur without exceeding the current limit threshold.

The soft-start time must be long enough not to trigger the hiccup mode protection after the soft start is finished.

4 cycles of

current limit

7 normal

switching

cycles

32768 hiccup

mode off cycles

64 cycles of

current limit

60 cycles of

current limit

32768 hiccup

mode off cycles

Inductor Current

Time

图9-21. Hiccup Mode Overload Protection

To avoid an unexpected hiccup mode operation during a harsh load transient condition, it is recommended to

have more margin when programming the peak-current limit.

9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage

When designing boost converters, the maximum duty cycle should be reviewed at the minimum supply voltage.

The minimum input supply voltage that can achieve the target output voltage is limited by the maximum duty

cycle limit, and it can be estimated as follows.

V_SUPPLY(MIN)ö V

+ V ì 1-D

_F) (

+I_SUPPLY(MAX)ìR_DCR+I_SUPPLY(MAX)ì R_DS(ON)+R_SìD

(

)

(

)

LOAD

MAX

(15)

where

• I_SUPPLY(MAX)is the maximum input current

• R_DCRis the DC resistance of the inductor

• R_DS(ON)is the on-resistance of the MOSFET

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f_SYNC

D_MAX1= 1- 0.1ì

f_RT

(16)

(17)

D_MAX2= 1-100nsì f_SW

The minimum input supply voltage can be further decreased by supplying f_SYNC, which is less than f_RT. D_MAXis

D_MAX1or D_MAX2, whichever is lower.

9.3.13 MOSFET Driver (GATE Pin)

The device provides an N-channel MOSFET driver that can source or sink a peak current of 1.5 A. The peak

sourcing current is larger when supplying an external VCC that is higher than 6.75 V VCC regulation target.

During start-up, especially when the input voltage range is below the VCC regulation target, the VCC voltage

must be sufficient to completely enhance the MOSFET. If the MOSFET drive voltage is lower than the MOSFET

gate plateau voltage during start-up, the boost converter may not start up properly and it can stick at the

maximum duty cycle in a high power dissipation state. This condition can be avoided by selecting a lower

threshold N-channel MOSFET switch and setting the V_SUPPLY(ON)greater than 6 to 7 V. Because the internal

VCC regulator has a limited sourcing capability, the MOSFET gate charge should satisfy the following inequality.

Q_G@VCCì f_SW< 35mA

(18)

An internal 1-MΩ resistor is connected between GATE and GND to prevent a false turnon during shutdown. In

boost topology, switch node dV/dT must be limited during the 65-µs internal start-up delay to avoid a false

turnon, which is caused by the coupling through C_DGparasitic capacitance of the MOSFET.

9.3.14 Overvoltage Protection (OVP)

The device has OVP for the output voltage. OVP is sensed at the FB pin. If the voltage at the FB pin rises above

the overvoltage threshold (V_OVTH), OVP is triggered and switching stops. During OVP, the internal error amplifier

is operational, but the maximum source and sink capability is decreased to 40 µA.

9.3.15 Thermal Shutdown (TSD)

An internal thermal shutdown turns off the VCC regulator, disables switching, and pulls down the SS when the

junction temperature exceeds the thermal shutdown threshold (T_TSD). After the temperature is decreased by

15°C, the VCC regulator is enabled again and the device performs a soft start.

9.4 Device Functional Modes

9.4.1 Shutdown Mode

If the UVLO pin voltage is below the enable threshold for longer than 35 µs (typical), the device goes to the

shutdown mode with all functions disabled. In shutdown mode, the device decreases the BIAS pin current

consumption to below 2.6 μA (typical)

9.4.2 Standby Mode

If the UVLO pin voltage is greater than the enable threshold and below the UVLO threshold for longer than 1.5

µs, the device is in standby mode with the VCC regulator operational, RT regulator operational, SS pin

grounded, and no switching at the GATE output. The PGOOD is activated when the VCC voltage is greater than

the VCC UV threshold.

9.4.3 Run Mode

If the UVLO pin voltage is above the UVLO threshold and the VCC voltage is sufficient, the device enters RUN

mode. In this mode, soft start starts 50 µs after the VCC voltage exceeds the 2.85 VCC UV threshold, or if the

VCC voltage is greater than 4.5 V, whichever comes first.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

How to Design a Boost Converter Using LM5156x explains how to design boost, SEPIC, and Flyback converters

using the device. This comprehensive application note includes component selections and loop response

optimization.

10.2 Typical Application

图10-1 shows all optional components to design a boost converter.

R_SNBC_SNB

V_SUPPLY

L_M

V_LOAD

R_BIAS

D_G

R_G

C_BIAS

C_OUT1C_OUT2

R_LOAD

C_VCC

C_IN

R_UVLOT

R_FBT

BIAS

GATE

VCC

R_UVLOS

UVLO/SYNC

R_F

R_SL

R_FBB

R_S

R_UVLOB

C_UVLO

C_F

GND

DITHOFF

PGOOD

MCU_VCC

R_PG

SS COMP

R_COMP

C_COMP

R_T

C_SS

C_HF

图10-1. Typical Boost Converter Circuit With Optional Components

10.2.1 Design Requirements

表10-1 shows the intended input, output, and performance parameters for this application example.

表10-1. Design Example Parameters

DESIGN PARAMETER

VALUE

Minimum input supply voltage (V_SUPPLY(MIN)

)

6 V

Target output voltage (V_LOAD

Maximum load current (I_LOAD

Typical switching frequency (f_SW

)

24 V

)

2 A (≈48 Watt)

440 kHz

)

10.2.2 Detailed Design Procedure

Use the LM5155x / LM5156x Boost Quick Start Calculator to expedite the process of designing of a regulator for

a given application based on the LM5156x device.

The LM5156x device is also WEBENCH® Designer enabled. The WEBENCH software uses an iterative design

procedure and accesses comprehensive data bases of components when generating a design.

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10.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5156x device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2.2.2 Recommended Components

表10-2 shows a recommended list of materials for this typical application.

表10-2. List of Materials⁽¹⁾

REFERENCE

DESIGNATOR

QTY.

SPECIFICATION

MANUFACTURER

PART NUMBER

R_T

RES, 49.9 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 47.0 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 2.0 k, 5%, 0.1 W, AEC-Q200 Grade 0, 0603

Vishay-Dale

CRCW060349K9FKEA

CRCW060347K0FKEA

CRCW06032K00JNEA

R_FBT

R_FBB

Inductor, Shielded, Composite, 6.8 µH, 18.5 A, 0.01 Ω,

L_M

Coilcraft

XAL1010-682MEB

SMD

R_S

R_SL

RES, 0.008, 1%, 3 W, AEC-Q200 Grade 0, 2512 WIDE

RES, 0, 5%, 0.1 W, 0603

Susumu

Yageo America

TDK

KRL6432E-M-R008-F-T1

RC0603JR-070RL

C_OUT1

CAP, CERM, 4.7 µF, 50 V, ±10%, X7R, 1210

C3225X7R1H475K250AB

CAP, Aluminum Polymer, 100 µF, 50 V, ±20%, 0.025 Ω,

C_OUT2(Bulk)

C_IN1

Chemi-Con

MuRata

HHXB500ARA101MJA0G

GRM32ER71H106KA12L

EEHZC1H101P

AEC-Q200 Grade 2, D10xL10mm SMD

CAP, CERM, 10 µF, 50 V, ±10%, X7R, 1210

CAP, Polymer Hybrid, 100 µF, 50 V, ±20%, 28 Ω, 10x10

C_IN2(Bulk)

Panasonic

SMD

MOSFET, N-CH, 40 V, 50 A, AEC-Q101, SON-8

Schottky, 60 V, 10 A, AEC-Q101, CFP15

Infineon

Nexperia

IPC50N04S5L5R5ATMA1

PMEG060V100EPDZ

CRCW060311K3FKEA

R_COMP

RES, 11.3 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

Vishay-Dale

CAP, CERM, 0.022 µF, 100 V, ±10%, X7R, AEC-Q200

Grade 1, 0603

C_COMP

C_HF

TDK

CGA3E2X7R2A223K080AA

CGA3E2C0G1H221J080AA

CAP, CERM, 220 pF, 20 V, ±5%, C0G/NP0, AEC-Q200

Grade 1, 0603

R_UVLOT

R_UVLOB

R_UVLOS

RES, 21.0 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 7.32 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

N/A

Vishay-Dale

N/A

CRCW060321K0FKEA

CRCW06037K32FKEA

N/A

CAP, CERM, 0.22 µF, 50 V, ±10%, X7R, AEC-Q200

Grade 1, 0603

C_SS

TDK

CGA3E3X7R1H224K080AB

D_G

R_G

C_F

R_F

N/A

RES, 0, 5%, 0.1 W, 0603

Yageo America

Kemet

RC0603JR-070RL

C0603C101F5GACTU

RC0603FR-07100RL

CAP, CERM, 100 pF, 50 V, ±1%, C0G/NP0, 0603

RES, 100, 1%, 0.1 W, 0603

Yageo America

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表10-2. List of Materials⁽¹⁾(continued)

REFERENCE

QTY.

SPECIFICATION

MANUFACTURER

PART NUMBER

DESIGNATOR

R_SNB

C_SNB

R_BIAS

N/A

RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0603

Panasonic

ERJ-3GEY0R00V

Samsung Electro-

Mechanics

C_BIAS

CAP, CERM, 0.01 µF, 50 V, ±10%, X7R, 0603

CL10B103KB8NCNC

CAP, CERM, 1 µF, 16 V, ±20%, X7R, AEC-Q200 Grade

1, 0603

C_VCC

R_PG

MuRata

GCM188R71C105MA64D

RC0603FR-0724K9L

RES, 24.9 k, 1%, 0.1 W, 0603

Yageo America

(1) See Third-party Products Disclaimer

10.2.2.3 Inductor Selection (L_M)

When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the

inductor current, and RHP zero frequency (f_RHP).

Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope of

the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle (additional R_SL

resistor is required if not). Higher f_RHP(= lower inductance) allows a higher crossover frequency and is always

preferred when using a small value output capacitor.

The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average

inductor current as a good compromise between RR, F_RHP, and inductor falling slope.

10.2.2.4 Output Capacitor (C_OUT

)

There are a few ways to select the proper value of output capacitor (C_OUT). The output capacitor value can be

selected based on output voltage ripple, output overshoot, or undershoot due to load transient.

The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using

multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the

diode and the MOSFET than the bulk aluminum capacitors to absorb the majority of the ripple current.

10.2.2.5 Input Capacitor

The input capacitors decrease the input voltage ripple. The required input capacitor value is a function of the

impedance of the source power supply. More input capacitors are required if the impedance of the source power

supply is not low enough.

10.2.2.6 MOSFET Selection

The MOSFET gate driver of the device is sourced from VCC. The maximum gate charge is limited by the 35-mA

VCC sourcing current limit.

A leadless package is preferred for high switching-frequency designs. The MOSFET gate capacitance should be

small enough so that the gate voltage is fully discharged during the off-time.

10.2.2.7 Diode Selection

A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery

charge. Low reverse leakage current is an important parameter when selecting the Schottky diode. The diode

must be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to

handle the average output current.

10.2.2.8 Efficiency Estimation

The total loss of the boost converter (P_TOTAL) can be expressed as the sum of the losses in the device (P_IC),

MOSFET power losses (P_Q), diode power losses (P_D), inductor power losses (P_L), and the loss in the sense

resistor (P_RS).

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P_TOTAL= P +P_Q+P_D+P +P_RS

(19)

P_ICcan be separated into gate driving loss (P_G) and the losses caused by quiescent current (P_IQ).

= P_G+ P

(20)

Each power loss is approximately calculated as follows:

P_G= Q_G(@VCC)ì V_BIASì f_SW

(21)

(22)

= V_BIASìI_BIAS

I_VINand I_VOUTvalues in each mode can be found in the supply current section of 节8.5.

P_Qcan be separated into switching loss (P_Q(SW)) and conduction loss (P_Q(COND)).

P_Q= P_Q(SW)+ P_Q(COND)

(23)

(24)

Each power loss is approximately calculated as follows:

P_Q(SW)= 0.5ì(V_LOAD+ V_F)ìI_SUPPLYì(t_R+ t_F)ì f_SW

t_Rand t_Fare the rise and fall times of the low-side N-channel MOSFET device. I_SUPPLYis the input supply current

of the boost converter.

P_Q(COND)= DìI_SUPPLY²ìR_DS(ON)

(25)

R_DS(ON)is the on-resistance of the MOSFET and is specified in the MOSFET data sheet. Consider the R_DS(ON)

increase due to self-heating.

P_Dcan be separated into diode conduction loss (P_VF) and reverse recovery loss (P_RR).

P_D= P_VF+ P_RR

(26)

Each power loss is approximately calculated as follows:

P_VF= (1-D)ì V_FìI_SUPPLY

(27)

P_RR= V_LOADìQ_RRì f_SW

(28)

Q_RRis the reverse recovery charge of the diode and is specified in the diode data sheet. Reverse recovery

characteristics of the diode strongly affect efficiency, especially when the output voltage is high.

P_Lis the sum of DCR loss (P_DCR) and AC core loss (P_AC). DCR is the DC resistance of inductor which is

mentioned in the inductor data sheet.

P = P_DCR+ P_AC

(29)

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Each power loss is approximately calculated as follows:

P_DCR= I_SUPPLY²ìR_DCR

(30)

(31)

P_AC= K ì DI^bì f_SW

V_SUPPLYìDì

f_SW

DI =

L_M

(32)

∆I is the peak-to-peak inductor current ripple. K, α, and βare core dependent factors which can be provided by

the inductor manufacturer.

P_RSis calculated as follows:

P_RS= DìI_SUPPLY²ìR_S

(33)

Efficiency of the power converter can be estimated as follows:

V_LOADìI_LOAD

Efficiency =

P_TOTAL+ V_LOADìI_LOAD

(34)

10.2.3 Application Curve

V_SUPPLY=18V

V_SUPPLY=12V

V_SUPPLY=9V

V_SUPPLY=6V

0.2 0.4 0.6 0.8

I_LOAD[A]

1.2 1.4 1.6 1.8

BSTE

图10-2. Efficiency

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10.3 System Examples

V_SUPPLY

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

GND

DITHOFF

PGOOD

SS COMP

图10-3. Typical Boost Application

V_SUPPLY= 3.5V - 60V

V_LOAD

Car

Battery

BIAS

GATE

VCC

To MCU

From MCU

PGOOD

GND

UVLO/SYNC

DITHOFF

SS COMP

图10-4. Typical Start-Stop Application

V_SUPPLY= 2.97V - 16V

= 12V / 24V

V_LOAD

1-cell or

2-cell

Battery

BIAS

GATE

VCC

PGOOD

From MCU

GND

UVLO/SYNC

DITHOFF

SS COMP

图10-5. Emergency-call / Boost On-Demand / Portable Speaker

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V_SUPPLY

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

GND

DITHOFF

PGOOD

SS COMP

图10-6. Typical SEPIC Application

Inductance should be small enough

to operate in DCM at full load

V_SUPPLY

= 30V-150V

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

From MCU

GND

DITHOFF

PGOOD

SS COMP

图10-7. LIDAR Bias Supply 1

> 150V-200V

V_LOAD

Voltage

Tripler

Inductance should be big enough

to operate in CCM

V_SUPPLY

BIAS

GATE

VCC

UVLO/SYNC

GND

DITHOFF

PGOOD

SS COMP

图10-8. LIDAR Bias Supply 2

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V_SUPPLY

V_LOAD

BIAS

GATE

VCC

UVLO/SYNC

To MCU

(Fault Indicator)

System Power

GND

DITHOFF

PGOOD

SS COMP

图10-9. Low-Cost LED Driver

V_SUPPLY

_LOAD= 5V/12V

BIAS

GATE

UVLO/SYNC

GND

VCC

DITHOFF

PGOOD

COMP

Optional Primary-Side

Soft-Start

图10-10. Secondary-Side Regulated Isolated Flyback

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V_LOAD2= +12V

V_SUPPLY

V_LOAD3= -8.5V

BIAS

GATE

UVLO/SYNC

GND

VCC

DITHOFF

To MCU

System Power

PGOOD

COMP

V_LOAD1= 3.3V/5V +/- 2%

图10-11. Primary-Side Regulated Multiple-Output Isolated Flyback

V_SUPPLY

V_LOAD

BIAS

GATE

UVLO/SYNC

GND

VCC

DITHOFF

To MCU

System Power

PGOOD

COMP

图10-12. Typical Non-Isolated Flyback

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I_LED

V_SUPPLY

BIAS

GATE

VCC

UVLO/SYNC

GND

DITHOFF

PGOOD

SS COMP

图10-13. LED Driver with High-Side Current Sensing

BIAS

GATE

VCC

UVLO/SYNC

GND

To MCU

(Fault Indicator)

System Power

DITHOFF

PGOOD

SS COMP

TAIL

BRAKE

TURN

BACKUP

TPS9261x

图10-14. Dual-Stage Automotive Rear-Lights LED Driver

11 Power Supply Recommendations

The device is designed to operate from a power supply or a battery whose voltage range is from 1.5 V to 60 V.

The input power supply must be able to supply the maximum boost supply voltage and handle the maximum

input current at 1.5 V. The impedance of the power supply and battery including cables must be low enough that

an input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required

at the supply input of the converter.

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12 Layout

12.1 Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. The following

guidelines will help users design a PCB with the best power conversion performance, thermal performance, and

minimize generation of unwanted EMI.

• Put the Q1, D1, and R_Scomponents on the board first.

• Use a small size ceramic capacitor for C_OUT

• Make the switching loop (C_OUTto D1 to Q1 to R_Sto C_OUT) as small as possible.

• Leave a copper area near the D1 diode for thermal dissipation.

• Put the device near the R_Sresistor.

• Put the C_VCCcapacitor as near the device as possible between the VCC and GND pins.

• Use a wide and short trace to connect the GND pin directly to the center of the sense resistor.

• Connect the CS pin to the center of the sense resistor. If necessary, use vias.

• Connect a filter capacitor between CS pin and power ground trace.

• Connect the COMP pin to the compensation components (R_COMPand C_COMP).

• Connect the C_COMPcapacitor to the power ground trace.

• Connect the GND pin directly to the analog ground plane. Connect the GND pin to the R_UVLOB, R_T, C_SS, and

R_FBBcomponents.

• Connect the exposed pad to the GND pin under the device.

• Connect the GATE pin to the gate of the Q1 FET. If necessary, use vias.

• Make the switching signal loop (GATE to Q1 to R_Sto GND to GATE) as small as possible.

• Add several vias under the exposed pad to help conduct heat away from the device. Connect the vias to a

large ground plane on the bottom layer.

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12.2 Layout Examples

V_SUPPLY

GND

L_M

C_VIN

Connect

to V_SUPPLY

Do not connect input and

output capacitor grounds

underneath the device

C_VIN

Connect

to V_SUPPLY

R_UVLOB

BIAS

UVLO

11 PGOOD

VCC

R_S

GATE

C_VCC

R_T

C_SS

GND

C_F

R_FBB

R_F

DITHOFF

COMP

C_COMP

R_COMP

Connect

to V_LOAD

R_FBT

Do not connect input and

output capacitor grounds

underneath the device

C_OUT1

C_OUT2

Thermal Dissipation

Area

V_LOAD

GND

图12-1. PCB Layout Example 1

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L_M

V_SUPPLY

C_VIN

GND

V_LOAD

Connect

to V_SUPPLY

Do not connect input and

output capacitor grounds

underneath the device

Connect

to V_SUPPLY

R_UVLOB

BIAS

UVLO

R_S

11 PGOOD

VCC

GND

GATE

C_VCC

R_T

C_OUT1

C_SS

GND

C_OUT2

C_F

R_FBB

Power Ground Plane

(Connect to EP via GND pin)

COMP

DITHOFF

R_COMP

Connect

to V_LOAD

R_FBT

R_F

Do not connect input and

output capacitor grounds

underneath the device

图12-2. PCB Layout Example 2

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13 Device and Documentation Support

13.1 Device Support

13.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

13.1.2 Development Support

For development support see the following:

• LM5155x / LM5156x Boost Quick Start Calculator

• LM5155x / LM5156x SEPIC Quick Start Calculator

• LM5155x / LM5156x Flyback Quick Start Calculator

13.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5156x device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, LM5156EVM-BST User's Guide

13.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

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13.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

13.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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27-Aug-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM51561DSSR

LM5156DSSR

ACTIVE

WSON

DSS

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

2GAH

2FUH

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Aug-2021

OTHER QUALIFIED VERSIONS OF LM5156, LM51561 :

Automotive : LM5156-Q1, LM51561-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Feb-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM51561DSSR

LM5156DSSR

WSON

DSS

3000

180.0

8.4

2.25

3.25

1.05

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Feb-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM51561DSSR

LM5156DSSR

WSON

DSS

3000

210.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DSS0012B

WSON - 0.8 mm max height

SCALE 4.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

0.35

0.25

PIN 1 INDEX AREA

0.3

0.2

3.1

2.9

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

SEATING PLANE

0.08 C

0.1

(0.2) TYP

SYMM

0.05

0.00

EXPOSED

THERMAL PAD

SEE TERMINAL

DETAIL

SYMM

2.5

2.65 0.1

10X 0.5

0.3

12X

0.2

0.1

0.05

0.35

0.25

12X

PIN 1 ID

(OPTIONAL)

C A B

4218908/A 01/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSS0012B

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1)

12X (0.5)

SYMM

12X (0.25)

SYMM

(2.65)

10X (0.5)

(R0.05) TYP

(1.075)

(

0.2) VIA

TYP

(1.9)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:25X

0.05 MIN

ALL AROUND

EXPOSDE METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218908/A 01/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSS0012B

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

EXPOSED METAL

TYP

12X (0.5)

SYMM

12X (0.25)

(0.685)

SYMM

10X (0.5)

2X (1.17)

(R0.05) TYP

2X (0.95)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 13:

83% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218908/A 01/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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