LM5157QRTERQ1 [TI]
LM5157x-Q1 2.2-MHz Wide VIN 50-V Boost/SEPIC/Flyback Converter with Dual Random Spread Spectrum;
| 型号： | LM5157QRTERQ1 |
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TEXAS INSTRUMENTS |
| 描述： | LM5157x-Q1 2.2-MHz Wide VIN 50-V Boost/SEPIC/Flyback Converter with Dual Random Spread Spectrum |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5157-Q1, LM51571-Q1
SNVSBK8 – OCTOBER 2020
LM5157x-Q1 2.2-MHz Wide VIN 50-V Boost/SEPIC/Flyback Converter with Dual
Random Spread Spectrum
1 Features
2 Applications
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +125°C TA
Suited for wide operating range for car battery
applications
– 2.9-V to 45-V input operating range
– 48-V maximum output (50-V abs max)
– Minimum boost supply voltage 1.5 V when
BIAS ≥ 2.9 V
•
Battery-powered wide input boost, SEPIC, flyback
converter
Automotive voltage stabilizer in SEPIC
Automotive start-stop application
Automotive emergency call application/backup
battery booster
High voltage LiDAR power supply
Automotive LED bias supply
Multiple-output flyback without optocoupler
Hold-up capacitor charger
•
•
•
•
•
•
•
•
•
•
– Input transient protection up to 50 V
– Minimized battery drain
•
•
Low shutdown current (IQ ≤ 2.6 µA)
Low operating current (IQ ≤ 670 µA)
Audio amplifier power supply
Piezo driver/motor driver bias supply
•
Small solution size and low cost
– Maximum switching frequency up to 2.2 MHz
– 16-pin QFN package (3 mm × 3 mm) with
wettable flanks
– Integrated error amplifier allows primary-side
regulation without optocoupler (flyback)
– Minimized undershoot during cranking (start-
stop application)
3 Description
The LM5157x-Q1 (LM5157-Q1 and LM51571-Q1)
device is a wide input range, non-synchronous boost
converter with integrated 50-V power switch.
The device can be used in boost, SEPIC, and flyback
topologies. The device can start up from a 1-cell
battery with a minimum of 2.9 V. It can operate with
the input supply voltage as low as 1.5 V if the BIAS
pin is greater than 2.9 V.
– Accurate current limit (see the Device
Comparison Table)
•
•
•
EMI mitigation
– Selectable dual random spread spectrum
– Lead-less package
Higher efficiency with low-power dissipation
– 45-mΩ RDSON switch
– Fast switching, small switching loss
Avoid AM band interference and crosstalk
– Optional clock synchronization
– Dynamically programmable wide switching
frequency from 100 kHz to 2.2 MHz
Integrated protection features
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LM5157x-Q1
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VLOAD
VSUPPLY
BIAS VCC
SW
UVLO
RT
FB
COMP
•
SS
PGOOD
PGND AGND MODE
– Constant current limiting over input voltage
– Selectable hiccup mode overload protection
– Programmable line UVLO
Typical SEPIC Application
– OVP protection
– Thermal shutdown
•
•
•
•
Accurate ±1% accuracy feedback reference
Adjustable soft start
PGOOD indicator
Create a custom design using the LM5157x-Q1
with the WEBENCH® Power Designer
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
LM5157-Q1, LM51571-Q1
SNVSBK8 – OCTOBER 2020
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 2
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings ....................................... 6
8.2 ESD Ratings .............................................................. 6
8.3 Recommended Operating Conditions ........................6
8.4 Thermal Information ...................................................7
8.5 Electrical Characteristics ............................................7
9 Detailed Description........................................................9
9.1 Overview.....................................................................9
9.2 Functional Block Diagram...........................................9
9.3 Feature Description...................................................10
9.4 Device Functional Modes..........................................21
10 Application and Implementation................................22
10.1 Application Information........................................... 22
10.2 Typical Application.................................................. 22
10.3 System Examples................................................... 25
11 Power Supply Recommendations..............................30
12 Layout...........................................................................31
12.1 Layout Guidelines................................................... 31
12.2 Layout Examples.................................................... 32
13 Device and Documentation Support..........................33
13.1 Device Support....................................................... 33
13.2 Receiving Notification of Documentation Updates..33
13.3 Support Resources................................................. 33
13.4 Trademarks.............................................................33
13.5 Electrostatic Discharge Caution..............................34
13.6 Glossary..................................................................34
14 Mechanical, Packaging, and Orderable
Information.................................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
October 2020
*
Initial release
5 Description (continued)
The BIAS pin operates up to 45-V (50-V absolute maximum) for automotive load dump. The switching frequency
is dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes
AM band interference and allows for a small solution size and fast transient response. To reduce the EMI of the
power supply, the device provides a selectable Dual Random Spread Spectrum which reduces the EMI over a
wide frequency range.
The device features an accurate peak current limit over the input voltage, which avoids overdesigning power
inductor. Low operating current and pulse-skipping operation improve efficiency at light loads.
The device has built-in protection features such as overvoltage protection, line UVLO, thermal shutdown, and
selectable hiccup mode overload protection. Additional features include low shutdown IQ, programmable soft
start, precision reference, power-good indicator, and external clock synchronization.
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6 Device Comparison Table
DEVICE OPTION
LM5157-Q1
MINIMUM PEAK CURRENT LIMIT
MAXIMUM SW VOLTAGE
6 A
4 A
48 V (50 V Abs Max)
LM51571-Q1
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7 Pin Configuration and Functions
16 15 14 13
PGND
1
2
3
4
12
11
SW
MODE
VCC
BIAS
EP
10 SS
9
FB
PGOOD
8
5
6
7
Figure 7-1. 16-Pin WQFN With Wettable Flanks RTE Package (Top View)
Table 7-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
1, 16
PGND
P
P
P
O
Power ground pin. Source connection of the internal N-channel power MOSFET
Output of the internal VCC regulator and supply voltage input of the internal MOSFET driver.
Connect a 1-µF ceramic bypass capacitor from this pin to PGND.
2
3
4
VCC
BIAS
Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.
Power-good indicator. An open-drain output that goes low if FB is below the under voltage threshold
(VUVTH). Connect a pullup resistor to the system voltage rail.
PGOOD
RT
Switching frequency setting pin. The switching frequency is programmed by a single resistor
between RT and AGND.
5
I
Enable pin. The converter shuts down when the pin is less than the enable threshold (VEN).
Undervoltage lockout programming pin. The converter start-up and shutdown levels can be
programmed by connecting this pin to the supply voltage through a voltage divider. If you are using a
programmable UVLO, connect the low-side UVLO resistor to AGND. This pin must not be left
floating. Connect to the BIAS pin if not used.
UVLO/
SYNC/EN
6
I
External synchronization clock input pin. The internal clock can be synchronized to an external clock
by applying a negative pulse signal into the pin.
7
8
AGND
COMP
G
O
Analog ground pin. Connect to the analog ground plane through a wide and short path.
Output of the internal transconductance error amplifier. Connect the loop compensation components
between this pin and AGND.
Inverting input of the error amplifier. Connect a voltage divider to set output voltage in boost, SEPIC,
or primary-side-regulated Flyback topologies. Connect the low-side feedback resistor as close to
AGND.
9
FB
SS
I
I
Soft-start time programming pin. An external capacitor and an internal current source set the ramp
rate of the internal error amplifier reference during soft start. Connect the ground connection of the
capacitor to AGND.
10
MODE = 0 V or connect to AGND during initial power up: Hiccup mode protection is disabled, Spread
Spectrum is disabled.
MODE = 370 mV or connect a 37.4-kΩ resistor between the pin and AGND during initial power up:
Hiccup mode protection is enabled, Spread Spectrum is enabled.
11
MODE
I
MODE = 620 mV or connect a 62.0-kΩ resistor between the pin and AGND during initial power up:
Hiccup mode protection is enabled, Spread Spectrum is disabled.
MODE > 1 V or connect a 100-kΩ resistor between the pin and AGND during initial power up: Hiccup
mode protection is disabled, Spread Spectrum is enabled.
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Table 7-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
SW
12, 13,
14
Switch pin. Drain connection of the internal N-channel power MOSFET
15
—
NC
—
—
No internal electrical contact. Optionally connect to PGND for improved thermal conductivity.
Exposed pad of the package. The exposed pad must be connected to AGND and the large ground
copper plane to decrease thermal resistance.
EP
(1) G = Ground, I = Input, O = Output, P = Power
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8 Specifications
8.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–5
MAX
UNIT
BIAS to AGND
UVLO to AGND
50
VBIAS + 0.3
3.8
SS, RT to AGND(2)
Input
V
FB to AGND
4.0
MODE to AGND
PGND to AGND
VCC to AGND
3.8
0.3
5.8(3)
PGOOD to AGND(4)
18
Output
COMP to AGND(5)
V
SW to AGND (DC)
50
SW to AGND (100ns transient)
(6)
Junction temperature, TJ
Storage temperature, Tstg
–40
150
150
°C
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) This pin is not specified to have an external voltage applied.
(3) Operating lifetime is de-rated when the pin voltage is greater than 5.5V
(4) The maximum current sink is limited to 1 mA when VPGOOD>VBIAS
.
(5) This pin has an internal max voltage clamp which can handle up to 1.6 mA.
(6) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
8.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
Electrostatic
discharge
V(ESD)
V
All pins
±500
±750
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
Corner pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 Recommended Operating Conditions
Over the recommended operating junction temperature range(1)
MIN
NOM
MAX
45
UNIT
V
VSUPPLY
VLOAD
VBIAS
VUVLO
VFB
Boost Converter Input (when BIAS ≥ 2.9V)
Boost Converter Output
BIAS Input(3)
1.5
VSUPPLY
48(2)
V
2.9
0
45
V
UVLO Input
45
V
FB Input
0
4.0
V
ISW
Switch Current
0
See note(4)
2200
2200
A
fSW
Typical Switching Frequency
Synchronization Pulse Frequency
100
100
kHz
kHz
fSYNC
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Over the recommended operating junction temperature range(1)
MIN
NOM
MAX
UNIT
TJ
Operating Junction Temperature(5)
–40
150
°C
(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2) Boost converter output can be up to 48V, but the SW pin voltage should be less than or equal to 50 V during transient.
(3) BIAS pin operating range is from 2.9 V to 45 V when VCC is supplied from the internal VCC regulator. When the VCC pin is directly
connected to the BIAS pin, the device requires minimum 2.85V at the BIAS pin to start up, and the BIAS pin operating range is from
2.75V to 5.5 V after starting up.
(4) Maximum switch currrent is limited by pre-programmed peak current limit (ILIM) , and is guaranteed when TJ < TTSD
(5) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
8.4 Thermal Information
LM5157x-Q1
THERMAL METRIC(1)
RTE(QFN)
16 PINS
45.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
45.3
20.0
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ΨJB
20.0
RθJC(bot)
6.9
(1) For more information about traditional and new thermal metrics, see the application report.
8.5 Electrical Characteristics
Typical values correspond to TJ = 25 °C. Minimum and maximum limits apply over TJ = -40 °C to 150 °C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISHUTDOWN(BIAS) BIAS shutdown current
IOPERATING(BIAS) BIAS operating current
VCC REGULATOR
VBIAS = 12 V, VUVLO = 0 V
2.6
5
uA
uA
VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF
RT = 220 kΩ
,
670
775
VVCC-REG
VCC regulation
VBIAS = 8 V, IVCC = 18 mA
VCC rising
4.66
2.75
4.9
2.8
0.1
5.14
2.85
V
V
V
VVCC-
VCC UVLO threshold
VCC UVLO hysteresis
UVLO(RISING)
VCC falling
ENABLE
VEN(RISING)
VEN(FALLING)
VEN(HYS)
Enable threshold
Enable threshold
Enable hysteresis
EN rising
EN falling
EN falling
0.4
0.54
0.49
0.7
V
V
V
0.33
0.63
0.055
UVLO/SYNC
VUVLO(RISING)
UVLO / SYNC threshold
UVLO rising
UVLO falling
1.425
1.370
1.5
1.45
0.05
5
1.575
1.520
V
V
VUVLO(FALLING) UVLO / SYNC threshold
VUVLO(HYS)
IUVLO
MODE, SPREAD SPECTRUM
FSW Modulation (Upper Limit)
UVLO / SYNC threshold hysteresis UVLO falling
V
UVLO hysteresis current
VUVLO = 1.6 V
4
6
uA
7.8
%
%
FSW Modulation (Lower Limit)
–7.8
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Typical values correspond to TJ = 25 °C. Minimum and maximum limits apply over TJ = -40 °C to 150 °C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SS
ISS
Soft-start current
9
10
50
11
uA
Ω
SS pull-down switch RDSON
PULSE WIDTH MODULATION
fsw1
Switching frequency
RT = 220 kΩ
85
388
100
440
2200
80
115
492
kHz
kHz
kHz
ns
fsw2
Switching frequency
Switching frequency
Minimum on-time
RT = 49.3 kΩ
RT = 9.09 kΩ
RT = 9.09 kΩ
RT = 9.09 kΩ
RT = 220 kΩ
fsw3
1980
2420
tON(MIN)
DMAX1
DMAX2
Maximum duty cycle limit
Maximum duty cycle limit
RT regulation voltage
80
90
85
90
96
%
93
%
0.5
V
CURRENT LIMIT, SLOPE COMPENSATION
ILIM
Internal MOSFET current limit
Internal MOSFET current limit
LM5157
6.5
7.5
5
8.5
A
A
LM51571
4.33
5.67
HICCUP MODE PROTECTION
Hiccup enable cycles
Hiccup timer reset cycles
ERROR AMPLIFIER
64
8
Cycles
Cycles
VREF
Gm
FB reference
0.99
1
2
1.01
V
mA/V
uA
V
Transconductance
COMP sourcing current
COMP clamp voltage
COMP clamp voltage
ΔVCOMP / ΔISW
VCOMP = 1.2 V
180
2.5
COMP rising (VUVLO = 2.0 V)
COMP falling
2.8
1
1.1
V
ACS
0.095
OVP
VOVTH
Overvoltage threshold
Overvoltage threshold
FB rising (referece to VREF
)
107
87
110
105
113
%
%
FB falling (referece to VREF
)
PGOOD
PGOOD pull-down switch RDSON
Undervoltage threshold
1 mA sinking
70
90
95
Ω
%
%
VUVTH
FB falling (referece to VREF
)
93
Undervoltage threshold
FB rising (referece to VREF)
POWER SWITCH
rDS(ON)
Internal MOSFET on-resistance
VBIAS = 12 V
VBIAS = 3.5 V
VSW = 12 V
45
47
90
95
mΩ
mΩ
nA
Leakage current
300
THERMAL SHUTDOWN
TTSD Thermal shutdown threshold
Thermal shutdown hysteresis
Temperature rising
175
15
°C
°C
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9 Detailed Description
9.1 Overview
The LM5157x-Q1 device is a wide input range, non-synchronous boost converter that uses peak-current-mode
control. The device can be used in boost, SEPIC, and flyback topologies.
The device can start up from a 1-cell battery with a minimum of 2.9 V. It can operate with the input supply
voltage as low as 1.5 V if the BIAS pin is greater than 2.9 V. The internal VCC regulator also supports BIAS pin
operation up to 45 V (50-V absolute maximum) for automotive load dump. The switching frequency is
dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes
AM band interference and allows for a small solution size and fast transient response. To reduce the EMI of the
power supply, the device provides an optional dual random spread spectrum which reduces the EMI over a wide
frequency span.
The device features an accurate current limit over the input voltage range. Low operating current and pulse
skipping operation improve efficiency at light loads.
The device also has built-in protection features such as overvoltage protection, line UVLO, and thermal
shutdown. Selectable hiccup mode overload protection protects the converter during prolonged current limit
conditions. Additional features include low shutdown IQ, programmable soft start, precision reference, power
good indicator, and external clock synchronization.
9.2 Functional Block Diagram
D1
VSUPPLY
LM
VLOAD
CIN
COUT
RLOAD
RFBT
FB
PGOOD
BIAS
SW
RFBB
VUVTH
+
œ
+
œ
IUVLO
VCC_OK
TSD
FB
VSUPPLY
AGND
œ
OVP
BIAS
Ready
VUVLO
VOVTH
RUVLOT
+
SYNC
Detector
Clock_Sync
VCC
EN
/UVLO
/SYNC
VCC
Regulator
RUVLOB
+
VCC_EN
VCC_OK
VCC_EN
C/L Comparator
œ
Hiccup
Mode
VEN
CVCC
VCC
UVLO
ICS
+
ILIM
S
Q
Q
œ
ICS
ISS
PWM
Comparator
R
1.1V+VSLOPE
Gain
= ACS
VCS
-
+
SS
+
+
MODE
Selection
VREF
œ
Clock Generator
Spread Spectrum
+
œ
CSS
VCS
Gm
Clock_Sync
FB
AGND
PGND
MODE
COMP
RT
RT
RCOMP
CCOMP
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9.3 Feature Description
9.3.1 Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
The device has a dual-level EN/UVLO circuit. During power-on, if the BIAS pin voltage is greater than 2.7 V and
the UVLO pin voltage is in between the enable threshold (VEN) and the UVLO threshold (VUVLO) for more than
1.5 µs (see Section 9.3.6 for more details), the device starts up and an internal configuration starts. The device
typically requires a 90-µs internal start-up delay before entering standby mode. In standby mode, the VCC
regulator and RT regulator are operational, SS pin is grounded, and there is no switching at the SW pin.
IUVLO
VSUPPLY
œ
VUVLO
RUN
RUVLOT
+
EN
/UVLO
/SYNC
RUVLOB
+
VCC_EN
œ
VEN
Figure 9-1. Line UVLO and Enable
When the UVLO pin voltage is above the UVLO threshold, the device enters run mode. In run mode, a soft-start
sequence starts if the VCC voltage is greater than VCC UV threshold (V VCC-UVLO). UVLO hysteresis is
accomplished with an internal 50-mV voltage hysteresis and an additional 5-μA current source that is switched
on or off. When the UVLO pin voltage exceeds the UVLO threshold, the UVLO hysteresis current source is
enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the UVLO
threshold, the current source is disabled, causing the voltage at the UVLO pin to fall quickly. When the UVLO pin
voltage is less than the enable threshold (VEN), the device enters shutdown mode after a 40-µs (typical) delay
with all functions disabled.
> 3 cycles
90-µs (typical)
internal start-up delay
BIAS
= VSUPPLY
2.7 V
VUVLO
VEN
UVLO
VCC
VVCC-UVLO
Shutdown
VREF
1.5 µs
SS is grounded
with 2 cycles
delay
UVLO should be greater than
VEN more than 1.5 µs to start-up
SS
SW
TSS
VLOAD
=
SS
1 V
VLOAD(TARGET)
VLOAD
Figure 9-2. Boost Start-Up Waveforms Case 1: Start-Up by VCC UVLO, UVLO Toggle After Start-Up
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90us (typical)
internal start-up delay
> 40us(typical)
90-µs (typical)
internal start-up delay
BIAS
= VSUPPLY
2.7 V
VUVLO
VEN
UVLO
VCC
VVCC-UVLO
Shutdown
VREF
1.5 µs
SS is grounded
with 2 cycles
delay
UVLO should be greater than
0.55 V more than 1.5 µs to start-up
SS
SW
TSS
VLOAD
=
SS
1 V
VLOAD(TARGET)
VLOAD
Figure 9-3. Boost Start-Up Waveforms Case 2: Start-Up by VCC UVLO, EN Toggle After Start-Up
The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5 V
(typical) when the input voltage is in the desired operating range. The values of RUVLOT and RUVLOB can be
calculated as shown in Equation 1 and Equation 2.
VUVLO(FALLING)
VSUPPLY(ON)
ì
- VSUPPLY(OFF)
VUVLO(RISING)
IUVLO
RUVLOT
=
(1)
where
•
•
VSUPPLY(ON) is the desired start-up voltage of the converter
VSUPPLY(OFF) is the desired turnoff voltage of the converter
VUVLO(RISING) ìRUVLOT
RUVLOB
=
VSUPPLY(ON) - VUVLO(RISING)
(2)
A UVLO capacitor (CUVLO) is required in case the input voltage drops below the VSUPPLY(OFF) momentarily during
the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an
additional series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when the 5-
μA hysteresis current turns on.
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IUVLO
VSUPPLY
VUVLO
œ
RUVLOT
RUVLOS
RUN
+
RUVLOB
EN/UVLO/SYNC
CUVLO
Figure 9-4. Line UVLO using Three UVLO Resistors
Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.
9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
The device has an internal wide input VCC regulator which is sourced from the BIAS pin. The wide input VCC
regulator allows the BIAS pin to be connected directly to supply voltages from 2.9 V to 45 V (transient protection
up to 50 V).
The VCC regulator turns on when the device is in standby or run mode. When the BIAS pin voltage is below the
VCC regulation target, the VCC output tracks the BIAS with a small dropout voltage. When the BIAS pin voltage
is greater than the VCC regulation target, the VCC regulator provides 4.9-V supply for the device and the internal
N-channel MOSFET driver.
The VCC regulator sources current into the capacitor connected to the VCC pin with a minimum of 40-mA
capability. The recommended VCC capacitor value is 1 µF.
The minimum supply voltage after start-up can be further decreased by supplying the BIAS pin from the boost
converter output or from an external power supply as shown in Figure 9-5. Also, this configuration allows the
device to handle more power when the VSUPPLY is less than 5 V. Practical minimum supply voltage after start-up
is decided by the maximum duty cycle limit (DMAX).
VLOAD
VSUPPLY
VLOAD
BIAS VCC
SW
UVLO
RT
FB
COMP
SS
PGOOD
PGND AGND MODE
Figure 9-5. Decrease the Minimum Operating Voltage After Start-Up
In flyback topology, the internal power dissipation of the device can be decreased by supplying the BIAS using
an additional transformer winding, especially in PSR flyback. In this configuration, the external BIAS supply
voltage (VAUX) must be greater than the regulation target of the external LDO, and the BIAS pin voltage must
always be greater than 2.9 V.
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VLOAD =12V
VSUPPLY
VAUX =12V
<11V
VAUX
BIAS VCC
SW
UVLO
RT
FB
COMP
SS
PGOOD
PGND AGND MODE
Figure 9-6. External BIAS Supply (PSR Flyback)
9.3.3 Soft Start (SS Pin)
The soft-start feature helps the converter gradually reach the steady state operating point, thus reducing start-up
stresses and surges. The device regulates the FB pin to the SS pin voltage or the internal reference, whichever
is lower.
At start-up, the internal 10-μA soft-start current source (ISS) turns on 90 µs after the VCC voltage exceeds the
VCC UV threshold. The soft-start current gradually increases the voltage on an external soft-start capacitor
connected to the SS pin. This results in a gradual rise of the output voltage. The SS pin is pulled down to ground
by an internal switch when the VCC is less than VCC UVLO threshold, the UVLO is less than the UVLO
threshold, during hiccup mode off-time or thermal shutdown.
In boost topology, soft-start time (tSS) varies with the input supply voltage. The soft-start time in boost topology is
calculated as shown in Equation 3.
≈
’
÷
◊
CSS
VSUPPLY
tSS
=
ì 1-
∆
ISS
VLOAD
«
(3)
In SEPIC topology, the soft-start time (tSS) is calculated as follows.
CSS
tSS
=
ISS
(4)
TI recommends choosing the soft-start time long enough so that the converter can start up without going into an
overcurrent state. See Section 9.3.11 for more detailed information.
Figure 9-7 shows an implementation of primary side soft start in flyback topology.
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COMP
FB SS
Figure 9-7. Primary-Side Soft Start in Flyback
Figure 9-8 shows an implementation of secondary side soft-start in flyback topology.
VLOAD
Secondary Side
Soft-start
Figure 9-8. Secondary-Side Soft-Start in Flyback
9.3.4 Switching Frequency (RT Pin)
The switching frequency of the device can be set by a single RT resistor connected between the RT and the
AGND pins. The resistor value to set the RT switching frequency (fRT) is calculated as shown in Equation 5.
2.21ì1010
fRT(TYPICAL)
RT =
- 955
(5)
The RT pin is regulated to 0.5 V by the internal RT regulator when the device is enabled.
9.3.5 Dual Random Spread Spectrum - DRSS (MODE Pin)
The device provides a digital spread spectrum which reduces the EMI of the power supply over a wide frequency
range. This function is enabled by a single resistor (37.4 kΩ or 100 kΩ) between the MODE pin and the AGND
pin or by programming the MODE pin voltage (370 mV or greater than 1.0 V) during initial power up. When the
spread spectrum is enabled, the internal modulator dithers the internal clock. When an external synchronization
clock is applied to the SYNC pin, the internal spread spectrum is disabled. DRSS (a) combines a low frequency
triangular modulation profile (b) with a high frequency cycle-by-cycle random modulation profile (c). The low
frequency triangular modulation improves performance in lower radio frequency bands (for example, AM band),
while the high frequency random modulation improves performance in higher radio frequency bands (for
example, FM band). In addition, the frequency of the triangular modulation is further modulated randomly to
reduce the likelihood of any audible tones. In order to minimize output voltage ripple caused by spread
spectrum, duty cycle is modified on a cycle-by-cycle basis to maintain a nearly constant duty cycle when
dithering is enabled (see Figure 9-9).
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Frequency
0.156 x fSW
(a) Low + High Frequency
Random Modulation
fSW
(b) Low Frequency
Random Modulation
(c) High Frequency
Random Modulation
Spread Spectrum
ON
Spread Spectrum
OFF
Figure 9-9. Dual Random Spread Spectrum
9.3.6 Clock Synchronization (UVLO/SYNC/EN Pin)
The switching frequency of the device can be synchronized to an external clock by pulling down the EN/UVLO/
SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input
during the forced off-time which is determined by the maximum duty cycle limit. The external synchronization
clock must pull down the EN/UVLO/SYNC pin voltage below V UVLO(FALLING). The duty cycle of the pulldown
pulse is not limited, but the minimum pulldown pulse width must be greater than 150 ns, and the minimum pullup
pulse width must be greater than 250 ns. Figure 9-10 shows an implementation of the remote shutdown function.
The UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In this
configuration, the device stops switching immediately after the UVLO pin is grounded, and the device shuts
down 40 µs (typical) after the UVLO pin is grounded.
VSUPPLY
MCU
UVLO/SYNC
SHUTDOWN
Figure 9-10. UVLO and Shutdown
Figure 9-11 shows an implementation of shutdown and clock synchronization functions together. In this
configuration, the device stops switching immediately when the UVLO pin is grounded, and the device shuts
down if the fSYNC stays in high logic state for longer than 40 µs (typical) (UVLO is in low logic state for more than
40 µs (typical). The device runs at fSYNC if clock pulses are provided after the device is enabled.
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VSUPPLY
MCU
UVLO/SYNC
FSYNC
Figure 9-11. UVLO, Shutdown, and Clock Synchronization
Figure 9-13 and Figure 9-14 show implementations of standby and clock synchronization functions together. In
this configuration, The device stops switching immediately if fSYNC stays in high logic state and enters standby
mode if fSYNC stays in high logic state for longer than two switching cycles. The device runs at the fSYNC if clock
pulses are provided. Because the device can be enabled when the UVLO pin voltage is greater than the enable
threshold for more than 1.5 µs, the configurations in Figure 9-13 and Figure 9-14 are recommended if the
external clock synchronization pulses are provided from the start before the device is enabled. This 1.5-µs
requirement can be relaxed when the duty cycle of the synchronization pulse is greater than 50%. Figure 9-12
shows the required minimum duty cycle to start up by synchronization pulses. When the switching frequency is
greater than 1.1 MHz, the UVLO pin voltage should be greater than the enable threshold for more than 1.5 µs
before applying the external synchronization pulse.
80
75
70
65
60
55
50
45
40
35
30
25
20
15
100 200 300 400 500 600 700 800 900 1000 1100
fSW [kHz]
SUby
Figure 9-12. Required Duty Cycle to Start-Up by External Synchronization Clock
VSUPPLY
MCU
UVLO/SYNC
>0.7V
FSYNC
Figure 9-13. UVLO, Standby, and Clock Synchronization (a)
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VSUPPLY
UVLO/SYNC
MCU
FSYNC
Figure 9-14. UVLO, Standby, and Clock Synchronization (b)
If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented
together by using one push-pull output of the MCU. In this configuration, the device shuts down if fSYNC stays in
low logic state for longer than 40 µs (typical). The device is enabled if fSYNC stays in high logic state for longer
than 1.5 µs. The device runs at the fSYNC if clock pulses are provided after the device is enabled. Also, in this
configuration, it is recommended to apply the external clock pulses after the BIAS is supplied. By limiting the
current flowing into the UVLO pin below 1 mA using a current limiting resistor, the external clock pulses can be
supplied before the BIAS is supplied (see Figure 9-15).
MCU
10 ꢀ
UVLO/SYNC
FSYNC
Figure 9-15. Shutdown and Clock Synchronization
Figure 9-16 shows an implementation of inverted enable using external circuit.
VSUPPLY
UVLO/SYNC
LMV431
Figure 9-16. Inverted UVLO
The external clock frequency (fSYNC) must be within +25% and –30% of fRT(TYPICAL). Because the maximum duty
cycle limit and the peak current limit with slope resistor (RSL) are affected by the clock synchronization, take
extra care when using the clock synchronization function. See Section 9.3.7 and Section 9.3.12 for more
information.
9.3.7 Current Sense and Slope Compensation
The device senses switch current which flows into the SW pin, and provides a fixed internal slope compensation
ramp, help to prevent subharmonic oscillation at high duty cycle. The internal slope compensation ramp is added
to the sensed switch current for the PWM operation, but no slope compensation ramp is added to the sensed
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inductor current for the current limit operation to provide an accurate peak current limit over the input supply
voltage (see Figure 9-17).
SW
Current Limit
Comparator
ILIM
ICS
œ
+
1.1V+VSLOPE
-
+
+
VCS
I-to-V
Gain = ACS
œ
PWM
Comparator
COMP
RCOMP
CHF
(optional)
CCOMP
Figure 9-17. Current Sensing and Slope Compensation
V
VCOMP
Slope
Compensation
Ramp
VSLOPE x D + 1.1V
ACS x ICS
Figure 9-18. Current Sensing and Slope Compensation (a) at PWM Comparator Inputs
I
ILIM
Sensed Inductor
)
Current (ICS
Figure 9-19. Current Sensing (b) at Current Limit Comparator Inputs
Use Equation 6 to calculate the value of the peak slope voltage (VSLOPE).
fRT
VSLOPE = 500mV ì
fSYNC
(6)
where
fSYNC = fRT if clock synchronization is not used
•
According to peak current mode control theory, the slope of the compensation ramp must be greater than half of
the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the
minimum amount of slope compensation in boost topology should satisfy the following inequality:
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V
LOAD + VF - V
(
)
LM
SUPPLY
0.5ì
ì ACS ìMargin < 500mV ì fSW
(7)
where
VF is a forward voltage drop of D1, the external diode
•
Typically 82% of the sensed inductor current falling slope is known as an optimal amount of the slope
compensation. By increasing the margin to 1.6, the amount of slope compensation becomes close to the optimal
amount.
If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used,
the fSW frequency equals the fSYNC frequency.
9.3.8 Current Limit and Minimum On-time
The device provides cycle-by-cycle peak current limit protection that turns off the internal MOSFET when the
inductor current reaches the current limit threshold (ILIM). To avoid an unexpected hiccup mode operation during
a harsh load transient condition, it is recommended to have more margin when programming the peak-current
limit.
Boost converters have a natural pass-through path from the supply to the load through the high-side power
diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot
provide current limit protection when the output voltage is close to or less than the input supply voltage. The
minimum on-time is shown in is calculated as Equation 8.
800ì10-15
tON(MIN)
ö
1
+ 4ì10-6
8ìRT
(8)
9.3.9 Feedback and Error Amplifier (FB, COMP Pin)
The feedback resistor divider is connected to an internal transconductance error amplifier that features high
output resistance (R O = 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error
amplifier sources current which is proportional to the difference between the FB pin and the SS pin voltage or the
internal reference, whichever is lower. The internal transconductance error amplifier provides symmetrical
sourcing and sinking capability during normal operation and reduces its sinking capability when the FB is greater
than OVP threshold.
To set the output regulation target, select the feedback resistor values as shown in Equation 9.
≈
∆
«
’
RFBT
RFBB
VLOAD = VREF
ì
+1
÷
◊
(9)
The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation
network. RCOMP, CCOMP, and optional CHF loop compensation components configure the error amplifier gain and
phase characteristics to achieve a stable loop response. The absolute maximum voltage rating of the FB pin is
4.0 V. If necessary, especially during automotive load dump transient, the feedback resistor divider input can be
clamped by using an external zener diode.
The COMP pin features internal clamps. The maximum COMP clamp limits the maximum COMP pin voltage
below its absolute maximum rating even in shutdown. The minimum COMP clamp limits the minimum COMP pin
voltage to start switching as soon as possible during no load to heavy load transition. The minimum COMP
clamp is disabled when FB is connected to ground in flyback topology.
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9.3.10 Power-Good Indicator (PGOOD Pin)
The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches
to a high impedance open-drain state when the FB pin voltage is greater than the feedback undervoltage
threshold (VUVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than the EN
threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The
recommended minimum pullup resistor value is 10 kΩ.
Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater
than VBIAS+ 0.3 V.
9.3.11 Hiccup Mode Overload Protection (MODE Pin)
To further protect the converter during prolonged current limit conditions, the device provides a selectable hiccup
mode overload protection. This function is enabled by a single resistor (37.4 kΩ or 62.0 kΩ) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV or 620 mV) during initial power up.
The internal hiccup mode fault timer of the device counts the PWM clock cycles when the cycle-by-cycle current
limiting occurs after soft start is finished. When the hiccup mode fault timer detects 64 cycles of current limiting,
an internal hiccup mode off timer forces the device to stop switching and pulls down SS. Then, the device will
restart after 32ꢀ768 cycles of hiccup mode off-time. The 64 cycle hiccup mode fault timer is reset if eight
consecutive switching cycles occur without exceeding the current limit threshold. The soft-start time must be long
enough not to trigger the hiccup mode protection after the soft start is finished.
4 cycles of
current limit
7 normal
switching
cycles
32768 hiccup
mode off cycles
64 cycles of
current limit
60 cycles of
current limit
32768 hiccup
mode off cycles
Inductor Current
Time
Figure 9-20. Hiccup Mode Overload Protection
9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense
resistor. The estimated duty cycle is calculated as shown in Equation 10.
VSUPPLY
D = 1-
VLOAD + VF
(10)
When designing boost converters, the maximum required duty cycle should be reviewed at the minimum supply
voltage. The minimum input supply voltage that can achieve the target output voltage is limited by the maximum
duty cycle limit, and it can be estimated as follows.
VSUPPLY(MIN) ö VLOAD + VF ì 1-D
+ISUPPLY(MAX) ìRDCR +ISUPPLY(MAX) ì110mìDMAX
MAX
(11)
where
•
•
ISUPPLY(MAX) is the maximum input current
RDCR is the DC resistance of the inductor
fSYNC
DMAX1 = 1- 0.1ì
fRT
(12)
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DMAX2 = 1-100nsì fSW
(13)
The minimum input supply voltage can be further decreased by supplying fSYNC which is less than fRT. Practical
DMAX is DMAX1 or DMAX2, whichever is lower.
9.3.13 Internal MOSFET (SW Pin)
The device provides an internal switch with a rDS(ON) that is typically 45 mΩ when the BIAS pin is greater than 5
V. The rDS(ON) of the internal switch is increased when the BIAS pin is less than 5 V. The device temperature
should be checked at the minimum supply voltage especially when the BIAS pin is less than 5 V.
The dV/dT of the SW pin must be limited during the 90-µs internal start-up delay to avoid a false turnon, which is
caused by the coupling through CDG parasitic capacitance of the internal MOSFET switch.
9.3.14 Overvoltage Protection (OVP)
The device has OVP for the output voltage. OVP is sensed at the FB pin. If the voltage at the FB pin rises above
the overvoltage threshold (VOVTH), OVP is triggered and switching stops. During OVP, the internal error amplifier
is operational, but the maximum source and sink capability is decreased to 60 µA.
9.3.15 Thermal Shutdown (TSD)
An internal thermal shutdown turns off the VCC regulator, disables switching, and pulls down the SS when the
junction temperature exceeds the thermal shutdown threshold (T TSD). After the junction temperature is
decreased by 15°C, the VCC regulator is enabled again and the device performs a soft start.
9.4 Device Functional Modes
9.4.1 Shutdown Mode
If the UVLO/EN/SYNC pin voltage is below VEN for longer than 40 µs (typical), the device goes into shutdown
mode with all functions disabled. In shutdown mode, the device decreases the BIAS pin current consumption to
below 2.6 μA (typical).
9.4.2 Standby Mode
If the UVLO/EN/SYNC pin voltage is greater than VEN and below VUVLO for longer than 1.5 µs, the device enters
standby mode with the VCC regulator operational, RT regulator operational, SS pin grounded, and no switching.
The PGOOD is activated when the VCC voltage is greater than the VCC UV threshold.
9.4.3 Run Mode
If the UVLO pin voltage is above VUVLO and the VCC voltage is sufficient, the device enters RUN mode.
9.4.3.1 Spread Spectrum Enabled
The spread spectrum function is enabled by a single resistor (37.4 kΩ ±5% or 100 kΩ ±5%) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV ±10% or greater than 1.0 V) during
initial power up. To switch the spread spectrum function, EN should be grounded for more than 60 µs, or VCC
must be fully discharged.
9.4.3.2 Hiccup Mode Protection Enabled
The hiccup mode protection is enabled by a single resistor (37.4 kΩ ±5% or 62.0 kΩ ±5%) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV ±10% or 620 mV ±10%) during initial
power up. To switch the hiccup mode protection function, EN should be grounded for more than 60 µs, or VCC
must be fully discharged.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
TI provides three application notes which explain how to design boost, SEPIC, and Flyback converters using the
device. These comprehensive application notes include component selections and loop response optimization.
See these application reports for more information on loop response and component selection:
•
•
•
How to Design a Boost Converter Using LM5157x
How to Design an Isolated Flyback Converter Using LM5157x
How to Design a SEPIC Converter Using LM5157x
Note
The hyperlinks above are linked to LM5155 application reports. Dedicated LM5157x reports will be
available soon.
For details on the application reports, please ask a new question at e2e or contact
LM5157_requests@list.ti.com.
10.2 Typical Application
Figure 10-1 shows all optional components to design a boost converter.
RSNB CSNB
LM
VLOAD
VSUPPLY
RBIAS
CBIAS
D1
CVCC
CIN
COUT1 COUT2
RUVLOT
RUVLOS
+
œ
BIAS VCC
SW
RLOAD
RFBT
UVLO
RT
FB
PGOOD
COMP
MCU_VCC
CHF
RUVLOB
RT
RFBB
SS
CSS
CUVLO
PGND AGND MODE
RCOMP
CCOMP
RMODE
Figure 10-1. Typical Boost Converter Circuit With Optional Components
10.2.1 Design Requirements
Table 10-1 shows the intended input, output, and performance parameters for this application example.
Table 10-1. Design Example Parameters
DESIGN PARAMETER
VALUE
6 V
Minimum input supply voltage (VSUPPLY(MIN)
)
Target output voltage (VLOAD
)
12 V
Maximum load current (ILOAD
)
1.6 A (≈ 19.2 Watt)
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Table 10-1. Design Example Parameters (continued)
DESIGN PARAMETER
VALUE
Typical switching frequency (fSW
)
2100 kHz
10.2.2 Detailed Design Procedure
Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application.
Download these Quick Start Calculator for more information on loop response and component selection:
•
•
•
LM5157x Boost Quick Start Calculator
LM5157x Flyback Quick Start Calculator
LM5157x SEPIC Quick Start Calculator
The device is also WEBENCH® Designer enabled. The WEBENCH software uses an iterative design procedure
and accesses comprehensive data bases of components when generating a design.
Note
The hyperlinks above are linked to LM5155 design tools. Dedicated LM5157x tools will be available
soon.
For details on the design tools, please ask
LM5157_requests@list.ti.com.
a
new question at e2e or contact
10.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2.2.2 Recommended Components
Table 10-2 shows a recommended list of materials for this typical application.
Table 10-2. List of Materials
REFERENCE
DESIGNATOR
MANUFACTURER
QTY.
SPECIFICATION
PART NUMBER
(1)
RT
1
1
1
RES, 9.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
RES, 49.9 k, 1%, 0.1 W, 0603
Vishay-Dale
Yageo America
Vishay-Dale
CRCW06039K53FKEA
RC0603FR-0749K9L
CRCW06034K53FKEA
RFBT
RFBB
RES, 4.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
Inductor, Shielded, Composite, 1.5 μH, 14 A, 0.01052 Ω,
AEC-Q200 Grade 1, SMD
LM
COUT1
1
6
2
4
Coilcraft
TDK
XEL6030-152MEB
CAP, CERM, 4.7 µF, 50 V, ±10%, X7R, 1210
C3225X7R1H475K250AB
HHXB500ARA101MJA0G
GRM32ER71H106KA12L
CAP, Aluminum Polymer, 100 µF, 50 V, ±20%, 0.025 Ω,
AEC-Q200 Grade 2, D10xL10mm SMD
COUT2 (Bulk)
CIN1
Chemi-Con
MuRata
CAP, CERM, 10 µF, 50 V, ±10%, X7R, 1210
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Table 10-2. List of Materials (continued)
REFERENCE
QTY.
MANUFACTURER
SPECIFICATION
PART NUMBER
(1)
DESIGNATOR
CAP, AL, 22 uF, 100 V, ±20%, 1.3 Ω, AEC-Q200 Grade
2, SMD
CIN2 (Bulk)
1
Panasonic
EEE-FK2A220P
D1
1
1
1
Diode, Schottky, 45 V, 10 A, AEC-Q101, CFP15
RES, 2.61 k, 1%, 0.1 W, 0603
Nexperia
Yageo America
Kemet
PMEG045V100EPDAZ
RC0603FR-072K61L
C0603X103K5RACTU
RCOMP
CCOMP
CAP, CERM, 0.01 μF, 50 V, ±10%, X7R, 0603
CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, AEC-Q200
Grade 0, 0603
CHF
1
TDK
CGA3E2NP01H101J080AA
RUVLOT
RUVLOB
RUVLOS
CSS
1
1
1
1
1
RES, 61.9 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
RES, 71.5 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
RES, 0, 5%, 0.1 W, 0603
Vishay-Dale
Vishay-Dale
Yageo America
Kemet
CRCW060361K9FKEA
CRCW060371K5FKEA
RC0603JR-070RL
CAP, CERM, 0.022 μF, 50 V, ±10%, X7R, 0603
RES, 0, 5%, 0.1 W, 0603
C0603X223K5RACTU
RC0603JR-070RL
RBIAS
Yageo America
CAP, CERM, 0.1 μF, 100 V, ±10%, X7R, AEC-Q200
Grade 1, 0603
CBIAS
CVCC
1
1
MuRata
TDK
GCJ188R72A104KA01D
CAP, CERM, 1 µF, 16 V, ±10%, X7R, AEC-Q200 Grade
1, 0603
CGA3E1X7R1C105K080AC
RPG
1
1
RES, 100 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
RES, 0, 5%, 0.1 W, 0603
Vishay-Dale
CRCW0603100KFKEA
RC0603JR-070RL
RMODE
Yageo America
(1) See the Third-Party Products Disclaimer.
10.2.2.3 Inductor Selection (LM)
When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the
inductor current, and RHP zero frequency (fRHP).
Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope of
the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle (additional RSL
resistor is required if not). Higher fRHP (= lower inductance) allows a higher crossover frequency and is always
preferred when using a small value output capacitor.
The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average
inductor current as a good compromise between RR, FRHP, and inductor falling slope.
10.2.2.4 Output Capacitor (COUT
)
There are a few ways to select the proper value of output capacitor (COUT). The output capacitor value can be
selected based on output voltage ripple, output overshoot, or undershoot due to load transient.
The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using
multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the
diode and the MOSFET than the bulk aluminum capacitors in order to absorb the majority of the ripple current.
10.2.2.5 Input Capacitor
The input capacitors decrease the input voltage ripple. The required input capacitor value is a function of the
impedance of the source power supply. More input capacitors are required if the impedance of the source power
supply is not low enough.
10.2.2.6 Diode Selection
A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery
charge. Low reverse leakage current is important parameter when selecting the Schottky diode. The diode must
be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to handle
the average output current.
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10.2.3 Application Curve
100
95
90
85
80
75
70
65
60
VSUPPLY = 9 V
VSUPPLY = 6 V
VSUPPLY = 4 V
VSUPPLY = 3 V
0
0.2
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
D001
Figure 10-2. Efficiency versus Output Current
10.3 System Examples
VLOAD
VSUPPLY
BIAS VCC
SW
UVLO
RT
FB
COMP
SS
PGOOD
PGND AGND MODE
Figure 10-3. Typical Boost Application
VSUPPLY = 2.9V - 45V
VLOAD
-
+
Car
Battery
BIAS VCC
SW
To MCU
FB
PGOOD
UVLO
RT
From MCU
COMP
SS
PGND AGND MODE
Figure 10-4. Typical Start-Stop Application
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VSUPPLY = Min 2.9V
VLOAD = 12V
+
BIAS VCC
SW
1-cell or
2-cell
Battery
FB
PGOOD
UVLO
RT
COMP
From MCU
-
SS
PGND AGND MODE
Figure 10-5. Emergency-call / Boost On-Demand / Portable Speaker
VLOAD
VSUPPLY
BIAS VCC
SW
UVLO
RT
FB
COMP
SS
PGOOD
PGND AGND MODE
Figure 10-6. Typical SEPIC Application
Inductance should be small enough
to operate in DCM at full load
VLOAD = 30V-150V
VSUPPLY
BIAS VCC
SW
UVLO
RT
FB
COMP
From MCU
SS
PGOOD
PGND AGND MODE
Figure 10-7. LIDAR Bias Supply 1 (DCM Operation)
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VLOAD
= 150V-200V
Voltage
Tripler
Inductance should be big enough
to operate in CCM
VSUPPLY
BIAS VCC
SW
From MCU
UVLO
RT
FB
COMP
SS
PGOOD
PGND AGND MODE
Figure 10-8. LIDAR Bias Supply 2 (CCM Operation)
VSUPPLY
VLOAD
BIAS VCC
SW
UVLO
RT
FB
COMP
SS
PGOOD
PGND AGND MODE
Enable Spread Spectrum
Figure 10-9. Low-Cost Single String LED Driver
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VSUPPLY
V
LOAD = 5V/12V
BIAS
SW
UVLO/SYNC
PGND
AGND
VCC
PGOOD
MODE
RT
FB
SS
COMP
Optional Primary-Side
Soft-Start
Figure 10-10. Secondary-Side Regulated Isolated Flyback
VLOAD2 = +12V
VSUPPLY
VLOAD3 = -8.5V
BIAS
SW
UVLO/SYNC
Optional DC Coupling
Capacitor for Low EMI
Isolated Sepic
AGND
PGND
To MCU
System Power
V
LOAD1 = 3.3V/5V +/-2%
PGOOD
MODE
RT
FB
COMP
SS
VCC
Figure 10-11. Primary-Side Regulated Multiple-Output Isolated Flyback / Isolated SEPIC
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VSUPPLY
V
LOAD = 5V/12V
BIAS
SW
UVLO/SYNC
PGND
AGND
To MCU
System Power
PGOOD
MODE
VCC
FB
RT
SS
COMP
Figure 10-12. Typical Non-Isolated Flyback
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11 Power Supply Recommendations
The device is designed to operate from a power supply or a battery whose voltage range is from 1.5 V to 45 V.
The input power supply must be able to supply the maximum boost supply voltage and handle the maximum
input current at 1.5 V. The impedance of the power supply and battery including cables must be low enough that
an input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required
at the supply input of the converter.
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12 Layout
12.1 Layout Guidelines
The performance of switching converters heavily depends on the quality of the PCB layout. The following
guidelines will help users design a PCB with the best power conversion performance, thermal performance, and
minimize generation of unwanted EMI.
•
•
•
•
•
•
•
•
Put the D1component on the board first.
Use a small size ceramic capacitor for COUT
Make the switching loop (COUT to D1 to SW to PGND to COUT) as small as possible.
Leave a copper area near the D1 diode for thermal dissipation.
Put the CVCC capacitor as near the device as possible between the VCC and PGND pins.
Connect the COMP pin to the compensation components (RCOMP and CCOMP).
Connect the CCOMP capacitor to the analog ground trace.
Connect the AGND pin directly to the analog ground plane. Connect the AGND pin to the RMODE, RUVLOB, RT,
CSS, and RFBB components.
.
•
•
Connect the exposed pad to the AGND pin under the device.
Add several vias under the exposed pad to help conduct heat away from the device. Connect the vias to a
large ground plane on the bottom layer.
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12.2 Layout Examples
Thermal Dissipation
Area
VSUPPLY
GND
VLOAD
Do not connect input and
output capacitor grounds
underneath the device
D1
CVIN
LM
COUT2
COUT1
GND
CVIN
Power Ground Plane
(Connect to EP via PGND pin)
16 15 14 13
Connect to the ground connection
of COUT using inner layer
Connect
to VLOAD
CVCC
PGND
1
2
3
4
12 SW
EP
RMODE
MODE
11
VCC
BIAS
Connect to the ground
connection of CIN using
inner layer
Connect to
VLOAD / VSUPPLY
10 SS
CSS
9
FB
PGOOD
RFBB
Connect to
pull-up resistor
8
5
6
7
RCOMP
CCOMP
RT
Analog Ground Plane
(Connect to EP via AGND pin)
Connect
to VSUPPLY
RUVLOT
Figure 12-1. PCB Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.1.2 Development Support
13.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5157x-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.1.3 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RTE0016K
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.15
2.85
B
A
PIN 1 INDEX AREA
3.15
2.85
0.1 MIN
(0.13)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
0.8
0.7
C
SEATING PLANE
0.08
0.05
0.00
1.66 0.1
(0.2) TYP
EXPOSED
THERMAL PAD
5
8
12X 0.5
4
9
(0.16)
TYP
4X
SYMM
A
A
17
1.5
1
12
0.30
0.18
16X
PIN 1 ID
(OPTIONAL)
16
13
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4224938/B 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTE0016K
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.66)
SYMM
16
13
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224938/B 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTE0016K
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.51)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
84% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4224938/B 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM51571QRTERQ1
LM5157QRTERQ1
XLM51571QRTERQ1
PREVIEW
PREVIEW
ACTIVE
WQFN
WQFN
WQFN
RTE
RTE
RTE
16
16
16
3000
3000
3000
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 150
-40 to 150
-40 to 150
XLM5157QRTERQ1
ACTIVE
WQFN
RTE
16
3000
TBD
Call TI
Call TI
-40 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Nov-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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SI9137LG
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SI9122E
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