LM5158 [TI]

LM5158x 2.2-MHz Wide VIN 85-V Output Boost/SEPIC/Flyback Converter with Dual Random Spread Spectrum;


型号：	LM5158
厂家：	TEXAS INSTRUMENTS
描述：	LM5158x 2.2-MHz Wide VIN 85-V Output Boost/SEPIC/Flyback Converter with Dual Random Spread Spectrum
文件：	总46页 (文件大小：1851K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM5158, LM51581

SNVSBZ7 – OCTOBER 2021

LM5158x 2.2-MHz Wide V_IN85-V Output Boost/SEPIC/Flyback Converter with Dual

Random Spread Spectrum

•

Industrial PLC

Inverter bias supply

Piezo driver/motor driver bias supply

1 Features

•

Suited for wide operating range for battery

applications

3 Description

– 3.2-V to 60-V input operating range (65-V abs

max)

– 83-V maximum output (85-V abs max)

– Minimum boost supply voltage of 1.5 V when

BIAS ≥ 3.2 V

The LM5158x device is a wide input range, non-

synchronous boost converter with an integrated 85-V,

3.26-A (LM5158) or 85-V, 1.63-A (LM51581) power

switch.

– Input transient protection up to 65 V

– Minimized battery drain

The device can be used in boost, SEPIC, and flyback

topologies. It can start up from a single-cell battery

with a minimum of 3.2 V. It can operate with the input

supply voltage as low as 1.5 V if the BIAS pin is

greater than 3.2 V.

•

Low shutdown current (I_Q≤ 2.6 µA)

Low operating current (I_Q≤ 670 µA)

•

Small solution size and low cost

– Maximum switching frequency up to 2.2 MHz

– 16-pin QFN package (3 mm × 3 mm)

– Integrated error amplifier allows primary-side

regulation without optocoupler (flyback)

– Accurate current limit (see the Device

Comparison Table)

EMI mitigation

– Selectable dual random spread spectrum

– Lead-less package

The BIAS pin operates up to 60 V (65-V absolute

maximum). The switching frequency is dynamically

programmable from 100 kHz to 2.2 MHz with an

external resistor. Switching at 2.2 MHz minimizes AM

band interference and allows for a small solution size

and fast transient response. The device provides a

selectable Dual Random Spread Spectrum to help

reduce the EMI over a wide frequency range.

•

Higher efficiency with low-power dissipation

– 133-mΩ R_DSONswitch

Device Information

PART NUMBER

LM5158

LM51581

PACKAGE⁽¹⁾

BODY SIZE (NOM)

– Fast switching, small switching loss

Avoid AM band interference and crosstalk

– Optional clock synchronization

– Dynamically programmable wide switching

frequency from 100 kHz to 2.2 MHz

Integrated protection features

WQFN (16)

3.00 mm × 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

V_LOAD

V_SUPPLY

•

– Constant current limiting over input voltage

– Selectable hiccup mode overload protection

– Programmable line UVLO

– OVP protection

– Thermal shutdown

BIAS VCC

UVLO

COMP

PGOOD

PGND AGND MODE

•

Accurate ±1% accuracy feedback reference

Adjustable soft start

PGOOD indicator

Create a custom design using the LM5158x with

the WEBENCH^®Power Designer

Typical SEPIC Application

2 Applications

•

Battery-powered wide input boost, SEPIC, flyback

converter

•

LED bias supply

Multiple-output flyback without optocoupler

Loop powered fire detection

Hold-up capacitor charger

Power module

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5158, LM51581

SNVSBZ7 – OCTOBER 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Device Comparison Table...............................................3

7 Pin Configuration and Functions...................................4

8 Specifications.................................................................. 6

8.1 Absolute Maximum Ratings........................................ 6

8.2 ESD Ratings............................................................... 6

8.3 Recommended Operating Conditions.........................6

8.4 Thermal Information....................................................7

8.5 Electrical Characteristics.............................................7

8.6 Typical Characteristics................................................9

9 Detailed Description......................................................12

9.1 Overview...................................................................12

9.2 Functional Block Diagram.........................................13

9.3 Feature Description...................................................13

9.4 Device Functional Modes..........................................25

10 Application and Implementation................................27

10.1 Application Information........................................... 27

10.2 Typical Boost Application........................................27

10.3 System Examples................................................... 30

11 Power Supply Recommendations..............................33

12 Layout...........................................................................34

12.1 Layout Guidelines................................................... 34

12.2 Layout Examples.................................................... 35

13 Device and Documentation Support..........................36

13.1 Device Support....................................................... 36

13.2 Documentation Support.......................................... 36

13.3 Receiving Notification of Documentation Updates..36

13.4 Support Resources................................................. 36

13.5 Trademarks.............................................................36

13.6 Electrostatic Discharge Caution..............................37

13.7 Glossary..................................................................37

14 Mechanical, Packaging, and Orderable

Information.................................................................... 38

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

October 2021

Initial Release

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5 Description (continued)

The device features an accurate peak current limit over the input voltage, which avoids overdesigning the power

inductor. Low operating current and pulse-skipping operation improve efficiency at light loads.

The device has built-in protection features such as overvoltage protection, line UVLO, thermal shutdown, and

selectable hiccup mode overload protection. Additional features include low shutdown I_Q, programmable soft

start, precision reference, a power-good indicator, and external clock synchronization.

6 Device Comparison Table

DEVICE OPTION

LM5158

MINIMUM PEAK CURRENT LIMIT

MAXIMUM SW VOLTAGE

3.26 A

1.63 A

83 V (85-V abs max)

LM51581

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7 Pin Configuration and Functions

PGND

MODE

VCC

BIAS

10 SS

PGOOD

Figure 7-1. RTE Package 16-Pin WQFN Top View

Table 7-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

1, 16

PGND

Power ground pin. Source connection of the internal N-channel power MOSFET

Output of the internal VCC regulator and supply voltage input of the internal MOSFET driver.

Connect a 1-µF ceramic bypass capacitor from this pin to PGND.

VCC

BIAS

Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.

Power-good indicator. An open-drain output, which goes low if FB is below the undervoltage

threshold (V_UVTH). Connect a pullup resistor to the system voltage rail.

PGOOD

Switching frequency setting pin. The switching frequency is programmed by a single resistor

between RT and AGND.

Enable pin. The converter shuts down when the pin is less than the enable threshold (V_EN).

Undervoltage lockout programming pin. The converter start-up and shutdown levels can be

programmed by connecting this pin to the supply voltage through a voltage divider. If using a

programmable UVLO, connect the low-side UVLO resistor to AGND. This pin must not be left

floating. Connect to the BIAS pin if not used.

EN/UVLO/

SYNC

External synchronization clock input pin. The internal clock can be synchronized to an external clock

by applying a negative pulse signal into the pin.

AGND

COMP

Analog ground pin. Connect to the analog ground plane through a wide and short path.

Output of the internal transconductance error amplifier. Connect the loop compensation components

between this pin and AGND.

Inverting input of the error amplifier. Connect a voltage divider to set the output voltage in boost,

SEPIC, or primary-side regulated flyback topologies. Connect the low-side feedback resistor as close

to AGND as possible.

Soft-start time programming pin. An external capacitor and an internal current source set the ramp

rate of the internal error amplifier reference during soft start. Connect the ground connection of the

capacitor to AGND.

MODE = 0 V or connect to AGND during initial power up: Hiccup mode protection is disabled and

spread spectrum is disabled.

MODE = 370 mV or connect a 37.4-kΩ resistor between this pin and AGND during initial power up:

Hiccup mode protection is enabled and spread spectrum is enabled.

MODE

MODE = 620 mV or connect a 62.0-kΩ resistor between this pin and AGND during initial power up:

Hiccup mode protection is enabled and spread spectrum is disabled.

MODE > 1 V or connect a 100-kΩ resistor between this pin and AGND during initial power up:

Hiccup mode protection is disabled and spread spectrum is enabled.

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Table 7-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

13, 14

12, 15

Switch pin. Drain connection of the internal N-channel power MOSFET

No internal electrical contact

—

Exposed pad of the package. The exposed pad must be connected to AGND and the large ground

copper plane to decrease thermal resistance.

—

(1) G = Ground, I = Input, O = Output, P = Power

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8 Specifications

8.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range⁽¹⁾

MIN

–0.3

–6

MAX

UNIT

BIAS to AGND

UVLO to AGND

V_BIAS+ 0.3

3.8

SS, RT to AGND⁽²⁾

Input

FB to AGND

4.0

MODE to AGND

PGND to AGND

VCC to AGND

3.8

0.3

5.8⁽³⁾

PGOOD to AGND⁽⁴⁾

Output

COMP to AGND⁽⁵⁾

SW to AGND (DC)

SW to AGND (5-ns transient)

(6)

Junction temperature, T_J

Storage temperature, T_stg

–40

150

°C

–55

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) These pins are not specified to have an external voltage applied.

(3) Operating lifetime is de-rated when the pin voltage is greater than 5.5 V.

(4) The maximum current sink is limited to 1 mA when V_PGOOD> V_BIAS

(5) This pin has an internal max voltage clamp which can handle up to 1.6 mA.

(6) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

Electrostatic

discharge

V_(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

Over the recommended operating junction temperature range⁽¹⁾

MIN

1.5

NOM

MAX

UNIT

V_SUPPLY

V_LOAD

V_BIAS

V_UVLO

V_FB

Boost converter input (when BIAS ≥ 3.2 V)

Boost converter output

BIAS input⁽³⁾

V_SUPPLY

3.2

83⁽²⁾

UVLO input

FB input

4.0

I_SW

Switch current

See note⁽⁴⁾

2200

125

f_SW

Typical switching frequency

Synchronization pulse frequency

Operating junction temperature

100

–40

kHz

°C

f_SYNC

T_J

(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test

conditions, see the Electrical Characteristics.

(2) The boost converter output can be up to 83 V, but the SW pin voltage should be less than or equal to 85 V during transient.

(3) The BIAS pin operating range is from 3.2 V to 60 V when VCC is supplied from the internal VCC regulator.

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(4) The maximum switch current is limited by pre-programmed peak current limit (I_LIM) when T_J< T_TSD

8.4 Thermal Information

LM5158x

THERMAL METRIC⁽¹⁾

RTE(QFN)

16 PINS

32.7

UNIT

R_θJA

Junction-to-ambient thermal resistance (LM5158EVM-BST)

Junction-to-ambient thermal resistance

°C/W

R_θJA

45.6

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

44.8

Junction-to-board thermal resistance

19.1

Ψ_JT

Junction-to-top characterization parameter (LM5158EVM-BST)

Junction-to-top characterization parameter

0.6

Ψ_JT

0.8

Ψ_JB

Junction-to-board characterization parameter (LM5158EVM-BST)

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

15.1

Ψ_JB

19.1

R_θJC(bot)

6.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= –40°C to 125°C. Unless otherwise

stated, V_BIAS= 12 V, R_T= 9.09 kΩ

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_{SHUTDOWN(BIAS)}BIAS shutdown current

I_{OPERATING(BIAS)}BIAS operating current

VCC REGULATOR

V_BIAS= 12 V, V_UVLO= 0 V

2.6

μA

V_BIAS= 12 V, V_UVLO= 2.0 V, V_FB= V_REF

R_T= 220 kΩ

670

850

V_VCC-REG

VCC regulation

V_BIAS= 8 V, I_VCC= 18 mA

VCC rising

4.66

3.05

4.9

3.10

0.1

5.14

3.15

V_VCC-

VCC UVLO threshold

VCC UVLO hysteresis

UVLO(RISING)

VCC falling

ENABLE

V_EN(RISING)

V_EN(FALLING)

V_EN(HYS)

Enable threshold

Enable hysteresis

EN rising

EN falling

0.4

0.52

0.49

0.03

0.7

0.33

0.63

UVLO/SYNC

V_UVLO(RISING)

UVLO / SYNC threshold

UVLO rising

UVLO falling

1.425

1.370

1.5

1.45

0.05

1.575

1.520

V_{UVLO(FALLING)}UVLO / SYNC threshold

V_UVLO(HYS)

I_UVLO

MODE, SPREAD SPECTRUM

F_SWmodulation (upper limit)

UVLO / SYNC threshold hysteresis UVLO falling

UVLO hysteresis current

V_UVLO= 1.6 V

μA

7.8%

F_SWmodulation (lower limit)

–7.8%

SOFT START

I_SS

Soft-start current

μA

SS pulldown switch R_DSON

PULSE WIDTH MODULATION

fsw1

Switching frequency

R_T= 220 kΩ

100

115

kHz

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Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= –40°C to 125°C. Unless otherwise

stated, V_BIAS= 12 V, R_T= 9.09 kΩ

PARAMETER

TEST CONDITIONS

MIN

TYP

440

2200

MAX

UNIT

kHz

fsw2

Switching frequency

Minimum on time

R_T= 49.3 kΩ

388

492

fsw3

R_T= 9.09 kΩ

R_T= 220 kΩ

1980

2420

t_ON(MIN)

D_MAX1

D_MAX2

Maximum duty cycle limit

RT regulation voltage

80%

90%

85%

93%

0.5

90%

96%

CURRENT LIMIT

I_LIM

Internal MOSFET current limit

LM5158

3.26

1.63

3.75

4.24

2.12

LM51581

1.875

HICCUP MODE PROTECTION

Hiccup enable cycles

Hiccup timer reset cycles

ERROR AMPLIFIER

Cycles

V_REF

FB reference

0.99

1.01

mA/V

μA

Transconductance

COMP sourcing current

COMP clamp voltage

ΔV_COMP/ ΔI_SW

V_COMP= 1.2 V

180

2.5

COMP rising (V_UVLO= 2.0 V)

COMP falling

2.8

1.1

A_CS

0.19

OVP

V_OVTH

Overvoltage threshold

FB rising (reference to V_REF

)

107%

87%

110%

105%

113%

FB falling (reference to V_REF

)

PGOOD

PGOOD pulldown switch R_DSON

Undervoltage threshold

1-mA sinking

90%

95%

V_UVTH

FB falling (reference to V_REF

)

93%

Undervoltage threshold

FB rising (reference to V_REF)

POWER SWITCH

r_DS(ON)

Internal MOSFET on-resistance

V_BIAS= 12 V

V_BIAS= 3.5 V

V_SW= 12 V

133

138

290

300

mΩ

Leakage current

1100

THERMAL SHUTDOWN

T_TSDThermal shutdown threshold

Thermal shutdown hysteresis

Temperature rising

175

°C

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8.6 Typical Characteristics

4.5

4.75

4.5

4.25

BIAS = 12V

BIAS = 60V

3.5

3.75

3.5

3.25

2.5

1.5

2.75

2.5

2.25

0.5

-40 -20

80 100 120 140 160

10 15 20 25 30 35 40 45 50 55 60

V_BIAS(V)

Temperature (C)

Figure 8-2. BIAS Shutdown Current vs

Temperature

Figure 8-1. BIAS Shutdown Current vs V_BIAS

1000

900

800

700

600

500

400

300

200

100

BIAS

VCC

-40 -20

80 100 120 140 160

Temperature (C)

V_BIAS(V)

Figure 8-3. BIAS Operating Current vs Temperature

Figure 8-4. V_VCCvs V_BIAS

10.8

10.6

10.4

10.2

9.8

9.6

9.4

9.2

-40 -20

80 100 120 140 160

100

120

Temperature (C)

I_VCC(mA)

Figure 8-6. I_SSvs Temperature

Figure 8-5. V_VCCvs I_VCC

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0.57

0.56

0.55

0.54

0.53

0.52

0.51

0.5

1.6

1.58

1.56

1.54

1.52

1.5

EN Rising

EN Falling

UVLO Rising

UVLO Falling

1.48

1.46

1.44

1.42

1.4

0.49

0.48

0.47

0.46

0.45

-40 -20

80 100 120 140 160

-40 -20

80 100 120 140 160

Temperature (C)

Figure 8-7. EN Threshold vs Temperature

Figure 8-8. UVLO Threshold vs Temperature

1.01

1.008

1.006

1.004

1.002

2400

2200

2000

1800

1600

1400

1200

1000

800

0.998

0.996

0.994

0.992

0.99

600

400

200

-40 -20

80 100 120 140 160

30 40 50 6070 100

RT Resistor (k)

200250

Temperature (C)

Figure 8-9. FB Reference vs Temperature

Figure 8-10. Frequency vs RT Resistance

110

2400

4.5

4.25

RT=220k

RT=9.09k

LM5158

LM51581

108

106

104

102

100

2360

2320

2280

2240

2200

2160

2120

2080

2040

2000

2.75

2.5

2.25

3.75

3.5

3.25

1.75

1.5

1.25

2.75

2.5

-40 -20

80 100 120 140 160

-40 -20

80 100 120 140 160

Temperature (C)

Figure 8-11. Frequency vs Temperature

Figure 8-12. Current Limit Threshold vs

Temperature

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4.5

4.25

290

270

250

230

210

190

170

150

130

110

LM5158

LM51581

2.75

2.5

2.25

3.75

3.5

3.25

1.75

1.5

1.25

2.75

F_SW=1MHz, L_M=5H, V_IN=6V

BIAS = 12V

BIAS = 3.5V

2.5

100

Duty Cycle (%)

-40 -20

80 100 120 140 160

Temperature (C)

Figure 8-14. Internal MOSFET Drain Source On-

state Resistance vs Temperature

Figure 8-13. Peak Current Limit vs Duty Cycle

200

190

180

170

160

150

140

130

120

110

100

250 500 750 1000 1250 1500 1750 2000 2250

Frequency (kHz)

250 500 750 1000 1250 1500 1750 2000 2250

Frequency (kHz)

Figure 8-15. Minimum On Time vs Frequency

Figure 8-16. Maximum Duty Cycle Limit vs

Frequency

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9 Detailed Description

9.1 Overview

The LM5158x is a wide input range, non-synchronous boost converter that uses peak-current-mode control. The

device can be used in boost, SEPIC, and flyback topologies.

The device can start up with a minimum of 3.2 V. It can operate with input supply voltage as low as 1.5 V if the

BIAS pin is greater than 3.2 V. The internal VCC regulator also supports BIAS pin operation up to 60 V (65-V

absolute maximum). The switching frequency is dynamically programmable from 100 kHz to 2.2 MHz with an

external resistor. Switching at 2.2 MHz minimizes AM band interference and allows for a small solution size and

fast transient response. The device provides an optional dual random spread spectrum to help reduce the EMI

over a wide frequency span.

The device features an accurate current limit over the input voltage range. Low operating current and pulse

skipping operation improve efficiency at light loads.

The device also has built-in protection features such as overvoltage protection, line UVLO, and thermal

shutdown. Selectable hiccup mode overload protection protects the converter during prolonged current limit

conditions. Additional features include the following:

•

Low shutdown I_Q

Programmable soft start

Precision reference

Power-good indicator

External clock synchronization

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9.2 Functional Block Diagram

V_SUPPLY

L_M

V_LOAD

C_IN

C_OUT

R_LOAD

R_FBT

PGOOD

BIAS

R_FBB

V_UVTH

I_UVLO

VCC_OK

TSD

V_SUPPLY

AGND

OVP

BIAS

Ready

V_UVLO

V_OVTH

R_UVLOT

SYNC

Detector

Clock_Sync

VCC

/UVLO

/SYNC

VCC

Regulator

R_UVLOB

VCC_EN

VCC_OK

VCC_EN

C/L Comparator

Hiccup

Mode

V_EN

C_VCC

VCC

UVLO

I_CS

I_LIM

I_CS

I_SS

PWM

Comparator

1.1V+V_SLOPE

Gain

= A_CS

V_CS

MODE

Selection

V_REF

Clock Generator

Spread Spectrum

C_SS

V_CS

Clock_Sync

AGND

PGND

MODE

COMP

R_T

R_COMP

C_COMP

9.3 Feature Description

9.3.1 Line Undervoltage Lockout (EN/UVLO/SYNC Pin)

The device has a dual-level EN/UVLO circuit. During power-on, if the BIAS pin voltage is greater than 2.7 V,

the UVLO pin voltage is in between the enable threshold (V_EN), and the UVLO threshold (V_UVLO) for more than

1.5 µs (see Section 9.3.6 for more details), the device starts up and an internal configuration starts. The device

typically requires a 90-µs internal start-up delay before entering standby mode. In standby mode, the VCC

regulator and RT regulator are operational, the SS pin is grounded, and there is no switching at the SW pin.

I_UVLO

V_SUPPLY

V_UVLO

RUN

R_UVLOT

/UVLO

/SYNC

R_UVLOB

VCC_EN

V_EN

Figure 9-1. Line UVLO and Enable

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When the UVLO pin voltage is above the UVLO threshold, the device enters run mode. In run mode, a

soft-start sequence starts if the VCC voltage is greater than VCC UV threshold (V_VCC-UVLO). UVLO hysteresis is

accomplished with an internal 50-mV voltage hysteresis and an additional 5-μA current source that is switched

on or off. When the UVLO pin voltage exceeds the UVLO threshold, the UVLO hysteresis current source

is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the UVLO

threshold, the current source is disabled, causing the voltage at the UVLO pin to fall quickly. When the UVLO pin

voltage is less than the enable threshold (V_EN), the device enters shutdown mode after a 40-µs (typical) delay

with all functions disabled.

> 3 cycles

90-µs (typical)

internal start-up delay

BIAS

= V_SUPPLY

2.7 V

V_UVLO

V_EN

UVLO

VCC

V_VCC-UVLO

Shutdown

V_REF

1.5 µs

SS is grounded

with 2 cycles

delay

UVLO should be greater than

V_ENmore than 1.5 µs to start-up

T_SS

V_LOAD

1 V

V_LOAD(TARGET)

V_LOAD

Figure 9-2. Boost Start-Up Waveforms Case 1: Start-Up by VCC UVLO, UVLO Toggle After Start-Up

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90us (typical)

internal start-up delay

> 40us(typical)

90-µs (typical)

internal start-up delay

BIAS

= V_SUPPLY

2.7 V

V_UVLO

V_EN

UVLO

VCC

V_VCC-UVLO

Shutdown

V_REF

1.5 µs

SS is grounded

with 2 cycles

delay

UVLO should be greater than

0.55 V more than 1.5 µs to start-up

T_SS

V_LOAD

1 V

V_LOAD(TARGET)

V_LOAD

Figure 9-3. Boost Start-Up Waveforms Case 2: Start-Up by VCC UVLO, EN Toggle After Start-Up

The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5

V (typical) when the input voltage is in the desired operating range. The values of R_UVLOTand R_UVLOBcan be

calculated as shown in Equation 1 and Equation 2.

V_{UVLO(FALLING)}

V_SUPPLY(ON)

- V_SUPPLY(OFF)

V_UVLO(RISING)

I_UVLO

R_UVLOT

(1)

where

•

V_SUPPLY(ON)is the desired start-up voltage of the converter.

V_SUPPLY(OFF)is the desired turn-off voltage of the converter.

V_UVLO(RISING)ìR_UVLOT

R_UVLOB

V_SUPPLY(ON)- V_UVLO(RISING)

(2)

A UVLO capacitor (C_UVLO) is required in case the input voltage drops below the V_SUPPLY(OFF)momentarily during

the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large,

an additional series UVLO resistor (R_UVLOS) can be used to quickly raise the voltage at the UVLO pin when the

5-μA hysteresis current turns on.

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I_UVLO

V_SUPPLY

V_UVLO

R_UVLOT

R_UVLOS

RUN

R_UVLOB

EN/UVLO/SYNC

C_UVLO

Figure 9-4. Line UVLO Using Three UVLO Resistors

Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.

9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)

The device has an internal wide input VCC regulator that is sourced from the BIAS pin. The wide input VCC

regulator allows the BIAS pin to be connected directly to supply voltages from 3.2 V to 60 V (transient protection

up to 65 V).

The VCC regulator turns on when the device is in standby or run mode. When the BIAS pin voltage is below the

VCC regulation target, the VCC output tracks the BIAS with a small dropout voltage. When the BIAS pin voltage

is greater than the VCC regulation target, the VCC regulator provides a 5-V supply (typical) for the device and

the internal N-channel MOSFET driver.

The VCC regulator sources current into the capacitor connected to the VCC pin. The recommended VCC

capacitor value is 1 µF.

The minimum supply voltage after start-up can be further decreased by supplying the BIAS pin from the boost

converter output or from an external power supply as shown in Figure 9-5. Also, this configuration allows the

device to handle more power when the V_SUPPLYis less than 5 V. Practical minimum supply voltage after start-up

is decided by the maximum duty cycle limit (D_MAX).

V_LOAD

V_SUPPLY

V_LOAD

BIAS VCC

UVLO

COMP

PGOOD

PGND AGND MODE

Figure 9-5. Decrease the Minimum Operating Voltage After Start-Up

In flyback topology, the internal power dissipation of the device can be decreased by supplying the BIAS using

an additional transformer winding, especially in PSR flyback. In this configuration, the external BIAS supply

voltage (V_AUX) must be greater than the regulation target of the external LDO, and the BIAS pin voltage must

always be greater than 3.2 V.

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V_LOAD=12V

V_SUPPLY

V_AUX=12V

<11V

V_AUX

BIAS VCC

UVLO

COMP

PGOOD

PGND AGND MODE

Figure 9-6. External BIAS Supply (PSR Flyback)

9.3.3 Soft Start (SS Pin)

The soft-start feature helps the converter gradually reach the steady state operating point, thus reducing start-up

stresses and surges. The device regulates the FB pin to the SS pin voltage or the internal reference, whichever

is lower.

At start-up, the internal 10-μA soft-start current source (I_SS) turns on after the VCC voltage exceeds the VCC

UV threshold. The soft-start current gradually increases the voltage on an external soft-start capacitor connected

to the SS pin. This results in a gradual rise of the output voltage. The SS pin is pulled down to ground by an

internal switch when the VCC is less than the VCC UVLO threshold, the UVLO is less than the UVLO threshold,

during hiccup mode off time or thermal shutdown.

In boost topology, soft-start time (t_SS) varies with the input supply voltage. The soft-start time in boost topology is

calculated as shown in Equation 3.

≈

’

◊

C_SS

V_SUPPLY

t_SS

ì 1-

∆

I_SS

V_LOAD

(3)

In SEPIC topology, the soft-start time (t_SS) is calculated as follows.

C_SS

t_SS

I_SS

(4)

TI recommends choosing the soft-start time long enough so that the converter can start up without going into an

overcurrent state. See Section 9.3.11 for more detailed information.

Figure 9-7 shows an implementation of primary-side soft start in flyback topology.

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COMP

FB SS

Figure 9-7. Primary-Side Soft Start in Flyback

Figure 9-8 shows an implementation of secondary-side soft start in flyback topology.

V_LOAD

Secondary Side

Soft-start

Figure 9-8. Secondary-Side Soft Start in Flyback

9.3.4 Switching Frequency (RT Pin)

The switching frequency of the device can be set by a single RT resistor connected between the RT and the

AGND pins. The resistor value to set the RT switching frequency (f_RT) is calculated as shown in Equation 5.

2.21ì10¹⁰

f_RT(TYPICAL)

R_T=

- 955

(5)

The RT pin is regulated to 0.5 V by the internal RT regulator when the device is enabled.

9.3.5 Dual Random Spread Spectrum – DRSS (MODE Pin)

The device provides a digital spread spectrum, which reduces the EMI of the power supply over a wide

frequency range. This function is enabled by a single resistor (37.4 kΩ or 100 kΩ) between the MODE pin

and the AGND pin or by programming the MODE pin voltage (370 mV or greater than 1.0 V) during initial

power up. When spread spectrum is enabled, the internal modulator dithers the internal clock. When an external

synchronization clock is applied to the SYNC pin, the internal spread spectrum is disabled. DRSS (a) combines

a low frequency triangular modulation profile (b) with a high frequency cycle-by-cycle random modulation profile

(c). The low frequency triangular modulation improves performance in lower radio frequency bands (for example,

the AM band), while the high frequency random modulation improves performance in higher radio frequency

bands (for example, the FM band). In addition, the frequency of the triangular modulation is further modulated

randomly to reduce the likelihood of any audible tones. In order to minimize output voltage ripple caused by

spread spectrum, duty cycle is modified on a cycle-by-cycle basis to maintain a nearly constant duty cycle when

dithering is enabled (see Figure 9-9).

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Frequency

0.156 x f_SW

(a) Low + High Frequency

Random Modulation

f_SW

(b) Low Frequency

Random Modulation

Spread Spectrum

OFF

Figure 9-9. Dual Random Spread Spectrum

9.3.6 Clock Synchronization (EN/UVLO/SYNC Pin)

The switching frequency of the device can be synchronized to an external clock by pulling down the EN/UVLO/

SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input

during the forced off time, which is determined by the maximum duty cycle limit. The external synchronization

clock must pull down the EN/UVLO/SYNC pin voltage below V_{UVLO(FALLING)}. The duty cycle of the pulldown

pulse is not limited, but the minimum pulldown pulse width must be greater than 150 ns, and the minimum

pullup pulse width must be greater than 250 ns. Figure 9-10 shows an implementation of the remote shutdown

function. The UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In

this configuration, the device stops switching immediately after the UVLO pin is grounded, and the device shuts

down 40 µs (typical) after the UVLO pin is grounded.

V_SUPPLY

MCU

UVLO/SYNC

SHUTDOWN

Figure 9-10. UVLO and Shutdown

Figure 9-11 shows an implementation of shutdown and clock synchronization functions together. In this

configuration, the device stops switching immediately when the UVLO pin is grounded, and the device shuts

down if the f_SYNCstays in high logic state for longer than 40 µs (typical) (UVLO is in low logic state for more than

40 µs (typical)). The device runs at f_SYNCif clock pulses are provided after the device is enabled.

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V_SUPPLY

MCU

UVLO/SYNC

F_SYNC

Figure 9-11. UVLO, Shutdown, and Clock Synchronization

Figure 9-13 and Figure 9-14 show implementations of standby and clock synchronization functions together. In

this configuration, The device stops switching immediately if f_SYNCstays in high logic state and enters Standby

mode if f_SYNCstays in high logic state for longer than two switching cycles. The device runs at f_SYNCif clock

pulses are provided. Because the device can be enabled when the UVLO pin voltage is greater than the enable

threshold for more than 1.5 µs, the configurations in Figure 9-13 and Figure 9-14 are recommended if the

external clock synchronization pulses are provided from the start before the device is enabled. This 1.5-µs

requirement can be relaxed when the duty cycle of the synchronization pulse is greater than 50%. Figure 9-12

shows the required minimum duty cycle to start up by synchronization pulses. When the switching frequency is

greater than 1.1 MHz, the UVLO pin voltage must be greater than the enable threshold for more than 1.5 µs

before applying the external synchronization pulse.

100 200 300 400 500 600 700 800 900 1000 1100

f_SW[kHz]

SUby

Figure 9-12. Required Duty Cycle to Start Up by External Synchronization Clock

V_SUPPLY

MCU

UVLO/SYNC

>0.7V

F_SYNC

Figure 9-13. UVLO, Standby, and Clock Synchronization (a)

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V_SUPPLY

UVLO/SYNC

MCU

F_SYNC

Figure 9-14. UVLO, Standby, and Clock Synchronization (b)

If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented

together by using one push-pull output of the MCU. In this configuration, the device shuts down if f_SYNCstays

in low logic state for longer than 40 µs (typical). The device is enabled if f_SYNCstays in high logic state for

longer than 1.5 µs. The device runs at f_SYNCif clock pulses are provided after the device is enabled. Also, in

this configuration, it is recommended to apply the external clock pulses after the BIAS is supplied. By limiting the

current flowing into the UVLO pin below 1 mA using a current limiting resistor, the external clock pulses can be

supplied before the BIAS is supplied (see Figure 9-15).

MCU

10 ꢀ

UVLO/SYNC

F_SYNC

Figure 9-15. Shutdown and Clock Synchronization

Figure 9-16 shows an implementation of inverted enable using external circuit.

V_SUPPLY

UVLO/SYNC

LMV431

Figure 9-16. Inverted UVLO

The external clock frequency (f_SYNC) must be within +25% and –30% of f_RT(TYPICAL). Because the maximum

duty cycle limit and the peak current limit with slope resistor (R_SL) are affected by the clock synchronization,

take extra care when using the clock synchronization function. See Section 9.3.7 and Section 9.3.12 for more

information.

9.3.7 Current Sense and Slope Compensation

The device senses switch current, which flows into the SW pin and provides a fixed internal slope compensation

ramp, which helps prevent subharmonic oscillation at high duty cycle. The internal slope compensation ramp is

added to the sensed switch current for the PWM operation. But, no slope compensation ramp is added to the

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sensed inductor current for the current limit operation to provide an accurate peak current limit over the input

supply voltage (see Figure 9-17).

Current Limit

Comparator

I_LIM

I_CS

1.1V+V_SLOPE

V_CS

I-to-V

Gain = A_CS

PWM

Comparator

COMP

R_COMP

C_HF

(optional)

C_COMP

Figure 9-17. Current Sensing and Slope Compensation

V_COMP

Slope

Compensation

Ramp

V_SLOPEx D + 1.1V

A_CSx I_CS

Figure 9-18. Current Sensing and Slope Compensation (a) at PWM Comparator Inputs

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I_LIM

Sensed Inductor

)

Current (I_CS

Figure 9-19. Current Sensing (b) at Current Limit Comparator Inputs

Use Equation 6 to calculate the value of the peak slope voltage (V_SLOPE).

f_RT

V_SLOPE= 500mV ì

f_SYNC

(6)

where

•

f_SYNCis f_RTif clock synchronization is not used.

According to peak current mode control theory, the slope of the compensation ramp must be greater than half

of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the

minimum amount of slope compensation in boost topology must satisfy the following inequality:

_LOAD+ V_F- V

(

)

L_M

SUPPLY

0.5ì

ì A_CSìMargin < 500mV ì f_SW

(7)

where

V_Fis a forward voltage drop of D1, the external diode.

•

Typically 82% of the sensed inductor current falling slope is known as an optimal amount of the slope

compensation. By increasing the margin to 1.6, the amount of slope compensation becomes close to the optimal

amount.

If clock synchronization is not used, the f_SWfrequency equals the f_RTfrequency. If clock synchronization is used,

the f_SWfrequency equals the f_SYNCfrequency.

9.3.8 Current Limit and Minimum On Time

The device provides cycle-by-cycle peak current limit protection that turns off the internal MOSFET when the

inductor current reaches the current limit threshold (I_LIM). To avoid an unexpected hiccup mode operation during

a harsh load transient condition, it is recommended to have more margin when programming the peak-current

limit.

Boost converters have a natural pass-through path from the supply to the load through the high-side power

diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot

provide current limit protection when the output voltage is close to or less than the input supply voltage. The

minimum on time is shown in Figure 8-15 and is calculated as Equation 8.

−15

800 × 10

≥ 20.83kΩ

−6

+ 4 × 10

8 × R

≈

(8)

ON MIN

−9

80 × 10

R < 20.83kΩ

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9.3.9 Feedback and Error Amplifier (FB, COMP Pin)

The feedback resistor divider is connected to an internal transconductance error amplifier, which features high

output resistance (R_O= 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error

amplifier sources current, which is proportional to the difference between the FB pin and the SS pin voltage or

the internal reference, whichever is lower. The internal transconductance error amplifier provides symmetrical

sourcing and sinking capability during normal operation and reduces its sinking capability when the FB is greater

than OVP threshold.

To set the output regulation target, select the feedback resistor values as shown in Equation 9.

≈

∆

’

R_FBT

R_FBB

V_LOAD= V_REF

◊

(9)

The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation

network. R_COMP, C_COMP, and optional C_HFloop compensation components configure the error amplifier gain and

phase characteristics to achieve a stable loop response. The absolute maximum voltage rating of the FB pin is

4.0 V. If necessary, the feedback resistor divider input can be clamped by using an external Zener diode.

The COMP pin features internal clamps. The maximum COMP clamp limits the maximum COMP pin voltage

below its absolute maximum rating even in shutdown. The minimum COMP clamp limits the minimum COMP

pin voltage in order to start switching as soon as possible during no load to heavy load transition. The minimum

COMP clamp is disabled when FB is connected to ground in flyback topology.

9.3.10 Power-Good Indicator (PGOOD Pin)

The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches

to a high impedance open-drain state when the FB pin voltage is greater than the feedback undervoltage

threshold (V_UVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than

the EN threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The

recommended minimum pullup resistor value is 10 kΩ.

Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater

than V_BIAS+ 0.3 V.

9.3.11 Hiccup Mode Overload Protection (MODE Pin)

To further protect the converter during prolonged current limit conditions, the device provides a selectable hiccup

mode overload protection. This function is enabled by a single resistor (37.4 kΩ or 62.0 kΩ) between the MODE

pin and the AGND pin or by programming the MODE pin voltage (370 mV or 620 mV) during initial power

up. The internal hiccup mode fault timer of the device counts the PWM clock cycles when the cycle-by-cycle

current limiting occurs after soft start is finished. When the hiccup mode fault timer detects 64 cycles of current

limiting, an internal hiccup mode off timer forces the device to stop switching and pulls down SS. Then, the

device restarts after 32,768 cycles of hiccup mode off time. The 64 cycle hiccup mode fault timer is reset if eight

consecutive switching cycles occur without exceeding the current limit threshold. The soft-start time must be long

enough not to trigger the hiccup mode protection after the soft start is finished.

4 cycles of

current limit

7 normal

switching

cycles

32768 hiccup

mode off cycles

64 cycles of

current limit

60 cycles of

current limit

32768 hiccup

mode off cycles

Inductor Current

Time

Figure 9-20. Hiccup Mode Overload Protection

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9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage

The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense

resistor. The estimated duty cycle is calculated as shown in Equation 10.

V_SUPPLY

D = 1-

V_LOAD+ V_F

(10)

When designing boost converters, the maximum required duty cycle must be reviewed at the minimum supply

voltage. The minimum input supply voltage that can achieve the target output voltage is limited by the maximum

duty cycle limit, and it can be estimated as follows.

V_SUPPLY(MIN)ö V_LOAD+ V_Fì 1-D

+I_SUPPLY(MAX)ìR_DCR+I_SUPPLY(MAX)ì110mìD_MAX

(

)

(

)

MAX

(11)

where

•

I_SUPPLY(MAX)is the maximum input current.

R_DCRis the DC resistance of the inductor.

f_SYNC

D_MAX1= 1- 0.1ì

f_RT

(12)

(13)

D_MAX2= 1-100nsì f_SW

The minimum input supply voltage can be further decreased by supplying f_SYNC, which is less than f_RT. Practical

D_MAXis D_MAX1or D_MAX2, whichever is lower.

9.3.13 Internal MOSFET (SW Pin)

The device provides an internal switch where r_DS(ON)is typically 133 mΩ when the BIAS pin is greater than 5 V.

The r_DS(ON)of the internal switch is increased when the BIAS pin is less than 5 V. The device temperature must

be checked at the minimum supply voltage especially when the BIAS pin is less than 5 V.

The dV/dT of the SW pin must be limited during the 90-µs internal start-up delay to avoid a false turn-on, which

is caused by the coupling through C_DGparasitic capacitance of the internal MOSFET switch.

9.3.14 Overvoltage Protection (OVP)

The device has OVP for the output voltage. OVP is sensed at the FB pin. If the voltage at the FB pin rises above

the overvoltage threshold (V_OVTH), OVP is triggered and switching stops. During OVP, the internal error amplifier

is operational, but the maximum source and sink capability is decreased to 60 µA.

9.3.15 Thermal Shutdown (TSD)

An internal thermal shutdown turns off the VCC regulator, disables switching, and pulls down the SS when

the junction temperature exceeds the thermal shutdown threshold (T_TSD). After the junction temperature is

decreased by 15°C, the VCC regulator is enabled again and the device performs a soft start.

9.4 Device Functional Modes

9.4.1 Shutdown Mode

If the EN/UVLO/SYNC pin voltage is below V_ENfor longer than 40 µs (typical), the device goes into shutdown

mode with all functions disabled. In shutdown mode, the device decreases the BIAS pin current consumption to

below 2.6 μA (typical).

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9.4.2 Standby Mode

If the EN/UVLO/SYNC pin voltage is greater than V_ENand below V_UVLOfor longer than 1.5 µs, the device enters

standby mode with the VCC regulator operational, the RT regulator operational, the SS pin grounded, and no

switching. The PGOOD is activated when the VCC voltage is greater than the VCC UV threshold.

9.4.3 Run Mode

If the UVLO pin voltage is above V_UVLOand the VCC voltage is sufficient, the device enters run mode.

9.4.3.1 Spread Spectrum Enabled

The spread spectrum function is enabled by a single resistor (37.4 kΩ ±5% or 100 kΩ ±5%) between the MODE

pin and the AGND pin or by programming the MODE pin voltage (370mV ±10% or greater than 1.0 V) during

initial power up. To switch the spread spectrum function, EN must be grounded for more than 60 μs or VCC must

be fully discharged.

9.4.3.2 Hiccup Mode Protection Enabled

Hiccup mode protection is enabled by a single resistor (37.4 kΩ ±5% or 62.0 kΩ ±5%) between the MODE pin

and the AGND pin or by programming the MODE pin voltage (370 mV ±10% or 620 mV ±10%) during initial

power up. To switch the hiccup mode protection function, EN must be grounded for more than 60 μs or VCC

must be fully discharged.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

TI provides application notes explaining how to design boost and flyback converters using the device. These

comprehensive application notes include component selections and loop response optimization.

See these application reports for more information on loop response and component selection:

•

How to Design a Boost Converter Using LM5157x / LM5158x

How to Design an Isolated Flyback Converter Using LM5157x / LM5158x

10.2 Typical Boost Application

Figure 10-1 shows all optional components to design a boost converter.

R_SNBC_SNB

L_M

V_LOAD

V_SUPPLY

R_BIAS

C_BIAS

C_VCC

C_IN

C_OUT1C_OUT2

R_UVLOT

R_UVLOS

BIAS

VCC

R_LOAD

R_FBT

UVLO

PGOOD

COMP

MCU_VCC

C_HF

R_UVLOB

R_T

R_FBB

C_SS

C_UVLO

PGND AGND MODE

R_COMP

C_COMP

R_MODE

Figure 10-1. Typical Boost Converter Circuit with Optional Components

10.2.1 Design Requirements

Table 10-1 shows the intended input, output, and performance parameters for this application example.

Table 10-1. Design Example Parameters

DESIGN PARAMETER

VALUE

6 V

Minimum input supply voltage (V_SUPPLY(MIN)

)

Target output voltage (V_LOAD

Maximum load current (I_LOAD

Typical switching frequency (f_SW

)

12 V

)

1.2 A (≈ 14.4 Watt)

2100 kHz

)

10.2.2 Detailed Design Procedure

Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application.

Download these Quick Start Calculator for more information on loop response and component selection:

•

LM5158x-Q1 Excel Quickstart Calculator for Boost Converter Design

LM5158x-Q1 Excel Quickstart Calculator for isolated Flyback Converter Design

LM5158x-Q1 Excel Quickstart Calculator for SEPIC Converter Design

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The device is also WEBENCH® Designer enabled. The WEBENCH software uses an iterative design procedure

and accesses comprehensive data bases of components when generating a design.

10.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5158x device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2.2.2 Recommended Components

Table 10-2 shows a recommended list of materials for this typical application.

Table 10-2. List of Materials

REFERENCE

DESIGNATOR

QTY.

SPECIFICATION

MANUFACTURER⁽¹⁾

PART NUMBER

R_T

RES, 9.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 49.9 k, 1%, 0.1 W, 0603

Vishay-Dale

Yageo America

Vishay-Dale

CRCW06039K53FKEA

RC0603FR-0749K9L

CRCW06034K53FKEA

R_FBT

R_FBB

RES, 4.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

Inductor, Shielded, Composite, 1.5 μH, 14 A,

0.01052 Ω, AEC-Q200 Grade 1, SMD

L_M

C_OUT1

Coilcraft

TDK

XEL6030-152MEB

C3225X7R1H475K250AB

HHXB500ARA101MJA0G

GRM32ER71H106KA12L

EEE-FK2A220P

CAP, CERM, 4.7 µF, 50 V, ±10%, X7R, 1210

CAP, Aluminum Polymer, 100 µF, 50 V, ±20%, 0.025

Ω, AEC-Q200 Grade 2, D10xL10mm SMD

C_OUT2(Bulk)

C_IN1

Chemi-Con

MuRata

CAP, CERM, 10 µF, 50 V, ±10%, X7R, 1210

CAP, AL, 22 μF, 100 V, ±20%, 1.3 Ω, AEC-Q200

Grade 2, SMD

C_IN2(Bulk)

Panasonic

Diode, Schottky, 45 V, 10 A, AEC-Q101, CFP15

RES, 2.61 k, 1%, 0.1 W, 0603

Nexperia

Yageo America

Kemet

PMEG045V100EPDAZ

RC0603FR-072K61L

C0603X103K5RACTU

R_COMP

C_COMP

CAP, CERM, 0.01 μF, 50 V, ±10%, X7R, 0603

CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, AEC-

Q200 Grade 0, 0603

C_HF

TDK

CGA3E2NP01H101J080AA

R_UVLOT

R_UVLOB

R_UVLOS

C_SS

RES, 61.9 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 71.5 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 0, 5%, 0.1 W, 0603

Vishay-Dale

Yageo America

Kemet

CRCW060361K9FKEA

CRCW060371K5FKEA

RC0603JR-070RL

CAP, CERM, 0.022 μF, 50 V, ±10%, X7R, 0603

RES, 0, 5%, 0.1 W, 0603

C0603X223K5RACTU

RC0603JR-070RL

R_BIAS

Yageo America

CAP, CERM, 0.1 μF, 100 V, ±10%, X7R, AEC-Q200

Grade 1, 0603

C_BIAS

C_VCC

MuRata

TDK

GCJ188R72A104KA01D

CAP, CERM, 1 µF, 16 V, ±10%, X7R, AEC-Q200

Grade 1, 0603

CGA3E1X7R1C105K080AC

R_PG

RES, 100 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

RES, 0, 5%, 0.1 W, 0603

Vishay-Dale

CRCW0603100KFKEA

RC0603JR-070RL

R_MODE

Yageo America

(1) See the Third-Party Products Disclaimer.

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10.2.2.3 Inductor Selection (L_M)

When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the

inductor current, and RHP zero frequency (f_RHP).

The inductor current ripple ratio is selected to have a balance between core loss and copper loss. The

falling slope of the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle

(additional R_SLresistor is required if not). Higher f_RHP(equal to lower inductance) allows a higher crossover

frequency and is always preferred when using a small value output capacitor.

The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average

inductor current as a good compromise between RR, F_RHP, and inductor falling slope.

10.2.2.4 Output Capacitor (C_OUT

)

There are a few ways to select the proper value of output capacitor (C_OUT). The output capacitor value can be

selected based on output voltage ripple, output overshoot, or undershoot due to load transient.

The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using

multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the

diode and the MOSFET than the bulk aluminum capacitors in order to absorb the majority of the ripple current.

10.2.2.5 Input Capacitor

The input capacitors decrease the input voltage ripple. The required input capacitor value is a function of the

impedance of the source power supply. More input capacitors are required if the impedance of the source power

supply is not low enough.

10.2.2.6 Diode Selection

A Schottky is the preferred type for D1 diode due to its low forward voltage drop and small reverse recovery

charge. Low reverse leakage current is important parameter when selecting the Schottky diode. The diode must

be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to handle

the average output current. For the optimal performance, it is highly recommended to use a diode with a junction

capacitance lower than 1 nF at 0 V.

10.2.3 Application Curve

100%

95%

90%

85%

80%

75%

70%

65%

60%

VIN = 3.5 V

VIN = 4 V

VIN = 6 V

VIN = 9 V

55%

50%

0.2

0.4

0.6

0.8

1.2

I_OUT(A)

Figure 10-2. Efficiency Versus Output Current

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10.3 System Examples

V_LOAD

V_SUPPLY

BIAS VCC

UVLO

COMP

PGOOD

PGND AGND MODE

Figure 10-3. Typical Boost Application

V_LOAD

V_SUPPLY

BIAS VCC

UVLO

COMP

PGOOD

PGND AGND MODE

Figure 10-4. Typical SEPIC Application

Inductance should be small enough

to operate in DCM at full load

V_LOAD= 15V - 83V

V_{SUPP LY}

BIAS VCC

UVLO

COMP

From MCU

PGOOD

PGND AGND MODE

Figure 10-5. LIDAR Bias Supply 1 (DCM Operation)

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V_LOAD

= 90V - 249V

Voltage

Tripler

Inductance should be big enough

to operate in CCM

V_SUPPLY

BIAS VCC

From MCU

UVLO

COMP

PGOOD

PGND AGND MODE

Figure 10-6. LIDAR Bias Supply 2 (CCM Operation)

V_SUPPLY

V_LOAD

BIAS VCC

UVLO

COMP

PGOOD

PGND AGND MODE

Enable Spread Spectrum

Figure 10-7. Low-Cost Single String LED Driver

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V_SUPPLY

_LOAD= 5V/12V

BIAS

UVLO/SYNC

PGND

AGND

VCC

PGOOD

MODE

COMP

Optional Primary-Side

Soft-Start

Figure 10-8. Secondary-Side Regulated Isolated Flyback

V_LOAD2= +12V

V_SUPPLY

V_LOAD3= -8.5V

BIAS

UVLO/SYNC

Optional DC Coupling

Capacitor for Low EMI

Isolated Sepic

AGND

PGND

To MCU

System Power

PGOOD

MODE

_LOAD1= 3.3V/5V +/-2%

COMP

VCC

Figure 10-9. Primary-Side Regulated Multiple-Output Isolated Flyback/Isolated SEPIC

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V_SUPPLY

_LOAD= 5V/12V

BIAS

UVLO/SYNC

PGND

AGND

To MCU

System Power

PGOOD

MODE

VCC

COMP

Figure 10-10. Typical Non-Isolated Flyback

11 Power Supply Recommendations

The device is designed to operate from a power supply or a battery with a voltage range from 1.5 V to 60 V. The

input power supply must be able to supply the maximum boost supply voltage and handle the maximum input

current at 1.5 V. The impedance of the power supply and battery including cables must be low enough that an

input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required at

the supply input of the converter.

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12 Layout

12.1 Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. The following

guidelines can help users design a PCB with the best power conversion performance, thermal performance, and

minimize generation of unwanted EMI.

•

Put the D1 component on the board first.

Use a small size ceramic capacitor for C_OUT

Make the switching loop (C_OUTto D1 to SW to PGND to C_OUT) as small as possible.

Leave a copper area near the D1 diode for thermal dissipation.

Put the C_VCCcapacitor as near the device as possible between the VCC and PGND pins.

Connect the COMP pin to the compensation components (R_COMPand C_COMP).

Connect the C_COMPcapacitor to the analog ground trace.

Connect the AGND pin directly to the analog ground plane. Connect the AGND pin to the R_MODE, R_UVLOB, R_T,

C_SS, and R_FBBcomponents.

•

Add several vias under the exposed pad to help conduct heat away from the device. Connect the vias to a

large ground plane on the bottom layer.

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12.2 Layout Examples

Thermal Dissipation

Area

V_SUPPLY

GND

V_LOAD

Do not connect input and output

capacitor grounds underneath the

device

C_VIN

L_M

C_OUT2

C_OUT1

GND

C_VIN

Power Ground Plane

(Connect to EP via PGND pin)

16 15 14 13

Connect to the ground connection of

C_OUTusing inner layer

Connect

to V_LOAD

C_VCC

PGND

12 NC

R_MODE

MODE

VCC

BIAS

Connect to

V_LOAD

V_SUPPLY

Connect to the ground connection

of C_INusing inner layer

10 SS

C_SS

PGOOD

R_FBB

Connect to

pull-up

resistor

R_COMP

C_COMP

R_T

Analog Ground Plane

(Connect to EP via AGND pin)

Connect

V_SUPPLY

R_UVLOT

Figure 12-1. PCB Layout Example

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.1.2 Development Support

For development support see the following:

•

LM5157x / LM5158x Boost Quick Start Calculator

LM5157x / LM5158x Flyback Quick Start Calculator

LM5157x / LM5158x SEPIC Quick Start Calculator

How to Design a Boost Converter Using LM5157x / LM5158x

How to Design an Isolated Flyback Converter Using LM5157x / LM5158x

13.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5158x device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, LM5158Q1EVM-BST User's Guide

Texas Instruments, LM5158Q1EVM-FLY User's Guide

Texas Instruments, LM5158Q1EVM-SEPIC User's Guide

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

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WEBENCH^®is a registered trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

23-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM51581RTER

LM5158RTER

ACTIVE

WQFN

RTE

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

L51581

LM5158

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Oct-2021

OTHER QUALIFIED VERSIONS OF LM5158, LM51581 :

Automotive : LM5158-Q1, LM51581-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM51581RTER

LM5158RTER

WQFN

RTE

3000

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM51581RTER

LM5158RTER

WQFN

RTE

3000

367.0

35.0

Pack Materials-Page 2

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LM5158 [TI]

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