LM5163H-Q1 [TI]
具有超低 IQ 的 100V 输入、0.5A 同步高温降压直流/直流转换器;
| 型号： | LM5163H-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有超低 IQ 的 100V 输入、0.5A 同步高温降压直流/直流转换器 转换器 |
| 文件： | 总36页 (文件大小：2912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5163H-Q1
ZHCSKN8A –DECEMBER 2019 –REVISED APRIL 2023
LM5163H-Q1 具有165°C 结温的100V、0.5A、10.5µA IQ 汽车类降压转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
动力总成系统中的冷却液可能很昂贵。随着制造商通过
减少系统中冷却液（水、空气）的使用来降低成本的现
实要求，动力总成对环境温度的要求不断提高。此外，
ADAS（摄像头模块）和动力总成中的耗电系统通常在
小机壳中需要较高的输出功率。这些要求促使直流/直
流转换器需要在高环境温度下工作，从而导致结温超过
150°C。LM5163H-Q1 同步降压转换器设计用于在最
高 165°C 的高温结温下工作，可实现支持高环境温度
和输出功率规格的高密度解决方案。LM5163H-Q1 可
在较宽的输入电压范围内工作，从而最大限度地减少了
对外部浪涌抑制器件的需求。
– 器件温度等级1：–40°C 至+125°C 的环境温
度范围
• 专为可靠耐用的应用而设计
– 6V 至100V 的宽输入电压范围
– 结温范围：-40°C 至+165°C
– 165°C 的热关断保护
– 峰值和谷值电流限制保护
– 输入UVLO 和固定的3ms 软启动
• 针对超低EMI 要求进行了优化
– 符合CISPR 25 5 类标准
• 适用于可扩展的汽车电源
50ns 的最短可控导通时间有助于实现较大的降压比，
支持从 48V 标称输入到低电压轨的直接降压转换，从
而降低系统的复杂性并减少解决方案成本。LM5163H-
Q1 能够在输入电压突降至 6V 时根据需要以接近
100% 的占空比继续工作，因而是高性能 48V 电池汽
车应用和MHEV/EV 系统的理想选择。
– 最短导通时间和关闭时间低：50ns
– 高达1MHz 的可调节开关频率
– 可实现高轻负载效率的二极管仿真
– 10.5µA 空载输入静态电流
– 3µA 关断静态电流
• 通过集成技术减小解决方案尺寸，降低成本
LM5163H-Q1 具有比汽车 AEC-Q100 1 级标准更高的
温度曲线，并采用8 引脚SO PowerPAD™ 集成电路封
装。该器件的 1.27mm 引脚间距可以为高电压应用提
供足够的间距。
– COT 模式控制架构
– 集成式0.725ΩNFET 降压开关
– 集成式0.34ΩNFET 同步整流器省去了外部肖
特基二极管
– 1.2V 内部电压基准
– 无环路补偿组件
封装信息
封装(1)
封装尺寸（标称值）
器件型号
– 内部VCC 偏置稳压器和自举二极管
• 使用WEBENCH® Power Designer 创建定制稳压器
设计
DDA（SO PowerPAD，
8）
LM5163H-Q1
4.89mm × 3.90mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 汽车48V 轻混合动力ECU 偏置电源
• HEV/EV 直流/直流转换器
• 汽车高温ADAS 应用
100
95
90
85
80
75
VOUT = 12 V
IOUT = 0.5 A
LO
U1
120 µH
VIN = 6 V...100 V
VIN
SW
CBST
2.2 nF
LM5163H-Q1
CIN
RFB1
2.2 µF
EN/UVLO
RON
BST
448 kW
COUT
22 µF
70
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
FB
RRON
65
60
RFB2
100 kW
49.9 kW
PGOOD
GND
0.001
0.01
0.1
0.5
D001
Load (A)
典型应用效率，VOUT = 12V
*VOUT tracks VIN if VIN < 12 V
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBN8
LM5163H-Q1
ZHCSKN8A –DECEMBER 2019 –REVISED APRIL 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................15
8 Application and Implementation..................................16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 17
8.3 Power Supply Recommendations.............................24
8.4 Layout....................................................................... 24
9 Device and Documentation Support............................28
9.1 Device Support......................................................... 28
9.2 Documentation Support............................................ 28
9.3 接收文档更新通知..................................................... 29
9.4 支持资源....................................................................29
9.5 Trademarks...............................................................29
9.6 静电放电警告............................................................ 29
9.7 术语表....................................................................... 29
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................10
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2019) to Revision A (April 2023)
Page
• 更新了数据表标题...............................................................................................................................................1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Remove maximum specifications for IQ-SHUTDOWN, IQ-SLEEP1, IQ-ACTIVE ............................................................ 5
• Updated trademark information.......................................................................................................................... 9
• Removed random color from image................................................................................................................. 12
• Removed random color in image......................................................................................................................27
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English Data Sheet: SNVSBN8
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5 Pin Configuration and Functions
GND
SW
1
8
VIN
BST
2
3
7
6
EP
EN/UVLO
PGOOD
RON
FB
4
5
图5-1. DDA Package 8-Pin SO PowerPAD™ Integrated Circuit Package Top View
表5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
1
GND
G
Ground connection for internal circuits
Regulator supply input pin to high-side power MOSFET and internal bias regulator. Connect directly
to the input supply of the buck converter with short, low impedance paths.
2
3
VIN
P/I
Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is
below 1.1 V, the converter is in shutdown mode with all functions disabled. If the UVLO voltage is
greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal VCC
regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up
sequence begins.
EN/UVLO
I
4
5
RON
FB
I
I
On-time programming pin. A resistor between this pin and GND sets the buck switch on-time.
Feedback input of voltage regulation comparator
Power good indicator. This pin is an open-drain output pin. Connect to a source voltage through an
external pullup resistor between 10 kΩto 100 kΩ.
6
7
PGOOD
BST
O
Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF 50-V X7R ceramic capacitor
between BST and SW to bias the internal high-side gate driver.
P/I
Switching node that is internally connected to the source of the high-side NMOS buck switch and
the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power
inductor.
8
SW
EP
P
Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and
connect to a large copper plane to reduce thermal resistance.
—
—
(1) G = Ground, I = Input, O = Output, P = Power
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English Data Sheet: SNVSBN8
LM5163H-Q1
ZHCSKN8A –DECEMBER 2019 –REVISED APRIL 2023
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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +165°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
100
100
5.5
UNIT
VIN to GND
EN to GND
FB to GND
RON to GND
Input voltage
V
5.5
Bootstrap
capacitor
External BST to SW capacitance
1.5
2.5
nF
V
BST to GND
105.5
5.5
–0.3
–0.3
–1.5
–3
BST to SW
Output voltage
SW to GND
100
SW to GND (20-ns transient)
PGOOD to GND
14
165
150
–0.3
–40
–65
Operating junction temperature, TJ
Storage temperature, Tstg
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC-Q100-002
HBM ESD Classification Level 2, all pins (1)
±2000
V
Electrostatic
discharge
Charged device model (CDM), per AEC-Q100-011
CDM ESD Classification level C4B. All pins except 1, 4, 5, and 8
V(ESD)
±500
±750
Charged device model (CDM), per AEC-Q100-011
CDM ESD Classification level C4B. Pins 1, 4, 5, and 8
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to +165°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
VIN
Input voltage
6
100
VSW
Switch node voltage
Enable voltage
100
V
VEN/UVLO
FSW
CBST
tON
100
V
Switching frequency
External BST to SW capacitance
Programmable on-time
1000
kHz
nF
ns
2.2
50
10000
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6.4 Thermal Information
LM5163H-Q1
THERMAL METRIC(1)
DDA (SOIC)
8 PINS
43.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
59.5
16.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.0
ΨJT
16.3
ΨJB
RθJC(bot)
3.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the full –40°C to 165°C junction
temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER
SUPPLY CURRENT
IQ-SHUTDOWN VIN shutdown current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VEN = 0 V
3
10.5
600
µA
µA
µA
IQ-SLEEP1
IQ-ACTIVE
EN/UVLO
VSD-RISING
VSD-FALLING
VEN-RISING
VEN-FALLING
FEEDBACK
VREF
VIN sleep current
VIN active current
VEN = 2.5 V, VFB = 1.5 V
VEN = 2.5 V
Shutdown threshold
Shutdown threshold
Enable threshold rising
Enable threshold falling
VEN/UVLO rising
VEN/UVLO falling
VEN/UVLO rising
VEN/UVLO falling
1.1
V
V
V
V
0.45
1.45
1.35
1.5
1.4
1.55
1.44
FB regulation voltage
VFB falling
1.181
1.2
1.218
V
TIMING
tON1
On-time1
On-time2
On-time3
On-time4
5000
1650
2550
830
ns
ns
ns
ns
VVIN = 6 V, RRON = 75 kΩ
VVIN = 6 V, RRON = 25 kΩ
VVIN = 12 V, RRON = 75 kΩ
VVIN = 12 V, RRON = 25 kΩ
tON2
tON3
tON4
PGOOD
FB upper threshold for PGOOD high to
low
VPG-UTH
VPG-LTH
VPG-HYS
VFB rising
VFB falling
1.105
1.055
1.14
1.08
1.175
1.1
V
V
FB lower threshold for PGOOD high to
low
PGOOD upper and lower threshold
hysteresis
VFB falling
VFB = 1 V
60
30
mV
RPG
PGOOD pulldown resistance
Ω
BOOTSTRAP
VBST-UV
Gate drive UVLO
VBST rising
2.7
3.4
V
POWER SWITCHES
RDSON-HS High-side MOSFET RDSON
RDSON-LS Low-side MOSFET RDSON
0.725
0.33
ISW = –100 mA
Ω
Ω
ISW = 100 mA
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English Data Sheet: SNVSBN8
LM5163H-Q1
ZHCSKN8A –DECEMBER 2019 –REVISED APRIL 2023
www.ti.com.cn
6.5 Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the full –40°C to 165°C junction
temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START
tSS
Internal soft-start time
1.75
3
4.75
ms
CURRENT LIMIT
IPEAK1
Peak current limit threshold (HS)
0.63
0.63
0.75
0.75
100
0.6
0.87
0.87
A
A
IPEAK2
Peak current limit threshold (LS)
Min of (IPEAK1 or IPEAK2) minus IVALLEY
Valley current limit threshold
IDELTA-ILIM
IVALLEY
mA
A
0.5
0.72
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
175
10
°C
°C
TSD-HYS
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6.6 Typical Characteristics
At TA = 25°C, VOUT = 12 V, LO = 120 µH, RRON = 105 kΩ, unless otherwise specified.
100
95
90
85
80
75
70
65
60
100
90
80
70
60
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
0.001
0.01
0.1
0.5
0
0.1
0.2
0.3
0.4
0.5
Load (A)
Load (A)
D001
D002
图6-1. Conversion Efficiency (Log Scale)
图6-2. Conversion Efficiency (Linear Scale)
30
25
20
15
10
5
25
20
15
10
5
Sleep
Shutdown
Sleep
Shutdown
0
0
-40
-10
20
50
80
110
140
165
0
10
20
30
40
Input Voltage (V)
50
60
70
80
90 100
Junction Temperature (èC)
D005
D006
图6-3. VIN Shutdown and Sleep Supply Current versus
图6-4. VIN Shutdown and Sleep Supply Current versus Input
Temperature
Voltage
700
675
650
625
600
575
550
525
600
580
560
540
520
500
-40
-10
20
50
80
110
140
165
0
10
20
30
40
Input Voltage (V)
50
60
70
80
90 100
Junction Temperature (èC)
D007
D008
图6-5. VIN Active Current versus Temperature
图6-6. VIN Active Current versus Input Voltage
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6.6 Typical Characteristics (continued)
At TA = 25°C, VOUT = 12 V, LO = 120 µH, RRON = 105 kΩ, unless otherwise specified.
1.21
1.205
1.2
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1.195
High-Side FET
Low-Side FET
1.19
-40
-10
20
50
80
110
140
165
-40
-10
20
50
80
110
140
165
Junction Temperature (èC)
Junction Temperature (èC)
D009
D010
图6-7. Feedback Comparator Threshold versus Temperature
图6-8. MOSFETs On-State Resistance versus Temperature
6
0.8
RRT = 105 kW
RRT = 43.2 kW
5
4
3
2
1
0
0.7
0.6
Peak Current
Valley Current
0
10
20
30
40
50
60
Input Voltage (V)
70
80
90 100
0.5
-40
D012
-10
20
50
80
110 140 165
图6-10. COT On-Time versus VIN
Junction Temperature (èC)
D011
图6-9. Peak and Valley Current Limit versus Temperature
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7 Detailed Description
7.1 Overview
The LM5163H-Q1 is an easy-to-use, ultra-low IQ constant on-time (COT) synchronous step-down buck regulator.
With integrated high-side and low-side power MOSFETs, the LM5163H-Q1 is a low-cost, highly efficient buck
converter that operates from a wide input voltage of 6 V to 100 V, delivering up to 0.5-A DC load current. The
LM5163H-Q1 is available in an 8-pin SO PowerPAD integrated circuit package with 1.27-mm pin pitch for
adequate spacing in high-voltage applications. This constant on-time (COT) converter is designed for low-noise,
high-current, and fast load transient requirements, operating with a predictive on-time switching pulse. Over the
input voltage range, input voltage feedforward is employed to achieve a quasi-fixed switching frequency. A
controllable on-time as low as 50 ns permits high step-down ratios and a minimum forced off-time of 50 ns
provides extremely high duty cycles, allowing VIN to drop close to VOUT before frequency foldback occurs. At light
loads, the device transitions into an ultra-low IQ mode to maintain high efficiency and prevent draining battery
cells connected to the input when the system is in standby. The LM5163H-Q1 implements a smart peak and
valley current limit detection circuit to ensure robust protection during output short-circuit conditions. Control loop
compensation is not required for this regulator, reducing design time and external component count.
The LM5163H-Q1 incorporates additional features for comprehensive system requirements, including an open-
drain power good circuit for the following:
• Power-rail sequencing and fault reporting
• Internally-fixed soft start
• Monotonic start-up into prebiased loads
• Precision enable for programmable line undervoltage lockout (UVLO)
• Smart cycle-by-cycle current limit for optimal inductor sizing
• Thermal shutdown with automatic recovery
These features enable a flexible and easy-to-use platform for a wide range of applications. The LM5163H-Q1
supports a wide range of end-equipment systems requiring a regulated output from a high input supply with the
ability to support high output power at high ambient temperatures. The following are examples of such end
equipment systems:
• 48-V automotive mild-hybrid systems
• High-temperature Automotive ADAS and powertrain systems
The pin arrangement is designed for a simple layout requiring only a few external components.
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7.2 Functional Block Diagram
VIN
VIN
VDD
BIAS
REGULATOR
CIN
VDD UVLO
RUV1
EN/UVLO
STANDBY
œ
+
THERMAL
RUV2
SHUTDOWN
1.5 V
SHUTDOWN
œ
+
BST
LOGIC
0.4 V
VIN
CBST
RON
ON/OFF
TIMERS
DISABLE
CONSTANT
ON-TIME
CONTROL
LOGIC
VOUT
LO
VOUT
SW
VCC
RFB1
FEEDBACK
COMPARATOR
SLEEP
COUT
FB
DETECT
œ
+
ZC
RRON
VREF
+
PGOOD
ZX DETECT
œ
RFB2
PEAK/VALLEY
CURRENT LIMIT
FB
œ
+
GND
PGOOD
COMPARATOR
0.9*VREF
7.3 Feature Description
7.3.1 Control Architecture
The LM5163H-Q1 step-down switching converter employs a constant on-time (COT) control scheme. The COT
control scheme sets a fixed on-time tON of the high-side FET using a timing resistor (RON). The tON is adjusted as
Vin changes and is inversely proportional to the input voltage to maintain a fixed frequency when in continuous
conduction mode (CCM). After tON expires, the high-side FET remains off until the feedback pin is equal or below
the reference voltage of 1.2 V. To maintain stability, the feedback comparator requires a minimal ripple voltage
that is in phase with the inductor current during the off-time. Furthermore, this change in feedback voltage during
the off-time must be large enough to dominate any noise present at the feedback node. The minimum
recommended ripple voltage is 20 mV. See 表 7-1 for different types of ripple injection schemes that ensure
stability over the full input voltage range.
During a rapid start-up or a positive load step, the regulator operates with minimum off-times until regulation is
achieved. This feature enables extremely fast load transient response with minimum output voltage undershoot.
When regulating the output in steady-state operation, the off-time automatically adjusts itself to produce the SW-
pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. In CCM, the
switching frequency FSW is programmed by the RRON resistor. Use 方程式1 to calculate the switching frequency.
V
V × 2500
OUT
R
F
kHz =
(1)
SW
kΩ
RON
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表7-1. Ripple Generation Methods
TYPE 1
TYPE 2
TYPE 3
Lowest Cost
Reduced Ripple
Minimum Ripple
LO
LO
LO
VOUT
VOUT
VIN
VIN
VOUT
VIN
VIN
SW
VIN
SW
VIN
SW
RA
CA
LM5163H-Q1
LM5163H-Q1
CBST
CBST
LM5163H-Q1
CFF
CIN
CIN
CBST
RFB1
RFB1
RESR
RESR
EN/UVLO
BST
EN/UVLO
BST
EN/UVLO
BST
RFB1
COUT
CB
FB
FB
RON
RON
FB
RON
RFB2
COUT
RFB2
COUT
RRON
RRON
RRON
RFB2
PGOOD
PGOOD
GND
GND
PGOOD
GND
10
× R
FB1
C
≥
(7)
A
20mV
∆ I
F
R
SW
FB2
R
≥
(4)
ESR
L nom
20mV × V
× ∆ I
OUT
R
R
≥
≥
(2)
ESR
R × C
(8)
V
A
A
FB1
L nom
V
OUT
V
− V
OUT
× t
R
C
≥
(5)
(6)
IN − nom
ON @V
IN − nom
ESR
2 × V × F
× C
IN
SW
OUT
≤
V
20mV
OUT
(3)
ESR
2 × V × F
IN SW
× C
OUT
1
≥
t
FF
TR − settling
2π × F
SW
× R
FB1
R
FB2
C
≥
(9)
B
3 × R
FB1
表 7-1 presents three different methods for generating appropriate voltage ripple at the feedback node. The
type-1 ripple generation method uses a single resistor, RESR, in series with the output capacitor. The generated
voltage ripple has two components: capacitive ripple caused by the inductor ripple current charging and
discharging the output capacitor and resistive ripple caused by the inductor ripple current flowing into the output
capacitor and through series resistance RESR. The capacitive ripple component is out of phase with the inductor
current and does not decrease monotonically during the off-time. The resistive ripple component is in phase with
the inductor current and decreases monotonically during the off-time. The resistive ripple must exceed the
capacitive ripple at VOUT for stable operation. If this condition is not satisfied, unstable switching behavior is
observed in COT converters, with multiple on-time bursts in close succession followed by a long off time. 方程式
2 and 方程式3 define the value of the series resistance RESR to ensure sufficient in-phase ripple at the feedback
node.
Type-2 ripple generation uses a CFF capacitor in addition to the series resistor. As the output voltage ripple is
directly AC-coupled by CFF to the feedback node, the RESR and ultimately the output voltage ripple are reduced
by a factor of VOUT / VFB1
.
Type-3 ripple generation uses an RC network consisting of RA and CA, and the switch node voltage to generate
a triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled into the
feedback node with capacitor CB. Because this circuit does not use output voltage ripple, it is suited for
applications where low output voltage ripple is critical. The AN-1481 Controlling Output Ripple and Achieving
ESR Independence in Constant On-time (COT) Regulator Designs Application Note provides additional details
on this topic.
Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains the highest
efficiency at light load currents by decreasing the effective switching frequency. DEM operation occurs when the
synchronous power MOSFET switches off as inductor valley current reaches zero. Here, the load current is less
than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current
reduces switching loss, and preventing negative current conduction reduces conduction loss. Power conversion
efficiency is higher in a DEM converter than an equivalent forced-PWM CCM converter. With DEM operation, the
duration that both power MOSFETs remain off progressively increases as load current decreases. When this idle
duration exceeds 15 μs, the converter transitions into an ultra-low IQ mode, consuming only 10-μA quiescent
current from the input.
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7.3.2 Internal VCC Regulator and Bootstrap Capacitor
The LM5163H-Q1 contains an internal linear regulator that is powered from VIN with a nominal output of 5 V,
eliminating the need for an external capacitor to stabilize the linear regulator. The internal VCC regulator
supplies current to internal circuit blocks including the synchronous FET driver and logic circuits. The input pin
(VIN) can be connected directly to line voltages up to 100 V. Because the power MOSFET has a low total gate
charge, use a low bootstrap capacitor value to reduce the stress on the internal regulator. It is required to select
a high-quality 2.2-nF 50-V X7R ceramic bootstrap capacitor as specified in the 节7.3.7 . Selecting a higher value
capacitance stresses the internal VCC regulator and damages the device. A lower capacitance than required is
not sufficient to drive the internal gate of the power MOSFET. An internal diode connects from the VCC regulator
to the BST pin to replenish the charge in the high-side gate drive bootstrap capacitor when the SW voltage is
low.
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 1.2-V reference. The LM5163H-Q1 voltage regulation
loop regulates the output voltage by maintaining the FB voltage equal to the internal reference voltage, VREF. A
resistor divider programs the ratio from output voltage VOUT to FB.
For a target VOUT setpoint, use 方程式10 to calculate RFB2 based on the selected RFB1
.
1.2V
R
=
× R
− 1.2V
(10)
FB2
FB1
V
OUT
TI recommends selecting RFB1 in the range of 100 kΩ to 1 MΩ for most applications. A larger RFB1 consumes
less DC current, which is mandatory if light-load efficiency is critical. TI does not recommend RFB1 larger than 1
MΩ as the feedback path becomes more susceptible to noise. Routing the feedback trace away from the noisy
area of the PCB and keeping the feedback resistors close to the FB pin is important.
7.3.4 Internal Soft Start
The LM5163H-Q1 employs an internal soft-start control ramp that allows the output voltage to gradually reach a
steady-state operating point, thereby reducing start-up stresses and current surges. The soft-start feature
produces a controlled, monotonic output voltage start-up. The soft-start time is internally set to 3 ms.
7.3.5 On-Time Generator
The on-time of the LM5163H-Q1 high-side FET is determined by the RRON resistor and is inversely proportional
to the input voltage, VIN. The inverse relationship with VIN results in a nearly constant frequency because VIN is
varied. Use 方程式11 to calculate the on-time.
R
kΩ
RON
V × 2.5
t
µs =
(11)
ON
V
IN
Use 方程式12 to determine the RRON resistor to set a specific switching frequency in CCM.
V
V × 2500
OUT
F
R
kΩ =
(12)
RON
kHz
SW
Select RRON for a minimum on-time (at maximum VIN) greater than 50 ns for proper operation. In addition to this
minimum on-time, the maximum frequency for this device is limited to 1 MHz.
7.3.6 Current Limit
The LM5163H-Q1 manages overcurrent conditions with cycle-by-cycle current limiting of the peak inductor
current. The current sensed in the high-side MOSFET is compared every switching cycle to the current limit
threshold (0.75 A). To protect the converter from potential current runaway conditions, the LM5163H-Q1 includes
a foldback valley current limit feature set at 0.6 A that is enabled if a peak current limit is detected. As shown in
图 7-1, if the peak current in the high-side MOSFET exceeds 0.75 A (typical), the present cycle is immediately
terminated regardless of the programmed on-time (tON), the high-side MOSFET is turned off and the foldback
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valley current limit is activated. The low-side MOSFET remains on until the inductor current drops below this
foldback valley current limit, after which the next on-pulse is initiated. This method folds back the switching
frequency to prevent overheating and limits the average output current to less than 0.75 A to ensure proper
short-circuit and heavy-load protection of the LM5163H-Q1.
VFB
VREF
iL
Peak ILIM
IAVG(ILIM)
Valley ILIM
IAVG1
tON
tSW
<tON
>tSW
图7-1. Current Limit Timing Diagram
Current is sensed after a leading-edge blanking time following the high-side MOSFET turnon transition. The
propagation delay of the current limit comparator is 100 ns. During high step-down conditions when the on-time
is less than 100 ns, a back-up peak current limit comparator in the low-side FET also set at 0.75 A enables the
foldback valley current limit set at 0.6 A. This innovative current limit scheme enables ultra-low duty-cycle
operation, permitting large step-down voltage conversions while ensuring robust protection of the converter.
7.3.7 N-Channel Buck Switch and Driver
The LM5163H-Q1 integrates an N-channel buck switch and associated floating high-side gate driver. The gate-
driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage bootstrap
diode. A high-quality 2.2-nF, 50-V X7R ceramic capacitor connected between the BST and SW pins provides the
voltage to the high-side driver during the buck switch on-time. See the 节 7.3.2 section for limitations. During the
off-time, the SW pin is pulled down to approximately 0 V, and the bootstrap capacitor charges from the internal
VCC through the internal bootstrap diode. The minimum off-timer, set to 50 ns (typical), ensures a minimum time
each cycle to recharge the bootstrap capacitor. When the on-time is less than 300 ns, the minimum off-timer is
forced to 250 ns to ensure that the BST capacitor is charged in a single cycle. This is vital during wake up from
sleep mode when the BST capacitor is most likely discharged.
7.3.8 Synchronous Rectifier
The LM5163H-Q1 provides an internal low-side synchronous rectifier N-channel MOSFET. This MOSFET
provides a low-resistance path for the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier operates in a diode emulation mode. Diode emulation enables the regulator to operate
in a pulse-skipping mode during light-load conditions. This mode leads to a reduction in the average switching
frequency at light loads. Switching losses and FET gate driver losses, both of which are proportional to switching
frequency, are significantly reduced at very light loads and efficiency is improved. This pulse-skipping mode also
reduces the circulating inductor current and losses associated with conventional CCM at light loads.
7.3.9 Enable/Undervoltage Lockout (EN/UVLO)
The LM5163H-Q1 contains a dual-level EN/UVLO circuit. When the EN/UVLO voltage is below 1.1 V (typical),
the converter is in a low-current shutdown mode and the input quiescent current (IQ) is dropped down to 3 µA.
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When the voltage is greater than 1.1 V but less than 1.5 V (typical), the converter is in standby mode. In standby
mode, the internal bias regulator is active while the control circuit is disabled. When the voltage exceeds the
rising threshold of 1.5 V (typical), normal operation begins. Install a resistor divider from VIN to GND to set the
minimum operating voltage of the regulator. Use 方程式 13 and 方程式 14 to calculate the input UVLO turnon
and turnoff voltages, respectively.
R
UV1
V
= 1.5V × 1 +
(13)
(14)
IN on
R
UV2
R
R
UV1
UV2
V
= 1.4V × 1 +
IN off
TI recommends selecting RUV1 in the range of 1 MΩ for most applications. A larger RUV1 consumes less DC
current, which is mandatory if light-load efficiency is critical. If input UVLO is not required, the power-supply
designer can either drive EN/UVLO as an enable input driven by a logic signal or connect it directly to VIN. If EN/
UVLO is directly connected to VIN, the regulator begins switching as soon as the internal bias rails are active.
7.3.10 Power Good (PGOOD)
The LM5163H-Q1 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level.
Use the PGOOD signal for start-up sequencing of downstream converters or for fault protection and output
monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 14 V.
The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the
voltage from a higher voltage pullup rail. When the FB voltage exceeds 95% of the internal reference VREF, the
internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls
below 90% of VREF, an internal 25-Ω PGOOD switch turns on and PGOOD is pulled low to indicate that the
output voltage is out of regulation. The rising edge of PGOOD has a built-in deglitch delay of 5 µs.
7.3.11 Thermal Protection
The LM5163H-Q1 includes an internal junction temperature monitor to protect the device in the event of a higher
than normal junction temperature. If the junction temperature exceeds 175°C (typical), thermal shutdown occurs
to prevent further power dissipation and temperature rise. The LM5163H-Q1 initiates a restart sequence when
the junction temperature falls to 165°C, based on a typical thermal shutdown hysteresis of 10°C. This is a non-
latching protection, so the device cycles into and out of thermal shutdown if the fault persists.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
EN/UVLO provides ON and OFF control for the LM5163H-Q1. When VEN/UVLO is below approximately 1.1 V, the
device is in shutdown mode. Both the internal linear regulator and the switching regulator are off. The quiescent
current in shutdown mode drops to 3 µA at VIN = 24 V. The LM5163H-Q1 also employs internal bias rail
undervoltage protection. If the internal bias supply voltage is below the UV threshold, the regulator remains off.
7.4.2 Active Mode
The LM5163H-Q1 is in active mode when VEN/UVLO is above the precision enable threshold and the internal bias
rail is above its UV threshold. In COT active mode, the LM5163H-Q1 is in one of three modes depending on the
load current:
• CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current
ripple
• Pulse skipping and diode emulation mode (DEM) when the load current is less than half of the peak-to-peak
inductor current ripple in CCM operation
• Current limit CCM with peak and valley current limit protection when an overcurrent condition is applied at the
output
7.4.3 Sleep Mode
The 节7.3.1 section gives a brief introduction to the LM5163H-Q1 diode emulation (DEM) feature. The converter
enters DEM during light-load conditions when the inductor current decays to zero and the synchronous MOSFET
is turned off to prevent negative current in the system. In the DEM state, the load current is lower than half of the
peak-to-peak inductor current ripple and the switching frequency decreases when the load is further decreased
as the device operates in a pulse skipping mode. A switching pulse is set when VFB drops below 1.2 V.
As the frequency of operation decreases and VFB remains above 1.2 V (VREF) with the output capacitor sourcing
the load current for greater than 15 µs, the converter enters an ultra-low IQ sleep mode to prevent draining the
input power supply. The input quiescent current (IQ) required by the LM5163H-Q1 decreases to 10 µA in sleep
mode, improving the light-load efficiency of the regulator. In this mode, all internal controller circuits are turned
off to ensure very low current consumption by the device. Such low IQ renders the LM5163H-Q1 as the best
option to extend operating lifetime for off-battery applications. The FB comparator and internal bias rail are active
to detect when the FB voltage drops below the internal reference VREF and the converter transitions out of sleep
mode into active mode. There is a 9-µs wake-up delay from sleep to active states.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The LM5163H-Q1 requires only a few external components to step down from a wide range of supply voltages to
a fixed output voltage. Several features are integrated to meet system design requirements, including the
following:
• Precision enable
• Input voltage UVLO
• Internal soft start
• Programmable switching frequency
• A PGOOD indicator
To expedite and streamline the process of designing a LM5163H-Q1-based converter, a comprehensive
LM5163H-Q1 quickstart calculator is available for download to assist the designer with component selection for a
given application. This tool is complemented by the availability of an evaluation module (EVM), numerous
PSPICE models, as well as TI's WEBENCH® Power Designer. To modify the LM5164-Q1EVM-041 for the
LM5163H-Q1, change the inductor LO to 120 µH, the resistor RA to 226 kΩ, and the capacitance COUT to 22 µF.
See the 节8.2 section for the LM5163H-Q1 application circuit.
8.1.1 High Temperature Specifications
The LM5163H-Q1 is capable of ultra-high junction temperature operation up to 165°C. High ambient
temperature applications with power dissipation on integrated chips often result in junction temperatures
exceeding the typical AEC-Q100 Grade 1 specification. The LM5163H-Q1 is designed to sustain these high
temperatures while maintaining performance and reliability. This is accomplished by ensured electrical
specifications up to 165°C. In addition, extra tests performed on this device show it exceeds AEC-Q100 Grade 1
requirements. For example, the LM5163H-Q1 passes the temperature profile displayed in 表 8-1. 表 8-1 shows
an automotive profile of time and temperature for an LM5163H-Q1 converter application specified with 12 000
POH at an input voltage of 100 V. Power On Hours (POH) for LM5163H-Q1 is a function of voltage, temperature,
and time. Usage at higher voltages and temperatures results in a reduction in POH to achieve the same
reliability performance.
表8-1. Power On Hours (POH) Breakdown
JUNCTION TEMPERATURE
HOURS (TOTAL = 12 000 HOURS)
-40°C
23°C
6% = 720 Hrs
20% = 2400 Hrs
65% = 7800 Hrs
7% = 840 Hrs
100°C
150°C
155°C
165°C
1% = 120 Hrs
1% = 120 Hrs
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8.2 Typical Application
图8-1 shows the schematic for a 12-V, 0.5-A COT converter.
VOUT = 12 V
IOUT = 0.5 A
LO
120 mH
U1
VIN = 15 V...100 V
VIN
SW
CA
3.3 nF
RA
CBST
LM5163H-Q1
CIN
226 kW
2.2 nF
RFB1
2.2 mF
EN/UVLO
BST
453 kW
COUT
CB
22 mF
56 pF
FB
RON
RRON
RFB2
100 kW
PGOOD
GND
49.9 kW
图8-1. Typical Application VIN(nom) = 48 V, VOUT = 12 V, IOUT(max) = 0.5 A, FSW(nom) = 300 kHz
备注
This and subsequent design examples are provided herein to showcase the LM5163H-Q1 converter in
several different applications. Depending on the source impedance of the input supply bus, an
electrolytic capacitor may be required at the input to ensure stability, particularly at low input voltage
and high output current operating conditions. See the 节8.3 section for more details.
8.2.1 Design Requirements
The target full-load efficiency is 92% based on a nominal input voltage of 48 V and an output voltage of 12 V.
The required input voltage range is 15 V to 100 V. The LM5163H-Q1 delivers a fixed 12-V output voltage. The
switching frequency is set by resistor RRON at 300 kHz. The output voltage soft-start time is 3 ms. 表8-2 lists the
required components. Refer to the LM5164-Q1EVM-041 User's Guide for more detail.
表8-2. List of Components
COUNT
REF DES
CIN
VALUE
2.2 µF
22 µF
DESCRIPTION
PART NUMBER
CGA6N3X7R2A225K230AB
TMK325B7226KMHT
CGA3E2X7R2A332K080AA
C0603C560J5GACTU
GCM155R71H222KA37D
MSS1260-124KL
MANUFACTURER
TDK
2
Capacitor, Ceramic, 2.2 µF, 100 V, X7R, 10%
Capacitor, Ceramic, 22 µF, 25 V, X7R, 10%
Capacitor, Ceramic, 3300 pF, 16 V, X7R, 10%
Capacitor, Ceramic, 56 pF, 50 V, X7R, 10%
Capacitor, Ceramic, 2200 pF, 50 V, X7R, 10%
Inductor, 120 µH, 210 mΩ, 1.65 A
COUT
CA
Taiyo Yuden
TDK
1
1
1
1
-
3300 pF
56 pF
CB
Kemet
CBST
LO
2.2 nF
120 µH
120 µH
MuRata
Coilcraft
Coilcraft
Susumu Co Ltd
Yageo
MSS1038T-124KL
LO
Inductor, 120 µH, 380 mΩ, 0.95 A, 165 °C
Resistor, Chip, 100 kΩ, 1%, 0.1 W, 0603
Resistor, Chip, 453 kΩ, 1%, 0.1 W, 0603
Resistor, Chip, 49.9 kΩ, 1%, 0.1 W, 0603
Resistor, Chip, 226 kΩ1%, 0.1 W, 0603
Wide VIN synchronous buck converter
RG1608P-1053-B-T5
RT0603BRD07448KL
RG1608P-4992-B-T5
RT0603BRD07226KL
LM5163H-Q1
1
1
1
1
1
RRON
RFB1
RFB2
RA
100 kΩ
453 kΩ
49.9 kΩ
226 kΩ
Susumu Co Ltd
Yageo
U1
TI
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5163H-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Switching Frequency (RRON
)
The switching frequency of the LM5163H-Q1 is set by the on-time programming resistor placed at RON. As
shown by 方程式15, a standard 100 kΩ, 1% resistor sets the switching frequency at 300 kHz.
V
V × 2500
OUT
F
R
kΩ =
(15)
RON
kHz
SW
Note that at very low duty cycles, the 50 ns minimum controllable on-time of the high-side MOSFET, tON(min)
,
limits the maximum switching frequency. In CCM, tON(min) limits the voltage conversion step-down ratio for a
given switching frequency. Use 方程式16 to calculate the minimum controllable duty cycle.
D
= t
× F
SW
(16)
MIN
ON min
Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range,
solution size, and efficiency. Use 方程式 17 to calculate the maximum supply voltage for a given tON(min) before
switching frequency reduction occurs.
V
OUT
V
=
(17)
IN MAX
t
× F
ON min
SW
8.2.2.3 Buck Inductor (LO)
Use 方程式 18 and 方程式 19 to calculate the inductor ripple current (assuming CCM operation) and peak
inductor current, respectively.
V
V
OUT
OUT
× L
∆ I =
× 1 −
(18)
(19)
L
F
V
SW
O
IN
∆ I
L
I
= I
×
OUT max
2
L PEAK
For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 50%
of the rated load current at nominal input voltage. Use 方程式20 to calculate the inductance.
V
V
OUT
OUT
× ∆ I
L
=
× 1 −
V
IN nom
(20)
O
F
SW
L
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Choosing a 120-μH inductor in this design results in 250-mA peak-to-peak ripple current at a nominal input
voltage of 48 V, equivalent to 50% of the 500-mA rated load current.
Check the inductor data sheet to make sure the saturation current of the inductor is well above the current limit
setting of the LM5163H-Q1. Ferrite-core inductors have relatively lower core losses and are preferred at high
switching frequencies, but exhibit a hard saturation characteristic – the inductance collapses abruptly when the
saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage
ripple, and reduced efficiency, in turn compromising reliability. Note that inductor saturation current levels
generally decrease as the core temperature increases.
8.2.2.4 Output Capacitor (COUT
)
Select a ceramic output capacitor to limit the capacitive voltage ripple at the converter output. This is the
sinusoidal ripple voltage that is generated from the triangular inductor current ripple flowing into and out of the
capacitor. Select an output capacitance using 方程式 21 to limit the voltage ripple component to 0.5% of the
output voltage.
∆ I
L
C
≥
(21)
OUT
8 × F
SW
× V
OUT ripple
Substituting ΔIL(nom) of 250-mA gives COUT greater than 3.1 μF. With voltage coefficients of ceramic capacitors
taken in consideration, a 22-µF, 25-V rated capacitor with X7R dielectric is selected.
8.2.2.5 Input Capacitor (CIN)
An input capacitor is necessary to limit the input ripple voltage while providing AC current to the buck power
stage at every switching cycle. To minimize the parasitic inductance in the switching loop, position the input
capacitors as close as possible to the VIN and GND pins of the LM5163H-Q1. The input capacitors conduct a
square-wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive
component of AC ripple voltage is a triangular waveform.
Along with the ESR-related ripple component, use 方程式 22 to calculate the peak-to-peak ripple voltage
amplitude.
I
× D × 1 − D
× C
OUT
F
V
=
+ I
× R
ESR
(22)
IN ripple
OUT
SW
IN
Use 方程式 23 to calculate the input capacitance required for a load current, based on an input voltage ripple
specification (VIN(ripple)).
I
× D × 1 − D
OUT
C
≥
(23)
IN
F
× V
− I × R
OUT ESR
SW
IN ripple
The recommended high-frequency input capacitance is 2.2 µF or higher. Ensure the input capacitor is a high-
quality X7S or X7R ceramic capacitor with sufficient voltage rating for CIN. Based on the voltage coefficient of
ceramic capacitors, choose a voltage rating that is twice the maximum input voltage. Additionally, some bulk
capacitance is required if the LM5163H-Q1 is not located within approximately 5 cm from the input voltage
source. This capacitor provides parallel damping to the resonance associated with parasitic inductance of the
supply lines and high-Q ceramics. See the 节8.3 section for more detail.
8.2.2.6 Type 3 Ripple Network
A Type 3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT to generate a
triangular ramp that is in phase with the inductor current. This triangular ramp is then AC-coupled into the
feedback node using capacitor CB as shown in 图8-1. Type 3 ripple injection is suited for applications where low
output voltage ripple is crucial.
Use 方程式24 and 方程式25 to calculate RA and CA to provide the required ripple amplitude at the FB pin.
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10
× R
FB1
C
≥
(24)
A
F
R
FB2
SW
For the feedback resistor values given in 图 8-1, 方程式 24 dictates a minimum CA of 742 pF. In this design, a
3300 pF capacitance is chosen. This is done to keep RA within practical limits between 100 kΩ and 1 MΩ when
using 方程式25.
V
− V
OUT
20mV
× t
ON nom
IN nom
R × C
≥
(25)
A
A
Based on CA set at 3.3 nF, RA is calculated to be 226 kΩ to provide a 20-mV ripple voltage at FB. The general
recommendation for a Type 3 network is to calculate RA and CA to get 20 mV of ripple at typical operating
conditions, while ensuring a 12-mV minimum ripple voltage on FB at minimum VIN.
While the amplitude of the generated ripple does not affect the output voltage ripple, it impacts the output
regulation as it reflects as a DC error of approximately half the amplitude of the generated ripple. For example, a
converter circuit with Type 3 network that generates a 40-mV ripple voltage at the feedback node has
approximately 10-mV worse load regulation scaled up through the FB divider to VOUT than the same circuit that
generates a 20-mV ripple at FB. Use 方程式26 to calculate the coupling capacitance CB.
t
TR − settling
C
≥
(26)
B
3 × R
FB1
where
• tTR-settling is the desired load transient response settling time
CB calculates to 56 pF based on a 75-µs settling time. This value avoids excessive coupling capacitor discharge
by the feedback resistors during sleep intervals when operating at light loads. To avoid capacitance fall-off with
DC bias, use a C0G or NP0 dielectric capacitor for CB.
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8.2.3 Application Curves
100
95
90
85
80
75
70
65
60
100
90
80
70
60
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
0.001
0.01
0.1
0.5
0
0.1
0.2
0.3
0.4
0.5
Load (A)
Load (A)
D001
D002
图8-2. Conversion Efficiency (Log Scale)
图8-3. Conversion Efficiency (Linear Scale)
12.6
12.5
12.4
12.3
12.2
12.1
12
VOUT 100mV/DIV
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
IOUT 250mA/DIV
11.9
11.8
100 µs/DIV
0
0.1
0.2 0.3
Output Current (A)
0.4
0.5
Load
VIN = 24 V
IOUT = 0.125 A to 0.5 A at 0.1
图8-4. Load and Line Regulation Performance
A/μs
图8-5. Load Step Response
VIN 10V/DIV
VIN 10V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IOUT 100mA/DIV
IOUT 100mA/DIV
1 ms/DIV
1 ms/DIV
VIN = 24 V
IOUT = 0 A
VIN = 24 V
IOUT = 0.5 A (Resistive)
图8-6. No-Load Start-up with VIN
图8-7. Full-Load Start-up with VIN
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EN 5V/DIV
EN 5V/DIV
VOUT 5V/DIV
VOUT 5V/DIV
IOUT 500mA/DIV
IOUT 500mA/DIV
2 ms/DIV
2 ms/DIV
VIN = 24 V
IOUT = 0 A
VIN = 24 V
IOUT = 0.5 A (Resistive)
图8-8. No-Load Start-up and Shutdown with EN/
图8-9. Full-Load Start-up and Shutdown with EN/
UVLO
UVLO
VOUT 5V/DIV
EN 5V/DIV
VOUT 5V/DIV
VSW 10V/DIV
IOUT 500mA/DIV
IOUT 500mA/DIV
500 µs/DIV
2 ms/DIV
VIN = 24 V
IOUT = 0 A
VIN = 24 V
Load = 0 A to Short
图8-10. Pre-bias Start-up with EN/UVLO
图8-11. Short Circuit Applied
VOUT 5V/DIV
VOUT 5V/DIV
VSW 10V/DIV
VSW 10V/DIV
100 µs/DIV
10 ms/DIV
IOUT 500mA/DIV
IOUT 500mA/DIV
VIN = 24 V
Load = 0 A to Short to 0 A
VIN = 24 V
Load = Short to 0 A
图8-13. No Load to Short Circuit/Short-Circuit
图8-12. Short-Circuit Recovery
Recovery
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VSW 10V/DIV
VSW 10V/DIV
VOUT 20mV/DIV
VOUT 50mV/DIV
10 ms/DIV
5 µs/DIV
VIN = 24 V
IOUT = 0 A
VIN = 24 V
IOUT = 0.5 A
图8-14. No-Load Switching
图8-15. Full-Load Switching
Peak
Average
Peak
Average
Start 30 MHz
Stop 108 MHz
Start 150 kHz
Stop
30 MHz
VIN = 48 V
Load = 0.5 A
VIN = 48 V
Load = 0.5 A
图8-17. CISPR 25 Class 5 Conducted Emissions
图8-16. CISPR 25 Class 5 Conducted Emissions
Plot, 30 MHz to 108 MHz
Plot, 150 kHz to 30 MHz
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8.3 Power Supply Recommendations
The LM5163H-Q1 buck converter is designed to operate from a wide input voltage range between 6 V and 100
V. The characteristics of the input supply must be compatible with 节 6.3 and 节 6.1. In addition, the input supply
must be capable of delivering the required input current to the fully-loaded regulator. Use 方程式 27 to estimate
the average input current.
V
× I
OUT
OUT
V
I
=
(27)
IN
× η
IN
where
• ηis the efficiency
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at
VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip
during a load transient. If the converter is operating close to the minimum input voltage, this dip can cause false
UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the
input supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics. The
moderate ESR of the electrolytic capacitor helps to damp the input resonant circuit and reduce any voltage
overshoots. A 10-μF electrolytic capacitor with a typical ESR of 0.5 Ω provides enough damping for most input
circuit configurations.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters
Application Report provides helpful suggestions when designing an input filter for any switching regulator.
8.4 Layout
8.4.1 Layout Guidelines
PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or
degrade the power supply performance.
1. To help eliminate these problems, bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with
a high-quality dielectric. Place CIN as close as possible to the LM5163H-Q1 VIN and GND pins. Grounding
for both the input and output capacitors must consist of localized top-side planes that connect to the GND
pin and GND PAD.
2. Minimize the loop area formed by the input capacitor connections to the VIN and GND pins.
3. Locate the inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive
capacitive coupling.
4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
5. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, soft-
start, and enable components to the ground plane. This prevents any switched or load currents from flowing
in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic
output voltage ripple behavior.
7. Make VIN, VOUT, and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
8. Minimize trace length to the FB pin. Place both feedback resistors, RFB1 and RFB2, close to the FB pin. Place
CFF (if needed) directly in parallel with RFB1. If output setpoint accuracy at the load is important, connect the
VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer
on the other side of a grounded shielding layer.
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9. The RON pin is sensitive to noise. Thus, locate the RRON resistor as close as possible to the device and
route with minimal lengths of trace. The parasitic capacitance from RON to GND must not exceed 20 pF.
10. Provide adequate heat sinking for the LM5163H-Q1 to keep the junction temperature below 150°C. For
operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of
heat-sinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper
layers, these thermal vias must also be connected to inner layer heat-spreading ground planes.
8.4.1.1 Compact PCB Layout for EMI Reduction
Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger
the area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimizing radiated EMI is to identify the pulsing current path and minimize the area of that path.
denotes the critical switching loop of the buck converter power stage in terms of EMI. The topological
architecture of a buck converter means that a particularly high di/dt current path exists in the loop, comprising
the input capacitor and the integrated MOSFETs of the LM5163H-Q1, and it becomes mandatory to reduce the
parasitic inductance of this loop by minimizing the effective loop area.
VIN
VIN
2
CIN
LM5163H
High
BST
di/dt
loop
High-side
NMOS
gate driver
Q1
LO
SW
VOUT
8
CO
Q2
Low-side
NMOS
gate driver
GND
1
GND
图8-18. DC/DC Buck Converter With Power Stage Circuit Switching Loop
The input capacitor provides the primary path for the high di/dt components of the current of the high-side
MOSFET. Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction.
Keep the trace connecting SW to the inductor as short as possible and just wide enough to carry the load current
without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to
minimize parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the
return terminal of the capacitor to the GND pin and exposed PAD of the LM5163H-Q1.
8.4.1.2 Feedback Resistors
Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin,
rather than close to the load. This reduces the trace length of FB signal and noise coupling. The FB pin is the
input to the feedback comparator, and as such, is a high impedance node sensitive to noise. The output node is
a low impedance node, so the trace from VOUT to the resistor divider can be long if a short path is not available.
Route the voltage sense trace from the load to the feedback resistor divider, keeping away from the SW node,
the inductor, and VIN to avoid contaminating the feedback signal with switch noise, while also minimizing the
trace length. This is most important when high feedback resistances greater than 100 kΩ are used to set the
output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node, and VIN so
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there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon. This
provides further shielding for the voltage feedback path from switching noise sources.
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8.4.2 Layout Example
图 8-19 shows an example layout for the PCB top layer of a 2-layer board with essential components placed on
the top side.
Type 3 ripple
injection
Connect BST cap
close to BST and SW
Place FB resistors very
close to FB and GND pins
PGOOD
connection
Thermal vias under
LM5164 PAD
Place resistor R8
close to the RON pin
GND
Optional RC
VOUT
connection
Connect ceramic
input cap close to
VIN and GND
EN/UVLO
connection
connection snubber to
reduce SW
node ringing
图8-19. LM5163H-Q1 Single-Sided PCB Layout Example
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9 Device and Documentation Support
9.1 Device Support
9.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.1.2 Development Support
• LM5163-Q1 Quickstart Calculator
• LM5163H-Q1 Simulation Models
• TI Reference Design Library
• Technical Articles:
– Use a Low-quiescent-current Switcher for High-voltage Conversion
– How a DC/DC Converter Package and Pinout Design Can Enhance Automotive EMI Performance
9.1.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the LM5163H-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, LM5164-Q1EVM-041 EVM User's Guide
• Texas Instruments, Selecting an Ideal Ripple Generation Network for Your COT Buck Converter Application
Report
• Texas Instruments, Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding
Applications White Paper
• Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies White Paper
• Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies White Paper
• Texas Instruments, 24-V AC Power Stage with Wide VIN Converter and Battery Gauge for Smart Thermostat
Design Guide
• Texas Instruments, Accurate Gauging and 50-μA Standby Current, 13S, 48-V Li-ion Battery Pack Reference
Design Guide
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• Texas Instruments, AN-2162: Simple Success with Conducted EMI from DC/DC Converters Application
Report
• Texas Instruments, Automotive Cranking Simulator User's Guide
• Texas Instruments, Powering Drones with a Wide VIN DC/DC Converter Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5163HQDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 165
5163HQ
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5163HQDDARQ1
SO
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
PowerPAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
LM5163HQDDARQ1
8
2500
Pack Materials-Page 2
重要声明和免责声明
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