LM5165DRCR [TI]
具备超低 IQ 的 3V 至 65V、150mA 同步降压转换器 | DRC | 10 | -40 to 150;
| 型号： | LM5165DRCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具备超低 IQ 的 3V 至 65V、150mA 同步降压转换器 | DRC | 10 | -40 to 150 转换器 |
| 文件： | 总49页 (文件大小：3007K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5165
ZHCSEQ3D –FEBRUARY 2016 –REVISED DECEMBER 2022
LM5165 具有超低IQ 的3V 至65V 输入、150mA 同步降压转换器
1 特性
3 说明
• 3V 至65V 的宽输入电压范围
• 10.5µA 空载静态电流
LM5165 器件是一款易于使用的紧凑型 3V 至 65V、超
低 IQ 同步降压转换器，可在宽输入电压和负载电流范
围内提供高效率。该器件具有集成式高侧和低侧功率
MOSFET，能够以 3.3V 或 5V 的固定输出电压或可调
输出电压提供高达 150mA 的输出电流。该转换器设计
旨在简化实现方案，同时优化目标应用的性能。脉频调
制 (PFM) 模式可确保在轻负载条件下获得最优效率，
恒定导通时间 (COT) 控制可实现近似恒定的工作频
率。这两种控制方案都不需要环路补偿，同时还能够针
对较高的降压转换比实现出色的线路和负载瞬态响应以
及短暂的脉宽调制(PWM) 导通时间。
• -40°C 至150°C 的结温范围
• 固定（3.3V 和5V）或可调节输出电压
• 符合EN55022/CISPR 22 EMI 标准
• 集成式2ΩPMOS 降压开关
– 支持100% 占空比，可实现低压降
• 集成式1ΩNMOS 同步整流器
– 无需使用外部整流二极管
• 可编程电流限制设置点（四级）
• 可选PFM 或COT 模式工作
• 1.223V ±1% 内部电压基准
• 900µs 内部或可编程软启动
• 可实现低EMI 的有效压摆率控制
• 二极管仿真模式和脉冲跳跃模式，可在轻负载下实
现超高效率
高侧 P 沟道 MOSFET 能够以 100% 占空比工作以确
保最低压差电压，而且不需要使用自举电容器进行栅极
驱动。另外，还可以调节电流限制设定值来优化电感器
选择，从而满足特定的输出电流要求。可选和可调节启
动时序选项包括最短延迟（无软启动）、内部固定值
(900µs) 以及可使用电容器进行外部编程的软启动。可
以使用开漏 PGOOD 指示器进行定序、故障报告和输
出电压监视。LM5165 降压转换器采用 10 引脚3mm ×
3mm 热增强型 VSON-10 封装（ 引脚间距为
0.5mm ） 。LM5165 和 LM5165X 还可以采用
VSSOP-10 封装。
• 单调启动至预偏置输出
• 无环路补偿或自举元件
• 具有迟滞功能的精密使能和输入UVLO
• 与LM5166 引脚对引脚兼容
• 具有迟滞功能的热关断保护
• 10 引脚3mm × 3mm VSON 封装
• 使用TPSM265R1 模块缩短产品上市时间
• 使用WEBENCH® Power Designer 创建定制稳压器
设计
器件信息
封装(1)
器件型号
LM5165
输出
可调节
2 应用
LM5165X
LM5165Y
5V 固定
3.3V 固定
DRC（VSON，10）
• 4–20mA 环路供电式传感器
• 汽车和电池供电设备
• 高电压LDO 替代产品
• 工业控制系统
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 通用偏置电源
100
90
LF
68
VIN = 3 V...65 V
VOUT = 5 V *
H
VIN
SW
80
LM5165X
CIN
COUT
22
EN
VOUT
70
1
F
F
60
PGOOD
HYS
SS
VIN = 8V
50
ILIM
VIN = 12V
VIN = 24V
VIN = 36V
40
GND
VIN = 65V
RT
* VOUT tracks VIN
if VIN < 5 V
30
0.1
1
10
30
D101
Output Current (mA)
典型原理图（固定输出）
典型效率(VOUT = 5V)
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSA47
LM5165
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ZHCSEQ3D –FEBRUARY 2016 –REVISED DECEMBER 2022
Table of Contents
7.4 Device Functional Modes..........................................19
8 Applications and Implementation................................20
8.1 Application Information............................................. 20
8.2 Typical Applications.................................................. 20
8.3 Power Supply Recommendations.............................34
8.4 Layout....................................................................... 35
9 Device and Documentation Support............................38
9.1 Device Support......................................................... 38
9.2 Documentation Support............................................ 38
9.3 接收文档更新通知..................................................... 40
9.4 支持资源....................................................................40
9.5 Trademarks...............................................................40
9.6 Electrostatic Discharge Caution................................40
9.7 术语表....................................................................... 40
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................7
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................13
Information.................................................................... 40
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (December 2020) to Revision D (December 2022)
Page
• 通篇去除了图的颜色并更新了图的编号格式....................................................................................................... 1
• Changed all instances of legacy terminology to commander and responder................................................... 17
• Added additional statement to Filter Inductor –LF .........................................................................................21
Changes from Revision B (July 2017) to Revision C (December 2020)
Page
• 添加了TPSM265R1 链接................................................................................................................................... 1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
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5 Pin Configuration and Functions
GND
HYS
GND
10
9
SW
VIN
ILIM
SS
1
10
9
SW
VIN
ILIM
SS
1
2
3
4
5
2
3
4
5
HYS
FB
8
8
VOUT
EN
7
7
EN
PGOOD
PGOOD
6
6
RT
RT
LM5165X, LM5165Y
Fixed Output Versions
LM5165
Adjustable Output Version
图5-1. DRC Package 10-Pin VSON With Exposed Thermal Pad (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
Switching node that is internally connected to the drain of the high-side PMOS buck switch and the
drain of the low-side NMOS synchronous rectifier. Connect to the switching side of the power inductor.
1
SW
P
P
I
Regulator supply input pin to high-side power MOSFET and internal bias rail LDO. Connect to input
supply and input capacitor CIN. Path from VIN to the input capacitor must be as short as possible.
2
3
VIN
Programming pin for current limit. Connecting the appropriate resistor from ILIM to GND selects one of
four preset current limit options. Short ILIM to GND for the maximum current setting.
ILIM
Programming pin for the soft-start time. If a 100-kΩresistor is connected from SS to GND, the internal
soft-start circuit is disabled and the FB comparator reference steps immediately from zero to full value
when the regulator is enabled by the EN input. If the SS pin is left open, the internal soft-start circuit
ramps the FB reference from zero to full value in 900 µs. If an appropriate capacitance is connected to
the SS pin, the soft-start time can be programmed as required.
4
5
SS
RT
I
I
Mode selection and on-time programming pin for Constant On-Time (COT) control. Short RT to GND to
select PFM (pulse frequency modulation) operation. Connect a resistor from RT to GND to program the
on-time, which sets the switching frequency for COT.
Power Good output flag pin. PGOOD is connected to the drain of an NFET that holds the pin low when
either FB or VOUT is below the regulation target. Use a pullup resistor of 10 kΩto 100 kΩto the
system voltage rail or VOUT (no higher than 12 V).
6
7
PGOOD
EN
O
I
Input pin of the precision enable / UVLO comparator. The converter is enabled when the EN voltage is
greater than 1.212 V.
Feedback input to voltage regulation loop. The VOUT pin connects the internal feedback resistor
divider to the regulator output voltage for fixed 3.3-V and 5-V options. The FB pin connects the internal
feedback comparator to an external resistor divider for the adjustable output voltage option. The FB
comparator reference voltage is nominally 1.223 V.
8
9
VOUT/FB
HYS
I
Drain of an internal NFET that is turned off when the EN input is greater than the EN threshold. An
external resistor from HYS to the EN pin UVLO resistor divider programs the input UVLO hysteresis
voltage.
O
10
GND
PAD
G
P
Regulator ground return
Exposed pad. Connect to the GND pin and system ground on PCB. Path to CIN must be as short as
possible.
—
(1) P = Power, G = Ground, I = Input, O = Output.
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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted).(1) (2)
MIN
–0.3
–0.7
–3
MAX
UNIT
VIN, EN to GND
SW to GND
68
V
VVIN + 0.3
V
V
20-ns transient
PGOOD, VOUT(3) to GND
HYS to GND
Survives short to automotive battery voltage
16
7
V
–0.3
–0.3
–0.3
–40
–55
V
ILIM, SS, RT, FB(4) to GND
Maximum junction temperature, TJ
Storage temperature, Tstg
3.6
150
150
V
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Fixed output versions.
(4) Adjustable output version.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Electrostatic
discharge
VESD
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
.
MIN
MAX
65
UNIT
VIN
3
–0.3
–0.3
–0.3
0
EN
65
Input voltages
V
PGOOD
12
HYS
5.5
150
100
150
IOUT (COT mode)
IOUT (PFM mode)
Operating junction temperature
Output current
Temperature
mA
°C
0
–40
(1) Operating Ratings are conditions under which the device is intended to be functional. For specifications and test conditions, see
Electrical Characteristics.
6.4 Thermal Information
LM5165
THERMAL METRIC(1)
DRC (VSON)
10 PINS
47.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
59.9
22.1
1
ψJT
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LM5165
THERMAL METRIC(1)
DRC (VSON)
UNIT
10 PINS
22.2
4
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to +125°C junction temperature
range. VIN = 12 V (unless otherwise noted).(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
QUIESCENT CURRENTS
IQ-SHD
VIN DC supply current, shutdown
VIN DC supply current, no load
VEN = 0 V, TA = 25°C
4.6
10.5
11
6
15
15
µA
µA
µA
µA
µA
IQ-SLEEP
VFB = 1.5 V, TA = 25°C
VFB = 1.5 V, VVIN = 65 V, TA = 25°C
PFM mode
IQ-SLEEP-VINMAX VIN DC supply current, no load
IQ-ACTIVE-PFM
IQ-ACTIVE-COT
VIN DC supply current, active
VIN DC supply current, active
205
300
COT mode, RRT = 107 kΩ
POWER SWITCHES
RDSON1 High-side MOSFET RDS(on)
RDSON2 Low-side MOSFET RDS(on)
2
1
ISW = –10 mA
Ω
Ω
ISW = 10 mA
CURRENT LIMITING
ILIM1-VSON
ILIM shorted to GND
RILIM = 24.9 kΩ
220
155
100
48
240
180
120
60
264
205
145
75
ILIM2-VSON
High-side peak current threshold
VSON-10 package
mA
ILIM3-VSON
ILIM4-VSON
REGULATION COMPARATOR
VVOUT50 VOUT 5-V DC setpoint
VVOUT33
RILIM = 56.2 kΩ
RILIM ≥100 kΩ
LM5165X
4.9
5
3.3
5.1
V
V
VOUT 3.3-V DC setpoint
VOUT pin input current
LM5165Y
3.23
3.37
VVOUT = 5 V, LM5165X
VVOUT = 3.3 V, LM5165Y
6.7
IVOUT
µA
V
3.9
VREF1
Lower FB regulation threshold (PFM, COT)
Upper FB regulation threshold (PFM)
FB comparator PFM hysteresis
FB comparator dropout hysteresis
FB pin input bias current
1.205
1.22
1.223
1.233
10
1.241
1.246
Adjustable output version
VREF2
FBHYS-PFM
FBHYS-COT
IFB
PFM mode
mV
mV
nA
COT mode
4
VFB = 1 V
100
FBLINE-REG
FB threshold variation over line
VVIN = 3 V to 65 V
0.001
0.001
%/V
LM5165X, VVIN = 6 V to 65 V
LM5165Y, VVIN = 4.5 V to 65 V
VOUTLINE-REG VOUT threshold variation over line
%/V
POWER GOOD
UVTRISING
FB voltage rising, relative to VREF1
FB voltage falling, relative to VREF1
VFB = 1 V
94%
87%
80
PGOOD comparator
UVTFALLING
RPGOOD
PGOOD on-resistance
200
1.65
100
Ω
V
VVIN falling, IPGOOD = 0.1 mA,
VPGOOD < 0.5 V
VINMIN-PGOOD
Minimum VIN for valid PGOOD
PGOOD off-state leakage current
1.2
10
IPGOOD
VFB = 1.2 V, VPGOOD = 5.5 V
nA
ENABLE / UVLO
VIN-ON
Turnon threshold
VIN voltage rising
2.6
2.75
2.95
V
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6.5 Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to +125°C junction temperature
range. VIN = 12 V (unless otherwise noted).(1) (2)
PARAMETER
TEST CONDITIONS
VIN voltage falling
MIN
2.35
TYP
2.45
1.212
1.144
68
MAX UNIT
VIN-OFF
VEN-ON
VEN-OFF
VEN-HYS
VEN-SD
RHYS
Turnoff threshold
2.6
1.262
1.178
V
V
Enable turnon threshold
Enable turnoff threshold
Enable hysteresis
EN voltage rising
EN voltage falling
1.163
1.109
V
mV
V
EN shutdown threshold
HYS on-resistance
EN voltage falling
VEN = 1 V
0.3
0.6
80
200
100
Ω
IHYS
HYS off-state leakage current
VEN = 1.5 V, VHYS = 5.5 V
10
nA
SOFT-START
ISS
Soft-start charging current
Soft-start rise time
VSS = 1 V
10
µA
µs
TSS-INT
SS floating
900
THERMAL SHUTDOWN
TJ-SD
Thermal shutdown threshold
Thermal shutdown hysteresis
170
10
°C
°C
TJ-SD-HYS
(1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as
follows: TJ = TA + (PD × RθJA) where RθJA (in °C/W) is the package thermal impedance provided in 节6.4.
6.6 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
Minimum controllable PWM on-time
PWM on-time
TEST CONDITIONS
MIN
TYP
180
MAX UNIT
TON-MIN
TON1
ns
ns
ns
250
16 kΩfrom RT to GND
TON2
PWM on-time
1000
75 kΩfrom RT to GND
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6.7 Typical Characteristics
Unless otherwise specified, VIN = 12 V, VOUT = 5 V. Please refer to Typical Applications for circuit designs.
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
VIN = 8V
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
0.1
1
10
30
D101
0.1
1
10
100 150
D102
Output Current (mA)
Output Current (mA)
5-V, 25-mA Design
LF = 470 µH
FSW(nom) = 100 kHz
ILIM ≥100 kΩ
See schematic,
LF = 220 µH
FSW(nom) = 230 kHz
RRT = 133 kΩ
COUT = 47 µF
COUT = 22 µF
R
图8-1
图6-1. Converter Efficiency: 5 V, 25 mA, PFM
图6-2. Converter Efficiency: 5 V, 150 mA, COT
100
100
90
80
70
60
90
80
70
60
VIN = 8V
VIN = 8V
50
50
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 12V
VIN = 24V
VIN = 36V
40
40
VIN = 65V
VIN = 65V
30
30
0.1
1
10
50
D103
0.1
1
10
100 150
D104
Output Current (mA)
Output Current (mA)
See schematic,
LF = 47 µH
FSW(nom) = 350 kHz
See schematic,
LF = 150 µH
FSW(nom) = 160 kHz
COUT = 10 µF
COUT = 22 µF
图8-14
RILIM = 56.2 kΩ
图8-26
RRT = 121 kΩ
图6-3. Converter Efficiency: 3.3 V, 50 mA, PFM
图6-4. Converter Efficiency: 3.3 V, 150 mA, COT
100
100
90
80
70
60
90
80
70
60
VIN = 18V
50
50
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
40
40
VIN = 65V
30
30
0.1
1
10
75
D105
0.1
1
10
100 150
D106
Output Current (mA)
Output Current (mA)
See schematic,
LF = 47 µH
FSW(nom) = 500 kHz
See schematic,
LF = 150 µH
FSW(nom) = 600 kHz
COUT = 10 µF
COUT = 10 µF
图8-21
RILIM = 24.9 kΩ
图8-29
RRT = 143 kΩ
图6-5. Converter Efficiency: 12 V, 75 mA, PFM
图6-6. Converter Efficiency: 15 V, 150 mA, COT
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4
3.5
3
2
1.5
1
2.5
2
1.5
1
0.5
0
0.5
-40°C
25°C
50
150°C
60
-40°C
25°C
50
150°C
0
0
10
20
30 40
Input Voltage (V)
70
0
10
20
30 40
Input Voltage (V)
60
70
D001
D002
图6-7. High-Side MOSFET On-State Resistance vs 图6-8. Low-Side MOSFET On-State Resistance vs
Input Voltage Input Voltage
1.24
1.22
1.2
1.25
1.245
1.24
1.235
1.23
1.18
1.16
1.14
1.12
1.1
1.225
1.22
1.215
1.21
Rising
Falling
Rising
Falling
1.205
-50
-25
0
25
Temperature (°C)
50
75
100
125
150
-50
-25
0
25
Temperature (°C)
50
75
100
125
150
D004
D005
图6-9. Enable Threshold Voltage vs Temperature
图6-10. Feedback Comparator Voltage vs
Temperature
5.08
5.06
5.04
5.02
5
3.36
3.34
3.32
3.3
4.98
4.96
4.94
3.28
3.26
3.24
Rising
Falling
Rising
Falling
4.92
4.9
-50
-25
0
25
Temperature (°C)
50
75
100
125
150
-50
-25
0
25
Temperature (°C)
50
75
100
125
150
D007
D006
LM5165X
LM5165Y
图6-11. VOUT Regulation Thresholds vs
图6-12. VOUT Regulation Thresholds vs
Temperature
Temperature
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95
94
93
92
91
90
89
88
87
86
300
250
200
150
100
50
FB Rising
FB Falling
60 mA
120 mA
180 mA
240 mA
85
0
-50
-25
0
25
Temperature (°C)
50
75
100
125
150
-50
-25
0
25
Temperature (°C)
50
75
100
125
150
D008
D009
图6-13. PGOOD Thresholds vs Temperature
图6-14. Peak Current Limits vs Temperature
300
150
250
200
150
100
50
125
100
75
50
60 mA
120 mA
180 mA
240 mA
25
0
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
0
10
20
30 40
Input Voltage (V)
50
60
70
D011
D010
图6-16. PGOOD and HYS Pulldown RDS(on) vs
图6-15. Peak Current Limits vs Input Voltage
Temperature
4
3
2.8
2.6
2.4
2.2
RT = 16 kΩ
RT = 75 kΩ
3.5
3
2.5
2
1.5
1
0.5
0
Rising
Falling
2
-50
-25
0
25
50
75
Temperature (°C)
100
125 150
0
10
20
30 40
Input Voltagae (V)
50
60
70
D013
D012
图6-18. Internal VIN UVLO Voltage vs Temperature
图6-17. COT One-Shot Timer TON vs Input Voltage
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20
15
10
5
12
10
8
6
4
2
Sleep
Shutdown
Sleep
Shutdown
0
0
-50
-25
0
25
Temperature (°C)
50
75
100
125
150
0
10
20
30 40
Input Voltage (V)
50
60
70
D014
D015
图6-19. VIN Sleep and Shutdown Supply Current
图6-20. VIN Sleep and Shutdown Supply Current
vs Temperature
vs Input Voltage
400
350
300
250
200
150
100
350
300
250
200
150
100
50
50
0
COT
PFM
COT
PFM
0
-50
-25
0
25
Temperature (°C)
50
75
100
125
150
0
10
20
30 40
Input Voltage (V)
50
60 70
D016
D017
RRT = 75 kΩ
RRT = 75 kΩ
图6-21. VIN Active Mode Supply Current vs
图6-22. VIN Active Mode Supply Current vs Input
Temperature
Voltage
VOUT
100 mV/DIV
VOUT
100 mV/DIV
IL
50 mA/DIV
VSW
5 V/DIV
VSW
5 V/DIV
IL
200 mA/DIV
20 ms/DIV
2 ms/DIV
5-V, 150-mA Design
5-V, 150-mA Design
图6-23. Full Load Switching Waveforms, COT
图6-24. No Load Switching Waveforms, COT
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IL 200 mA/DIV
VIN 5 V/DIV
VOUT 1 V/DIV
IL 100 mA/DIV
VSW 10 V/DIV
2 ms/DIV
200 ms/DIV
5-V, 150-mA Design
5-V, 150-mA Design
图6-25. Full Load Start-Up, COT
VOUT 100 mV/DIV
图6-26. Short Circuit, COT
VOUT 100 mV/DIV
VSW 5 V/DIV
IL
IL 20 mA/DIV
20 mA/DIV
VSW 10 V/DIV
2 ms/DIV
20 ms/DIV
5-V, 25-mA Design
5-V, 25-mA Design
图6-27. Full Load Switching Waveforms, PFM
图6-28. No Load Switching Waveforms, PFM
IL 20 mA/DIV
VIN 5 V/DIV
VOUT 1 V/DIV
IOUT 50 mA/DIV
VSW 10 V/DIV
100 ms/DIV
2 ms/DIV
5-V, 25-mA Design
5-V, 25-mA Design
图6-29. Full Load Start-Up, PFM
图6-30. Short Circuit, PFM
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7 Detailed Description
7.1 Overview
The LM5165 converter is an easy-to-use synchronous buck DC-DC regulator that operates from a 3-V to
65-V supply voltage. The device is intended for step-down conversions from 3.3-V, 5-V, 12-V, 24-V, and 48-V
unregulated, semi-regulated and fully-regulated supply rails. With integrated high-side and low-side power
MOSFETs, the LM5165 delivers up to 150-mA DC load current with high efficiency and ultra-low input quiescent
current in a very small solution size. Designed for simple implementation, a choice of operating modes offers
flexibility to optimize its usage according to the target application. In constant on-time (COT) mode of operation,
ideal for low-noise, high current, fast load transient requirements, the device operates with predictive on-time
switching pulse. A quasi-fixed switching frequency over the input voltage range is achieved by using an input
voltage feedforward to set the on-time. Alternatively, pulse frequency modulation (PFM) mode, complemented by
an adjustable peak current limit, achieves exceptional light-load efficiency performance. Control loop
compensation is not required with either operating mode, reducing design time and external component count.
The LM5165 incorporates other features for comprehensive system requirements, including an open-drain
Power Good circuit for power-rail sequencing and fault reporting, internally-fixed or externally-adjustable soft-
start, monotonic start-up into prebiased loads, precision enable with customizable hysteresis for programmable
line undervoltage lockout (UVLO), adjustable cycle-by-cycle current limit for optimal inductor sizing, and thermal
shutdown with automatic recovery. These features enable a flexible and easy-to-use platform for a wide range of
applications. The pin arrangement is designed for simple Layout, requiring only a few external components.
7.2 Functional Block Diagram
LM5165
VIN
LDO BIAS
REGULATOR
IN
VDD
VDD UVLO
THERMAL
SHUTDOWN
EN
VIN UVLO
1.212 V
1.144 V
ILIM
I-LIMIT
ADJUST
HYS
ENABLE
VIN
CURRENT
LIMIT
+
ON-TIME ONE
SHOT
SW
Control
Logic
OUT
VIN
ZERO CROSS
DETECT
VOUT/FB
+
HYSTERETIC
MODE
ZC
RT
R1(1)
FEEDBACK
R2(1)
+
GND
SS
ENABLE
VOLTAGE
REFERENCE
PGOOD
1.223 V
UV
PG
REFERENCE
SOFT-START
1.150 V
1.064 V
Note:
(1) R1, R2 are implemented in the xed output voltage versions only.
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7.3 Feature Description
7.3.1 Integrated Power MOSFETs
The LM5165 is a step-down buck converter with integrated high-side PMOS buck switch and low-side NMOS
synchronous switch. During the high-side MOSFET on-time, the SW voltage VSW swings up to approximately
VIN, and the inductor current increases with slope (VIN –VOUT)/LF. When the high-side MOSFET is turned off by
the control logic, the low-side MOSFET turns on after an adaptive deadtime. Inductor current flows through the
low-side MOSFET with slope –VOUT/LF. Duty cycle D is defined as TON/TSW, where TON is the high-side
MOSFET conduction time and TSW is the switching period.
7.3.2 Selectable PFM or COT Mode Converter Operation
图7-1 and 图7-2 show converter schematics for PFM and COT modes of operation.
VIN
VOUT
VIN
VOUT
LF
LF
VIN
EN
VIN
SW
SW
LM5165X
LM5165Y
RUV1
LM5165
RFB1
EN
VOUT
FB
SS
CIN
CIN
COUT
COUT
RUV2
PGOOD
HYS
PGOOD
HYS
SS
RFB2
ILIM
CSS
RILIM
ILIM
RHYS
RT
RT
GND
GND
(a)
(b)
图7-1. PFM Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable Output
Voltage With Programmable Soft Start, Current Limit, and UVLO
VIN
VOUT
VIN
VOUT
LF
LF
VIN
EN
VIN
SW
SW
FB
LM5165X
LM5165Y
RUV1
RFB1
LM5165
RESR
COUT
RESR
EN
VOUT
CIN
CIN
RUV2
PGOOD
HYS
PGOOD
SS
COUT
SS
RFB2
HYS
RT
ILIM
CSS
RILIM
ILIM
RT
RHYS
RRT
RRT
GND
GND
(a)
(b)
图7-2. COT Mode Converter Schematics: (a) Fixed Output Voltage of 5 V or 3.3 V, (b) Adjustable Output
Voltage With Programmable Soft Start, Current Limit, and UVLO
The LM5165 operates in PFM mode when RT is shorted to GND. Configured as such, the LM5165 behaves as a
hysteretic voltage regulator operating in boundary conduction mode, controlling the output voltage within upper
and lower hysteresis levels according to the PFM feedback comparator hysteresis of 10 mV. 图 7-3 is a
representation of the relevant output voltage and inductor current waveforms. The LM5165 provides the required
switching pulses to recharge the output capacitor, followed by a sleep period where most of the internal circuits
are shut off. The load current is supported by the output capacitor during this time, and the LM5165 current
consumption approaches the sleep quiescent current of 10.5 µA. The sleep period duration depends on load
current and output capacitance.
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VIN
SW
Voltage
VOUT
VREF = 1.233 V
10 mV
FB Voltage
(internal)
ILIM
Inductor
Current
IOUT2
t
IOUT1
ACTIVE
SLEEP
ACTIVE SLEEP
ACTIVE SLEEP ACTIVE
图7-3. PFM Mode SW Node Voltage, Feedback Voltage, and Inductor Current Waveforms
When operating in PFM mode at given input and output voltages, the chosen filter inductance dictates the PFM
pulse frequency in 方程式1:
≈
’
÷
◊
VOUT
VOUT
FSW(PFM)
=
∂ 1-
∆
LF ∂IPK(PFM)
V
IN
«
(1)
where
• IPK(PFM) corresponds to one of the four programmable levels for peak limit of inductor current. See Adjustable
Current Limit for more detail.
Configured in COT mode, the LM5165 based converter turns on the high-side MOSFET with on-time inversely
proportional to VIN to operate with essentially fixed switching frequency when in continuous conduction mode
(CCM). Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains highest
efficiency at light load currents by decreasing the effective switching frequency. The COT-controlled LM5165
waveforms in CCM and DEM are represented in 图7-4. The PWM on-time is set by resistor RRT connected from
RT to GND as shown in 图 7-2. The control loop maintains a constant output voltage by adjusting the PWM off-
time.
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VIN
SW
Voltage
Extended
On-Time
VOUT
FB Voltage
(internal)
VREF
4 mV
DCM
Operation
IOUT2
Inductor
Current
CCM
Operation
IOUT1
t
ACTIVE
SLEEP
ACTIVE SLEEP
图7-4. COT Mode SW Node Voltage, Feedback Voltage, and Inductor Current Waveforms
The required on-time adjust resistance for a particular frequency is given in 方程式 2 and tabulated in 表 7-1.
The maximum programmable on-time is 15 µs.
104
VOUT
V
» ÿ
⁄
RRT kW =
∂
»
ÿ
⁄
FSW kHz 1.75
»
ÿ
⁄
(2)
表7-1. On-Time Adjust Resistance (E96 EIA Values) for Various Switching
Frequencies and Output Voltages
RRT (kΩ)
FSW (kHz)
VOUT = 1.8 V
102
VOUT = 3.3 V
187
VOUT = 5 V
287
VOUT = 12 V
681
100
200
300
400
500
600
51.1
95.3
143
240
34
63.4
95.3
226
25.5
47.5
71.5
169
20.5
37.4
57.6
137
16.9
31.6
47.5
115
The choice of control mode and switching frequency requires a compromise between conversion efficiency,
quiescent current, and passive component size. Lower switching frequency implies reduced switching losses
(including gate charge losses, transition losses, and so forth) and higher overall efficiency. Higher switching
frequency, on the other hand, implies a smaller LC output filter and hence a more compact design. Lower
inductance also helps transient response as the large-signal slew rate of inductor current increases. The ideal
switching frequency in a given application is a tradeoff and thus is determined on a case-by-case basis. It relates
to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit
size requirement. At light loads, the PFM converter has a relatively longer sleep time interval and thus operates
with lower input quiescent current and higher efficiency.
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7.3.3 COT Mode Light-Load Operation
Diode emulation mode (DEM) operation occurs when the low-side MOSFET switches off as inductor valley
current reaches zero. Here, the load current is less than half of the peak-to-peak inductor current ripple in CCM.
Turning off the low-side MOSFET at zero current reduces switching loss, and preventing negative current
conduction reduces conduction loss. Power conversion efficiency is thus higher in a DEM converter than an
equivalent forced-PWM CCM converter. With DEM operation, the duration that both power MOSFETs remain off
progressively increases as load current decreases.
7.3.4 Low Dropout Operation and 100% Duty Cycle Mode
If RDSON1 and RDSON2 are the high-side and low-side MOSFET on-state resistances, respectively, and RDCR is
the inductor DC resistance, the duty cycle in COT (CCM) or PFM mode is given by 方程式3.
VOUT + R
+ RDCR ∂I
(
)
VOUT
DSON2
OUT
D =
ö
V - RDSON1 -RDSON2 ∂I
V
IN
OUT
IN
(3)
The LM5165 offers a low input voltage to output voltage dropout by engaging the high-side MOSFET at 100%
duty cycle. In COT mode, a frequency foldback feature effectively extends maximum duty cycle to 100% during
low dropout conditions or load-on transients. Based on the 4-mV FB comparator dropout hysteresis, the duty
cycle extends as needed at low input voltage conditions, corresponding to lower switching frequency. The PWM
on-time extends based on the requirement that the FB voltage exceeds the dropout hysteresis during a given
on-time. 100% duty cycle operation is eventually reached as the input voltage decreases towards the output
setpoint. The output voltage stays in regulation at a lower supply voltage, thus achieving an extremely low
dropout voltage.
Note that PFM mode operation provides an inherently natural transition to 100% duty cycle if needed for low
dropout applications.
Use 方程式4 to calculate the minimum input voltage to maintain output regulation.
V
= VOUT +IOUT ∂ RDSON1 +RDCR
IN(min)
(4)
7.3.5 Adjustable Output Voltage (FB)
Three voltage feedback options are available: the fixed 3.3-V and 5-V versions include internal feedback
resistors that sense the output directly through the VOUT pin; the adjustable voltage option senses the output
through an external resistor divider connected from the output to the FB pin.
The LM5165 voltage regulation loop regulates the output voltage by maintaining the FB voltage equal to the
internal reference voltage, VREF1. A resistor divider programs the ratio from output voltage VOUT to FB. For a
target VOUT setpoint, calculate RFB2 based on the selected RFB1 using 方程式5.
1.223V
RFB2
=
∂RFB1
VOUT -1.223V
(5)
Selecting RFB1 in the range of 100 kΩ to 1 MΩ is recommended for most applications. A larger RFB1 consumes
less DC current, which is mandatory if light-load efficiency is critical. However, RFB1 larger than 1 MΩ is not
recommended as the feedback path becomes more susceptible to noise. High feedback resistances generally
require more careful feedback path PCB layout. It is important to route the feedback trace away from the noisy
area of the PCB. For more layout recommendations, see Layout.
7.3.6 Adjustable Current Limit
The LM5165 manages overcurrent conditions by cycle-by-cycle current limiting of the peak inductor current. The
current sensed in the high-side MOSFET is compared every switching cycle to the current limit threshold set by
the ILIM pin. Current is sensed after a leading-edge blanking time following the high-side MOSFET turnon
transition. The propagation delay of current limit comparator is 100 ns.
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Four programmable peak current levels are available: 60 mA, 120 mA, 180 mA and 240 mA, corresponding to
resistors of 100 kΩ, 56.2 kΩ, 24.9 kΩ and 0 Ω connected at the ILIM pin, respectively. In turn, 25-mA, 50-mA,
75-mA, and 100-mA output current levels in boundary conduction mode PFM operation are possible,
respectively.
Note that in PFM mode, the inductor current ramps from zero to the chosen peak threshold every switching
cycle. Consequently, the maximum output current is equal to half the peak inductor current. Meanwhile, the
corresponding output current capability in COT mode is higher as the ripple current is determined by the input
and output voltage and the chosen inductance.
7.3.7 Precision Enable (EN) and Hysteresis (HYS)
The precision EN input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed
independently through the HYS pin for application specific power-up and power-down requirements. EN
connects to a comparator-based input referenced to a 1.212-V bandgap voltage with 68-mV hysteresis. An
external logic signal can be used to drive the EN input to toggle the output on and off and for system sequencing
or protection. The simplest way to enable the LM5165 operation is to connect EN directly to VIN. This allows the
LM5165 to start up when VIN is within its valid operating range. However, many applications benefit from using a
resistor divider RUV1 and RUV2 as shown in 图 7-5 to establish a precision UVLO level. In tandem with the EN
setting, use HYS to increase the voltage hysteresis as needed.
VIN
VIN
LM5165
LM5165
RUV1
RUV1
Enable
Comparator
Enable
Comparator
EN
EN
7
7
9
RUV2
RUV2
1.212 V
1.144 V
1.212 V
1.144 V
RHYS
HYS
80Ω
(a)
(b)
图7-5. Programmable Input Voltage UVLO With (a) Fixed Hysteresis, (b) Adjustable Hysteresis
Use 方程式6 and 方程式7 to calculate the input UVLO voltages turnon and turnoff voltages, respectively.
≈
’
÷
◊
RUV1
RUV2
V
= 1.212V ∂ 1+
∆
IN(on)
«
(6)
≈
’
÷
◊
RUV1
V
= 1.144V ∂ 1+
∆
IN(off)
RUV2 + RHYS
«
(7)
There is also a low IQ shutdown mode when EN is pulled below a base-emitter voltage drop (approximately 0.6
V at room temperature). If EN is below this hard shutdown threshold, the internal LDO regulator powers off and
the internal bias supply rail collapses, shutting down the bias currents of the LM5165. The LM5165 operates in
standby mode when the EN voltage is between the hard shutdown and precision enable thresholds.
7.3.8 Power Good (PGOOD)
The LM5165 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level. Use
the PGOOD signal for start-up sequencing of downstream converters, as shown in 图 7-6, or for fault protection
and output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater
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than 12 V. Typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease
the voltage from a higher voltage pullup rail.
VIN(on) = 4.50 V
VIN(off) = 3.15 V
RUV1
VOUT(COMMANDER) = 2.5 V
VOUT(RESPONDER) = 1.5 V
100 k
LM5165
LM5165
EN
7
9
EN
7
9
RFB3
22.3 k
RPGOOD
10 k
RUV2
PGOOD
6
8
RFB1
100 k
PGOOD
6
36.5 k
HYS
HYS
FB
FB
8
1.223 V
1.223 V
RHYS
20 k
RFB4
100 k
RFB2
95.3 k
Regulator #1
Startup based on Input
Voltage UVLO
Regulator #2
Sequen al Startup
based on PGOOD
图7-6. Commander-Responder Sequencing Implementation Using PGOOD and EN
When the FB voltage exceeds 94% of the internal reference VREF1, the internal PGOOD switch turns off and
PGOOD can be pulled high by the external pullup. If the FB voltage falls below 87% of VREF1, the internal
PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. The
rising edge of PGOOD has a built-in deglitch delay of 5 µs.
7.3.9 Configurable Soft Start (SS)
The LM5165 has a flexible and easy-to-use soft-start control pin, SS. The soft-start feature prevents inrush
current impacting the LM5165 and the input supply when power is first applied. Soft start is achieved by slowly
ramping up the target regulation voltage when the device is first enabled or powered up. Selectable and
adjustable start-up timing options include minimum delay (no soft-start), 900-µs internally fixed soft start, and an
externally programmable soft start.
The simplest way to use the LM5165 is to leave the SS pin open. The LM5165 employs the internal soft-start
control ramp and starts up to the regulated output voltage in 900 µs. In applications with a large amount of
output capacitance, higher VOUT, or other special requirements, extend the soft-start time by connecting an
external capacitor CSS from SS to GND. Longer soft-start time further reduces the supply current needed to
charge the output capacitors and supply any output loading. An internal current source ISS of 10 µA charges CSS
and generates a ramp to control the ramp rate of the output voltage. Use 方程式 8 to calculate the CSS
capacitance for a desired soft-start time tSS
.
CSS nF = 8.1∂t ms
»
ÿ
»
ÿ
⁄
SS
⁄
(8)
CSS is discharged by an internal FET when VOUT is shutdown by EN, UVLO, or thermal shutdown.
It is desirable in some applications for the output voltage to reach its nominal setpoint in the shortest possible
time. Connecting a 100-kΩ resistor from SS to GND disables the soft-start circuit, and the LM5165 operates in
current limit during start-up to rapidly charge the output capacitance.
As negative inductor current is prevented, the LM5165 is capable of start-up into prebiased output conditions.
With a prebiased output voltage, the LM5165 waits until the soft-start ramp allows regulation above the
prebiased voltage and then follows the soft-start ramp to the regulation setpoint.
7.3.10 Thermal Shutdown
Thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related to
overheating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C to prevent
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further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the
LM5165 restarts when the junction temperature falls to 160°C.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides ON and OFF control for the LM5165. When VEN is below approximately 0.6 V, the device is
in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown
mode drops to 4.6 µA at VIN = 12 V. The LM5165 also employs internal bias rail undervoltage protection. If the
internal bias supply voltage is below its UV threshold, the regulator remains off.
7.4.2 Standby Mode
The internal bias rail LDO has a lower enable threshold than the regulator itself. When VEN is above 0.6 V and
below the precision enable threshold (1.212 V typically), the internal LDO is on and regulating. The precision
enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action and voltage
regulation are not enabled until VEN rises above the precision enable threshold.
7.4.3 Active Mode in COT
The LM5165 is in active mode when VEN is above the precision enable threshold and the internal bias rail is
above its UV threshold. In COT active mode, the LM5165 is in one of three modes depending on the load
current:
1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current
ripple;
2. Pulse skipping and diode emulation mode (DEM) when the load current is less than half of the peak-to-peak
inductor current ripple in CCM operation. Refer to COT More Light-Load Operation for more detail;
3. Frequency foldback mode to maintain output regulation at low dropout and for improved load-on transient
response. Refer to Low Dropout Operation and 100% Duty Cycle Mode for more detail.
7.4.4 Active Mode in PFM
Similarly, the LM5165 is in PFM active mode when VEN and the internal bias rail are above the relevant
thresholds, FB has fallen below the lower hysteresis level (VREF1), and boundary conduction mode is recharging
the output capacitor to the upper hysteresis level (VREF2). There is a 4-µs wake-up delay from sleep to active
states.
7.4.5 Sleep Mode in PFM
The LM5165 is in PFM sleep mode when VEN and the internal bias rail are above the relevant threshold levels,
VFB has exceeded the upper hysteresis level (VREF2), and the output capacitor is sourcing the load current. In
PFM sleep mode, the LM5165 operates with very low quiescent current.
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8 Applications and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The LM5165 only requires a few external components to convert from a wide range of supply voltages to a fixed
output voltage. To expedite and streamline the process of designing of a LM5165-based converter, a
comprehensive LM5165 Quick-start design tool is available for download to assist the designer with component
selection for a given application. WEBENCH online software is also available to generate complete designs,
leveraging iterative design procedures and access to comprehensive component databases. The following
sections discuss the design procedure for both COT and PFM modes using specific circuit design examples.
As mentioned previously, the LM5165 also integrates several optional features to meet system design
requirements, including precision enable, UVLO, programmable soft start, programmable switching frequency in
COT mode, adjustable current limit, and PGOOD indicator. Each application incorporates these features as
needed for a more comprehensive design. The application circuits detailed below show LM5165 configuration
options suitable for several application use cases. Refer to the LM5165EVM-HD-C50X and LM5165EVM-HD-
P50A EVM user's guides for more detail.
8.2 Typical Applications
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of an LM5165-powered
implementation, refer to Field Transmitter with Bluetooth® Low Energy Connectivity Powered from 4 to 20-mA Current Loop reference
design.
8.2.1 Design 1: Wide VIN, Low IQ COT Converter Rated at 5 V, 150 mA
The schematic diagram of a 5-V, 150-mA COT converter is given in 图8-1.
LF
U1
220 ꢀH
VOUT = 5 V
VIN = 5 V...65 V
VIN
EN
SW
IOUT = 150 mA
LM5165X
RESR
CIN
VOUT
1.5 W
1 ꢀF
COUT
HYS
SS
ILIM
GND
22 ꢀF
CSS
RT
RRT
133 kW
47 nF
PGOOD
图8-1. Schematic for Design 1 With VIN(nom) = 12 V, VOUT = 5 V, IOUT(max) = 150 mA, FSW(nom) = 220 kHz
8.2.1.1 Design Requirements
The target full-load efficiency is 91% based on a nominal input voltage of 12 V and an output voltage of 5 V. The
required input voltage range is 5 V to 65 V. The LM5165X is chosen to deliver a fixed 5-V output voltage. The
switching frequency is set by resistor RRT at 220 kHz. The output voltage soft-start time is 6 ms. The required
components are listed in 表8-1.
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表8-1. List of Components for Design 1
REF DES
CIN
QTY SPECIFICATION
VENDOR
PART NUMBER
1
1
1 µF, 100 V, X7R, 1206 ceramic
TDK
C3216X7R2A105K160AA
GRM31CR71A226KE15L
COUT
22 µF, 10 V, X7R, 1206 ceramic
Murata
Würth Electronik WE-TPC 5828 744053221
220 µH ±20%, 0.29 A, 0.92 Ωtyp DCR, 5.8 x 5.8 x 2.8 mm
220 µH ±30%, 0.3 A, 1.25 Ωmax DCR, 5.8 x 5.8 x 3.0 mm
1.5 Ω, 5%, 0402
LF
1
Bourns
Std
SRR5028-221Y
RESR
R RT
CSS
U1
1
1
1
1
Std
Std
Std
133 kΩ, 1%, 0402
47 nF, 10 V, X7R, 0402 ceramic
Std
Std
LM5165X Synchronous Buck Converter, VSON-10, 5V Fixed
TI
LM5165XDRCR
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5165 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Switching Frequency –RT
As mentioned, the switching frequency of a COT-configured LM5165 is set by the on-time programming resistor
at the RT pin. As shown by 方程式2, a standard 1% resistor of 133 kΩgives a switching frequency of 230 kHz.
Note that at very low duty cycles, the minimum controllable on-time of the high-side MOSFET, TON(min), of 180 ns
may affect choice of switching frequency. In CCM, TON(min) limits the voltage conversion step-down ratio for a
given switching frequency. The minimum controllable duty cycle is given by 方程式9:
DMIN = TON(min) ∂ FSW
(9)
Given a fixed TON(min), it follows that higher switching frequency implies a larger minimum controllable duty cycle.
Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range,
solution size and efficiency. The maximum supply voltage for a given TON(min) before switching frequency
reduction occurs is given by 方程式10.
VOUT
V
=
IN(max)
TON(min) ∂ FSW
(10)
8.2.1.2.3 Filter Inductor –LF
Added additional statement to inductor selection in applications section.
The inductor ripple current (assuming CCM operation) and peak inductor current are given respectively by 方程
式11 and 方程式12.
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≈
’
÷
◊
VOUT
VOUT
DIL =
∂ 1-
∆
FSW ∂LF
V
IN
«
(11)
(12)
DIL
2
IL(peak) = IOUT(max)
+
For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 50%
of the rated load current at nominal input voltage. Calculate the inductance using 方程式13.
≈
∆
«
’
VOUT
VOUT
LF =
∂ 1-
∆
÷
÷
◊
FSW ∂ DIL(nom)
V
IN(nom)
(13)
Choosing a 220-µH inductor in this design results in 55-mA peak-to-peak ripple current at nominal input voltage
of 12 V, equivalent to 37% of the 150-mA rated load current. The peak inductor current at maximum input
voltage of 65 V is 195 mA, sufficiently below the LM5165 peak current limit of 240 mA.
The inductors selected for the following designs were meant for nominal operating conditions, and component
behavior can deviate from expected results in situations like over current. Check the inductor data sheet to
ensure that the inductor saturation current is well above the current limit setting of a particular design. Ferrite
designs have low core loss and are preferred at high switching frequencies, so design goals can then
concentrate on copper loss and preventing saturation. However, ferrite core materials exhibit a hard saturation
characteristic – the inductance collapses abruptly when the saturation current is exceeded. This results in an
abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and
compromised reliability. Note that inductor saturation current generally deceases as the core temperature
increases.
8.2.1.2.4 Output Capacitors –COUT
Select the output capacitor to limit the capacitive voltage ripple at the converter output. This is the sinusoidal
ripple voltage that arises from the triangular ripple current flowing in the capacitor. Select an output capacitance
using 方程式14 to limit the voltage ripple component to 0.5% of the output voltage.
DIL(nom) ∂100
COUT
í
FSW ∂ VOUT
(14)
Substituting ΔIL(nom) of 55 mA gives COUT greater than 5 μF. Mindful of the voltage coefficient of ceramic
capacitors, select a 22-µF, 10-V capacitor with X7R dielectric in 1206 footprint.
8.2.1.2.5 Series Ripple Resistor –RESR
Select a series resistor such that sufficient ripple in phase with the SW node voltage appears at the feedback
node, FB. Use 方程式15 to calculate the required ripple resistance, designated RESR
.
20mV ∂ VOUT
VREF ∂ DIL(nom)
RESR
í
(15)
With VOUT of 5 V, VREF of 1.223 V, and ΔIL(nom) of 55 mA at the nominal input voltage of 12 V, the required RESR
is 1.5 Ω. Calculate the total output voltage ripple in CCM using 方程式16.
2
≈
∆
«
’
÷
◊
1
2
DVOUT = DIL ∂ RESR
+
8 ∂FSW ∂COUT
(16)
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8.2.1.2.6 Input Capacitor –CIN
An input capacitor is necessary to limit the input ripple voltage while providing switching-frequency AC current to
the buck power stage. To minimize the parasitic inductance in the switching loop, position the input capacitors as
close as possible to the VIN and GND pins of the LM5165. The input capacitors conduct a square-wave current
of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component of AC
ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak ripple
voltage amplitude is given by 方程式17.
IOUT ∂D ∂ 1- D
(
)
+ IOUT ∂RESR
DV
=
IN
FSW ∂CIN
(17)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by 方程式18.
IOUT ∂D∂ 1-D
(
)
CIN
í
FSW ∂ DVIN -IOUT ∂RESR
(18)
The recommended high-frequency capacitance is 1 µF or higher and must be a high-quality ceramic type X5R or
X7R with sufficient voltage rating. Based on the voltage coefficient of ceramic capacitors, choose a voltage rating
of twice the maximum input voltage. Additionally, some bulk capacitance is required if the LM5165 circuit is not
located within approximately 5 cm from the input voltage source. This capacitor provides damping to the
resonance associated with parasitic inductance of the supply lines and high-Q ceramics.
8.2.1.2.7 Soft-Start Capacitor –CSS
Connect an external soft-start capacitor for a specific soft-start time. In this example, select a soft-start
capacitance of 47 nF based on 方程式8 to achieve a soft-start time of 6 ms.
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8.2.1.3 Application Curves
Unless otherwise stated, application performance curves were taken at TA = 25°C.
100
5.1
90
5.05
80
70
5
60
VIN = 8V
VIN = 12V
50
4.95
VIN = 24V
VIN = 36V
VIN = 65V
40
VIN = 12V
VIN = 24V
30
0.1
4.9
1
10
100 150
D102
0
25
50
75
Output Current (mA)
100
125 150
Output Current (mA)
VOUT = 5 V
图8-2. Efficiency
图8-3. Load Regulation
70
60
50
40
30
20
10
0
1
MHz
10 MHz
VOUT 100 mV/DIV
CISPR22
Peak detector
VSW 5 V/DIV
20 ms/DIV
Average detector
-10
Start 150 kHz
Stop 30 MHz
VIN = 12 V
IOUT = 0 mA
Date:
26.FEB.2016 11:12:48
VIN = 13.5 V IOUT = 100 mA
LIN = 22 µH CIN(EXT) = 10 µF
图8-5. SW Node and Output Ripple Voltage, No
图8-4. EMI Plot –CISPR 22 Filtered Emissions
Load
VOUT 100 mV/DIV
VOUT 100 mV/DIV
VSW 2 V/DIV
4 ms/DIV
4 ms/DIV
VSW 5 V/DIV
VIN = 12 V
IOUT = 150 mA
VIN = 5.7 V
IOUT = 150 mA
图8-6. SW Node and Output Ripple Voltage, Full
图8-7. SW Node and Output Ripple Voltage
Load
Showing Frequency Foldback Near Dropout
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VOUT 1 V/DIV
VOUT 1 V/DIV
VIN 5 V/DIV
VEN 1 V/DIV
IOUT 50 mA/DIV
IOUT 50 mA/DIV
2 ms/DIV
2 ms/DIV
VIN = 24 V
VIN stepped to 24 V
30-ΩLoad
30-ΩLoad
图8-9. Enable ON and OFF
图8-8. Startup, Full Load
VIN 1 V/DIV
VIN 1 V/DIV
VOUT 1 V/DIV
VOUT 1 V/DIV
IOUT 50 mA/DIV
IOUT 50 mA/DIV
4 ms/DIV
4 ms/DIV
VIN brownout to 3.2 V
VIN brownout to 3.2 V
图8-10. Dropout Performance, 75-mA Resistive
图8-11. Dropout Performance, 150-mA Resistive
Load
Load
VOUT 100 mV/DIV
VIN 2 V/DIV
IOUT 50 mA/DIV
IL 50 mA/DIV
VOUT 2 V/DIV
10 ms/DIV
200 ms/DIV
VIN = 24 V
IOUT = 150 mA
图8-12. Load Transient, 50 mA to 150 mA, 1 A/µs
图8-13. Input Transient (Automotive Cold Crank
Profile)
8.2.2 Design 2: Small Solution Size PFM Converter Rated at 3.3 V, 50 mA
The schematic diagram of a 3.3-V, 50-mA PFM converter with minimum component count is given in 图8-14.
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LF
U1
47 ꢀH
VOUT = 3.3 V
IOUT = 50 mA
VIN = 3.5 V...65 V
VIN
SW
LM5165Y
CIN
COUT
EN
VOUT
1 ꢀF
10 ꢀF
SS
ILIM
GND
HYS
PGOOD
RT
RILIM
56.2 kW
图8-14. Schematic for Design 2 With VIN(nom) = 12 V, VOUT = 3.3 V, IOUT(max) = 50 mA, FSW(nom) = 350 kHz
8.2.2.1 Design Requirements
The target full-load efficiency of this design is 88% based on a nominal input voltage of 12 V and an output
voltage of 3.3 V. The required total input voltage range is 3.5 V to 65 V. The LM5165 has an internally-set soft-
start time of 900 µs and an adjustable peak current limit threshold. The BOM is listed in 表8-2.
表8-2. List of Components for Design 2
REF DES
QTY SPECIFICATION
VENDOR
PART NUMBER
C2012X7S2A474M125AE
JMK212AB7106KG-T
GRM21BR70J106KE76K
LPS4018-473MRC
74404042470
CIN
1
1 µF, 100 V, X7S, 0805 ceramic
TDK
Taiyo Yuden
Murata
Coilcraft
Würth
COUT
1
10 µF, 6.3 V, X7R, 0805 ceramic
47 µH ±20%, 0.56 A, 650 mΩmaximum DCR, 3.9 × 3.9 × 1.7 mm
47 µH ±20%, 0.7 A, 620 mΩtypical DCR, 4.0 × 4.0 × 1.8 mm
47 µH ±20%, 0.57 A, 650 mΩtypical DCR, 4.0 × 4.0 × 1.8 mm
56.2 kΩ, 1%, 0402
LF
1
Taiyo Yuden
Std
NR4018T470M
R ILIM
U1
1
1
Std
LM5165Y Synchronous Buck Converter, VSON-10, 3.3-V Fixed
TI
LM5165YDRCR
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Peak Current Limit Setting –RILIM
Install a 56.2-kΩ resistor from ILIM to GND to select a 120-mA peak current limit threshold setting to meet the
rated output current of 50 mA.
8.2.2.2.2 Switching Frequency –LF
Tie RT to GND to select PFM mode of operation. The inductor, input voltage, output voltage, and peak current
determine the pulse switching frequency of a PFM-configured LM5165. For a given input voltage, output voltage
and peak current, the inductance of LF sets the switching frequency when the output is in regulation. Use 方程式
19 to select an inductance of 47 µH based on the target PFM converter switching frequency of 350 kHz at 12-V
input.
≈
’
÷
◊
VOUT
VOUT
LF =
∂ 1-
∆
FSW(PFM) ∂IPK(PFM)
V
IN
«
(19)
IPK(PFM) in this example is the peak current limit setting of 120 mA plus an additional 10% margin added to
include the effect of the 100-ns peak current comparator delay. An additional constraint on the inductance is the
180-ns minimum on-time of the high-side MOSFET. Therefore, to keep the inductor current well controlled,
choose an inductance that is larger than LF(min) using 方程式 20 where VIN(max) is the maximum input supply
voltage for the application, tON(min) is 180 ns, and IL(max) is the maximum allowed peak inductor current.
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V
IN(max) ∂ tON(min)
LF(min)
=
IL(max)
(20)
Choose an inductor with saturation current rating above the peak current limit setting, and allow for derating of
the saturation current at the highest expected operating temperature.
8.2.2.2.3 Output Capacitor –COUT
The output capacitor, COUT, filters the inductor ripple current and stores energy to meet the load current
requirement when the LM5165 is in sleep mode. The output ripple has a base component of amplitude VOUT/123
related to the 10-mV typical feedback comparator hysteresis in PFM. The wakeup time from sleep to active
mode adds a ripple voltage component that is a function of the output current. Approximate the total output ripple
by 方程式21.
IOUT ∂ 4ꢀs VOUT
DVOUT
=
+
COUT
123
(21)
Also, the output capacitance must be large enough to accept the energy stored in the inductor without a large
deviation in output voltage. Setting this voltage change equal to 0.5% of the output voltage results in:
2
I
≈
’
PK(PFM)
COUT í 100 ∂L ∂
∆
∆
÷
÷
F
VOUT
«
◊
(22)
In general, select the capacitance of COUT to limit the output voltage ripple at full load current, ensuring that it is
rated for worst-case RMS ripple current given by IRMS = IPK(PFM)/2. In this design example, choose a 10-µF, 6.3-
V ceramic output capacitor with X7R dielectric and 0805 footprint.
8.2.2.2.4 Input Capacitor –CIN
The input capacitor, CIN, filters the high-side MOSFET triangular current waveform, see 图8-36. To prevent large
ripple voltage, use a low-ESR ceramic input capacitor sized for the worst-case RMS ripple current given by IRMS
= IOUT/2. In this design example, choose a 1-µF, 100-V ceramic input capacitor with X7S dielectric and 0805
footprint.
For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's Power House blog
series.
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8.2.2.3 Application Curves
100
VOUT 100 mV/DIV
90
80
70
VSW 5 V/DIV
60
VIN = 8V
50
40
30
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
10 ms/DIV
0.1
1
10
50
D103
VIN = 12 V
IOUT = 50 mA
Output Current (mA)
VOUT = 3.3 V
图8-16. SW Node and Output Ripple Voltage, Full
Load
图8-15. Efficiency
VEN 1 V/DIV
VIN 2 V/DIV
VOUT 1 V/DIV
VOUT 1 V/DIV
IOUT 20 mA/DIV
IOUT 20 mA/DIV
1 ms/DIV
1 ms/DIV
VIN = 12 V
VIN stepped to 12 V
66-ΩLoad
66-ΩLoad
图8-18. Enable ON and OFF
图8-17. Start-Up, Full Load
VIN 2 V/DIV
VOUT 100 mV/DIV
VOUT 1 V/DIV
IOUT 20 mA/DIV
200 ms/DIV
10 ms/DIV
IOUT = 50 mA
VIN = 12 V
图8-20. Input Voltage Transient (Atuomotive Cold
图8-19. Load Transient, 0 mA to 50 mA, 1 A/µs
Crank Profile)
8.2.3 Design 3: High Density 12-V, 75-mA PFM Converter
The schematic diagram of 12-V, 75-mA PFM converter is given in 图8-21.
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LF
U1
47 ꢀH
VOUT = 12 V
VIN = 18 V...65 V
VIN
EN
SW
IOUT = 75 mA
RUV1
RFB1
LM5165
10 MW
1 MW
COUT
CIN
FB
SS
10 ꢀF
RUV2
1 ꢀF
PGOOD
HYS
825 kW
RFB2
CSS
ILIM
113 kW
22 nF
RHYS
RILIM
37.4 kW
24.9 kW
RT
GND
图8-21. Schematic for Design 3 With VIN(nom) = 24 V, VOUT = 12 V, IOUT(max) = 75 mA, FSW(nom) = 500 kHz
8.2.3.1 Design Requirements
The full-load efficiency specification is 92% based on a nominal input voltage of 24 V and an output voltage of 12
V. The total input voltage range is 18 V to 65 V, with UVLO turnon and turnoff at 16 V and 14.5 V, respectively.
The output voltage setpoint is established by feedback resistors, RFB1 and RFB2. The switching frequency is set
by inductor LF at 500 kHz at nominal input voltage. The required components are listed in 表8-3.
表8-3. List of Components for Design 3
REF DES QTY SPECIFICATION
VENDOR
Murata
TDK
PART NUMBER
1 µF, 100 V, X7S, 0805 ceramic
GRJ21BC72A105KE11L
CGA4J3X7S2A105K125AE
EMK212BB7106MG-T
CGA4J1X7S1C106K125AC
CIN
1
1 µF, 100 V, X7S, 0805 ceramic, AEC-Q200
10 µF, 16 V, X7R, 0805 ceramic
Taiyo Yuden
TDK
COUT
1
1
10 µF, 16 V, X7R, 0805 ceramic, AEC-Q200
47 µH ±20%, 0.56 A, 650 mΩmaximum DCR, 3.9 × 3.9 × 1.7 mm
AEC-Q200
LF
Coilcraft
LPS4018-473MRC
R ILIM
R FB1
R FB2
R UV1
R UV2
R HYS
C SS
1
1
1
1
1
1
1
1
Std
Std
Std
Std
Std
Std
Std
TI
Std
24.9 kΩ, 1%, 0402
Std
1 MΩ, 1%, 0402
Std
113 kΩ, 1%, 0402
Std
10 MΩ, 1%, 0603
Std
825 kΩ, 1%, 0402
Std
37.4 kΩ, 1%, 0402
22 nF, 10 V, X7R, 0402
LM5165 Synchronous Buck Converter, VSON-10, 3 mm × 3 mm
Std
U1
LM5165DRCR
8.2.3.2 Detailed Design Procedure
The component selection procedure for this PFM design is quite similar to that of Design 2, see 图8-14.
8.2.3.2.1 Peak Current Limit Setting –RILIM
Install a 24.9-kΩ resistor from ILIM to GND to select the 180-mA peak current limit setting for a rated output
current of 75 mA.
8.2.3.2.2 Switching Frequency –LF
Tie RT to GND to select PFM mode of operation. Set the switching frequency by the filter inductance, LF.
Calculate an inductance of 47 µH based on the target PFM converter switching frequency of 500 kHz at 24-V
input using 方程式 19. Use a peak current limit setting, IPK(PFM), of 180 mA plus an additional 50% margin in this
high-frequency design to include the effect of the 100-ns current limit comparator delay. Choose an inductor with
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saturation current rating well above the peak current limit setting, and allow for derating of the saturation current
at the highest expected operating temperature.
8.2.3.2.3 Input and Output Capacitors –CIN, COUT
Choose a 1-µF, 100-V ceramic input capacitor with 0805 footprint. Such a capacitor is typically available in X5R
or X7S dielectric. Based on 方程式 22, select a 10-µF, 16-V ceramic output capacitor with X7R dielectric and
0805 footprint.
8.2.3.2.4 Feedback Resistors –RFB1, RFB2
The output voltage of the LM5165 is externally adjustable using a resistor divider network. The divider network
comprises the upper feedback resistor RFB1 and lower feedback resistor RFB2. Select RFB1 of 1 MΩ to minimize
quiescent current and improve light-load efficiency in this application. With the desired output voltage setpoint of
12 V and VFB = 1.223 V, calculate the resistance of RFB2 using 方程式 5 as 113.5 kΩ. Choose the closest
available standard value of 113 kΩfor RFB2. Please refer to Adjustable Output Voltage (FB) for more detail.
8.2.3.2.5 Undervoltage Lockout Setpoint –RUV1, RUV2, RHYS
Adjust the undervoltage lockout (UVLO) using an externally-connected resistor divider network of RUV1, RUV2
,
and RHYS. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brownouts when the input voltage is falling. The EN rising threshold for the LM5165 is 1.212 V.
Rearranging 方程式6 and 方程式7, the expressions to calculate RUV2 and RHYS are as follows:
VEN(on)
RUV2
=
∂RUV1
V
- VEN(on)
IN(on)
(23)
(24)
VEN(off)
- VEN(off)
RHYS
=
∂RUV1 -RUV2
V
IN(off)
Choose RUV1 as 10 MΩ to minimize input quiescent current. Given the desired input voltage UVLO thresholds of
16 V and 14.5 V, calculate the resistance of RUV2 and RHYS as 825 kΩ and 37.4 kΩ, respectively. See 节 7.3.7
for more detail.
8.2.3.2.6 Soft Start –CSS
Install a 22-nF capacitor from SS to GND for a soft-start time of 3 ms.
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8.2.3.3 Application Curves
100
90
80
70
60
50
40
30
VOUT 2 V/DIV
VIN 5 V/DIV
IOUT 20 mA/DIV
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
1 ms/DIV
0.1
1
10
75
D105
VIN stepped to 24 V
160-ΩLoad
Output Current (mA)
VOUT = 12 V
图8-23. Start-Up, Full Load
图8-22. Efficiency
VOUT 500 mV/DIV
VOUT 500 mV/DIV
VSW 10 V/DIV
VSW 10 V/DIV
10 ms/DIV
10 ms/DIV
VIN = 24 V
IOUT = 75 mA
VIN = 24 V
IOUT = 0 mA
图8-24. SW Node and Output Ripple Voltage, Full
图8-25. SW Node and Output Ripple Voltage, No
Load
Load
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8.2.4 Design 4: 3.3-V, 150-mA COT Converter With High Efficiency
The schematic diagram of a 3.3-V, 150-mA COT converter is given in 图8-26.
LF
U1
150 ꢀH
VOUT = 3.3 V *
IOUT = 150 mA
VIN = 3 V...65 V
VIN
EN
SW
LM5165Y
RESR
CIN
VOUT
0.5 W
1 ꢀF
COUT
HYS
RT
SS
22 ꢀF
CSS
ILIM
RRT
121 kW
33 nF
GND
PGOOD
* VOUT tracks VIN if VIN Ç 3.3V
图8-26. Schematic for Design 4 With VIN(nom) = 24 V, VOUT = 3.3 V, IOUT(max) = 150 mA, FSW(nom) = 160 kHz
8.2.4.1 Design Requirements
The target full-load efficiency is 91% based on a nominal input voltage of 24 V and an output voltage of 3.3 V.
The required input voltage range is 3 V to 65 V. The LM5165Y is chosen to deliver a fixed 3.3-V output voltage.
The switching frequency is set by resistor RRT at approximately 160 kHz. The output voltage soft-start time is 4
ms. The required components are listed in 表 8-4. The component selection procedure for this COT design is
quite similar to that of Design 1, see 图8-1.
表8-4. List of Components for Design 4
REF DES
CIN
QTY SPECIFICATION
VENDOR
Murata
Murata
Coilcraft
Std
PART NUMBER
GRM31CR72A105KA01L
GRM21BR660J226ME39K
LPS5030-154MLC
Std
1
1
1
1
1
1
1
1 µF, 100 V, X7R, 1206 ceramic
COUT
LF
22 µF, 6.3 V, X7S, 0805 ceramic
150 µH ±20%, 0.29 A, 0.86 Ωtypical DCR, 4.8 × 4.8 × 2.9 mm
0.5 Ω, 5%, 0402
RESR
R RT
CSS
Std
Std
121 kΩ, 1%, 0402
33 nF, 10 V, X7R, 0402 ceramic
Std
Std
U1
LM5165Y Synchronous Buck Converter, VSON-10, 3.3-V Fixed
TI
LM5165YDRCR
8.2.4.2 Application Curves
100
90
80
70
60
50
40
30
VOUT 0.5 V/DIV
VIN = 8V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 65V
4 ms/DIV
VSW 5 V/DIV
VIN = 24 V
IOUT = 150 mA
0.1
1
10
100 150
D104
图8-28. SW Node and Output Ripple Voltages, Full
Output Current (mA)
Load
图8-27. Efficiency
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8.2.5 Design 5: 15-V, 150-mA, 600-kHz COT Converter
The schematic diagram of a 15-V, 150-mA COT converter is given in 图8-29.
LF
U1
150 ꢀH
VOUT = 15 V
IOUT = 150 mA
VIN = 24 V...48 V
VIN
EN
SW
RUV1
CFF
10 pF
RFB1
499 kW
LM5165
RESR
10 MW
0.5 W
FB
SS
CIN
RUV2
681 kW
COUT
1 ꢀF
PGOOD
RFB2
44.2 kW
10 ꢀF
HYS
RT
CSS
ILIM
RHYS
40.2 kW
47 nF
GND
RRT
143 kW
图8-29. Schematic for Design 5 With VIN(nom) = 36 V, VOUT = 15 V, IOUT(max) = 150 mA, FSW(nom) = 600 kHz
8.2.5.1 Design Requirements
The target full-load efficiency is 92% based on a nominal input voltage of 36 V and an output voltage of 15 V.
The input voltage operating range is 24 V to 48 V, but transients as high as 65 V are possible in the application.
UVLO turnon and turnoff are set at 19 V and 17 V, respectively. The LM5165 switching frequency is set at
approximately 600 kHz by resistor RRT of 143 kΩ. The output voltage soft-start time is 6 ms. The required
components are listed in 表 8-5. The component selection procedure for this COT design is quite similar to that
of Design 1, see 图8-1.
表8-5. List of Components for Design 5
REF DES
CIN
QTY SPECIFICATION
VENDOR
PART NUMBER
1
1
1
1
1
1
1
1
1
1
1
1
1
1 µF, 100 V, X7R, 1206 ceramic
AVX
12061C105KAT2A
COUT
LF
10 µF, 25 V, X7R, 1206 ceramic
150 µH ±20%, 0.29 A, 0.86 Ωtypical DCR, 4.8 × 4.8 × 2.9 mm
2.2 Ω, 5%, 0402
Taiyo Yuden
Coilcraft
Std
TMK316B7106KL-TD
LPS5030-154MLC
RESR
R RT
R FB1
R FB2
R UV1
R UV2
R HYS
CFF
Std
Std
Std
143 kΩ, 1%, 0402
Std
Std
499 kΩ, 1%, 0402
Std
Std
44.2 kΩ, 1%, 0402
Std
Std
10 MΩ, 1%, 0603
Std
Std
681 kΩ, 1%, 0402
Std
Std
40.2 kΩ, 1%, 0402
10 pF, 10 V, X7R, 0402 ceramic
47 nF, 10 V, X7R, 0402 ceramic
LM5165 Synchronous Buck Converter, VSON-10, 3 mm × 3 mm
Std
Std
CSS
Std
Std
U1
TI
LM5165DRCR
8.2.5.2 Detailed Design Procedure
8.2.5.2.1 COT Output Ripple Voltage Reduction
Depending on the required ripple resistance when operating in COT mode, the resultant output voltage ripple
may be deemed too high for a given application. One option is to place a feedforward capacitor CFF in parallel
with the upper feedback resistor RFB1. Capacitor CFF increases the high-frequency gain from VOUT to VFB close
to unity such that the output voltage ripple couples directly to the FB node.
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8.2.5.3 Application Curves
100
90
80
70
60
50
VIN 10 V/DIV
VOUT 5 V/DIV
IOUT 100 mA/DIV
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 65V
40
30
2 ms/DIV
0.1
1
10
100 150
D106
VIN stepped to 36 V
IOUT = 150 mA
Output Current (mA)
VOUT = 15 V
图8-31. Start-Up, Full Load
图8-30. Efficiency
VOUT 100 m/DIV
VOUT 100 mV/DIV
VSW 10 V/DIV
10 ms/DIV
VSW 10 V/DIV
1 ms/DIV
VIN = 36 V
IOUT = 0 mA
VIN = 36 V
IOUT = 150 mA
图8-33. SW Node and Output Ripple Voltage, No
图8-32. SW Node and Output Ripple Voltage, Full
Load
Load
VEN 1 V/DIV
VIN 10 V/DIV
VOUT 5 V/DIV
VOUT 1 V/DIV
IOUT 100 mA/DIV
IOUT 100 mA/DIV
400 ms/DIV
2 ms/DIV
VIN = 36 V
VIN = 36 V
图8-34. Enable ON and OFF
图8-35. Short Circuit Recovery
8.3 Power Supply Recommendations
The LM5165 is designed to operate from an input voltage supply range between 3 V and 65 V. This input supply
must be able to provide the maximum input current and maintain a voltage above 3 V. Ensure that the resistance
of the input supply rail is low enough that an input current transient does not cause a high enough drop at the
LM5165 supply rail to cause a false UVLO fault triggering and system reset. If the input supply is located more
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than a few inches from the LM5165 converter, additional bulk capacitance may be required in addition to the
ceramic input capacitance. A 4.7-μF electrolytic capacitor is a typical choice for this function, whereby the
capacitor ESR provides a level of damping against input filter resonances. A typical ESR of 0.5 Ω provides
enough damping for most input circuit configurations.
8.4 Layout
The performance of any switching converter depends as much upon PCB layout as it does the component
selection. The following guidelines are provided to assist with designing a PCB with the best power conversion
performance, thermal performance, and minimized generation of unwanted EMI.
8.4.1 Layout Guidelines
PCB layout is a critical for good power supply design. There are several paths that conduct high slew-rate
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or
degrade the power supply performance.
1. Bypass the VIN pin to GND with a low-ESR ceramic capacitor of X5R or X7R dielectric. Place CIN as close
as possible to the LM5165 VIN and GND pins. Ground return paths for both the input and output capacitors
must consist of localized top-side planes that connect to the GND pin and exposed PAD.
2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins.
3. Locate the power inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent
excessive capacitive coupling.
4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
5. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, soft-
start, and enable components to the ground plane. This prevents any switched or load currents from flowing
in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic
output voltage ripple behavior.
7. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
8. Minimize trace length to the FB pin. Locate both feedback resistors close to the FB pin. Place CFF (if used)
directly in parallel with RFB1. Route the VOUT sense path away from noisy nodes and preferably on a layer at
the other side of a shielding layer.
9. Locate the components at RT and SS as close as possible to the device. Route with minimal trace lengths.
10. Provide adequate heatsinking for the LM5165 to keep the junction temperature below 150°C. For operation
at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-
sinking vias to connect the exposed PAD to the PCB ground plane. If the PCB has multiple copper layers,
connect these thermal vias to inner-layer ground planes.
8.4.1.1 Compact PCB Layout for EMI Reduction
Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimize radiated EMI is to identify the pulsing current path and minimize the area of that path.
The critical switching loop of the power stage in terms of EMI is denoted in 图 8-36. The topological architecture
of a buck converter means that a particularly high di/dt current effective path exists in the loop comprising the
input capacitor and the LM5165 integrated MOSFETs, and it becomes mandatory to reduce the parasitic
inductance of this loop by minimizing the effective loop area.
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VIN
VIN
2
CIN
LM5165
High
di/dt
loop
High-side
PMOS
gate driver
Q1
LF
SW
VOUT
1
COUT
Q2
Low-side
NMOS
gate driver
GND
10
GND
图8-36. Synchronous Buck Converter With Power Stage Critical Switching Loop
The input capacitor provides the primary path for the high di/dt components of the high-side MOSFET current.
Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction. Keep the
trace connecting SW to the inductor as short as possible and just wide enough to carry the load current without
excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize
parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the capacitor
return terminal to the LM5165 GND pin and exposed PAD.
8.4.1.2 Feedback Resistor Layout
For the adjustable output voltage version of the LM5165, reduce noise sensitivity of the output voltage feedback
path by placing the resistor divider close to the FB pin, rather than close to the load. This reduces the trace
length of FB signal and noise coupling. The FB pin is the input to the feedback comparator and, as such, is a
high impedance node sensitive to noise. The output node is a low impedance node, so the trace from VOUT to
the resistor divider can be long if a short path is not available.
Route the voltage sense trace from the load to the feedback resistor divider away from the SW node path, the
inductor and VIN path to avoid contaminating the feedback signal with switch noise, while also minimizing the
trace length. This is most important when high feedback resistances, greater than 100 kΩ, are used to set the
output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node and VIN path,
such that there is a ground plane that separates the feedback trace from the inductor and SW node copper
polygon. This provides further shielding for the voltage feedback path from switching noise sources.
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8.4.2 Layout Example
图 8-37 shows an example layout for the PCB top layer of a single-sided design. The bottom layer is essentially
a full ground plane except for short connecting traces for SW, EN, and PGOOD.
GND
connection
Short SW node trace
routed underneath
RESR
LF
VIN
VOUT
connection
connection
COUT
CIN
Connect ceramic input
cap close to VIN and
GND
SW via
RFB2 RFB1 CFF RPG
RUV1
RILIM
RUV2
EN connection
PGOOD
connection
CSS
RRT
RHYS
Place FB resistors very
close to FB & GND pins
Thermal vias under
LM5165 PAD
Place SS cap close
to pin
图8-37. PCB Layout Example
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
9.1.2 Development Support
For development support, see the following:
• LM5165 Quick-start Design Tool
• LM5165 Simulation Models
• For TI's reference design library, visit TIDesigns
• For TI's WEBENCH Design Environment, visit the WEBENCH Design Center
• To view a related device of this product, see the LM5166
9.1.3 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5165 device with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, LM5165EVM-HD-P50A EVM User's Guide
• Texas Instruments, LM5165EVM-HD-C50X EVM User's Guide
• Texas Instruments, LM5166EVM-C50A EVM User’s Guide
• Texas Instruments, Low-IQ Synchronous Buck Converter Enables Intelligent Field-sensor Applications
• Texas Instruments, Low EMI Buck Converter Powers a Multivariable Sensor Transmitter with BLE
Connectivity
• TI Designs:
– Texas Instruments, Field Transmitter with Bluetooth® Low Energy Connectivity Powered from 4 to 20-mA
Current Loop
– Texas Instruments, 24-V AC Power Stage with Wide VIN Converter and Battery Backup for Smart
Thermostat
– Texas Instruments, 24-V AC Power Stage with Wide VIN Converter and Battery Gauge for Smart
Thermostat
• Industrial Strength Blogs:
– Texas Instruments, Powering Smart Sensor Transmitters in Industrial Applications
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– Texas Instruments, Trends in Building Automation: Predictive Maintenance
– Texas Instruments, Trends in Building Automation: Connected Sensors for User Comfort
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ZHCSEQ3D –FEBRUARY 2016 –REVISED DECEMBER 2022
• White Paper:
– Texas Instruments, Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding
Applications
• Texas Instruments, Selecting an Ideal Ripple Generation Network for Your COT Buck Converter
• Texas Instruments, AN-2162: Simple Success with Conducted EMI from DC-DC Converters
• Texas Instruments, Automotive Cranking Simulator User's Guide
• Texas Instruments, Using New Thermal Metrics
• Texas Instruments, Semiconductor and IC Package Thermal Metrics
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG Inc.
所有商标均为其各自所有者的财产。
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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22-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5165DRCR
LM5165DRCT
LM5165XDRCR
LM5165XDRCT
LM5165YDRCR
LM5165YDRCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
5165
5165
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
5165X
5165X
5165Y
5165Y
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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22-Nov-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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OTHER QUALIFIED VERSIONS OF LM5165 :
Automotive : LM5165-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5165DRCR
LM5165DRCR
LM5165DRCT
LM5165DRCT
LM5165XDRCR
LM5165XDRCR
LM5165XDRCT
LM5165XDRCT
LM5165YDRCR
LM5165YDRCR
LM5165YDRCT
LM5165YDRCT
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
10
3000
3000
250
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
250
3000
3000
250
250
3000
3000
250
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5165DRCR
LM5165DRCR
LM5165DRCT
LM5165DRCT
LM5165XDRCR
LM5165XDRCR
LM5165XDRCT
LM5165XDRCT
LM5165YDRCR
LM5165YDRCR
LM5165YDRCT
LM5165YDRCT
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
10
3000
3000
250
335.0
367.0
182.0
210.0
367.0
335.0
182.0
210.0
367.0
335.0
210.0
182.0
335.0
367.0
182.0
185.0
367.0
335.0
182.0
185.0
367.0
335.0
185.0
182.0
25.0
35.0
20.0
35.0
35.0
25.0
20.0
35.0
35.0
25.0
35.0
20.0
250
3000
3000
250
250
3000
3000
250
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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