LM5181 [TI]

具有 100V、0.75A 集成式 MOSFET 的 65V 输入电压非光电反激式转换器;


型号：	LM5181
厂家：	TEXAS INSTRUMENTS
描述：	具有 100V、0.75A 集成式 MOSFET 的 65V 输入电压非光电反激式转换器光电转换器
文件：	总34页 (文件大小：2712K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM5181

ZHCSL47A –APRIL 2020 –REVISED JANUARY 2021

具有100V、0.75A 集成MOSFET 的LM5181 65V_INPSR 反激式直流/直流转换器

1 特性

2 应用

• 提供功能安全

• 隔离式现场发送器和现场传动器

• 适用于模拟输入模块的多输出轨

• 电机驱动器：IGBT 和SiC 栅极驱动电源

• 楼宇自动化HVAC 系统

– 可帮助进行功能安全系统设计的文档

• 专为可靠耐用的应用而设计

– 4.5V 至65V 的宽输入电压范围，启动后的工作

电压低至3.5V

• 隔离式偏置电源

– 稳定可靠的解决方案，只有一个组件穿过隔离层

– ±1.5% 的总输出稳压精度

– 可选V_OUT温度补偿

– 6ms 内部或可编程软启动

– 输入UVLO 和热关断保护

– 断续模式过流故障保护

3 说明

LM5181 是一款初级侧稳压 (PSR) 反激式转换器，在

4.5V 至 65V 的宽输入范围内具有高效率。隔离输出电

压采样自初级侧反激式电压，因此，无需使用光耦合

器、电压基准或变压器的第三绕组进行输出电压稳压。

– 具有–40°C 至+150°C 的结温范围

• 通过集成技术减小解决方案尺寸，降低成本

凭借高度的集成性，可实现简单可靠的高密度设计，其

中只有一个组件穿过隔离层。通过采用边界导电模式

(BCM) 开关，可实现紧凑的磁解决方案以及优于

±1.5% 的负载和线路调节性能。集成的 100V 功率

MOSFET 能够提供高达 4W 的输出功率并提高应对线

路瞬变的余量。

– 集成100V、0.4Ω功率MOSFET

– 无需光耦合器或变压器辅助绕组即可进行V_OUT

稳压

– 内部环路补偿

• 高效率PSR 反激运行

LM5181 反激式转换器采用 8 引脚 4mm × 4mm 热增

强型WSON 封装，引脚间距为0.8mm。

– MOSFET 在BCM 模式下实现准谐振关断

– 低输入静态电流

器件信息

封装⁽¹⁾

– 具有用于提升效率的外部偏置选项

– 具有单输出和多输出实施手段

• 超低的EMI 传导和辐射信号

封装尺寸（标称值）

器件型号

LM5181

WSON (8)

4.00mm × 4.00mm

– 软开关可避免二极管反向恢复

– 针对CISPR 32 EMI 要求进行了优化

• 使用WEBENCH^®Power Designer 创建定制稳压器

设计

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

D_FLY

V_IN= 4.5 V...65 V

V_OUT= 5 V

T₁

D_Z

C_OUT

100 ꢀF

3 : 1

C_IN

D_F

VIN

EN/UVLO

2.2 ꢀF

R_FB

LM5181

158 kW

V_IN= 12V

V_IN= 24V

GND

RSET

V_IN= 36V

V_IN= 48V

V_IN= 65V

R_SET

SS/BIAS

12.1 kW

100

200

300 400

Output Current (mA)

500

600

700

D002

典型效率(V_OUT= 5V)

典型应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSBM6

LM5181

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ZHCSL47A –APRIL 2020 –REVISED JANUARY 2021

Table of Contents

9 Application and Implementation..................................17

9.1 Application Information............................................. 17

9.2 Typical Applications.................................................. 17

10 Power Supply Recommendations..............................24

11 Layout...........................................................................25

11.1 Layout Guidelines................................................... 25

11.2 Layout Examples.....................................................26

12 Device and Documentation Support..........................27

12.1 Device Support....................................................... 27

12.2 Documentation Support.......................................... 28

12.3 接收文档更新通知................................................... 28

12.4 支持资源..................................................................28

12.5 Trademarks.............................................................28

12.6 静电放电警告.......................................................... 28

12.7 术语表..................................................................... 29

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 2

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 Recommended Operating Conditions.........................4

7.4 Thermal Information....................................................4

7.5 Electrical Characteristics.............................................5

7.6 Typical Characteristics................................................6

8 Detailed Description........................................................9

8.1 Overview.....................................................................9

8.2 Functional Block Diagram...........................................9

8.3 Feature Description.....................................................9

8.4 Device Functional Modes..........................................16

Information.................................................................... 29

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (April 2020) to Revision A (January 2021)

Page

• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1

• 向特性添加了功能安全项目................................................................................................................................1

5 Description (continued)

The LM5181 flyback converter simplifies implementation of isolated DC/DC supplies with optional features to

optimize performance for the target end equipment. The output voltage is set by one resistor, while an optional

resistor improves output voltage accuracy by negating the thermal coefficient of the flyback diode voltage drop.

Additional features include an internally-fixed or externally-programmable soft start, optional bias supply

connection for higher efficiency, precision enable input with hysteresis for adjustable line UVLO, hiccup-mode

overload protection, and thermal shutdown protection with automatic recovery.

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6 Pin Configuration and Functions

GND

RSET

VIN

EN/UVLO

SS/BIAS

图6-1. NGU Package 8-Pin WSON With Wettable Flanks Top View

表6-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NO.

NAME

Switch node that is internally connected to the drain of the N-channel power MOSFET.

Connect to the primary-side switching terminal of the flyback transformer.

Primary-side feedback pin. Connect a resistor from FB to SW. The ratio of the FB resistor to

the resistor at the RSET pin sets the output voltage.

Input supply connection. Source for internal bias regulators and input voltage sensing pin.

Connect directly to the input supply of the converter with short, low impedance paths.

VIN

P/I

Enable input and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is

below 1.1 V, the converter is in shutdown mode with all functions disabled. If the EN/UVLO

voltage is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the

internal regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the

start-up sequence begins.

EN/UVLO

SS/BIAS

Soft start or bias input. Connect a capacitor from SS/BIAS to GND to adjust the output start-up

time and input inrush current. If SS/BIAS is left open, the internal 6-ms soft-start timer is

activated. Connect an external supply to SS/BIAS to supply bias to the internal voltage

regulator and enable internal soft start.

Temperature compensation pin. Tie a resistor from TC to RSET to compensate for the

temperature coefficient of the forward voltage drop of the secondary diode, thus improving

regulation at the secondary-side output.

Reference resistor tied to GND to set the reference current for FB. Connect a 12.1-kΩ resistor

from RSET to GND.

RSET

GND

DAP

Analog and power ground. Ground connection of internal control circuits and power MOSFET.

Die attach pad. Connect to PCB ground plane.

(1) P = Power, G = Ground, I = Input, O = Output.

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)⁽¹⁾

MIN

–0.3

–1.5

–3

MAX

UNIT

VIN to GND

EN/UVLO to GND

TC to GND

Input voltage

SS/BIAS to GND

FB to GND

70.3

0.3

FB to VIN

RSET to GND

SW to GND

100

Output voltage

SW to GND (20-ns transient)

Operating junction temperature, T_J

Storage temperature, T_stg

150

°C

–40

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001, all pins⁽¹⁾

±2000

HBM ESD Classification Level 2

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

±500

CDM ESD Classification Level C4B

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_IN

Input voltage

4.5

V_SW

SW voltage

V_EN/UVLO

V_SS/BIAS

T_J

EN/UVLO voltage

SS/BIAS voltage

Operating junction temperature

150

°C

–40

7.4 Thermal Information

LM5181

THERMAL METRIC⁽¹⁾

NGU (WSON)

8 PINS

41.3

UNIT

R_ΘJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

°C/W

R_ΘJC(top)

R_ΘJB

34.7

19.1

0.3

Ψ_JT

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LM5181

THERMAL METRIC⁽¹⁾

NGU (WSON)

8 PINS

19.2

UNIT

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

°C/W

Ψ_JB

R_ΘJC(bot)

3.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits aaply over the full –40°C to 150°C junction

temperature range unless otherwise indicated. V_IN= 24 V and V_EN/UVLO= 2 V unless otherwise stated.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

I_SHUTDOWN

I_ACTIVE

I_ACTIVE-BIAS

V_SD-FALLING

VIN shutdown current

VIN active current

V_EN/UVLO= 0 V

260

µA

V_EN/UVLO= 2.5 V, V_RSET= 1.8 V

V_SS/BIAS= 6 V

350

VIN current with BIAS connected

Shutdown threshold

V_EN/UVLOfalling

0.3

ENABLE AND INPUT UVLO

V_SD-RISING

V_UV-RISING

Standby threshold

Enable threshold

V_EN/UVLOrising

V_EN/UVLOfalling

0.8

1.5

1.45

0.04

4.2

1.53

V_UV-HYST

Enable voltage hysteresis

Enable current hysteresis

0.05

I_UV-HYST

FEEDBACK

I_RSET

V_EN/UVLO= 1.6 V

5.5

µA

RSET current

100

µA

R_RSET= 12.1 kΩ

I_FB= 80 µA

V_RSET

RSET regulation voltage

FB to VIN voltage

1.191

1.21

1.224

V_FB-VIN1

V_FB-VIN2

–40

I_FB= 120 µA

SWITCHING FREQUENCY

F_SW-MIN

F_SW-MAX

t_ON-MIN

Minimum switching frequency

350

140

kHz

Maximum switching frequency

Minimum switch on-time

DIODE THERMAL COMPENSATION

V_TCTC voltage

POWER SWITCHES

I_TC= ±10 µA, T_J= 25°C

I_SW= 100 mA

1.2

0.4

1.27

R_DS(on)

MOSFET on-state resistance

SOFT-START AND BIAS

I_SS

t_SS

SS ext capacitor charging current

µA

Internal SS time

V_BIAS-UVLO-

BIAS enable voltage

V_SS/BIASrising

V_SS/BIASfalling

5.5

5.75

0.88

RISE

V_BIAS-UVLO-

BIAS UVLO hysteresis

190

HYST

CURRENT LIMIT

I_SW-PEAK

Peak current limit threshold

0.62

0.75

THERMAL SHUTDOWN

T_SD

Thermal shutdown threshold

Thermal shutdown hysteresis

T_Jrising

175

°C

T_SD-HYS

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7.6 Typical Characteristics

V_IN= 24 V, V_EN/UVLO= 2 V (unless otherwise stated).

5.2

5.15

5.1

5.05

4.95

4.9

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 65V

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 65V

4.85

4.8

100

200

300 400

Output Current (mA)

500

600

700

100

200

300 400

Output Current (mA)

500

600

700

D003

D002

See 图9-1

图7-1. Efficiency versus Load

图7-2. Output Voltage versus Load

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

SW 20V/DIV

-50

-25

100

125

150

1 ms/DIV

Junction Temperature (èC)

D001

I_OUT= 0.5 A

See 图9-1

图7-4. Shutdown Quiescent Current versus

图7-3. Primary-side Switching Waveform in BCM

Temperature

290

280

270

260

250

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

V_IN= 12 V

V_IN= 24 V

V_IN= 48 V

240

-50

-25

100

125 150

-25

100 125 150

Junction Temperature (èC)

D002

D003

V_SS/BIAS= 6 V

图7-5. Active Quiescent Current versus

图7-6. Active Quiescent Current with BIAS versus

Temperature

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102

104

102

100

101

100

-50

30 40

Input Voltage (V)

-25

100

125

150

Junction Temperature (èC)

D004

D005

图7-7. RSET Current versus Input Voltage

图7-8. RSET Current versus Temperature

1.8

1.54

1.52

1.5

1.6

1.4

1.2

1.48

1.46

1.44

1.42

V_EN/UVLORising

V_EN/UVLOFalling

1.4

-50

0.8

-50

-25

100 125 150

-25

100

125

150

Junction Temperature (èC)

D007

D006

图7-10. EN/UVLO Threshold Voltages versus

图7-9. TC Voltage versus Temperature

Temperature

5.3

5.2

5.1

0.8

0.7

0.6

0.5

0.4

0.3

0.2

4.9

4.8

4.7

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D008

D009

图7-11. EN/UVLO Hysteresis Current versus

图7-12. MOSFET R_DS(on)versus Temperature

Temperature

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0.8

0.6

0.4

0.2

160

155

150

145

140

135

130

BCM / DCM

FFM

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D010

D011

图7-13. Switch Peak Current Limits versus

图7-14. Minimum Switch On-Time versus

Temperature

12.5

380

370

360

350

340

330

320

11.5

-50

-25

100

125

150

-50

-25

100

125

150

Junction Temperature (èC)

D012

D013

图7-15. Minimum Switching Frequency versus

图7-16. Maximum Switching Frequency versus

Temperature

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8 Detailed Description

8.1 Overview

The LM5181 primary-side regulated (PSR) flyback converter is a high-density, cost-effective solution for

industrial systems requiring less than 4 W of isolated DC/DC power. This compact, easy-to-use flyback converter

with low I_Qcan be applied over a wide input voltage range from 4.5 V to 65 V, with operation down to 3.5 V after

start-up. Innovative frequency and current amplitude modulation enables high conversion efficiency across the

entire load and line range. Primary-side regulation of the isolated output voltage using sampled values of the

primary winding voltage eliminates the need for an opto-coupler or an auxiliary transformer winding for feedback.

Regulation performance that rivals that of traditional opto-coupler solutions is achieved without the associated

cost, solution size, and reliability concerns. The LM5181 converter services a wide range of applications

including IGBT-based motor drives, factory automation, and medical equipment.

8.2 Functional Block Diagram

V_OUT

V_IN

D_FLY

N_P: N_S

D_Z

C_OUT

5 mA

LM5181

SS/BIAS

BIAS

REGULATOR

C_IN

EN/UVLO

Standby

1.5 V

1.45 V

VDD

VIN

D_F

VDD UVLO

Shutdown

VIN

SAMPLED

FEEDBACK

THERMAL

SHUTDOWN

1.1 V

100-V Power

MOSFET

RSET

COMP

VDD

g_m

VREF

TRIMMED

REFERENCE

CONTROL

LOGIC

R_TC

R_SET

ILIM

0.75 A

REGULATION

VDD

R_FB

SS/BIAS

GND

Internal SS

C_SS

8.3 Feature Description

8.3.1 Integrated Power MOSFET

The LM5181 is a flyback dc/dc converter with integrated 100-V, 0.75-A N-channel power MOSFET. During the

MOSFET on-time, the transformer primary current increases from zero with a slope of V_IN/ L_MAG(where L_MAGis

the transformer primary-referred magnetizing inductance) while the output capacitor supplies the load current.

When the MOSFET is turned off by the control logic, the SW voltage V_SWswings up to approximately V_IN+ (N_PS

× V_OUT), where N_PS= N_P/ N_Sis the primary-to-secondary turns ratio of the transformer. The magnetizing current

flows in the secondary side through the flyback diode, charging the output capacitor and supplying current to the

load. Duty cycle D is defined as t_ON/ t_SW, where t_ONis the MOSFET conduction time and t_SWis the switching

period.

图 8-1 shows a typical schematic of the LM5181 PSR flyback circuit. Components denoted in red are optional

depending on the application requirements.

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D_FLY

T₁

V_IN

V_OUT

D_CLAMP

C_OUT

D_OUT

R_UV1

N_P: N_S

D_F

C_IN

VIN

EN/UVLO

R_UV2

R_FB

LM5181

GND

RSET

SS/BIAS

R_TC

R_SET

C_SS

图8-1. LM5181 Flyback Converter Schematic (Optional Components in Red)

8.3.2 PSR Flyback Modes of Operation

The LM5181 uses a variable-frequency, peak current-mode (VFPCM) control architecture with three possible

modes of operation as illustrated in 图8-2.

Frequency

foldback mode

(FFM)

Discontinuous conduction mode (DCM)

Boundary conduction mode (BCM)

400

350

300

250

200

150

100

% Total Rated Output Power

图8-2. Three Modes of Operation Illustrated by Variation of Switching Frequency With Load

The LM5181 operates in boundary conduction mode (BCM) at heavy loads. The power MOSFET turns on when

the current in the secondary winding reaches zero, and the MOSFET turns off when the peak primary current

reaches the level dictated by the output of the internal error amplifier. As the load is decreased, the frequency

increases to maintain BCM operation. The duty cycle of the flyback converter is given 方程式1.

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+ V_D∂N

(

)

OUT

D =

+ V

+ V_D∂N

(

)

OUT

(1)

where

• V_Dis the forward voltage drop of the flyback diode as its current approaches zero

The output power in BCM is given by 方程式 2, where the applicable switching frequency and peak primary

current in BCM are specified by 方程式3 and 方程式4, respectively.

L_MAG∂I_PRI-PK(BCM)

P_OUT(BCM)

∂F_SW(BCM)

(2)

F_SW(BCM)

≈

’

L_MAG

N_PS∂ V

I_PRI-PK(BCM)

∂

∆

+ V_D

OUT

(

)

◊

(3)

(4)

2∂ V

(

+ V_D∂I

OUT

)

OUT

I_PRI-PK(BCM)

V ∂D

As the load decreases, the LM5181 clamps the maximum switching frequency to 350 kHz, and the converter

enters discontinuous conduction mode (DCM). The power delivered to the output in DCM is proportional to the

peak primary current squared as given by 方程式 5 and 方程式 6. Thus, as the load decreases, the peak current

reduces to maintain regulation at 350-kHz switching frequency.

L_MAG∂I_PRI-PK(DCM)

P_OUT(DCM)

∂F_SW(DCM)

(5)

2∂I_OUT∂ V

+ V_D

(

)

OUT

I_PRI-PK(DCM)

L_MAG∂F_SW(DCM)

(6)

(7)

L_MAG∂I_PRI-PK(DCM)∂F_SW(DCM)

D_DCM

At even lighter loads, the primary-side peak current set by the internal error amplifier decreases to a minimum

level of 0.15 A, or 20% of its 0.75-A peak value, and the MOSFET off-time extends to maintain the output load

requirement. The system operates in frequency foldback mode (FFM), and the switching frequency decreases

as the load current is reduced. Other than a fault condition, the lowest frequency of operation of the LM5181 is

12 kHz, which sets a minimum load requirement of approximately 0.5% full load.

8.3.3 Setting the Output Voltage

To minimize output voltage regulation error, the LM5181 senses the reflected secondary voltage when the

secondary current reaches zero. The feedback (FB) resistor, which is connected between SW and FB as shown

in 图8-1, is determined using 方程式8.

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R_SET

R_FB= V

+ V_D∂N

∂

(

)

OUT

V_REF

(8)

where

• R_SETis nominally 12.1 kΩ

8.3.3.1 Diode Thermal Compensation

The LM5181 employs a unique thermal compensation circuit that adjusts the feedback setpoint based on the

thermal coefficient of the forward voltage drop of the flyback diode. Even though the output voltage is measured

when the secondary current is effectively zero, there is still a non-zero forward voltage drop associated with the

flyback diode. Select the thermal compensation resistor using 方程式9.

R_FBkW

⁄

R_TCkW =

∂

⁄

N_PS

TC_DiodemV èC

» ÿ

⁄

(9)

The temperature coefficient of the diode voltage drop may not be explicitly provided in the diode data sheet, so

the effective value can be estimated based on the measured output voltage shift overtemperature when the TC

resistor is not installed.

8.3.4 Control Loop Error Amplifier

The inputs of the error amplifier include a level-shifted version of the FB voltage and an internal 1.21-V reference

set by the resistor at RSET. A type-2 internal compensation network stabilizes the converter. In BCM operation

when the output voltage is in regulation, an on-time interval is initiated when the secondary current reaches zero.

The power MOSFET is subsequently turned off when an amplified version of the peak primary current exceeds

the error amplifier output.

8.3.5 Precision Enable

The precision EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis for

application specific power-up and power-down requirements. EN/UVLO connects to a comparator with a 1.5-V

reference voltage and 50-mV hysteresis. An external logic signal can be used to drive the EN/UVLO input to

toggle the output on and off for system sequencing or protection. The simplest way to enable the LM5181 is to

connect EN/UVLO directly to V_IN. This allows the LM5181 to start up when V_INis within its valid operating range.

However, many applications benefit from using a resistor divider R_UV1and R_UV2as shown in 图 8-3 to establish

a precision UVLO level.

LM5181

VCC

V_IN

5 ꢀA

R_UV1

EN/UVLO

R_UV2

UVLO

Comparator

1.5 V

1.45 V

图8-3. Programmable Input Voltage UVLO With Hysteresis

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Use 方程式10 and 方程式11 to calculate the input UVLO voltages turnon and turnoff voltages, respectively.

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≈

’

◊

R_UV1

R_UV2

= V_UV-RISING1+

∆

IN(on)

(10)

where

• V_UV-RISINGand V_UV-FALLINGare the UVLO comparator thresholds

• I_UV-HYSTis the hysteresis current

≈

’

◊

R_UV1

R_UV2

= V_UV-FALLING1+

-I_UV-HYST∂R_UV1

∆

IN(off)

(11)

where

• V_UV-RISINGand V_UV-FALLINGare the UVLO comparator thresholds

• I_UV-HYSTis the hysteresis current

The LM5181 also provides a low-I_Qshutdown mode when the EN/UVLO voltage is pulled below a base-emitter

voltage drop (approximately 0.6 V at room temperature). If the EN/UVLO voltage is below this hard shutdown

threshold, the internal LDO regulator powers off, and the internal bias-supply rail collapses, shutting down the

bias currents of the LM5181. The LM5181 operates in standby mode when the EN/UVLO voltage is between the

hard shutdown and precision-enable thresholds.

8.3.6 Configurable Soft Start

The LM5181 has a flexible and easy-to-use soft-start control pin, SS/BIAS. The soft-start feature prevents inrush

current impacting the LM5181 and the input supply when power is first applied. This is achieved by controlling

the voltage at the output of the internal error amplifier. Soft start is achieved by slowly ramping up the target

regulation voltage when the device is first enabled or powered up. Selectable and adjustable start-up timing

options include a 6-ms internally-fixed soft start and an externally-programmable soft start.

The simplest way to use the LM5181 is to leave SS/BIAS open. The LM5181 employs an internal soft-start

control ramp and starts up to the regulated output voltage in 6 ms.

However, in applications with a large amount of output capacitance, higher V_OUTor other special requirements,

the soft-start time can be extended by connecting an external capacitor C_SSfrom SS/BIAS to GND. A longer

soft-start time further reduces the supply current needed to charge the output capacitors while sourcing the

required load current. When the EN/UVLO voltage exceeds the UVLO rising threshold and a delay of 20 µs

expires, an internal current source I_SSof 5 µA charges C_SSand generates a ramp to control the primary current

amplitude. Calculate the soft-start capacitance for a desired soft-start time, t_SS, using 方程式12.

C_SSnF = 5 ∂ t

⁄

(12)

C_SSis discharged by an internal FET when switching is disabled by EN/UVLO or thermal shutdown.

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8.3.7 External Bias Supply

D_FLY

T₁

V_IN

V_OUT

D_CLAMP

C_OUT

D_OUT

R_UV1

N_P: N_S

D_F

C_IN

VIN

EN/UVLO

R_UV2

R_FB

LM5181

GND

D_BIAS1

RSET

SS/BIAS

D_BIAS2

12 V

C_BIAS

22 nF

R_SET

N_P: N_AUX

图8-4. External Bias Supply Using Transformer Auxiliary Winding

The LM5181 has an external bias supply feature that reduces input quiescent current and increases efficiency.

When the voltage at SS/BIAS exceeds a rising threshold of 5.5 V, bias power for the internal LDO regulator can

be derived from an external voltage source or from a transformer auxiliary winding as shown in 图 8-4. With a

bias supply connected, the LM5181 then uses its internal soft-start ramp to control the primary current during

start-up.

When using a transformer auxiliary winding for bias power, the total leakage current related to diodes D_BIAS1and

_BIAS2in 图8-4 should be less than 1 µA across the full operating temperature range.

8.3.8 Minimum On-Time and Off-Time

When the internal power MOSFET is turned off, the leakage inductance of the transformer resonates with the

SW node parasitic capacitance. The resultant ringing behavior can be excessive with large transformer leakage

inductance and can corrupt the secondary zero-current detection. To prevent such a situation, a minimum switch

off-time, designated as t_OFF-MIN, of a maximum of 360 ns is set internally to ensure proper functionality. This sets

a lower limit for the transformer magnetizing inductance as discussed in 节9.2.1.2.

Furthermore, noise effects as a result of power MOSFET turnon can impact the internal current sense circuit

measurement. To mitigate this effect, the LM5181 provides a blanking time after the MOSFET turns on. This

blanking time forces a minimum on-time, t_ON-MIN, of 140 ns.

8.3.9 Overcurrent Protection

In case of an overcurrent condition on the isolated output or outputs, the output voltage drops lower than the

regulation level since the maximum power delivered is limited by the peak current capability on the primary side.

The peak primary current is maintained at 0.75 A (plus an amount related to the 100-ns propagation delay of the

current limit comparator) until the output decreases to the secondary diode voltage drop to impact the reflected

signal on the primary side. At this point, the LM5181 assumes the output cannot be recovered and re-calibrates

its switching frequency to 9 kHz until the overload condition is removed. The LM5181 responds with similar

behavior to an output short circuit condition.

For a given input voltage, 方程式 13 gives the maximum output current prior to the engagement of overcurrent

protection, where ηis the efficiency. The typical threshold value for I_SW-PEAKfrom 节7 is 0.75 A.

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I_SW-PEAK

I_OUT(max)

∂

≈

∆

’

◊

V_OUT

N_PS

(13)

A failsafe current limit set at 1.2 A, or 1.6 times the nominal peak current limit, provides redundant fault

protection in case of transformer short circuit or saturation effects. This initiates a 7.5-ms hiccup interval after

eight overcurrent events.

8.3.10 Thermal Shutdown

Thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related to

overheating. Thermal shutdown turns off the device when the junction temperature exceeds 175°C to prevent

further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the

LM5181 restarts when the junction temperature falls to 169°C.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

EN/UVLO facilitates ON and OFF control for the LM5181. When V_EN/UVLOis below approximately 0.6 V, the

device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in

shutdown mode drops to 3 μA at V_IN= 24 V. The LM5181 also employs internal bias rail undervoltage

protection. If the internal bias supply voltage is below its UV threshold, the converter remains off.

8.4.2 Standby Mode

The internal bias rail LDO regulator has a lower enable threshold than the converter itself. When V_EN/UVLOis

above 0.6 V and below the precision-enable threshold (1.5 V typically), the internal LDO is on and regulating.

The precision enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action

and voltage regulation are not enabled until V_EN/UVLOrises above the precision enable threshold.

8.4.3 Active Mode

The LM5181 is in active mode when V_EN/UVLOis above the precision-enable threshold and the internal bias rail is

above its UV threshold. The LM5181 operates in one of three modes depending on the load current requirement:

1. Boundary conduction mode (BCM) at heavy loads

2. Discontinuous conduction mode (DCM) at medium loads

3. Frequency foldback mode (FFM) at light loads

Refer to 节8.3.2 for more details.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The LM5181 requires only a few external components to convert from a wide range of supply voltages to one or

more isolated output rails. To expedite and streamline the process of designing of a LM5181-based converter, a

comprehensive LM5181 quick-start calculator is available for download to assist the designer with component

selection for a given application. WEBENCH^®online software is also available to generate complete designs,

leveraging iterative design procedures and access to comprehensive component databases. The following

sections discuss the design procedure for both single- and dual-output implementations using specific circuit

design examples.

As mentioned previously, the LM5181 also integrates several optional features to meet system design

requirements, including precision enable, input UVLO, programmable soft start, output voltage thermal

compensation, and external bias supply connection. Each application incorporates these features as needed for

a more comprehensive design.

The application circuits detailed in 节 9.2 show LM5181 configuration options suitable for several application use

cases.

9.2 Typical Applications

For step-by-step design procedures, circuit schematics, bill of materials, PCB files, simulation and test results of LM5181-powered

implementations, refer to the TI reference designs library.

9.2.1 Design 1: Wide V_IN, Low I_QPSR Flyback Converter Rated at 5 V, 0.5 A

The schematic diagram of a 5-V, 0.5-A PSR flyback converter is given in 图9-1.

D_FLY

V_IN= 10 V...65 V

T₁

V_OUT= 5 V

I_OUT= 0.5 A

D_CLAMP

24 V

C_OUT

D_OUT

R_UV1

5.6 V

47 ꢀF

536 kW

3 : 1

C_IN

D_F

VIN

EN/UVLO

44 mH

2.2 ꢀF

R_UV2

R_FB

LM5181

100 kW

158 kW

GND

RSET

SS/BIAS

R_TC

R_SET

C_SS

130 kW

12.1 kW

47 nF

图9-1. Schematic for Design 1 With V_IN(nom)= 24 V, V_OUT= 5 V, I_OUT= 0.5 A

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9.2.1.1 Design Requirements

The required input, output, and performance parameters for this application example are shown in 表9-1.

表9-1. Design Parameters

DESIGN PARAMETER

VALUE

10 V to 65 V

9.5 V on, 6.5 V off

5 V

Input voltage range

Input UVLO thresholds

Output voltage

Rated load current, V_IN= 24 V

Output voltage regulation

Output voltage ripple

0.5 A

±1.5%

< 100 mV

The target full-load efficiency is 87.5% based on a nominal input voltage of 24 V and an isolated output voltage

of 5 V. The LM5181 is chosen to deliver a fixed 5-V output voltage set by resistor R_FBconnected between the

SW and FB pins. The input voltage turnon and turnoff thresholds are established by R_UV1and R_UV2. The

required components are listed in 表9-2. Transformers for other designs are listed in 表9-3.

表9-2. List of Components for Design 1

REF DES QTY SPECIFICATION

VENDOR

PART NUMBER

12061C225KAT4A

C3225X7R2A225K230AB

GCJ32DR72A225KA01L

HMK325B7225KN-T

C3225X7S1A476M250AC

GRM32ER71A476KE15L

LMK325B7476MM-TR

Std

2.2 µF, 100 V, X7R, 1206, ceramic

AVX

TDK

C_IN

2.2 µF, 100 V, X7R, 1210, ceramic

Murata

Taiyo Yuden

TDK

47 µF, 10 V, X7S, 1210, ceramic

47 µF, 10 V, X7R, 1210, ceramic

C_OUT

Murata

Taiyo Yuden

Std

C_SS

47 nF, 16 V, X7R, 0402

D_CLAMP

D_F

Zener, 24 V, 1 W, PowerDI-123

Switching diode, 75 V, 0.25 A, SOD-323

Schottky diode, 40 V, 2 A, SOD-123

Zener, 5.6 V, 5%, SOD-523

158 kΩ, 1%, 0402

DFLZ24-7

CMDD4448

FSV340FP

BZX585-C5V6

Std

Diodes Inc.

Central Semi

Onsemi

D_FLY

D_OUT

R _FB

R_SET

R _TC

R _UV1

R _UV2

T₁

Nexperia

Std

12.1 kΩ, 1%, 0402

Std

130 kΩ, 1%, 0402

Std

536 kΩ, 1%, 0603

Std

100 kΩ, 1%, 0402

44 µH, 1.4 A, 3 : 1, 8.2 × 8.6 × 9.6 mm

LM5181 PSR flyback converter, VSON-8

Würth Electronik

Texas Instruments

750318633

U₁

LM5181NGUR

表9-3. Magnetic Components for Various Output Voltages

OUTPUT VOLTAGE (RANGE)

3.3 V (up to 4 V)

TURNS RATIO

L_MAG, I_SAT

DIMENSIONS

VENDOR

PART NUMBER

750319117

750318633

750318737

750318738

750319118

750319119

4 : 1

40 µH, 1 A

5 V (4 V to 5.5 V)

3 : 1

12 V (5.5 V to 16 V)

24 V (16 V to 32 V)

48 V (32 V to 50 V)

15 V and –7.5 V dual

1 : 1

44 µH, 1 A

30 µH, 1 A

8.6 × 8.26 × 9.65 mm Würth Electronik

1 : 2

1 : 3

1 : 1.5 : 0.8

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9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5181 device with WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.1.2.2 Custom Design With Excel Quickstart Tool

Select components based on the converter specifications using the LM5181 quick-start calculator.

9.2.1.2.3 Flyback Transformer –T₁

Choose a turns ratio based on an approximate 60% max duty cycle at minimum input voltage using 方程式 14,

rounding up or down as needed.

D_MAX

0.6

10V

IN(min)

N_PS

∂

= 3

1-D_MAXV_OUT+ V_D1- 0.6 5V + 0.3V

(14)

Select a magnetizing inductance based on the minimum off-time constraint using 方程式 15. Choose a value of

44 µH and a saturation current of minimum 1 A for this application.

+ V_D∂N_PS∂ t_OFF-MIN

)

I_SW-PEAK(FFM)

5V + 0.3V ∂3∂360ns

(

)

0.15A

OUT

L_MAG

= 38ꢀH

(15)

Note that a higher magnetizing inductance provides a larger operating range for BCM and FFM, but the leakage

inductance can increase based on a higher number of primary turns, N_P. The primary and secondary winding

RMS currents are given by 方程式16 and 方程式17, respectively.

I_PRI-RMS

∂I_PRI-PK

(16)

2∂I_OUT∂I_PRI-PK∂N_PS

I_SEC-RMS

(17)

Find the maximum output current for a given turns ratio using 方程式 18, where the typical value for I_SW-PEAKis

the 0.75-A switch current peak threshold. Iterate by increasing the turns ratio if the output current capability is too

low at minimum input voltage.

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0.42A at V = 12V

I_SW-PEAK

0.85 0.75A

I_OUT(max)

∂

≈

∆

’

◊

≈

∆

’

◊

V_OUT

0.6A at V = 24V

N_PS

(18)

9.2.1.2.4 Flyback Diode –D_FLY

The flyback diode reverse voltage is given by 方程式19.

65V

IN(max)

V_D-REV

+ V_OUT

+ 5V ö 27V

N_PS

(19)

Select a 40-V, 3-A Schottky diode for this application to account for inevitable diode voltage overshoot and

ringing related to the resonance of transformer leakage inductance and diode parasitic capacitance. Connect an

appropriate RC snubber circuit (for example, 100 Ωand 22 pF) across the flyback diode if needed.

In general, choose a flyback diode with current rating greater than the maximum peak secondary winding current

of N_PS× I_SW-PEAK. As mentioned in 节 11, place adequate copper at the cathode of the diode to improve its

thermal performance and prevent overheating during high ambient temperature or overload conditions. Beware

of the high leakage current typical of a Schottky diode at elevated operating temperatures.

9.2.1.2.5 Zener Clamp Circuit –D_F, D_CLAMP

Connect a diode-Zener clamping circuit across the primary winding to limit the peak switch-node voltage after

MOSFET turnoff below the maximum level of 95 V, as given by 方程式20.

V_DZ(clamp)< V_SW(max)- V

IN(max)

(20)

Choosing the zener, D_CLAMP, with clamp voltage of approximately 1.5 times the reflected output voltage, as

specified by 方程式 21, provides a balance between the maximum SW voltage excursion and the leakage

inductance demagnetization time.

V_DZ(clamp)= 1.5∂N_PS∂ V

+ V_D= 1.5∂3∂ 5V + 0.3V ö 24V

(

)

(

)

OUT

(21)

Select an ultra-fast switching diode or Schottky diode for D_Fwith rated voltage greater than the maximum input

voltage and with low forward recovery voltage drop.

9.2.1.2.6 Output Capacitor –C_OUT

The output capacitor determines the voltage ripple at the converter output, limits the voltage excursion during a

load transient, and sets the dominant pole of the converter's small-signal response. For a flyback converter

specifically, the output capacitor supplies the load current when the main switch is on, therefore, the output

voltage ripple is a function of load current and duty cycle.

Select an output capacitance using 方程式 22 to limit the ripple voltage amplitude to less than 1% of the output

voltage at minimum input voltage.

44ꢀH∂ 0.75A

L_MAG∂I_SW-PEAK

(

)

1+ D

1+ 0.6

≈

’

≈

’

C_OUT

∂

= 32ꢀF

∆

◊

∆

◊

2∂ DV_OUT∂ V_OUT

2∂50mV ∂5V

(22)

Mindful of the voltage coefficient of ceramic capacitors, select a 47-µF, 10-V capacitor in 1210 case size with

X7S or better dielectric. 方程式23 gives the output capacitor RMS ripple current.

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2∂N_PS∂I_PRI-PK

I_COUT-RMS= I_OUT

∂

-1

3 ∂I_OUT

(23)

9.2.1.2.7 Input Capacitor –C_IN

Select an input capacitance using 方程式 24 to limit the ripple voltage amplitude to less than 5% of the input

voltage when operating at nominal input voltage.

≈

’

I_PRI-PK∂D∂ 1-

∆

◊

C_IN

2∂F_SW∂ DV

(24)

Substituting the input current at full load, switching frequency, peak primary current, and peak-to-peak ripple

specification gives C_INgreater than 1 μF. Mindful of the voltage coefficient of ceramic capacitors, select a 2.2-

µF, 100-V ceramic input capacitor with X7R dielectric in 1210 case size. 方程式 25 gives the input capacitor

RMS ripple current.

D ∂I_PRI-PK

I_CIN-RMS

∂

-1

3 ∂D

(25)

9.2.1.2.8 Feedback Resistor –R_FB

Select a feedback resistor, designated R_FB, of 158 kΩbased on the secondary winding voltage at the end of the

flyback conduction interval (the sum of the 5-V output voltage and the Schottky diode forward voltage drop)

reflected by the transformer turns ratio of 3 : 1. The forward voltage drop of the flyback diode is 0.3 V as its

current approaches zero.

+ V_D∂N

5V + 0.3V ∂3

(

)

0.1mA

(

)

OUT

R_FB

= 158 kW

0.1mA

(26)

9.2.1.2.9 Thermal Compensation Resistor –R_TC

Select a resistor for output voltage thermal compensation, designated R_TC, based on 方程式27.

R_FBkW

⁄

158

R_TCkW =

∂

= 130 kW

⁄

N_PS

TC_DiodemV èC

1.2

⁄

(27)

9.2.1.2.10 UVLO Resistors –R_UV1, R_UV2

Given V_IN(on)and V_IN(off)as the input voltage turn-on and turn-off thresholds of 9.5 V and 6.5 V, respectively,

select the upper and lower UVLO resistors using the following expressions:

V_UV-FALLING

V_UV-RISING

I_UV-HYST

1.45 V

1.5 V

5 ꢀA

∂

- V

IN(off)

9.5 V ∂

- 6.5 V

IN(on)

R_UV1

= 536kW

(28)

(29)

V_UV-RISING

1.5 V

9.5 V -1.5 V

R_UV2= R_UV1

∂

= 536 kW ∂

= 100 kW

- V_UV-RISING

IN(on)

Calculate the actual input turn-on and turn-off voltage thresholds as follows:

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≈

’

◊

R_UV1

R_UV2

≈

’

◊

536 kW

100kW

= V_UV-RISING1+

= 1.5V 1+

= 9.54V

∆

IN(on)

(30)

(31)

≈

’

R_UV1

R_UV2

≈

’

◊

536kW

100kW

= V_UV-FALLING1+

-I_UV-HYST∂R_UV1= 1.45V 1+

- 5ꢀA ∂536kW = 6.54V

∆

◊

∆

IN(off)

9.2.1.2.11 Soft-Start Capacitor –C_SS

Connect an external soft-start capacitor for a specific soft-start time. In this example, select a soft-start

capacitance of 47 nF based on 方程式12 to achieve a soft-start time of 8 ms.

For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's Power Management

technical articles.

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9.2.2 Application Curves

Unless otherwise stated, application performance curves were taken at T_A= 25°C.

5.2

5.15

5.1

5.05

4.95

4.9

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 65V

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 65V

4.85

4.8

100

200

300 400

Output Current (mA)

500

600

700

100

200

300 400

Output Current (mA)

500

600

700

D002

D003

图9-2. Efficiency (Linear Scale)

图9-3. Load Regulation (Linear Scale)

SW 20V/DIV

V_DFLY5V/DIV

1 ms/DIV

V_IN= 24 V

I_OUT= 0.5 A

V_IN= 24 V

I_OUT= 0.5 A

图9-5. Flyback Diode Voltage

图9-4. Switch Node Voltage

Average detector

Peak detector

Average detector

Start 150 kHz

Stop 30 MHz

Start 30 MHz

Stop 108 MHz

V_IN= 24 V

150 kHz to 30 MHz

L_IN= 4.7 µH

C_IN= 10 µF

V_IN= 24 V

I_OUT= 0.5 A

30 MHz to 108 MHz

L_IN= 4.7 µH

C_IN= 10 µF

I_OUT= 0.5 A

图9-6. CISPR 25 Class 5 Conducted EMI Plot

图9-7. CISPR 25 Class 5 Conducted EMI Plot

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10 Power Supply Recommendations

The LM5181 PSR flyback DC/DC converter operates over a wide input voltage range from 4.5 V to 65 V. The

characteristics of the input supply must be compatible with the 节 7. In addition, the input supply must be

capable of delivering the required input current to the fully-loaded regulator. Estimate the average input current

with 方程式32.

V_OUT∂I_OUT

I_IN

V ∂ h

(32)

where

• ηis the efficiency

If the converter is connected to an input supply through long wires or PCB traces with a large impedance, special

care is required to achieve stable performance. The parasitic inductance and resistance of the input cables can

have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR

ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at

VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip

during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false

UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the

input supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics. The

moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage

overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps

to hold the input voltage steady during large load transients. A typical ESR of 0.25 Ω provides enough damping

for most input circuit configurations.

An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as

well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for

DC-DC Converters provides helpful suggestions when designing an input filter for any switching regulator.

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11 Layout

The performance of any switching converter depends as much upon PCB layout as it does the component

selection. The following guidelines are provided to assist with designing a PCB with the best power conversion

performance, thermal performance, and minimized generation of unwanted EMI. 图 11-1 and 图 11-2 provide

layout examples for single-output and dual-output designs, respectively.

11.1 Layout Guidelines

PCB layout is a critical for good power supply design. There are several paths that conduct high slew-rate

currents or voltages that can interact with transformer leakage inductance or parasitic capacitance to generate

noise and EMI or degrade the performance of the power supply.

1. Bypass the VIN pin to GND with a low-ESR ceramic capacitor, preferably of X7R or X7S dielectric. Place C_IN

as close as possible to the LM5181 VIN and GND pins. Ground return paths for the input capacitor or

capacitors must consist of localized top-side planes that connect to the GND pin and exposed PAD.

2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins.

3. Locate the transformer close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive

e-field or capacitive coupling.

4. Minimize the loop area formed by the diode-Zener clamp circuit connections and the primary winding

terminals of the transformer.

5. Minimize the loop area formed by the flyback rectifying diode, output capacitor, and the secondary winding

terminals of the transformer.

6. Connect adequate copper at the cathode of the flyback diode to prevent overheating during overload or high

ambient temperature conditions.

7. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.

8. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.

9. Have a single-point ground connection to the plane. Route the return connections for the reference resistor,

soft-start, and enable components directly to the GND pin. This prevents any switched or load currents from

flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation

or erratic output voltage ripple behavior.

10. Make V_IN+, V_OUT+, and ground bus connections short and wide. This reduces any voltage drops on the input

or output paths of the converter and maximizes efficiency.

11. Minimize trace length to the FB pin. Locate the feedback resistor close to the FB pin.

12. Locate components R_SET, R_TC, and C_SSas close as possible to their respective pins. Route with minimal

trace lengths.

13. Place a capacitor between input and output return connections to route common-mode noise currents

directly back to their source.

14. Provide adequate heatsinking for the LM5181 to keep the junction temperature below 150°C. For operation

at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-

sinking vias to connect the exposed PAD to the PCB ground plane. If the PCB has multiple copper layers,

connect these thermal vias to inner-layer ground planes. The connection to V_OUT+provides heatsinking for

the flyback diode.

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11.2 Layout Examples

Place the input capacitor close

to the VIN pin and connect to

the GND plane under the IC

Keep the DZ clamp and RC snubber

components close to the primary winding pins

Use adequate heatsinking

copper connected to the

cathode of the flyback

diode (VOUT)

Locate the converter IC close

to the transformer and connect

to the GND plane as shown

Keep the secondary

winding, flyback diode

and output capacitor

loop as tight as possible

Locate the RSET, TC and FB resistors and

the SS capacitor close to their respective pins

Place the Y-cap close to the transformer so that common-mode

currents from the secondary to the primary side return in a tight loop

图11-1. Single-Output PCB Layout

Place the ceramic input

capacitor close to the IC to

minimize the switching loop area

Locate the converter IC close

to the transformer and connect

to the GND plane as shown

Minimize the area of the

secondary winding,

flyback diode and output

capacitor switching loops

Maintain the appropriate primary-

to-secondary clearance distance

Place the RSET, TC, FB and SS small-signal

components near their respective pins

图11-2. Dual-Output PCB Layout

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12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.1.2 Development Support

With input voltage range and current capability as specified in 表 12-1, the PSR flyback DC/DC converter family

of parts from TI provides flexibility, scalability and optimized solution size for a range of applications. Using an 8-

pin WSON package with 4-mm × 4-mm footprint and 0.8-mm pin pitch, these converters enable isolated DC/DC

solutions with high density and low component count.

表12-1. PSR Flyback DC/DC Converter Family

PSR FLYBACK

DC/DC

CONVERTER

MAXIMUM LOAD CURRENT, V_OUT= 12 V, N_PS= 1

INPUT VOLTAGE

RANGE

PEAK SWITCH

CURRENT

V_IN= 4.5 V

V_IN= 13.5 V

V_IN= 24 V

LM5181

LM5180

LM25180

LM25183

LM25184

4.5 V to 65 V

4.5 V to 42 V

0.75 A

1.5 A

2.5 A

4.1 A

90 mA

180 mA

360 mA

600 mA

1 A

225 mA

450 mA

750 mA

1.25 A

180 mA

300 mA

500 mA

For development support, see the following:

• LM5181 Quick-start Calculator

• LM5181 Simulation Models

• For TI's reference design library, visit TIDesigns

• For TI's WEBENCH Design Environment, visit the WEBENCH^®Design Center.

• To view a related device of this product, see the LM5180 product page.

• TI Designs:

– Isolated IGBT Gate-Drive Power Supply Reference Design With Integrated Switch PSR Flyback Controller

– Compact, Efficient, 24-V Input Auxiliary Power Supply Reference Design for Servo Drives

– Reference Design for Power-Isolated Ultra-Compact Analog Output Module

– HEV/EV Traction Inverter Power Stage with 3 Types of IGBT/SiC Bias-Supply Solutions Reference Design

– 4.5-V to 65-V Input, Compact Bias Supply With Power Stage Reference Design for IGBT/SiC Gate Drivers

– Channel-to-Channel Isolated Analog Input Module Reference Design

– SiC/IGBT Isolated Gate Driver Reference Design With Thermal Diode and Sensing FET

– >95% Efficiency, 1-kW Analog Control AC/DC Reference Design for 5G Telecom Rectifier

– 3.5-W Automotive Dual-output PSR Flyback Regulator Reference Design

• TI Technical Articles:

– Flyback Converters: Two Outputs are Better Than One

– Common Challenges When Choosing the Auxiliary Power Supply for Your Server PSU

– Maximizing PoE PD Efficiency on a Budget

12.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5181 device with WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• LM5180EVM-S05 EVM User's Guide (SNVU592)

• LM5180EVM-DUAL EVM User's Guide (SNVU609)

• LM25184EVM-S12 EVM User's Guide (SNVU680)

• Selecting Output Capacitor to Optimize Output Ripple and Stability in PSR Flyback Converters (SLYT800)

• How an Auxless PSR-Flyback Converter can Increase PLC Reliability and Density (SLYT779)

• Why Use PSR-Flyback Isolated Converters in Dual-Battery mHEV Systems (SLYT791)

• IC Package Features Lead to Higher Reliability in Demanding Automotive and Communications Equipment

Systems (SNVA804)

• PSR Flyback DC/DC Converter Transformer Design for mHEV Applications (SNVA805)

• Flyback Transformer Design Considerations for Efficiency and EMI (SLUP338)

• Under the Hood of Flyback SMPS Designs (SLUP261)

• White Papers:

– Valuing Wide V_IN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding Applications

(SLYY104)

– An Overview of Conducted EMI Specifications for Power Supplies (SLYY136)

– An Overview of Radiated EMI Specifications for Power Supplies (SLYY142)

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®are registered trademarks of Texas Instruments.

is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

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12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages have mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM5181NGUR

ACTIVE

WSON

NGU

4500 RoHS & Green

Level-2-260C-1 YEAR

-40 to 150

LM5181

NGU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM5181NGUR

WSON

NGU

4500

330.0

12.4

4.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

WSON NGU

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

LM5181NGUR

4500

Pack Materials-Page 2

MECHANICAL DATA

NGU0008B

SDC08B (Rev A)

www.ti.com

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LM5181 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E