LM53635NQRNLRQ1_技术文档

LM53625-Q1, LM53635-Q1

SNVSAA7B – DECEMBER 2015 – REVISED JULY 2021

LM53625/35-Q1, 2.5-A or 3.5-A, 36-V Synchronous, 2.1-MHz, Step-Down DC-DC

Converter

1 Features

3 Description

•

AEC-Q100 automotive qualified:

The LM53625-Q1/LM53635-Q1 synchronous buck

regulator is optimized for automotive applications,

providing an output voltage of 5 V, 3.3 V, or

an adjustable output. Advanced high-speed circuitry

allows the LM53625-Q1/LM53635-Q1 to regulate from

an input of 18 V to an output of 3.3 V at a fixed

frequency of 2.1 MHz. Innovative architecture allows

this device to regulate a 3.3-V output from an input

voltage of only 3.55 V. All aspects of the LM53625-

Q1/LM53635-Q1 are optimized for automotive and

performance-driven industrial customers. An input

voltage range up to 36 V, with transient tolerance

up to 42 V, eases input surge protection design.

The automotive-qualified Hotrod QFN package with

wettable flanks reduces parasitic inductance and

resistance while increasing efficiency, minimizing

switch node ringing, and dramatically lowering

electromagnetic interference (EMI). An open-drain

reset output, with built-in filtering and delay, provides

a true indication of system status. This feature

negates the requirement for an additional supervisory

component, saving cost and board space. Seamless

transition between PWM and PFM modes and

low quiescent current (only 15 µA for the 3.3 V

option) ensure high efficiency and superior transient

responses at all loads.

– Device temperature grade 1: –40°C to +125°C

ambient operating temperature range

– Device HBM classification level 2

– Device CDM classification level C6

–40°C to +150°C junction temperature range

15-µA quiescent urrent at no load (typical) with

3.3-V output

5.0-mm × 4.0-mm VQFN package with or without

wettable flanks and 0.6-mm V_INspacing

Low EMI and switch noise

•

Spread spectrum option

External frequency synchronization

RESET output with internal filter and 3-ms release

timer

Pin-selectable forced PWM mode

Built-in compensation, soft start, current limit,

thermal shutdown, and UVLO

0.6-V dropout at 3.5 A at 105°C T_A

±1% output voltage tolerance (–40°C to 125°C T_J)

Available with fixed 5-V, 3.3-V or adjustable output

•

2 Applications

•

Telematics

Head unit

Instrumentation cluster

Battery-powered applications

Device Information

DEVICE NAME

LM53625-Q1

PACKAGE⁽¹⁾

BODY SIZE

VQFN-HR (22)

5.00 mm × 4.00 mm

LM53635-Q1

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Automotive Layout (22 mm x 12.5 mm)

Typical Application Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM53625-Q1, LM53635-Q1

SNVSAA7B – DECEMBER 2015 – REVISED JULY 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison.........................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................7

7.6 System Characteristics............................................... 9

7.7 Timing Characteristics.................................................9

7.8 Typical Characteristics.............................................. 11

8 Detailed Description......................................................13

8.1 Overview...................................................................13

8.2 Functional Block Diagram.........................................14

8.3 Feature Description...................................................15

8.4 Device Functional Modes..........................................20

8.5 Spread-Spectrum Operation.....................................23

9 Application and Implementation..................................24

9.1 Application Information............................................. 24

9.2 Typical Applications.................................................. 24

9.3 What to Do and What Not to Do............................... 41

10 Power Supply Recommendations..............................41

11 Layout...........................................................................42

11.1 Layout Guidelines................................................... 42

11.2 Layout Example...................................................... 43

12 Device and Documentation Support..........................44

12.1 Device Support....................................................... 44

12.2 Documentation Support.......................................... 44

12.3 Receiving Notification of Documentation Updates..44

12.4 Support Resources................................................. 44

12.5 Trademarks.............................................................44

12.6 Electrostatic Discharge Caution..............................44

12.7 Glossary..................................................................44

13 Mechanical, Packaging, and Orderable

Information.................................................................... 44

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May 2016) to Revision B (July 2021)

Page

•

Updated the numbering format for tables, figures, and cross-references throughout the document. ................1

Updated applications.......................................................................................................................................... 1

Added the non-wettable flank options.................................................................................................................3

Changes from Revision * (December 2015) to Revision A (May 2016)

Page

•

Product Preview to Production Data ..................................................................................................................1

2

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5 Device Comparison

Table 5-1. LM53625-Q1 Devices (2.5-A Output)

SPREAD

SPECTRUM

WETTABLE

FLANKS

PART NUMBER

OUTPUT VOLTAGE

PACKAGE QTY

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Adjustable

3.3 V

No

3000

250

Y

N

No

3000

250

3.3 V

No

5 V

No

3000

250

5 V

No

Adjustable

3.3 V

Yes

3000

250

3000

250

3.3 V

5 V

3000

250

5 V

3.3 V

3000

Adjustable

5 V

Table 5-2. LM53635-Q1 Devices (3.5-A Output)

SPREAD

SPECTRUM

PART NUMBER

OUTPUT VOLTAGE

PACKAGE QTY

Wettable Flanks

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Adjustable

3.3 V

No

3000

250

Y

N

No

3000

250

3.3 V

No

5 V

No

3000

250

5 V

No

Adjustable

3.3 V

Yes

3000

250

3000

250

3.3 V

5 V

3000

250

5 V

Adjustable

3.3 V

3000

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6 Pin Configuration and Functions

PGND1

PGND2

PGND1

PGND2

PGND1

SW

PVIN 2

AVIN

PVIN 1

SYNC

CBOOT

VCC

FPWM

NC

EN

RESET AGND

FB

BIAS

Figure 6-1. RNL Package 22-Pin VQFN Top View

Table 6-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NO.

NAME

Internal 3.1-V LDO output. Used as supply to internal control circuits. Connect a high-quality

4.7-µF capacitor from this pin to AGND.

1

VCC

A

P

Bootstrap capacitor connection for gate drivers. Connect a high quality 470-nF capacitor

from this pin to the SW pin.

2

CBOOT

SYNC

Synchronization input to regulator. Used to synchronize the device switching frequency to a

system clock. Triggers on rising edge of external clock; frequency must be in the range of 1.9

MHz and 2.3 MHz.

3

I

Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND

pins. Connect PVIN1 and PVIN2 pins directly together at PCB.

4

PVIN1

PGND1

P

G

Power ground to internal low side MOSFET. These pins must be tied together on the PCB.

Connect PGND1 and PGND2 directly together at PCB. Connect to AGND and system

ground.

5, 6, 7, 8

9

SW

P

Regulator switch node. Connect to power inductor.

Power ground to internal low side MOSFET. These pins must be tied together. Connect

PGND1 and PGND2 directly together at PCB. Connect to AGND and system ground.

10, 11, 12, 13

PGND2

G

Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND

pins. Connect PVIN1 and PVIN2 pins directly together at PCB.

14

PVIN2

P

15

16

17

18

AVIN

FPWM

NC

A

I

Analog VIN, Connect to PVIN1 and PVIN2 on PCB.

Do not float. Mode control input of regulator. High = FPWM, low = Automatic light load mode.

No internal connection

—

I

EN

Enable input to regulator. High = on, Low = off. Can be connected to VIN. Do not float.

Open drain reset output flag. Connect to suitable voltage supply through a current limiting

resistor. High = regulator OK, Low = regulator fault. Goes low when EN = low.

19

20

RESET

AGND

O

G

Analog ground for regulator and system. All electrical parameters are measured with respect

to this pin. Connect to PGND on PCB

Feedback input to regulator. Connect to output voltage node for fixed VOUT options.

Connect to feedback voltage divider for adjustable option.

21

22

FB

A

P

BIAS

Input to auxiliary bias regulator. Connect to output voltage node.

(1) A = Analog, O = Output, I = Input, G = Ground, P = Power

4

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7 Specifications

7.1 Absolute Maximum Ratings

over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted)⁽¹⁾

PARAMETER

VIN (AVIN,PVIN1 and PVIN2) to AGND, PGND1 and PGND2⁽²⁾

SW to AGND, PGND⁽³⁾

MIN

–0.3

MAX

UNIT

V

40

V_IN+ 0.3

3.6

V

CBOOT to SW

V

EN to AGND, PGND^{(2) (4)}

40

V

BIAS to AGND, PGND

16

V

FB to AGND, PGND

16

V

RESET to AGND, PGND

8

V

RESET sink current⁽⁵⁾

10

mA

V

SYNC to AGND,PGND^{(2) (4)}

FPWM to AGND,PGND⁽⁴⁾

VCC to AGND,PGND

–0.3

–40

40

V

3.6

V

Junction temperature

150

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Section 7.1 may cause permanent damage to the device. These are stress ratings only, functional

operation of the device at these or any other conditions beyond those indicated under Section 7.3 are not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) A maximum of 42 V can be sustained at this pin for a duration of ≤ 500 ms at a duty cycle of ≤ 0.01%.

(3) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.

(4) Under no conditions should the voltage on this pin be allowed to exceed the voltage on the PVIN1,PVIN2 or AVIN pins by more than

0.3 V.

(5) Do not exceed the voltage rating on this pin.

7.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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7.3 Recommended Operating Conditions

over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted)

MIN

NOM

MAX

36

UNIT

V

Input voltage after start-up⁽¹⁾

3.9

Output voltage for 3.3-V LM53625/35-Q1⁽²⁾

3.4

5.2

10

V

Output voltage for 5-V LM53625/35-Q1⁽²⁾

V

Output adjustment for adjustable version of LM53625/35-Q1⁽²⁾

Load current for LM53625-Q1, fixed output option and adjustable

Load current for LM53635-Q1, fixed output option and adjustable

Junction temperature for 1000-hour lifetime

3.3

V

2.5

3.5

125

150

A

–40

°C

Junction temperature for 408-hour lifetime

(1) An extended input voltage range to 3.5 V is possible; see Section 7.6 table. See Input UVLO for start-up conditions.

(2) The output voltage must not be allowed to fall below zero volts during normal operation.

7.4 Thermal Information

LM53625/35-Q1

THERMAL METRIC⁽¹⁾

RNL (VQFN)

22 PINS

29.4

UNIT

R_θJA

R_θJC

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

14.2

5.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.2

ψ_JB

5.4

R_θJC(bot)

2.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

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7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_j= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

V_IN= 3.8 V to 36 V, T_J= 25°C

V_IN= 3.8 V to 36 V

MIN

TYP

MAX

UNIT

–1%

1%

V_FB

Initial output voltage accuracy

–1.5%

1.5%

Operating quiescent current;

measured at VIN pin when

enabled and not switching⁽¹⁾

V_IN= 13.5 V, V_BIAS= 5 V

6

I_Q

µA

V_IN= 13.5 V, V_BIAS= 5 V, T_J= 85°C

16

V_IN= 13.5 V, V_BIAS= 5 V, FPWM = 0

V

35

Bias current into BIAS pin,

enabled, not switching

I_B

V_IN= 13.5 V, V_BIAS= 3.3 V, FPWM =

0 V

35

2

EN ≤ 0.4 V, T_J= 25°C

EN ≤ 0.4 V, T_J= 85°C

EN ≤ 0.4V, T_J= 150°C

Rising

Shutdown quiescent current;

measured at VIN pin

I_SD

3

5

µA

V

3.2

2.95

3.55

3.25

0.3

3.95

3.55

0.4

V_IN-OPERATE

Minimum input voltage to operate Falling

Hysteresis

0.28

RESET upper threshold voltage

RESET lower threshold voltage

Magnitude of RESET lower

Rising, % of V_OUT

105%

92%

107%

94%

110%

96.5%

Falling, % V_OUT

V_RESET

Steady-state output voltage and

threshold from steady state output RESET threshold read at the same

96%

voltage

T_Jand V_IN

RESET hysteresis as a percent of

output voltage setpoint

V_{RESET_HYST}

V_{RESET_VALID}

±1

Minimum input voltage for proper 50-µA pullup to RESET pin, EN = 0

RESET function

1.5

0.4

V

V, T_J= 25°C

50-µA pullup to RESET pin, V_IN=1.5

V, EN = 0 V

Low level RESET function output 0.5-mA pullup to RESET pin, V_IN

V_OL

0.4

voltage

=13.5 V, EN=0 V

1-mA pullup to RESET pin, V_IN

=13.5 V, EN=3.3 V

0.4

V_IN= 13.5 V, center frequency with

spread spectrum, PWM operation

1.85

2.1

2.35

F_SW

Switching frequency

MHz

V_IN= 13.5 V, without spread

spectrum, PWM operation

2.1

F_SYNC

D_SYNC

Sync frequency range

1.9

25%

1.5

2.3

Sync input duty cycle range

High state input < 5.5 V and > 2.3 V

FPWM input high (MODE = FPWM)

75%

FPWM input low (MODE = AUTO

with diode emulation)

V_FPWM

FPWM input threshold voltage

0.4

1

V

FPWM input hysteresis

0.15

1.81

Frequency span of spread

spectrum operation

FS_SS

F_PSS

±3%

Spread-spectrum pattern

frequency⁽²⁾

9

Hz

Switching Frequency while in

spread spectrum

F_SW-SS

V_IN= 13.5 V, PWM operation

MHz

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Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_j= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

V_IN= 13.5 V, V_FPWM= 3.3 V

V_IN= V_FPWM= 13.5 V

V_IN= 13.5 V, V_SYNC= 3.3 V

V_IN= V_SYNC= 13.5 V

LM53625

MIN

TYP

MAX

UNIT

1

I_FPWM

I_SYNC

I_L-HS

FPWM leakage current

µA

5

1

SYNC leakage current

µA

A

5

3.5

4.5

2.5

3.5

5

6.5

7.5

4.1

5.1

High-side switch current limit

Low-side switch current limit

LM53635

6

LM53625

3.5

4.5

I_L-LS

A

LM53635

Zero-cross current limit FPWM =

low

I_L-ZC

–0.02

–1.5

60

A

Negative current limit FPWM =

high

I_L-NEG

High-side MOSFET R_DSON, V_IN= 13

V, IL=1A

130

80

R_DSON

Power switch on-resistance

mΩ

V

Low-side MOSFET R_DSON, V_IN= 13

V, IL=1A

40

Enable input threshold voltage -

rising

V_EN

Enable rising

1.7

2

V_{EN_HYST}

V_{EN_WAKE}

I_EN

Enable threshold hysteresis

Enable wake-up threshold

EN pin input current

0.45

0.4

0.55

V

V_IN= V_EN= 13.5 V

2

3.05

3.15

2.7

185

20

5

µA

V_IN13.5 V, V_BIAS= 0 V

V_IN= 13.5 V, V_BIAS= 3.3 V

V_INrising

V_CC

Internal V_CCvoltage

V

Internal V_CCinput undervoltage

lockout

V_{CC_UVLO}

I_FB

Hysteresis below V_CC-UVLO

Adjustable LM53625/35-Q1, FB=1 V

T_J= 25°C

mV

nA

Input current from FB to AGND

0.993

0.99

1

1.007

1.01

Reference voltage for adjustable

option only

V_REF

T_J= –40°C to 125°C

T_J= –40°C to 150°C

1

V

Ω

V

0.985

1

1.015

Pull FB pin low. Sink 1-mA at

RESET pin

R_RESET

R_DSONof RESEToutput

50

85

V_IH

1.5

V_SYNC

V_IL

0.4

1

V_HYST

0.15

155

Rising

175

T_SD

Thermal shutdown thresholds⁽²⁾

°C

Hysteresis

15

F_sw= 2.1 MHz

While in dropout⁽²⁾

80%

D_MAX

Maximum switch duty cycle

98%

(1) This is the current used by the device while not switching, open loop on the ATE. It does not represent the total input current from the

regulator system.

(2) Ensured by Design, Not tested at production.

8

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7.6 System Characteristics

The following specifications are ensured by design provided that the component values in the typical application circuit

are used. These parameters are not ensured by production testing. Limits apply over the recommended operating junction

temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are specified through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for

reference purposes only. Unless otherwise stated the following conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Minimum input voltage for full

functionality at 1.5 A load, after start- V_OUT= 3.3 V +2/–3% regulation

up.

3.5

V_IN-MIN

V

Minimum input voltage for full

functionality at maximum rated load

3.5 A after start-up.

V_OUT= 3.3 V +2/–3% regulation

3.9

Output voltage for 5-V option

Output voltage for 3.3-V option

V_IN= 5.6 V to 36 V, I_OUT= 3.5 A

V_IN3.9 V to 36 V, I_OUT= 3.5 A

4.925

3.24

5

5.08

3.35

3.3

V_IN= 5.5 V to 36 V, I_OUT= 100 µA to 100

mA

V

Output voltage for 5-V option

4.92

5.05

3.33

5.125

V_OUT

V_IN= 3.8 V to 36 V, I_OUT= 100 µA to 100

mA

Output voltage for 3.3-V option

3.24

3.38

2.25%

40

Output voltage for adjustable option

V_IN= V_OUT+ 1 V to 36 V, I_OUT= 3.5 A

–2.25%

V_IN= 13.5 V, V_OUT= 3.3 V, I_OUT= 0 A

FPWM = 0

15

20

I_Q-VIN

Input current to VIN pin

µA

V_IN= 13.5 V, V_OUT= 5.0 V and I_OUT= 0 A

FPWM = 0

Minimum input to output voltage

differential to maintain regulation

accuracy without inductor DCR drop

V_OUT= 3.3 V/5 V, I_OUT= 3.5 A, +2/–3%

output accuracy

V_DROP1

0.35

1.1

0.6

1.4

V

Minimum input to output voltage

differential to maintain F_SW≥ 1.85

MHz without inductor DCR drop

V_OUT= 3.3 V/5 V, I_OUT=3.5 A, F_SW= 1.85

MHz, 2% regulation accuracy

V_DROP2

V_IN= 13.5 V, V_OUT= 5.0 V, I_OUT= 3.5 A

V_IN= 13.5 V, V_OUT= 3.3 V, I_OUT= 3.5 A

V_IN= 13.5 V, V_OUT= 5 V, I_OUT= 100 mA

90%

84%

88%

Typical Efficiency without inductor

loss

Efficiency

7.7 Timing Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

MIN

NOM

65

60

3

MAX

84

80

4

UNIT

t_ON

Minimum switch on time, V_IN= 18 V, I_L=1 A

Minimum switch off time, V_IN= 3.8 V, I_L=1 A

Delay time to RESET high signal

ns

t_OFF

ns

t_RESET-act

t_RESET-filter

t_SS

2

12

2

ms

µs

Glitch filter time for RESET function⁽¹⁾

Soft-Start Time from first switching pulse to V_REFat 90%

Turn-on delay, C_VCC= 2.2 µF⁽²⁾

25

3.2

1

45

5

ms

t_EN

t_W

Short circuit wait time (hiccup time)⁽³⁾

6

Change transition time from AUTO to FPWM MODE, 20-mA load,

V_IN= 13.5 V

100

80

µs

t_FPWM

Change transition time from FPWM to AUTO MODE, 20-mA load,

V_IN= 13.5 V

(1) See Section 8.

(2) This is the time from the rising edge of EN to the time that the soft-start ramp begins.

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(3) T_wis the wait time between current limit trip and re-start. T_wis nominally 4× the soft-start time. However, provision must be made to

make T_wlonger to ensure survivability during an output short circuit.

10

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7.8 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 12 V, T_A= 25°C. Specified temperatures are

ambient.

100.2%

100.1%

100%

2.2

2.175

2.15

2.125

2.1

99.9%

99.8%

99.7%

99.6%

99.5%

99.4%

99.3%

99.2%

2.075

2.05

2.025

2

-40 -20

0

20

40

60

80 100 120 140 160

-50

-25

0

25

50

75

100

125

150

Temperature (èC)

D024

Temperature (èC)

D023

V_IN= 12 V

Figure 7-1. Reference Voltage Drift

Figure 7-2. Switching Frequency vs Temperature

6.4

6.2

6

4.8

LM53635

LM53625

4.6

4.4

4.2

4

5.8

5.6

5.4

5.2

5

3.8

3.6

3.4

3.2

4.8

4.6

4.4

4.2

4

LM53635

LM53625

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (èC)

D034

D035

V_IN= 12 V

V_IN= 12V

Figure 7-3. High Side/Peak Current Limit for

LM53625/35-Q1

Figure 7-4. Low Side/Valley Current Limit for

LM53625/35-Q1

0.065

0.06

0.055

0.05

0.045

0.04

0.035

0.03

0.025

0.02

0.015

0.01

0.005

0

14

5 Vin

8 Vin

12 Vin

13.5 Vin

18 Vin

36 Vin

12

10

8

6

4

2

0

5

10

15

20

25

Input Voltage (V)

30

35

40

-40 -20

0

20

40

60

80 100 120 140 160

D004

Temperature (èC)

D028

V_IN= 12 V

Figure 7-5. Short Circuit Average Input Current for

LM53635-Q1

Figure 7-6. Shutdown Current

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108%

106%

104%

102%

100%

98%

5.4

V_{RESET_UPPER}

5.3

V_{RESET_UPPER_FALLING}

5.2

5.1

V_OUT

5

4.9

V_{RESET_LOWER_RISING}

4.8

4.7

4.6

4.5

V_{RESET_LOWER}

96%

V_{RESET_LOWER}

94%

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (èC)

D027

Termperature (èC)

D026

Figure 7-8. RESET Threshold as Percentage of

Output Voltage

Figure 7-7. RESET Threshold Fixed 5-V output

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8 Detailed Description

8.1 Overview

The LM53625/35-Q1 is a wide input voltage range, low quiescent current, high performance regulator with

internal compensation designed specifically for the automotive market. This device is designed to minimize

end-product cost and size while operating in demanding automotive environments. Normal operating frequency

is 2.1 MHz allowing the use of small passive components. Because the operating frequency is above the AM

band, significant saving in input filtering is also achieved. This device has a low unloaded current consumption

eliminating the need for an external back-up LDO. The LM53625/35-Q1 low shutdown current and high

maximum operating voltage also allows the elimination of an external load switch. To further reduce system

cost, an advanced reset output is provided, which can often eliminate the use of an external reset device.

The LM53625/35-Q1 is designed with a flip-chip or HotRod technology, greatly reducing the parasitic inductance

of pins. In addition, the layout of the device allows for reduction in the radiated noise generated by the switching

action through partial cancellation of the current generated magnetic field.

As a result the switch-node waveform exhibits less overshoot and ringing.

Figure 8-1. Switch Node Waveform (V_IN=13.5V, I_OUT=3.5A)

The LM53625/35-Q1 is AEC-Q1 qualified as well as having electrical characteristics ensured up to a maximum

junction temperature of 150°C.

The LM53625/35-Q1 is available in VQFN package with wettable-flanks which allows easy inspection of the

soldering job without the requirement of X-ray checks.

Please note that, throughout this data sheet, references to the LM53625 apply equally to the LM53635. The

difference between the two devices is the maximum output current and specified MOSFET current limits.

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8.2 Functional Block Diagram

SYNC

VCC BIAS

VIN

* = Not used in -ADJ

INT. REG.

BIAS

OSCILLATOR

CBOOT

ENABLE

LOGIC

HS CURRENT

SENSE

EN

FB

ꢀ

1.0 V

Reference

PWM

COMP.

ERROR

AMPLIFIER

+

-

CONTROL

LOGIC

DRIVER

SW

*

+

-

LS CURRENT

SENSE

RESET

MODE

RESET

LOGIC

CONTROL

FPWM

AGND PGND

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8.2.1 Control Scheme

The LM53625/35-Q1 control scheme allows this device to operate under a wide range of conditions with a

low number of external components. Peak current mode control allows a wide range of input voltages and

output capacitance values, while maintaining a constant switching frequency. Stable operation is maintained

while output capacitance is changed during operation as well. This allows use in systems that require high

performance during load transients and which have load switches that remove loads as system operating state

changes. Short minimum on and off times ensure constant frequency regulation over a wide range of conversion

ratios. These on and off times allow for a duty factor window of 13% to 87% at 2.1-MHz switching frequency.

This architecture uses frequency spreading in order to achieve low dropout voltage maintaining output regulation

as the input voltage falls close to output voltage. The frequency spreading is smooth and continuous, and

activated as off time approaches its minimum. Under these conditions, the LM53625/35-Q1 operates much like

a constant off-time converter allowing the maximum duty cycle to reach 98% and output voltage regulation with

300-mV dropout at 3.5 A.

While input voltage is high enough to require duty factor below 13%, frequency is reduced smoothly to allow

lower duty factors. In this mode many of the beneficial properties of current-mode control such as insensitivity to

output capacitance is maintained. The LM53625/35-Q1 has short enough minimum on time to maintain 2.1-MHz

operation while converting a 18 V input to a 3.3-V output.

As load current is reduced, the LM53625/35-Q1 transitions to light load mode. In this mode, diode emulation is

used to reduce RMS inductor current and switching frequency is reduced. Also, fixed voltage versions do not

need a voltage divider connected to FB saving additional power. As a result, only 15 µA (typical, while converting

13.5 V to 3.3 V) is consumed to regulate output voltage if output is unloaded. Average output voltage increases

slightly while lightly loaded as well.

For applications that require constant operating frequency regardless of the load condition, the FPWM pin allows

the user to disable the light load operating mode. The device then switches at 2.1 MHz regardless of the output

current. Diode emulation is also turned off when the FPWM pin is set high.

8.3 Feature Description

8.3.1 RESET Flag Output

The RESET function, built into the LM53625/35-Q1, has special features not found in the ordinary Power-Good

function. A glitch filter prevents false flag operation for short excursions in the output voltage, such as during

line and load transients. Furthermore, there is a delay between the point at which the output voltage is within

specified limits and the flag asserts Power Good. Because the RESET comparator and the regulation loop

share the same reference, the thresholds track with the output voltage. This allows the LM53625/35-Q1 to be

specified with a 96.5% maximum threshold, while at the same time specifying a 94 % worst case threshold

with respect to the actual output voltage for that device. This allows tighter tolerance than is possible with an

external supervisor device. The net result is a more accurate Power-Good function while expanding the system

allowance for transients, and so forth. RESET operation can best be understood by reference to Figure 8-2

and Figure 8-3. The values for the various filter and delay times can be found in Section 7.7. Output voltage

excursions lasting less than T_RESET-filterdo not trip RESET. Once the output voltage is within the prescribed

limits, a delay of T_RESET-actis imposed before RESET goes high.

This output consists of an open-drain NMOS; requiring an external pullup resistor to a suitable logic supply. It

can also be pulled up to either V_CCor V_OUT, through an appropriate resistor, as desired. The pin can be left

floating or grounded if the RESET function is not used in the application. When EN is pulled low, the flag output

isl also be forced low. With EN low, RESET remains valid as long as the input voltage is ≥ 1.5 V. The maximum

current into this pin should be limited to 10 mA, while the maximum voltage must be less than 8 V.

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Figure 8-2. Static RESET Operation

Figure 8-3. RESET Timing Behavior

While the LM53625/35-Q1 reset function resembles a standard Power-Good function, its functionality is

designed to replace a discrete reset device, reducing additional component cost. There are three major

differences between the reset function and the normal power good function seen in most regulators.

•

A delay has been added for release of reset. See Figure 8-2 and Figure 8-3 for more detail.

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•

RESET Output signals a fault (pulls its output to ground) while the part is disabled.

RESET Continues to operate with input voltage as low as 1.5 V. Below this input voltage, RESET Output may

be high impedance.

The threshold voltage for the RESET function is specified taking advantage of the availability of the LM53625/35-

Q1 internal feedback threshold to the RESET circuit. This allows a maximum threshold of 96.5% of selected

output voltage to be specified at the same time as 96 % of actual set point. The net result is a more accurate

reset function while expanding the system allowance for transient response without the need for extremely

accurate internal circuitry.

8.3.2 Enable and Start-Up

Start-up and shutdown of the LM53625/35-Q1 are controlled by the EN input. Applying a voltage of ≥ 2 V

activates the device, while a voltage of ≤ 0.8 V is required to shut it down. The EN input may also be connected

directly to the input voltage supply. This input must not be left floating. The LM53625/35-Q1 utilizes a reference-

based soft start that prevents output voltage overshoots and large inrush currents as the regulator is starting up.

A typical start-up waveform is shown in Figure 8-4 along with timing definitions.

The waveforms shown in Figure 8-4 indicate the sequence and timing between the enable input and the output

voltage and RESET. From the figure we can define several different start-up times depending on what is relevant

to the application. Table 8-1 lists some definitions and typical values for the timings.

Figure 8-4. Typical Start-up Waveform

Table 8-1. Typical Start-up Times

PARAMETER

Total start-up sequence

DEFINITION

VALUE

UNIT

t_RESET-READY

Time from EN to RESET released

7.5

ms

time

t_POWER-UP

t_SS

Start-up time

Soft-start time

Delay time

Time from EN to 90% of V_OUT

Rise time of V_OUTfrom 10% to 90%

Time from EN to start of V_OUTrising

4

3.2

1

ms

t_EN

Time from output voltage within 94% and RESET

released

t_RESET-ACT

RESET time

3

ms

8.3.3 Soft-Start Function

Soft-start time is fixed internally at about 3 ms. Soft start is achieved by ramping the internal reference. The

LM53625/35-Q1 operates correctly even if there is a voltage present on the output before activation of the

LM53625/35-Q1 (pre-biased start-up). The device operates in AUTO mode during soft start, and the state of the

FPWM pin is ignored during that period.

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8.3.4 Current Limit

The LM53625/35-Q1 incorporates valley current limit for normal overloads and for short-circuit protection. In

addition, the low-side switch is also protected from excessive negative current when the device is in FPWM

mode. Finally, a high-side peak-current limit is employed for protection of the top NMOS FET.

During overloads the low-side current limit, I_L-LS(see Section 7.5), determines the maximum load current that the

LM53625/35-Q1 can supply. When the low-side switch turns on, the inductor current begins to ramp down. If the

current does not fall below I_L-LSbefore the next turnon cycle, then that cycle is skipped, and the low-side FET is

left on until the current falls below I_L-LS. This is somewhat different than the more typical peak current limit, and

results in Equation 1 for the maximum load current.

(

V

_IN- V_OUT

2∂F_S∂L

)

∂

V_OUT

I_OUT

= I_LS

+

max

V

IN

(1)

The LM53625/35-Q1 uses two current limits, which allow use of smaller inductors than systems utilizing a

single current limit. A coarse high side or peak current limit is provided to protect against faults and saturated

inductors. A precision valley current limit prevents excessive average output current from the buck converter of

the LM53625/35-Q1. A new switching cycle is not initiated until inductor current drops below the valley current

limit. This scheme allows use of inductors with saturation current rated less than twice the rated operating

current of the LM53625/35-Q1.

If the converter keeps triggering valley current limit for more than about 64 clock cycles, the device turns off both

high and low side switches for approximately 5.5 ms (see T_Win Section 7.7. If the overload is still present after

the hiccup time, another 64 cycles is counted, and the process is repeated. If the current limit is not tripped for

two consecutive clock cycles, the counter is reset. Figure 8-5 shows the inductor current with a hard short on the

output. The hiccup time allows the inductor current to fall to zero, resetting the inductor volt-second balance. This

is the method used for short-circuit protection and keeps the power dissipation low during a fault. Of course the

output current is greatly reduced in this condition (see Section 7.8. A typical short-circuit transient and recovery

is shown in Figure 8-6.

Short Removed

Short Applied

VOUT, 2V/div

Iinductor, 2A/div

5ms/div

21mmss//ddiivv

Figure 8-5. Inductor Current Bursts in Short Circuit

Figure 8-6. Short-Circuit Transient and Recovery

The high-side current limit trips when the peak inductor current reaches I_L-HS(see Section 7.5). This is a

cycle-by-cycle current limit and does not produce any frequency or current foldback. It is meant to protect the

high-side MOSFET from excessive current. Under some conditions, such as high input voltage, this current limit

may trip before the low-side protection. The peak value of this current limit varies with duty cycle.

In FPWM mode, the inductor current is allowed to go negative. Should this current exceed I_NEG, the low side

switch is turned off until the next clock cycle. This is used to protect the low-side switch from excessive negative

current. When the device is in AUTO mode, the negative current limit is increased to about I_ZC(about 0 A). This

allows the device to operate in DCM.

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The LM53625/35-Q1 response to a short circuit is: Peak current limit prevents excessive peak current while

valley current limit prevents excessive average inductor current. After a small number of cycles of valley current

limit triggers, hiccup mode is activated.

8.3.5 Hiccup Mode

In order to prevent excessive heating and power consumption under sustained short circuit conditions, a hiccup

mode is included. If an overcurrent condition is maintained, the LM53625/35-Q1 shuts off its output and waits for

T_W(approximately 6 ms), after which the LM53625/35-Q1 restarts operation beginning by activating soft start.

Vout

Figure 8-7. Hiccup Operation

During hiccup mode operation the switch node of the LM53625/35-Q1 is high impedance after a short circuit or

overcurrent persists for a short duration. Periodically, the LM53625/35-Q1 attempts to restart. If the short has

been removed before one of these restart attempts, the LM53625/35-Q1 operates normally.

8.3.6 Synchronizing Input

It is often desirable to synchronize the operation of multiple regulators in a single system. This technique results

in better-defined EMI and can reduce the need for capacitance on some power rails. The LM53625/35-Q1

provides a SYNC input which allows synchronization with an external clock. The LM53625/35-Q1 implements an

in-phase locking scheme – the rising edge of the clock signal provided to the LM53625/35-Q1 input corresponds

to turning on the high-side device within the LM53625/35-Q1. This function is implemented using phase locking

over a limited frequency range eliminating large glitches upon initial application of an external clock. The clock

fed into the LM53625/35-Q1 replaces the internal free running clock but does not affect frequency foldback

operation. Output voltage continues to be well regulated with duty factors outside of the normal 15% through

87% range though at reduced frequency.

The internal clock of the LM53625/35-Q1 can be synchronized to a system clock through the SYNC input. This

input recognizes a valid high level as that ≥ 1.5 V, and a valid low as that ≤ 0.4 V. The frequency synchronization

signal must be in the range of 1.9 MHz to 2.3 MHz with a duty cycle of from 10% to 90%. The internal clock

is synced to the rising edge of the external clock. Ground this input if not used. The maximum voltage on this

input is 5.5 V and should not be allowed to float. See Section 8.4 to determine which modes are valid for

synchronizing the clock.

The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided.

8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)

The LM53625/35-Q1 incorporates an input UVLO function. The device accepts an EN command when the input

voltage rises above about 3.64 V and shuts down when the input falls below about 3.3 V. See Section 7.5 under

V_IN-OPERATEfor detailed specifications.

TSD is provided to protect the device from excessive temperature. When the junction temperature reaches about

165°C, the device shuts down; re-start occurs at a temperature of about 150°C.

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8.3.8 Input Supply Current

The LM53625/35-Q1 is designed to have very low input supply current when regulating light loads. One way

this is achieved is by powering much of the internal circuitry from the output. The BIAS pin is the input to the

LDO that powers the majority of the control circuits. By connecting the BIAS input to the output of the regulator,

this current acts as a small load on the output. This current is reduced by the ratio of V_OUT/V_IN, just like any

other load. Another advantage of the LM53625/35-Q1 is that the feedback divider is integrated into the device.

This allows the use of much larger resistors than can be used externally; >> 100 kΩ. This results in much lower

divider current than is possible with external resistors.

Equation 2 can be used as a guide to indicate how the various terms affect the input supply current in AUTO

mode in unloaded conditions. The Section 9.2.2.3 show measured values for the input supply current for both

the 3.3-V and the 5-V output voltage versions.

8.4 Device Functional Modes

Please refer to Table 8-2 and the following paragraphs for a detailed description of the functional modes for

the LM53625/35-Q1. These modes are controlled by the FPWM input as shown in Table 8-2. This input can be

controlled by any compatible logic, and the mode changed, while the regulator is operating. If it is desired to fix

the mode for a given application, the input can be either connected to ground, a logic supply, or the VCC pin, as

desired. The maximum input voltage on this pin is 5.5 V; the FPWM pin should not be allowed to float.

Table 8-2. Mode Selection

FPWM INPUT VOLTAGE

OPERATING MODE

Forced PWM: The regulator operates as a constant frequency, current mode, full-

synchronous converter for all loads; without diode emulation.

> 1.5 V

AUTO: The regulator moves between PFM and PWM as the load current changes, utilizing

diode-emulation mode to allow DCM (see the Glossary ).

< 0.4 V

8.4.1 AUTO Mode

In AUTO mode the device moves between PWM and PFM as the load changes. At light loads the regulator

operates in PFM . At higher loads the mode changes to PWM. The load currents at which the mode changes can

be found in the Section 9.2.2.3.

In PWM, the converter operates as a constant frequency, current mode, full synchronous converter using PWM

to regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a

constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line

and load regulation and low output voltage ripple. When in PWM the converter synchronizes to any valid clock

signal on the SYNC input (see Section 8.4.3 and Section 8.4.4 ).

In PFM the high side FET is turned on in a burst of one or more cycles to provide energy to the load. The

frequency of these bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency

(see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current

required to regulate the output voltage at small loads. This trades off very good light load efficiency for larger

output voltage ripple and variable switching frequency. Also, a small increase in the output voltage occurs in

PFM. The actual switching frequency and output voltage ripple will depend on the input voltage, output voltage,

and load. Typical switching waveforms for PFM are shown in Figure 8-8. See the Section 9.2.2.3 for output

voltage variation in AUTO mode. The SYNC input is ignored during PFM operation.

A unique feature of this device is that a minimum input voltage is required for the regulator to switch from PWM

to PFM at light load. This feature is a consequence of the advanced architecture employed to provide high

efficiency at light loads. Figure 8-9 and Figure 8-10 indicates typical values of input voltage required to switch

modes at no load. Also, once the regulator switches to PFM, at light load, it remains in that mode if the input

voltage is reduced.

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6.2

6

Light Load Activation Thsld (rising)

Light Load Deactivation Thsld (falling)

SW, 5V/div

5.8

5.6

5.4

5.2

5

VOUT, 50mV/div

Iinductor, 500mA/div

10µs/div

2 ms/div

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

Figure 8-8. Typical PFM Switching Waveforms

D033

Figure 8-9. Input Voltage for Mode Change — Fixed

5-V Output, 2.2-µH Inductor

4.2

4

Light Load Activation Thsld (rising)

Light Load Deactivation Thsld (falling)

3.8

3.6

3.4

3.2

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D038

Figure 8-10. Input Voltage for Mode Change — Fixed 3.3-V Output, 2.2-µH Inductor

I_{Q_VIN}is the current consumed by a converter utilizing a LM53635-Q1 or LM53625-Q1 device while regulating

without a load. While operating without a load, the LM53635-Q1 or LM53625-Q1 is only powering itself. The

device draws power from two sources, its V_INpin, I_Q, and either its FB pin for fixed versions or BIAS pin for

adjustable versions, I_B. Since BIAS or FB is connected to the output of the circuit, the power consumed is

converted from input power with an effective efficiency, ηeff, of approximately 80 %. Here, effective efficiency is

the added input power needed when lightly loading the converter of the LM53625-Q1 and LM53635- Q1 devices

and is divided by the corresponding additional load. This allows unloaded current to be calculated as follows:

Output Voltage

I_{Q_ VIN}= I_Q+I_EN+ I +I

(

)

B

div

h_effìInput Voltage

(2)

where

•

I_{Q_VIN}is the current consumed by the operating (switching) buck converter utilizing the LM53625-Q1 or

LM53635-Q1 while unloaded.

•

I_Qis the current drawn by the LM53625-Q1 or LM53635-Q1 from its V_INterminal. See I_Qin Section 7.5.

I_ENis current drawn by the LM53625-Q1 or LM53635-Q1 from its EN terminal. Include this current if EN is

connected to VIN. See I_ENin Section 7.5. Note that this current drops to a very low value if connected to a

voltage less than 5 V.

•

I_Bis bias/feedback current drawn by the LM53625-Q1 or LM53635-Q1 while the Buck converter utilizing it is

unloaded. See I_Bin Section 7.5.

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•

I_divis the current drawn by the feedback voltage divider used to set output voltage for adjustable devices.

This current is zero for fixed output voltage devices.

η_effis the light load efficiency of the Buck converter with I_{Q_VIN}removed from the input current of the buck

converter input current. 0.8 is a conservative value that can be used under normal operating conditions.

Note

The EN pin consumes a few micro-amperes when tied to high; see I_EN. Add I_ENto I_Qas shown in

Equation 2 if EN is tied to V_IN. If EN is tied to a voltage less than 5 V, virtually no current is consumed

allowing EN to be used as an UVLO pin once a voltage divider is added.

8.4.2 FPWM Mode

With a logic high on the FPWM input, the device is locked in PWM mode. This operation is maintained, even at

no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load

efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In this

mode, a negative current limit of I_NEGis imposed to prevent damage to the low-side FET of the regulator. When

in FPWM the converter synchronizes to any valid clock signal on the SYNC input (see Section 8.4.3 and Section

8.4.4.

When constant frequency operation is more important than light load efficiency, pull the LM53625/35-Q1 FPWM

input high or provide a valid synchronization input. Once activated, this feature ensures that the switching

frequency stays above the AM frequency band, while operating between the minimum and maximum duty cycle

limits. Essentially, the diode emulation feature is turned off in this mode. This means that the device remains

in CCM under light loads. Under conditions where the device must reduce the on time or off time below the

ensured minimum, the frequency reduces to maintain the effective duty cycle required for regulation. This can

occur for high input/output voltage ratios.

With the FPWM pin pulled low (normal mode), the diode emulation feature is activated. Device operation is the

same as above; however, the regulator goes into DCM operation when the valley of the inductor current reaches

zero.

This feature may be activated and deactivated while the part is regulating without removing the load. This feature

activates and deactivates gradually, over approximately 40 µs, preventing perturbation of output voltage. When

in FPWM mode, a limited reverse current is allowed through the inductor allowing power to pass from the

regulators output to its input. In this case, care must be taken to ensure that a large enough input capacitor is

used to absorb this reverse current.

Note

While FPWM is activated, larger currents pass through the inductor than in AUTO mode when lightly

loaded. This may result in more EMI, though at a predictable frequency. Once loads are heavy enough

to necessitate CCM operation, FPWM has no measurable effect on the operation of the regulator.

8.4.3 Dropout

One of the parameters that influences the dropout performance of a buck regulator is the minimum off time. As

the input voltage is reduced, to near the output voltage, the off time of the high-side switch starts to approach

the minimum value (see Section 7.5). Beyond this point the switching may become erratic and/or the output

voltage falls out of regulation. To avoid this problem, the LM53625/35-Q1 automatically reduces the switching

frequency to increase the effective duty cycle. This results in two specifications regarding dropout voltage, as

shown in Section 7.6. One specification indicates when the switching frequency drops to 1.85 MHz; avoiding the

A.M. radio band. The other specification indicates when the output voltage has fallen to 3% of nominal. See the

Section 9.2.2.3 for typical dropout values. The overall dropout characteristic for the 5-V option can be seen in

Figure 8-11 and Figure 8-12. The SYNC input is ignored during frequency foldback in dropout. Additional dropout

information is discussed in for 5-V output (Section 9.2.2.3 and for 3.3 V output (Section 9.2.3.3).

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5.2

2.5E+6

2E+6

1.5E+6

1E+6

5E+5

0

5

4.8

4.6

4.4

4.2

0 A

1 A

2 A

3 A

0 A

1 A

2 A

3 A

3.5 A

4

4.25

4.5

4.75

Input Voltage (V)

5

5.25

5.5

4

4.5

5 5.5

Input Voltage (V)

6

6.5

D029

D030

Figure 8-11. Overall Dropout Characteristics (V_OUT

= 5 V)

Figure 8-12. Frequency Dropout Characteristics

(V_OUT= 5 V)

8.4.4 Input Voltage Frequency Foldback

At higher input voltages the on time of the high-side switch becomes small. When the minimum is reached (see

Section 7.5), the switching may become erratic and/or the output voltage may fall out of regulation. To avoid this

behavior, the LM53625/35-Q1 automatically reduces the switching frequency at input voltages above about 20 V

(see Section 9.2.2.3). In this way the device avoids the minimum on-time restriction and maintains regulation at

abnormally high battery voltages. The SYNC input is ignored during frequency foldback at high input voltages.

Frequency foldback patterns are different for the fixed 3.3-V and the 5-V output options. The fixed 3.3-V option

has a deeper foldback pattern to accommodate the lower duty cycle. The adjustable option has a fold-back

patterns is similar to that of the fixed 3.3-V option.

8.5 Spread-Spectrum Operation

The spread spectrum is a factory option. In order to find which parts have spread spectrum enabled, see Section

5.

The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading

emissions across a wider range of frequencies than a part with fixed frequency operation. In most systems

containing the LM53625-Q1 and LM53635-Q1 devices, low frequency conducted emissions from the first few

harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction of

emissions at higher harmonics which fall in the FM band. These harmonics often couple to the environment

through electric fields around the switch node. The LM53625-Q1 and LM53635-Q1 devices use a ±3% spread

of frequencies which spread energy smoothly across the FM band but is small enough to limit sub-harmonic

emissions below its switching frequency. Peak emissions at the part’s switching frequency are only reduced by

slightly less than 1 dB, while peaks in the FM band are typically reduced by more than 6 dB.

The LM53625-Q1 and LM53635-Q1 devices use a cycle to cycle frequency hopping method based on a linear

feedback shift register (LFSR). Intelligent pseudo random generator limits cycle to cycle frequency changes to

limit output ripple. Pseudo random pattern repeats by approximately 8 Hz which is below the audio band.

The spread spectrum is only available while the clock of the LM53625-Q1 and LM53635-Q1 devices is free

running at its natural frequency. Any of the following conditions overrides spread spectrum, turning it off:

1. An external clock is applied to the SYNC/MODE terminal.

2. The clock is slowed due to operation low input voltage – this is operation in dropout.

3. The clock is slowed due to high input voltage – input voltage above approximately 21 V disables spread

spectrum.

4. The clock is slowed under light load in Auto mode – this is normally not seen above 200 mA of load. In

FPWM mode, spread spectrum is active even if there is no load.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The LM53625/35-Q1 is a step-down DC-DC converter, typically used to convert a higher DC voltage to a lower

DC voltage with a maximum output current of 2.5 A or 3.5 A. The following design procedures can be used to

select components for the LM53625/35-Q1. Alternately, the WEBENCH^®Design Tool may be used to generate

a complete design. This tool utilizes an iterative design procedure and has access to a comprehensive database

of components. This allows the tool to create an optimized design and allows the user to experiment with various

design options.

9.2 Typical Applications

9.2.1 General Application

Figure 9-1 shows a general application schematic. FPWM, SYNC and EN are digital inputs. RESET is an

open-drain output. FB connection is different for the fixed output options and the adjustable option.

•

The FPWM pin can be connected to GND to enable light-load PFM operation. Select this option if current

consumption at light load is critical. The pin can be connected to VCC or VIN for forced 2-MHz operation.

Select this option if constant switching frequency is critical over the entire load range. The pin can also be

driven by an external signal and can be toggled while the part is in operation (by an MCU for example.) Refer

to the Section 7.5 and Section 8.4 for more details on the operation and signal requirements of the FPWM

pin.

•

The SYNC pin can be used to control the switching frequency and the phase of the converter. If the function

is not needed, tie the SYNC pin to GND or 3 V.

The RESET pin can be left floating if the function is not required. If the function is needed, the pin must be

connected to a DC rail through a pullup resistor (100 kΩ is the typical recommended value). Check Section

7.5 and Section 8.3.1 for the details of the RESET-pin function.

•

If the device is a fixed-output version (3.3 V or 5 V output option), connect the FB pin directly to the output. In

the case of an adjustable-output part, connect the output to the FB pin through a voltage divider. See Section

9.2.1.2 for details on component selection.

The BIAS pin can be connected directly to the output except in applications that can experience inductive

shorts (such as cases with long leads on the output). In those cases, a 3 Ω or so is necessary between

the output and the BIAS pin, and a small capacitor to GND is necessary close to the BIAS pin (C_BIAS).

Alternatively, a Schottky diode can be connected between the OUT and GND to limit the negative voltage that

can arise on the output during inductive shorts. In addition, BIAS can also be connected to an external rail

if necessary and if available. The typical current into the bias pin is 15 mA when the device is operating in

PWM mode at 2.1 MHz.

•

Power components must be chosen carefully for proper operation of the converter. Section 9.2.1.2 discusses

the details of the process of choosing the input capacitors, output capacitors, and inductor for the application.

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Figure 9-1. General Application Circuit

9.2.1.1 Design Requirements

See Table 9-4, Table 9-5, and Table 9-6. The minimum input voltage shown in Figure 9-1 is not the minimum

operating voltage of the LM53625-Q1/LM53635-Q1. Rather, it is a typical operating range for the systems. For

the complete information regarding minimum input voltage, please refer to Section 7.5

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 External Components Selection

The device requires input capacitors and an output inductor-capacitor filter. These components are critical to the

performance of the device.

9.2.1.2.1.1 Input Capacitors

The input capacitor supplies the AC switching current drawn from the switching action of the internal power

FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor

is large. The input capacitor must be rated to handle both the RMS current and the dissipated power.

The device is designed to be used with ceramic capacitors on the input of the buck regulator. The recommended

dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper tolerances over

voltage and temperature.

The device requires a minimum of 22 µF of ceramic capacitance at the input. TI recommends 2 × 10 µF, 10 µF

for PVIN1 and 10 µF for PVIN2. Place these capacitors close to the PVIN1 and PGND1 / PVIN2 and PGND2

pads.

In addition, it is especially important to have small ceramic capacitors of 10 nF to 100 nF very close to the PVIN1

and PVIN2 inputs in order to minimize ringing and EMI generation due to the high speed switching of the device

coupled with trace inductance.

Many times it is desirable to use an additional electrolytic capacitor on the input, in parallel with the ceramics.

This is especially true if longs leads/traces are used to connect the input supply to the regulator. The moderate

ESR of this capacitor can help damp any ringing on the input supply caused by long power leads. The use of this

additional capacitor will also help with voltage dips caused by input supplies with unusually high impedance.

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9.2.1.2.1.1.1 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying ripple

current and isolating switching noise from other circuits. Table 9-1 shows the nominal and minimum values of

total input capacitance recommenced for the LM53625/35-Q1. Also shown are the measured values of effective

capacitance for the indicated capacitor. In addition, small high frequency bypass capacitors connected directly

between the VIN and PGND pins are very helpful in reducing noise spikes and aid in reducing conducted EMI. TI

recommends that a small case size 10-nF ceramic capacitor be placed across the input, as close to the device

as possible. Additional high-frequency capacitors can be used to help manage conducted EMI or voltage spike

issues that may be encountered.

Table 9-1. Recommended Input Capacitors

NOMINAL INPUT CAPACITANCE

MINIMUM INPUT CAPACITANCE

PART NUMBER

RATED

CAPACITANCE

MEASURED

MEASURED CAPACITANCE⁽¹⁾

RATED CAPACITANCE

CAPACITANCE⁽¹⁾

3 × 10 μF

22.5 μF

2 × 10 μF

15 μF

CL32B106KBJNNNE

(1) Measured at 14 V and 25°C.

9.2.1.2.1.2 Output Inductors and Capacitors Selection

There are several design considerations related to the selection of output inductors and capacitors:

•

Load transient response

Stability

Efficiency

Output ripple voltage

Overcurrent ruggedness

The device has been optimized for use with nominal LC values as shown in the Figure 9-1.

9.2.1.2.1.2.1 Inductor Selection

The LM53625/35-Q1 is optimized for a nominal inductance of 2.2 μH for the 5-V and 3.3-V versions. This gives

a ripple current that is approximately 20% to 30% of the full load current of 3.5 A. For output voltages greater

than 5 V, a proportionally larger inductor can be used, thus keeping the ratio of inductor current slope to internal

compensating slope constant.

The most important inductor parameters are saturation current and parasitic resistance. Inductors with a

saturation current of between 7 A and 8 A are appropriate for most applications when using the LM53625/35-Q1.

Of course, the inductor parasitic resistance must be as low as possible to reduce losses at heavy loads. Table

9-2 gives a list of several possible inductors that can be used with the LM53625/35-Q1.

The LM53625 and LM53635 devices run in current mode and with internal compensation. This compensation

is stable with inductance between 1.5 µH and 10 µH. For most applications, use 2.2 µH with the fixed 5-V

and 3.3-V versions of the LM53625 and LM53635 devices. Adjustable devices operate at the same frequency

under high input-voltage conditions as devices set to deliver 3.3 V (see Switching Frequency vs Input Voltage).

Inductor current ripple at high input voltages can become excessive when using a 2.2-µH inductor with an

adjustable device that is delivering output voltage above 6 V. A 4.7-µH inductor might be necessary. Inductance

that is too high is not recommended as it can result in poor load transient behavior and instability for extreme

inductance choice. See Table 9-2 for typical recommended values.

The inductor must be rated to handle the peak load current plus the ripple current — take care when reviewing

the different saturation current ratings specified by different manufacturers. Saturation current ratings are

typically specified at 25°C, so ratings at maximum ambient temperature of the application should be requested

from the manufacturer. For the LM53635, TI recommends a saturation current of 7.5 A or higher, and for the

LM53625, a saturation current of 6.5 A or higher is recommended

Table 9-2. Recommended Inductors

MANUFACTURER

PART NUMBER

SATURATION CURRENT

DC RESISTANCE

Würth

7440650022

6 A

15 mΩ

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Table 9-2. Recommended Inductors (continued)

MANUFACTURER

Coilcraft

PART NUMBER

SATURATION CURRENT

DC RESISTANCE

11 mΩ

DO3316T-222MLB

7.8 A

7.9 A

8 A

Coiltronics

Vishay

MPI4040R3-2R2-R

48 mΩ

IHLP2525CZER2R2M01

IHLP2525BDER2R2M01

18 mΩ

Vishay

6.5 A

28 mΩ

The designer should choose the inductors that best match the system requirements. A very wide range of

inductors are available as regarding physical size, height, maximum current (thermally limited, and inductance

loss limited), series resistance, maximum operating frequency, losses, and so forth. In general, inductors of

smaller physical size have higher series resistance (DCR) and implicitly lower overall efficiency is achieved.

Very low-profile inductors may have even higher series resistance. TI recommends finding the best compromise

between system performance and cost.

9.2.1.2.1.2.2 Output Capacitor Selection

The LM53625/35-Q1 is designed to work with low-ESR ceramic capacitors. For automotive applications, TI

recommends X5R and X7R type capacitors. The effective value of these capacitors is defined as the actual

capacitance under voltage bias and temperature. All ceramic capacitors have a large voltage coefficient,

in addition to normal tolerances and temperature coefficients. Under DC bias, the capacitance value drops

considerably. Larger case sizes and/or higher voltage capacitors are better in this regard. To help mitigate these

effects, multiple small capacitors can be used in parallel to bring the minimum effective capacitance up to the

desired value. This can also ease the RMS current requirements on a single capacitor. Table 9-3 shows the

nominal and minimum values of total output capacitance recommended for the LM53625/35-Q1. The values

shown also provide a starting point for other output voltages, when using the adjustable option. Also shown are

the measured values of effective capacitance for the indicated capacitor. More output capacitance can be used

to improve transient performance and reduce output voltage ripple.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load

transient testing and Bode plots are the best way to validate any given design and should always be completed

before the application goes into production. Make a careful study of temperature and bias voltage variation of

any candidate ceramic capacitor in order to ensure that the minimum value of effective capacitance is provided.

The best way to obtain an optimum design is to use the Texas Instruments WEBENCH Design Tool.

In adjustable applications the feed-forward capacitor, C_FF, provides another degree of freedom when stabilizing

and optimizing the design. Refer to Optimizing Transient Response of Internally Compensated dc-dc Converters

With Feedforward Capacitor (SLVA289) for helpful information when adjusting the feed-forward capacitor.

In addition to the capacitance shown in Table 9-3, a small ceramic capacitor placed on the output can help to

reduce high frequency noise. Small case-size ceramic capacitors in the range of 1 nF to 100 nF can be very

helpful in reducing spikes on the output caused by inductor parasitics.

Limit the maximum value of total output capacitance to between 300 μF and 400 μF. Large values of output

capacitance can prevent the regulator from starting up correctly and adversely effect the loop stability. If values

in the range given above, or greater, are to be used, then a careful study of start-up at full load and loop stability

must be performed.

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Table 9-3. Recommended Output Capacitors

OUTPUT VOLTAGE

NOMINAL OUTPUT CAPACITANCE

MINIMUM OUTPUT CAPACITANCE

PART NUMBER

RATED

CAPACITANCE

MEASURED

RATED

CAPACITANCE

MEASURED

CAPACITANCE⁽¹⁾

3.3 V (fixed option)

5 V (fixed option)

6 V

3 × 22 µF

5 × 22 μF

63 µF

60 µF

98 µF

80 µF

2 × 22 µF

3 × 22 μF

42 µF

40 µF

58 µF

48 µF

C3225X7R1C226M250AC

10 V⁽²⁾

(1) Measured at indicated V_OUTat 25°C.

(2) L = 4.7 μH.

The output capacitor of a switching converter absorbs the AC ripple current from the inductor and provides

the initial response to a load transient. The ripple voltage at the output of the converter is the product of the

ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the

capacitor can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on

the frequency of the ripple current. Ceramic capacitors have very low ESR and remain capacitive up to high

frequencies. Their inductive component can be usually neglected at the frequency ranges the switcher operates.

The output-filter capacitor smooths out the current flow from the inductor to the load and helps maintain a steady

output voltage during transient load changes. It also reduces output voltage ripple. These capacitors must be

selected with sufficient capacitance and low enough ESR to perform these functions.

Consult Output Ripple Voltage for Buck Switching Regulator (SLVA630) for more details on the estimation of the

output voltage ripple for this converter.

9.2.1.2.2 Setting the Output Voltage

For the fixed output voltage versions, the FB input is connected directly to the output voltage node. Preferably,

near the top of the output capacitor. If the feedback point is located further away from the output capacitors (that

is, remote sensing), then a small 100-nF capacitor may be needed at the sensing point.

9.2.1.2.2.1 FB for Adjustable Versions

The adjustable version of the LM53625-Q1 and LM53635-Q1 devices regulates output voltage to a level that

results in the FB node being V_REF, which is approximately 1 V; see Section 7.5. Output voltage given a specific

feedback divider can be calculated using Equation 3:

R_FBB+ R_FBT

R_FBB

Output Voltage = V_ref

ì

(3)

See Figure 9-34 for an example of the use of adjustable versions of the LM53625-Q1 and LM53635-Q1 devices.

To ensure proper behavior for all modes of operation, a 50 kΩ resistor is recommended for R_FBT. R_FBBcan then

be determined using :

V

ìR_FBT

ref

R_FBB

=

Output Voltage - V

ref

(4)

In addition a feed-forward capacitor C_FFmay be required to optimize the transient response. For output voltages

greater than 6 V, the WEBENCH Design Tool can be used to optimize the design.

9.2.1.2.3 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the LM53625/35-Q1. This

output requires a 4.7-µF, 10-V ceramic capacitor connected from VCC to GND for proper operation. X7R type is

recommended for automotive applications. In general this output must not be loaded with any external circuitry.

However, it can be used to supply a logic level to the FPWM input or for the pullup resistor used with the RESET

output. The nominal output of the LDO is 3.15 V.

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9.2.1.2.4 BIAS

The BIAS pin is the input to the internal LDO. As mentioned in Section 8.3.8, this input is connected to V_OUT

in order to provide the lowest possible supply current at light loads. Because this input is connected directly to

the output, it must be protected from negative voltage transients. Such transients may occur when the output is

shorted at the end of a long PCB trace or cable. If this is likely in a given application, then place a small resistor

in series between the BIAS input and V_OUT, as shown in Figure 9-4. Size the resistor to limit the current out of

the BIAS pin to < 100 mA. Values in the range of 2 Ω to 5 Ω are usually sufficient. Values greater than 5 Ω are

not recommended. As a rough estimate, assume that the full negative transient will appear across R_BIASand

design for a current of < 100 mA. In severe cases, a Schottky diode can be placed in parallel with the output to

limit the transient voltage and current.

When a resistor is used between the output and the BIAS pin, a 0.1-µF capacitor is required close to the BIAS

pin. In general, TI recommends having a 0.1-µF capacitor near the BIAS pin, regardless of the presence or not

of the resistor, unless the trace between the output capacitors and the BIAS pin is very short.

The typical current into the bias pin is 15 mA when the device is operating in PWM mode at 2.1 MHz.

9.2.1.2.5 CBOOT

The LM53625/35-Q1 requires a boot-strap capacitor between the CBOOT pin and the SW pin. This capacitor

stores energy that is used to supply the gate drivers for the power MOSFETs. A ceramic capacitor of 0.47 µF, ≥

6.3 V is required.

9.2.1.2.6 Maximum Ambient Temperature

As with any power conversion device, the LM53625/35-Q1 dissipates internal power while operating. The effect

of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die

temperature (T_J) is a function of the ambient temperature, the power loss, and the effective thermal resistance,

R_θJAof the device and PCB combination. The maximum internal die temperature for the LM53625/35-Q1 is

150°C, thus establishing a limit on the maximum device power dissipation and therefore load current at high

ambient temperatures. Equation 5 shows the relationships between the important parameters.

(

T_J- T_A

R_qJA

)

∂

h

1- h

1

I_OUT

=

∂

(

)

V_OUT

(5)

The device uses an advanced package technology that utilizes the pads/pins as heat spreading paths. As a

result, the pads should be connected to large copper areas in order to dissipate the heat from the IC. All pins

provide some heat relief capability but the PVINs, PGNDs and SW pins are of particular importance for proper

heat dissipation. Utilization of all the board layers for heat dissipation using vias as heat pipes is recommended.

The Layout Guideline section includes example that shows layout for proper heat management.

9.2.1.3 Application Curves

These parameters are not tested and represent typical performance only. Unless otherwise stated, the following

conditions apply: V_IN= 12 V, T_A= 25°C. For the purpose of offering the more information to the designer,

information for the application with FPWM pin high (FPWM mode) and FPWM pin low (AUTO mode) is included,

although the schematic shows the application running specifically in FPWM mode. The mode is specified under

each following graph.

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4

3.5

3

8 Vin

5.5 Vin

8 Vin

12 Vin

13.5 Vin

18 Vin

36 Vin

3.5

3

12 Vin

13.5 Vin

18 Vin

36 Vin

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

0.5

1

1.5 2

Output Current (A)

2.5

3

3.5

0

0.5

1

1.5 2

Output Current (A)

2.5

3

3.5

D0312

D031

Figure 9-3. Power Dissipation 3.3-V Output

Figure 9-2. Power Dissipation 5-V Output

9.2.2 Fixed 5-V Output for USB-Type Applications

Figure 9-4. Fixed 5-V, 3.5-A Output Power Supply

9.2.2.1 Design Requirements

Example requirements for a typical 5-V application. The input voltages are here for illustration purposes only.

See Section 7.5 for minimum operating input voltage. The minimum input voltage necessary to achieve proper

output regulation depends on the components used. See Dropout for –3% Regulation for typical drop-out

behavior.

Table 9-4. Example Requirements for 5-V Typical Application

DESIGN PARAMETER

EXAMPLE VALUE

8 V to 18 V steady state, 5.5 V to 36 V transients

0 A to 3.5 A

Input voltage range

Output current

Switching Frequency at 0-A load

Current Consumption at 0-A load

Synchronization

Critical: must have > 1.85 MHz

Not critical: < 100 mA acceptable

Yes: 1.9 MHz supplied by MCU

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9.2.2.2 Detailed Design Procedure

•

BIAS is connected to the output. This example assumes that the load is connected to the output through long

wires so a 3 Ω resistor is inserted to minimize risks of damage to the part during load shorts. As a result a

0.1-µF capacitor is required close to the bias pin.

FB is connected directly to the output. BIAS and FB are connected to the output via separate traces. This is

important in order to reduce noise and achieve good performances. See Section 11.1 for more details on the

proper layout method.

SYNC is connected to ground through a pulldown resistor, and an external synchronization signal can be

applied. The pulldown resistor ensures that the pin is not floating when the SYNC pin is not driven by any

source.

•

EN is connected to VIN so the device operates as soon as the input voltage rises above the V_IN-OPERATE

threshold.

FPWM is connected to VCC. This causes the device to operate in FPWM mode. In this mode, the switching

frequency is not affected by the output current and is ensured to be within the boundaries set by F_SW. The

drawback is that the efficiency is not optimized for light loads. See Section 8.4 for more details.

A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin This ensures stable operation

of the internal LDO.

RESET is biased to the output in this example. A pullup resistor is necessary. A 100-kΩ is selected for this

application and is generally sufficient. The value can be selected to match the needs of the application but

must not lead to excessive current into the RESET pin when RESET is in a low state. Consult Section 7.1 for

the maximum current allowed. In addition, a low pullup resistor could lead to an incorrect logic level due to

the value of R_RESET. Consult Section 7.5 for details on the RESET pin.

•

Input capacitor selection is detailed in Section 9.2.1.2.1.1. It is important to connect small high-frequency

capacitors C_{IN_HF1}and C_{IN_HF2}as close to both inputs PVIN1 and PVIN2 as possible.

Output capacitor selection is detailed in Section 9.2.1.2.1.2.2.

Inductor selection is detailed in Section 9.2.1.2.1.2.1. In general, a 2.2-µH inductor is recommended for the

fixed output options. For the adjustable options, the inductance can vary with the output voltage due to ripple

and current limit requirements.

•

9.2.2.3 Application Curves

The following characteristics apply only to the circuit of Section 9.2.2. These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 12 V, T_A=

25°C. For the purpose of offering the more information to the designer, information for the application with

FPWM pin high (FPWM mode) and FPWM pin low (AUTO mode) is included, although the schematic shows the

application running specifically in FPWM mode. The mode is specified under each following graph.

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100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

5.5Vin

8Vin

12Vin

13.5Vin

18Vin

36Vin

8Vin

12Vin

13.5Vin

18Vin

0

0.5

1

1.5 2

Output Current (A)

2.5

3

3.5

1E-5

0.0001

0.001 0.01

Output Current (A)

0.10.2 0.5 1 2 34

D006

D002

V_OUT= 5 V

FPWM

V_OUT= 5 V

AUTO

Figure 9-6. Efficiency

Figure 9-5. Efficiency

5.08

5.06

5.04

5.02

5

5.05

8Vin

5.025

5

12Vin

18Vin

36Vin

4.975

4.95

4.925

4.9

5.5Vin

8Vin

12Vin

13.5Vin

18Vin

36Vin

4.875

4.85

4.825

4.8

4.98

4.96

4.775

0

0.5

1

1.5 2

Output Current (A)

2.5

3

3.5

0

0.5

1

1.5 2

Output Current (A)

2.5

3

3.5

D007

D003

V_OUT= 5 V

FPWM

V_OUT= 5 V

AUTO

Figure 9-8. Load and Line Regulation

Figure 9-7. Load and Line Regulation

36

34

32

30

28

26

24

22

20

18

550

500

450

400

350

300

250

200

150

100

4

8

12

16

20

24

Input Voltage (V)

28

32

36

6

9

12

15

18

21

24

Input Voltage (V)

27

30

33

36

D017

D015

V_OUT= 5 V

AUTO

I_OUT= 0 A

Figure 9-10. Load Current for PFM-to-PWM

transition

Figure 9-9. Input Supply Current (includes Leakage

Current of the Capacitor)

32

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1.5

1.2

0.9

0.6

0.3

0

-40C

25C

105C

1.2

0.9

0.6

0.3

-40C

25C

105C

0

0.5

1

1.5

Output Current (A)

2

2.5

3

3.5

0

0.5

1

1.5

Output Current (A)

2

2.5

3

3.5

D022

D021

V_OUT= 5 V

Figure 9-11. Dropout for –3% Regulation

Figure 9-12. Dropout for ≥ 1.85 MHz

5E+6

2.5

2

1E+6

1E+5

1E+4

1E+3

1.5

1

8Vin

12Vin

18Vin

0.5

0

1E+2

5E+1

1E-6

1E-5 0.0001 0.001 0.01

Output Current (A)

0.1

1

5

0

4

8

12

16

20

Vin (V)

24

28

32

36

40

D018

D001

V_OUT= 5 V

AUTO

V_OUT= 5 V

FPWM

Figure 9-13. Switching Frequency vs Load Current

Figure 9-14. Switching Frequency vs Input Voltage

5

4.5

4

3.5

LM53635

LM53625

AUTO

V_OUT= 5 V

I_OUT= 10 mA to

3.5 A

L = 2.2 µH

3

C_OUT= 3 × 22 µF

T_R= T_F= 1 µs

5

10

15

20 25

Input Voltage (V)

30

35

40

D005

V_OUT= 5 V

L = 2.2µH

Figure 9-16. Load Transients

Figure 9-15. Output Current Level Limit Before

Overcurrent Protection

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FPWM

C_OUT= 3 × 22 µF

V_OUT= 5 V

L = 2.2 µH

T_R= T_F= 1µs

I_OUT= 0 A to 3.5 A

Figure 9-17. Load Transient

9.2.3 Fixed 3.3-V Output

Figure 9-18. Fixed 3.3-V, 3.5-A Output Power Supply

9.2.3.1 Design Requirements

Example requirements for a typical 3.3-V application. The input voltages are here for illustration purposes

only. See Section 7.5 for minimum operating input voltage. The minimum input voltage necessary to achieve

proper output regulation depends on the components used. See Dropout for –3% Regulation for typical drop-out

behavior.

Table 9-5. Example Requirements for 3.3-V Application

DESIGN PARAMETER

EXAMPLE VALUE

8-V to 18-V steady state, 4.0-V to 36-V transients

0 A to 3.5 A

Input voltage range

Output current

Swtiching Frequency at 0-A load

Current Consumption at 0-A load

Synchronization

Not critical: Need >1.85 MHz at high load only

Critical: Need to ensure low current consumption to reduce battery drain

No

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9.2.3.2 Detailed Design Procedure

•

BIAS is connected to the output. This example assumes that the load is close to the output so no bias

resistance is necessary. A 0.1-µF capacitor is still recommended close to the bias pin.

FB is connected directly to the output. BIAS and FB are connected to the output via separate traces. This is

important to reduce noise and achieve good performances. See Section 11.1 for more details on the proper

layout method.

•

SYNC is connected to ground directly as there is no need for this function in this application.

EN is connected to VIN so the device perates as soon as the input voltage rises above the V_IN-OPERATE

threshold.

•

FPWM is connected to GND. This causes the device to operate in AUTO mode. In this mode, the switching

frequency is adjusted at light loads to keep efficiency maximum. As a result the switching frequency will

change with the output current until medium load is reached. The part will then switch at the frequency

defined by F_SW. See Section 8.4 for more details.

•

A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin This ensures stable operation

of the internal LDO.

RESET is biased to an external rail in this example. A pullup resistor is necessary. A 100 kΩ is selected for

this application and is generally sufficient. The value can be selected to match the needs of the application

but must not lead to excessive current into the RESET pin when RESET is in a low state. Consult Section 7.1

for the maximum current allowed. In addition, a low pull-up resistor could lead to an incorrect logic level due

to the value of R_RESET. Consult Section 7.5 for details on the RESET pin.

•

it is important to connect small high frequency capacitors C_{IN_HF1}and C_{IN_HF2}as close to both inputs PVIN1

and PVIN2 as possible. For the detailed process of choosing input capacitors, refer to Section 9.2.1.2.1.1.

Output capacitor selection is detailed in Section 9.2.1.2.1.2.2.

Inductor selection is detailed in Section 9.2.1.2.1.2.1. In general, a 2.2-µH inductor is recommended for the

fixed output options. For the adjustable options, the inductance can vary with the output voltage due to ripple

and current limit requirements.

•

9.2.3.3 Application Curves

The following characteristics apply only to the circuit of Figure 9-18. These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 12 V, T_A=

25°C. For the purpose of offering the more information to the designer, information for the application with

FPWM pin high (FPWM mode) and FPWM pin low (AUTO mode) is included, although the schematic shows the

application running specifically in AUTO mode. The mode is specified under each of the following graphs.

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100%

90%

80%

70%

60%

50%

40%

30%

20%

3.4

3.38

3.36

3.34

3.32

3.3

5.5Vin

8Vin

12Vin

18Vin

36Vin

3.28

3.26

3.24

3.22

3.2

8Vin

12Vin

13.5Vin

18Vin

0.0001

0.001

0.01 0.05

Output Current (A)

0.2 0.5

1

2 3 4

0

0.5

1

1.5 2

Output Current (A)

2.5

3

3.5

D008

D009

V_OUT= 3.3 V

AUTO

V_OUT= 3.3 V

AUTO

Figure 9-19. Efficiency

Figure 9-20. Load and Line Regulation

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

3.4

5.5Vin

8Vin

12Vin

18Vin

36Vin

3.38

3.36

3.34

3.32

3.3

5.5Vin

8Vin

12Vin

13.5Vin

18Vin

36Vin

3.28

3.26

3.24

3.22

3.2

0

0.5

1

1.5 2

Output Current (A)

2.5

3

3.5

0

0.5

1

1.5 2

Output Current (A)

2.5

3

3.5

D010

D011

V_OUT= 3.3 V

FPWM

V_OUT= 3.3 V

FPWM

Figure 9-21. Efficiency

Figure 9-22. Load and Line Regulation

45

40

35

30

25

20

15

900

800

700

600

500

400

300

200

100

0

6

12

18 24

Input Voltage (V)

30

36

42

0

5

10

15

20

25

Input Voltage (V)

30

35

40

D014

D016

V_OUT= 3.3 V

AUTO

I_OUT= 0A

Figure 9-24. Load Current for PFM-to-PWM

Transition

Figure 9-23. Input Supply Current (Includes

Leakage Current of Capacitor)

36

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1.5

1.2

0.9

0.6

0.3

0

-40C

25C

105C

1.2

0.9

0.6

0.3

-40C

25C

105C

0

0.5

1

1.5

Output Current (A)

2

2.5

3

3.5

0

0.5

1

1.5

Output Current (A)

2

2.5

3

3.5

D020

D019

V_OUT= 3.3 V

Figure 9-25. Dropout for –3% Regulation

Figure 9-26. Dropout for ≥ 1.85 MHz

5E+6

2.5

2.25

2

2E+6

1E+6

5E+5

2E+5

1E+5

5E+4

1.75

1.5

1.25

1

2E+4

1E+4

5E+3

2E+3

1E+3

5E+2

0.75

0.5

0.25

0

8 Vin

12 Vin

18 Vin

2E+2

1E+2

5E+1

1E-6

1E-5 0.0001 0.001 0.01

Output Current (A)

0.1 0.5 23 5

0

4

8

12

16

20

24

Input Voltage (V)

28

32

36

40

D036

D012

V_OUT= 3.3 V

AUTO

V_OUT= 3.3 V

FPWM

I_OUT= 1 A

Figure 9-27. Switching Frequency vs Load Current

Figure 9-28. Switching Frequency vs Input Voltage

5

4.5

4

3.5

LM53635

LM53625

AUTO

V_OUT= 3.3 V

L = 2.2 µH,

3

C_OUT= 3 × 22 µF

I_OUT= 0 A to 3.5 A

T_R= T_F= 1 µs

5

10

15

20 25

Input Voltage (V)

30

35

40

D005

Figure 9-30. Load Transient

V_OUT= 3.3 V

L=2.2 µH

I_OUT= 1 A

Figure 9-29. Output Current Level for Overcurrent

Protection Trip

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FPWM

V_OUT= 3.3 V

L = 2.2 µH,

V_OUT= 3.3 V

I_OUT= 10 mA

C_OUT= 3 × 22 µF

I_OUT= 0 A to 3.5 A

T_R= T_F= 1 µs

Figure 9-32. Mode Change Transient AUTO to

FPWM mode

Figure 9-31. Load Transient

V_OUT= 3.3 V

I_OUT= 10 mA

Figure 9-33. Mode Change Transient FPWM to AUTO Mode

9.2.4 Adjustable Output

Figure 9-34. 6 V Output Power Supply

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9.2.4.1 Design Requirements

The application highlighted in this section is for a typical 6-V system but can be used as a basis for the

implementation of the adjustable version of the LM53625/LM53635 for other output voltages as well. The input

voltages are here for illustration purposes only. See Section 7.5 for minimum operating input voltage.

Table 9-6. Example Requirements for 6-V Application

DESIGN PARAMETER

EXAMPLE VALUE

8-V to 18-V steady state

0 A to 3.5 A

Input voltage range

Output current

Swtiching Frequency at 0-A load

Current Consumption at 0-A load

Synchronization

Constant frequency preferred

Not critical

No

9.2.4.2 Detailed Design Procedure

•

BIAS is connected to the output. This example assumes that inductive short are a risk for this application so a

3-Ω resistor is added between BIAS and the output. A 0.1-µF capacitor is added close the BIAS pin.

FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin

when the output is at 6 V. A 12-pF capacitance is added in parallel with the top feedback resistor in order to

improve transient behavior. BIAS and FB are connected to the output via separate traces. This is important

to reduce noise and achieve good performances. See Section 11.1 for more details on the proper layout

method.

•

SYNC is connected to ground directly as there is no need for this function in this application.

EN is toggled by an external device (like an MCU for example). A pulldown resistor is placed to ensure the

part does not turn on if the external source is not driving the pin (Hi-Z condition).

FPWM is connected to GND. This leads the device to operate in AUTO mode. In this mode, the switching

frequency is adjusted at light loads to keep efficiency maximum. As a result the switching frequency changes

with the output current until medium load is reached. The device then switches at the frequency defined by

F_SW. See Section 8.4 for more details.

•

A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensure stable operation

of the internal LDO.

RESET is not used in this example so the pin has been left floating. Other possible connections can be seen

in the previous typical applications and in Section 8.3.1.

Power components (input capacitor, output capacitor, and inductor) selection can be found here in Section

9.2.1.2.1.

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9.2.4.3 Application Curves

The following characteristics apply only to the circuit of Figure 9-34. These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 12 V, T_A

= 25°C. For the purpose of offering meaningful information to the designer, information is included for the

application with FPWM pin high (FPWM mode) and FPWM pin low (AUTO mode) although the schematic shows

the application running specifically in AUTO mode. The mode is specified under each of the following graphs.

2.5E+6

2.25E+6

2E+6

1.75E+6

1.5E+6

1.25E+6

1E+6

7.5E+5

5E+5

2.5E+5

0

V_OUT= 6 V (ADJ part)

FPWM

I_OUT= 0 A

0

4

8

12

16

20

24

Input Voltage (V)

28

32

36

40

D037

Figure 9-36. Start-up Waveform

V_OUT= 6 V (ADJ part)

FPWM

I_OUT= 0 A

Figure 9-35. Switching Frequency vs Input Voltage

V_OUT= 6 V (ADJ part)

FPWM

V_OUT= 6 V (ADJ part)

FPWM

I_OUT= 0 A

Figure 9-38. Load Transient

Figure 9-37. Start-up Waveform (EN tied to VIN)

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9.3 What to Do and What Not to Do

•

Don't: Exceed the Section 7.1.

Don't: Exceed the Section 7.3.

Don't: Allow the EN, FPWM or SYNC input to float.

Don't: Allow the output voltage to exceed the input voltage, nor go below ground.

Don't: Use the thermal data given in the Section 7.4 table to design your application.

Do: Follow all of the guidelines and/or suggestions found in this data sheet before committing a design

to production. TI Application Engineers are ready to help critique designs and PCB layouts to help ensure

successful projects.

•

Do: Refer to the helpful documents found in Section 12.2.1.

10 Power Supply Recommendations

The characteristics of the input supply must be compatible with the Section 7.1 and Section 7.3 found in this

data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded

regulator. The average input current can be estimated with Equation 6:

V_OUT∂I_OUT

I_IN=

V ∂ h

IN

(6)

where

•

η is the efficiency.

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the regulator. The parasitic inductance, in combination with the low ESR ceramic input

capacitors, can form an under-damped resonant circuit. This circuit may cause overvoltage transients at the VIN

pin, each time the input supply is cycled on and off. The parasitic resistance causes the voltage at the VIN pin

to dip when the load on the regulator is switched on or exhibits a transient. If the regulator is operating close

to the minimum input voltage, this dip may cause the device to shut down and/or reset. The best way to solve

these kinds of issues is to reduce the distance from the input supply to the regulator and/or use an aluminum or

tantalum input capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors helps to

damp the input resonant circuit and reduce any voltage overshoots. A value in the range of 20 µF to 100 µF is

usually sufficient to provide input damping and help to hold the input voltage steady during large load transients.

Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead

to instability, as well as some of the effects mentioned above, unless it is designed carefully. SNVA538 and

SNVA489c provide helpful suggestions when designing an input filter for any switching regulator.

In some cases a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device

has a snap-back V-I characteristic (thyristor type). The use of a device with this type of characteristic is not

recommend. When the TVS fires, the clamping voltage drops to a very low value. If this holding voltage is less

than the output voltage of the regulator, the output capacitors are discharged through the regulator back to the

input. This uncontrolled current flow could damage the regulator.

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11 Layout

11.1 Layout Guidelines

The PCB layout of a DC-DC converter is critical for optimal performance of the application. For a buck converter

the input loop formed by the input capacitors and power grounds are very critical. The input loop carries fast

transient currents that cause larger transient voltages when reacting with a parasitic loop inductance. The IC

uses two input loops in parallel IN1 and IN2 as shown in Figure 11-1 that cuts the parasitic input inductance in

half. To get the minimum input loop area two small high frequency capacitors CIN1 and CIN2 are placed as close

as possible.

To further reduce inductance, an input current return path should be placed underneath the loops IN1 and IN2.

The closest metal plane is MID1 Layer2, and with a solid copper plane placed right under the IN1 and IN2

loop the parasitic loop inductance is minimized. Connecting this MID1 Layer2 plane then to GND will provide

a nice bridge connection between GND1 and GND2 as well. Minimizing the parasitic input loop inductance will

minimize switch node ringing and EMI.

The output current loop can be optimized as well by using two ceramic output caps COUT1 and COUT2 to

each side. They will form two parallel ground return paths OUT1 from COUT1 back to the low side FET PGND1

pins 5,6,7,8 and a second symmetric ground return path OUT2 from COUT2 back to low side FET PGND2 pins

10,11,12 and 13. Having two parallel ground return path will yield into reduced “ground bouncing” and reduced

sensitivity of surrounding circuits sensitive to it.

Figure 11-1. Layout of the Power Components and Current Flow

Providing adequate thermal paths to dissipate heat is critical for operation at full current. The recommended

method for heat dissipation is to use large solid 2 oz copper planes well connected to the power pins VIN1,

VIN2, GND1 and GND2 which transfer the heat out of the IC over the TOP Layer1 copper planes. It is important

to leave the TOP Layer1 copper planes as unbroken as much as possible so that heat is not trapped near the IC.

The heat flow can be further optimized by thermally connecting the TOP Layer 1 plane to large BOTTOM Layer4

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2oz. copper planes with vias. MID2 Layer3 is then open for all other signal routing. A fully filled / solid BOTTOM

Layer4 ground plane without any interruptions or ground splitting is beneficial for EMI as well. Most important

for low EMI is to use the smallest possible switch node copper area. The switch node including the C_BOOTcap

has the largest dv/dt signal causing common mode noise coupling. Using any kind of grounded shield around the

switch node will “shorten” and reduce this e-field.

All these DC/DC converter descriptions can be transformed into layout guidelines:

1. Place two 0.047-µF / 50-V high frequency input capacitors C_IN1and C_IN2as close as possible to the VIN1/2

and PGND1/2 pins to minimize switch node ringing.

2. Place bypass capacitors for VCC and BIAS close to their respective pins. Make sure AGND pin “sees” the

C_VCCand C_BIAScapacitors first before connecting it to GND.

3. Place C_BOOTcapacitor with smallest parasitic loop. Shielding the C_BOOTcapacitor and switch node will

have biggest impact to reduce common mode noise. Placing a small R_BOOTresistor (less than 3 Ω is

recommended) in series to C_BOOTwill slow down the dV/dt of the switch node and reduce EMI.

4. Place the feedback resistor divider for adjustable parts as close as possible to the FB pin and to AGND pin

of the device. Use dedicated feedback trace and away from switch node and C_BOOTcapacitor to avoid any

cross coupling into sensitive analog feedback.

5. Use dedicated BIAS trace to avoid noise into feedback trace.

6. Use a 3-Ω to 5-Ω resistor between the output and BIAS if the load is far from the output of the converter or

inductive shorts on the output are possible.

7. Use well connected large 2-oz. TOP and BOTTOM copper planes for all power pins VIN1/2 and PGND1/2.

8. Minimize switch node and C_BOOTarea for lowest EMI common mode noise.

9. For lowest EMI place input and output wires on same side of PCB, using EMI filter and away from switch

node.

10. The resources in Section 12 provide additional important guidelines.

11.2 Layout Example

This example layout is the one used in REV A of the LM53635 EVM. It shows the C_INand C_{IN_HF}capacitors

placed symmetrically either side of the device.

Figure 11-2. Recommended Layout for LM53625/35-Q1

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Product Folder Links: LM53625-Q1 LM53635-Q1

LM53625-Q1, LM53635-Q1

SNVSAA7B – DECEMBER 2015 – REVISED JULY 2021

www.ti.com

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For additional information, see the following:

•

Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor

(SLVA289)

•

Output Ripple Voltage for Buck Switching Regulator (SLVA630)

AN-1149 Layout Guidelines for Switching Power Supplies (SNVA021)

AN-1229 Simple Switcher® PCB Layout Guidelines (SNVA054 )

Constructing Your Power Supply- Layout Considerations (SLUP230)

AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)

Semiconductor and IC Package Thermal Metrics (SPRA953)

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®is a registered trademark of TI.

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

44

Submit Document Feedback

Product Folder Links: LM53625-Q1 LM53635-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM536253QRNLRQ1

LM536253QRNLTQ1

LM536255QRNLRQ1

LM536255QRNLTQ1

LM53625AQRNLRQ1

LM53625AQRNLTQ1

LM53625LQRNLRQ1

LM53625LQRNLTQ1

LM53625LQURNLRQ1

LM53625MQRNLRQ1

LM53625MQRNLTQ1

VQFN-

HR

RNL

22

3000

250

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

12.4

4.3

5.3

1.3

8.0

12.0

Q1

VQFN-

HR

VQFN-

HR

3000

250

VQFN-

HR

VQFN-

HR

3000

250

VQFN-

HR

VQFN-

HR

3000

250

VQFN-

HR

VQFN-

HR

3000

250

VQFN-

HR

VQFN-

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Sep-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

HR

LM53625MQURNLRQ1 VQFN-

HR

RNL

22

3000

250

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

12.4

4.3

5.3

1.3

8.0

12.0

Q1

LM53625NQRNLRQ1

LM53625NQRNLTQ1

LM53625NQURNLRQ1

LM536353QRNLRQ1

LM536353QRNLTQ1

LM536355QRNLRQ1

LM536355QRNLTQ1

LM53635AQRNLRQ1

LM53635AQRNLTQ1

LM53635LQRNLRQ1

LM53635LQRNLTQ1

LM53635MQRNLRQ1

LM53635MQRNLTQ1

VQFN-

HR

VQFN-

HR

VQFN-

HR

3000

250

VQFN-

HR

VQFN-

HR

VQFN-

HR

3000

250

VQFN-

HR

VQFN-

HR

3000

250

VQFN-

HR

VQFN-

HR

3000

250

VQFN-

HR

VQFN-

HR

3000

250

VQFN-

HR

LM53635MQURNLRQ1 VQFN-

HR

3000

250

LM53635NQRNLRQ1

LM53635NQRNLTQ1

LM53635NQURNLRQ1

VQFN-

HR

VQFN-

HR

VQFN-

HR

3000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM536253QRNLRQ1

LM536253QRNLTQ1

LM536255QRNLRQ1

LM536255QRNLTQ1

LM53625AQRNLRQ1

LM53625AQRNLTQ1

LM53625LQRNLRQ1

LM53625LQRNLTQ1

LM53625LQURNLRQ1

LM53625MQRNLRQ1

LM53625MQRNLTQ1

LM53625MQURNLRQ1

LM53625NQRNLRQ1

LM53625NQRNLTQ1

LM53625NQURNLRQ1

LM536353QRNLRQ1

LM536353QRNLTQ1

LM536355QRNLRQ1

LM536355QRNLTQ1

LM53635AQRNLRQ1

VQFN-HR

RNL

22

3000

250

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Sep-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM53635AQRNLTQ1

LM53635LQRNLRQ1

LM53635LQRNLTQ1

LM53635MQRNLRQ1

LM53635MQRNLTQ1

LM53635MQURNLRQ1

LM53635NQRNLRQ1

LM53635NQRNLTQ1

LM53635NQURNLRQ1

VQFN-HR

RNL

22

250

3000

250

213.0

367.0

213.0

367.0

213.0

367.0

213.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

191.0

367.0

35.0

38.0

35.0

38.0

35.0

38.0

35.0

38.0

3000

250

3000

250

3000

Pack Materials-Page 4

GENERIC PACKAGE VIEW

RNL 22

5 X 4, 0.5 mm pitch

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226989/A

www.ti.com

PACKAGE OUTLINE

RNL0022A

VQFN-HR - 0.9 mm max height

SCALE 2.800

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

5.1

4.9

0.1 MIN

(0.05)

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

0.9

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2

1

0.45

0.35

2X 0.8 0.1

8X 0.5

5X

(0.2) TYP

9

8

10

7

4

11

2X

1.45 0.1

2X

2.175

2.95 0.1

0.25

PKG

14

0.3

0.2

15X

2X

2

2X 0.85

A

0.1

0.05

C A B

C

0.65

0.45

5X

22

17

1

2X 0.575

0.45

0.35

18

0.45

0.35

SYMM

2

0.5

0.3

11X

0.5

0.3

4221861/E 07/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RNL0022A

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

18

SYMM

15X (0.25)

22

12X (0.6)

2X (0.4)

(2.325)

1

17

2X (2)

5X (0.75)

2X (1.425)

SEE SOLDER MASK

DETAILS

3X (0.4)

2X (0.575)

2X (1)

2X (0.4)

0.000 PKG

2X (0.25)

14

(0.295)

4

(

0.2) VIA TYP

NOTE 4

(3.15)

(1.125)

2X (1.65)

2X (1.875)

(2.175)

(1.955)

11

7

4X (0.5)

8

9

(2)

10

(3.4)

6X (3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

SOLDER MASK DETAILS

(PREFERRED)

4221861/E 07/2019

NOTES: (continued)

3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RNL0022A

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

SYMM

15X (0.25)

5X (0.75)

18

22

12X (0.6)

2X (0.4)

(2.325)

1

2X (2)

17

(R0.05) TYP

2X (1.425)

2X (0.575)

6X

EXPOSED

METAL

7X

EXPOSED

METAL

(1.4)

(0.12)

0.000 PKG

(0.25)

4X ( 0.4)

4

14

(0.71)

(2)

2X (1.445)

(1.54)

4X (0.5)

11

2X (2.175)

2X (2.305)

4X

(0.66)

7

(2.37)

9

10

8

8X (0.4)

4X (0.63)

(2)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR PADS 4,8,9,10 & 14

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4221861/E 07/2019

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

RNL0022B

VQFN-HR - 0.9 mm max height

SCALE 2.800

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

5.1

4.9

PIN 1 INDEX AREA

0.9

0.8

SEATING PLANE

0.08 C

0.05

0.00

2

0.9

0.7

0.45

0.35

2X

1

5X

(0.2) TYP

9

8

10

8X 0.5

7

4

11

1.55

1.35

2X

3.05

2.85

2X

2.175

0.25

PKG

14

0.3

0.2

0.1

15X

2X

2

2X 0.85

C A B

C

0.65

0.45

5X

22

0.05

17

1

2X 0.575

0.45

0.35

18

0.45

0.35

SYMM

2

0.5

0.3

11X

0.5

0.3

4226904/A 07/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RNL0022B

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

18

SYMM

15X (0.25)

22

12X (0.6)

2X (0.4)

(2.325)

1

17

2X (2)

5X (0.75)

2X (1.425)

SEE SOLDER MASK

DETAILS

3X (0.4)

2X (0.575)

2X (1)

2X (0.4)

0.000 PKG

2X (0.25)

14

(0.295)

4

(

0.2) VIA TYP

NOTE 4

(3.15)

(1.125)

2X (1.65)

2X (1.875)

(2.175)

(1.955)

11

7

4X (0.5)

8

9

(2)

10

(3.4)

6X (3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

SOLDER MASK DETAILS

(PREFERRED)

4226904/A 07/2021

NOTES: (continued)

3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RNL0022B

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

SYMM

15X (0.25)

5X (0.75)

18

22

12X (0.6)

2X (0.4)

(2.325)

1

2X (2)

17

(R0.05) TYP

2X (1.425)

2X (0.575)

6X

EXPOSED

METAL

7X

EXPOSED

METAL

(1.4)

(0.12)

0.000 PKG

(0.25)

4X ( 0.4)

4

14

(0.71)

(2)

2X (1.445)

(1.54)

4X (0.5)

11

2X (2.175)

2X (2.305)

4X

(0.66)

7

(2.37)

9

10

8

8X (0.4)

4X (0.63)

(2)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR PADS 4,8,9,10 & 14

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4226904/A 07/2021

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM53635NQRNLRQ1
厂家：	TEXAS INSTRUMENTS
描述：	3.5A、36V 同步、2.1MHz、汽车类降压直流/直流转换器 \| RNL \| 22 \| -40 to 150 转换器
文件：	总59页 (文件大小：3112K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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