LM56BIMX/NOPB [TI]
具有风扇控制功能的 3°C 双路输出电阻可编程温度开关 | D | 8 | -40 to 125;
| 型号： | LM56BIMX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有风扇控制功能的 3°C 双路输出电阻可编程温度开关 | D | 8 | -40 to 125 开关 输出元件 风扇 传感器 换能器 |
| 文件： | 总25页 (文件大小：967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM56
www.ti.com
SNIS120G –APRIL 2000–REVISED FEBRUARY 2013
LM56 Dual Output Low Power Thermostat
Check for Samples: LM56
1
FEATURES
DESCRIPTION
The LM56 is a precision low power thermostat. Two
stable temperature trip points (VT1 and VT2) are
generated by dividing down the LM56 1.250V
bandgap voltage reference using 3 external resistors.
The LM56 has two digital outputs. OUT1 goes LOW
when the temperature exceeds T1 and goes HIGH
when the the temperature goes below (T1–THYST).
Similarly, OUT2 goes LOW when the temperature
exceeds T2 and goes HIGH when the temperature
goes below (T2–THYST). THYST is an internally set 5°C
typical hysteresis.
2
•
•
•
•
•
Digital Outputs Support TTL Logic Levels
Internal Temperature Sensor
2 Internal Comparators with Hysteresis
Internal Voltage Reference
Available in 8-pin SOIC and VSSOP Packages
APPLICATIONS
•
•
•
•
•
•
•
•
Microprocessor Thermal Management
Appliances
The LM56 is available in an 8-lead VSSOP surface
mount package and an 8-lead SOIC.
Portable Battery Powered 3.0V or 5V Systems
Fan Control
Industrial Process Control
HVAC Systems
Remote Temperature Sensing
Electronic System Protection
Table 1. Key Specifications
VALUE
2.7V–10
230
UNIT
V
Power Supply Voltage
Power Supply Current
VREF
μA (max)
V ±1% (max)
°C
1.250
5
Hysteresis Temperature
(+6.20 mV/°C x T) +
395 mV
Internal Temperature Sensor Output Voltage
mV
Table 2. Temperature Trip Point Accuracy
LM56BIM
±2°C (max)
±2°C (max)
±3°C (max)
LM56CIM
+25°C
±3°C (max)
±3°C (max)
±4°C (max)
+25°C to +85°C
−40°C to +125°C
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
LM56
SNIS120G –APRIL 2000–REVISED FEBRUARY 2013
Simplified Block Diagram and Connection Diagram
Block Diagram
www.ti.com
Typical Application
VT1 = 1.250V x (R1)/(R1 + R2 + R3)
VT2 = 1.250V x (R1 + R2)/(R1 + R2 + R3)
where:
(R1 + R2 + R3) = 27 kΩ and
VT1 or T2 = [6.20 mV/°C x T] + 395 mV therefore:
R1 = VT1/(1.25V) x 27 kΩ
R2 = (VT2/(1.25V) x 27 kΩ) − R1
R3 = 27 kΩ − R1 − R2
Figure 1. Microprocessor Thermal Management
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNIS120G –APRIL 2000–REVISED FEBRUARY 2013
Absolute Maximum Ratings(1)
Input Voltage
Input Current at any pin(2)
12V
5 mA
Package Input Current(2)
Package Dissipation at TA = 25°C(3)
20 mA
900 mW
Human Body Model - Pin 3 Only
800V
1000V
All other pins
ESD Susceptibility(4)
Machine Model
Storage Temperature
125V
−65°C to + 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the LM56 Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
(2) When the input voltage (VI) at any pin exceeds the power supply (VI < GND or VI > V+), the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 5 mA to four.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (junction to ambient thermal resistance) and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PD = (TJmax–TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax
125°C. For this device the typical thermal resistance (θJA) of the different package types when board mounted follow:
(4) The human body model is a 100 pF capacitor discharge through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin.
=
Operating Ratings(1)(2)(3)
Operating Temperature Range
TMIN ≤ TA ≤ TMAX
LM56BIM, LM56CIM
−40°C ≤ TA ≤ +125°C
+2.7V to +10V
+10V
Positive Supply Voltage (V+)
Maximum VOUT1 and VOUT2
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the LM56 Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
(2) Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging.
(3) Reflow temperature profiles are different for lead-free and non-lead-free packages.
Package Type
D0008A
θJA
110°C/W
250°C/W
DGK0008A
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LM56 Electrical Characteristics
The following specifications apply for V+ = 2.7 VDC, and VREF load current = 50 μA unless otherwise specified. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C unless otherwise specified.
LM56BIM LM56CIM
Symbol
Parameter
Conditions
Typical(1)
Units (Limits)
Limits(2)
Limits(2)
Temperature Sensor
Trip Point Accuracy (Includes VREF
Comparator Offset, and Temperature
Sensitivity errors)
,
±2
±2
±3
3
±3
±3
±4
3
°C (max)
°C (max)
°C (max)
°C (min)
°C (max)
°C (min)
°C (max)
°C (min)
°C (max)
°C (min)
°C (max)
mV/°C
+25°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
TA = −40°C
Trip Point Hysteresis
4
6
6
TA = +25°C
TA = +85°C
TA = +125°C
5
6
3.5
6.5
4.5
7.5
4
3.5
6.5
4.5
7.5
4
6
8
8
Internal Temperature Sensitivity
Temperature Sensitivity Error
+6.20
±2
±3
±3
±4
°C (max)
°C (max)
Ω (max)
mV/V (max)
Output Impedance
Line Regulation
−1 μA ≤ IL ≤ +40 μA
+3.0V ≤ V+ ≤ +10V,
1500
1500
–0.72/+0.3 –0.72/+0.3
+25 °C ≤ TA ≤ +85 °C
6
6
+3.0V ≤ V+ ≤ +10V,
−40 °C ≤ TA <25 °C
+2.7V ≤ V+ ≤ +3.3V
–1.14/+0.6 –1.14/+0.6
mV/V (max)
mV (max)
1
1
±2.3
±2.3
VT1 and VT2 Analog Inputs
IBIAS
VIN
Analog Input Bias Current
Analog Input Voltage Range
150
V+ − 1
GND
2
300
8
300
8
nA (max)
V
V
VOS
Comparator Offset
mV (max)
VREF Output
VREF
VREF Nominal
VREF Error
1.250V
V
±1
±12.5
0.25
1.1
±1
±12.5
0.25
1.1
% (max)
mV (max)
mV/V (max)
mV (max)
mV/μA (max)
ΔVREF/ΔV+ Line Regulation
+3.0V ≤ V+ ≤ +10V
+2.7V ≤ V+ ≤ +3.3V
+30 μA ≤ IL ≤ +50 μA
0.13
0.15
ΔVREF/ΔIL
Load Regulation Sourcing
0.15
0.15
(1) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(2) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
Symbol
V+ Power Supply
IS
Parameter
Conditions
Typical(1)
Limits(2)
Units (Limits)
Supply Current
V+ = +10V
V+ = +2.7V
230
230
μA (max)
μA (max)
Digital Outputs
IOUT(“1”)
Logical “1” Output Leakage Current
Logical “0” Output Voltage
V+ = +5.0V
1
μA (max)
VOUT(“0”)
IOUT = +50 μA
0.4
V (max)
(1) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(2) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
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SNIS120G –APRIL 2000–REVISED FEBRUARY 2013
Typical Performance Characteristics
Quiescent Current
vs
VREF Output Voltage
vs
Temperature
Load Current
Figure 2.
Figure 3.
OUT1 and OUT2 Voltage Levels
Trip Point Hysteresis
vs
vs
Load Current
Temperature
Figure 4.
Figure 5.
Temperature Sensor Output Voltage
Temperature Sensor Output Accuracy
vs
vs
Temperature
Temperature
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Trip Point Accuracy
vs
Comparator Bias Current
vs
Temperature
Temperature
Figure 8.
Figure 9.
OUT1 and OUT2 Leakage Current
VTEMP Output Line Regulation
vs
vs
Temperature
Temperature
Figure 10.
Figure 11.
VREF Start-Up Response
VTEMP Start-Up Response
Figure 12.
Figure 13.
6
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SNIS120G –APRIL 2000–REVISED FEBRUARY 2013
FUNCTIONAL DESCRIPTION
Pin Functions
V+
This is the positive supply voltage pin. This pin should be bypassed with a 0.1 µF capacitor to ground.
GND
VREF
This is the ground pin.
This is the 1.250V bandgap voltage reference output pin. In order to maintain trip point accuracy this pin
should source a 50 µA load.
VTEMP
OUT1
This is the temperature sensor output pin.
This is an open collector digital output. OUT1 is active LOW. It goes LOW when the temperature is greater
than T1 and goes HIGH when the temperature drops below T1– 5°C. This output is not intended to directly
drive a fan motor.
OUT2
This is an open collector digital output. OUT2 is active LOW. It goes LOW when the temperature is greater
than the T2 set point and goes HIGH when the temperature is less than T2– 5°C. This output is not intended to
directly drive a fan motor.
VT1
VT2
This is the input pin for the temperature trip point voltage for OUT1.
This is the input pin for the low temperature trip point voltage for OUT2.
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SNIS120G –APRIL 2000–REVISED FEBRUARY 2013
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VT1 = 1.250V x (R1)/(R1 + R2 + R3)
VT2 = 1.250V x (R1 + R2)/(R1 + R2 + R3)
where:
(R1 + R2 + R3) = 27 kΩ and
VT1 or T2 = [6.20 mV/°C x T] + 395 mV therefore:
R1 = VT1/(1.25V) x 27 kΩ
R2 = (VT2/(1.25V) x 27 k)Ω–R1
R3 = 27 kΩ − R1 − R2
Application Hints
LM56 TRIP POINT ACCURACY SPECIFICATION
For simplicity the following is an analysis of the trip point accuracy using the single output configuration shown in
Figure 14 with a set point of 82°C.
Trip Point Error Voltage = VTPE
,
Comparator Offset Error for VT1E
Temperature Sensor Error = VTSE
Reference Output Error = VRE
Figure 14. Single Output Configuration
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SNIS120G –APRIL 2000–REVISED FEBRUARY 2013
1. VTPE = ±VT1E − VTSE + VRE
Where:
2. VT1E = ±8 mV (max)
3. VTSE = (6.20 mV/°C) x (±3°C) = ±18.6 mV
4. VRE = 1.250V x (±0.01) R2/(R1 + R2)
Using Equations from Figure 1.
VT1= 1.25V x R2/(R1 + R2) = 6.20 mV/°C)(82°C) + 395 mV
Solving for R2/(R1 + R2) = 0.7227
then,
5. VRE = 1.250V x (±0.01) R2/(R1 + R2) = (0.0125) x (0.7227) = ±9.03 mV
The individual errors do not add algebraically because, the odds of all the errors being at their extremes are rare.
This is proven by the fact the specification for the trip point accuracy stated in the LM56 Electrical Characteristics
for the temperature range of −40°C to +125°C, for example, is specified at ±3°C for the LM56BIM. Note this trip
point error specification does not include any error introduced by the tolerance of the actual resistors used, nor
any error introduced by power supply variation.
If the resistors have a ±0.5% tolerance, an additional error of ±0.4°C will be introduced. This error will increase to
±0.8°C when both external resistors have a ±1% tolerance.
BIAS CURRENT EFFECT ON TRIP POINT ACCURACY
Bias current for the comparator inputs is 300 nA (max) each, over the specified temperature range and will not
introduce considerable error if the sum of the resistor values are kept to about 27 kΩ as shown in the typical
application of Figure 1. This bias current of one comparator input will not flow if the temperature is well below the
trip point level. As the temperature approaches trip point level the bias current will start to flow into the resistor
network. When the temperature sensor output is equal to the trip point level the bias current will be 150 nA
(max). Once the temperature is well above the trip point level the bias current will be 300 nA (max). Therefore,
the first trip point will be affected by 150 nA of bias current. The leakage current is very small when the
comparator input transistor of the different pair is off (see Figure 15).
The effect of the bias current on the first trip point can be defined by the following equations:
(1)
where IB = 300 nA (the maximum specified error).
The effect of the bias current on the second trip point can be defined by the following equations:
(2)
where IB = 300 nA (the maximum specified error).
The closer the two trip points are to each other the more significant the error is. Worst case would be when VT1
VT2 = VREF/2.
=
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Figure 15. Simplified Schematic
MOUNTING CONSIDERATIONS
The majority of the temperature that the LM56 is measuring is the temperature of its leads. Therefore, when the
LM56 is placed on a printed circuit board, it is not sensing the temperature of the ambient air. It is actually
sensing the temperature difference of the air and the lands and printed circuit board that the leads are attached
to. The most accurate temperature sensing is obtained when the ambient temperature is equivalent to the
LM56's lead temperature.
As with any IC, the LM56 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage
and corrosion. This is especially true if the circuit operates at cold temperatures where condensation can occur.
Printed-circuit coatings are often used to ensure that moisture cannot corrode the LM56 or its connections.
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SNIS120G –APRIL 2000–REVISED FEBRUARY 2013
VREF AND VTEMP CAPACITIVE LOADING
Figure 16. Loading of VREF and VTEMP
The LM56 VREF and VTEMP outputs handle capacitive loading well. Without any special precautions, these outputs
can drive any capacitive load as shown in Figure 16.
NOISY ENVIRONMENTS
Over the specified temperature range the LM56 VTEMPoutput has a maximum output impedance of 1500Ω. In an
extremely noisy environment it may be necessary to add some filtering to minimize noise pickup. It is
recommended that 0.1 μF be added from V+ to GND to bypass the power supply voltage, as shown in Figure 16.
In a noisy environment it may be necessary to add a capacitor from the VTEMP output to ground. A 1 μF output
capacitor with the 1500Ω output impedance will form a 106 Hz lowpass filter. Since the thermal time constant of
the VTEMP output is much slower than the 9.4 ms time constant formed by the RC, the overall response time of
the VTEMP output will not be significantly affected. For much larger capacitors this additional time lag will increase
the overall response time of the LM56.
APPLICATIONS CIRCUITS
Figure 17. Reducing Errors Caused by Bias Current
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The circuit shown in Figure 17 will reduce the effective bias current error for VT2 as discussed in Section 3.0 to
be equivalent to the error term of VT1. For this circuit the effect of the bias current on the first trip point can be
defined by the following equations:
(3)
where IB = 300 nA (the maximum specified error).
Similarly, bias current affect on VT2 can be defined by:
(4)
where IB = 300 nA (the maximum specified error).
The current shown in Figure 18 is a simple overtemperature detector for power devices. In this example, an
audio power amplifier IC is bolted to a heat sink and an LM56 Celsius temperature sensor is mounted on a PC
board that is bolted to the heat sink near the power amplifier. To ensure that the sensing element is at the same
temperature as the heat sink, the sensor's leads are mounted to pads that have feed throughs to the back side of
the PC board. Since the LM56 is sensing the temperature of the actual PC board the back side of the PC board
also has large ground plane to help conduct the heat to the device. The comparator's output goes low if the heat
sink temperature rises above a threshold set by R1, R2, and the voltage reference. This fault detection output
from the comparator now can be used to turn on a cooling fan. The circuit as shown in design to turn the fan on
when heat sink temperature exceeds about 80°C, and to turn the fan off when the heat sink temperature falls
below approximately 75°C.
Figure 18. Audio Power Amplifier Overtemperature Detector
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SNIS120G –APRIL 2000–REVISED FEBRUARY 2013
Figure 19. Simple Thermostat
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REVISION HISTORY
Changes from Revision F (February 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
14
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM56BIM
NRND
SOIC
SOIC
D
D
8
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
LM56
BIM
LM56BIM/NOPB
ACTIVE
95
RoHS & Green
SN
LM56
BIM
Samples
LM56BIMM/NOPB
LM56BIMMX/NOPB
LM56BIMX/NOPB
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
1000 RoHS & Green
3500 RoHS & Green
2500 RoHS & Green
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
T02B
Samples
Samples
Samples
T02B
LM56
BIM
LM56CIM
NRND
SOIC
SOIC
D
D
8
8
95
95
Non-RoHS
& Green
Call TI
SN
Level-1-235C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
LM56
CIM
LM56CIM/NOPB
ACTIVE
RoHS & Green
LM56
CIM
Samples
LM56CIMM/NOPB
LM56CIMMX/NOPB
LM56CIMX
ACTIVE
ACTIVE
NRND
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
1000 RoHS & Green
3500 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-235C-UNLIM
-40 to 125
-40 to 125
-40 to 125
T02C
Samples
Samples
T02C
2500
Non-RoHS
& Green
Call TI
LM56
CIM
LM56CIMX/NOPB
ACTIVE
SOIC
D
8
2500 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM56
CIM
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Sep-2022
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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7-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM56BIMM/NOPB
LM56BIMMX/NOPB
LM56BIMX/NOPB
LM56CIMM/NOPB
LM56CIMMX/NOPB
LM56CIMX
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
8
8
1000
3500
2500
1000
3500
2500
2500
178.0
330.0
330.0
178.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
6.5
5.3
5.3
6.5
6.5
3.4
3.4
5.4
3.4
3.4
5.4
5.4
1.4
1.4
2.0
1.4
1.4
2.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
VSSOP
VSSOP
SOIC
DGK
DGK
D
LM56CIMX/NOPB
SOIC
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM56BIMM/NOPB
LM56BIMMX/NOPB
LM56BIMX/NOPB
LM56CIMM/NOPB
LM56CIMMX/NOPB
LM56CIMX
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
8
8
1000
3500
2500
1000
3500
2500
2500
208.0
367.0
367.0
208.0
367.0
367.0
367.0
191.0
367.0
367.0
191.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
VSSOP
VSSOP
SOIC
DGK
DGK
D
LM56CIMX/NOPB
SOIC
D
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM56BIM
LM56BIM
D
D
D
D
D
D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
8
8
8
8
8
8
95
95
95
95
95
95
495
495
495
495
495
495
8
8
8
8
8
8
4064
4064
4064
4064
4064
4064
3.05
3.05
3.05
3.05
3.05
3.05
LM56BIM/NOPB
LM56CIM
LM56CIM
LM56CIM/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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