LM57TPW [TI]
具有电阻可编程温度开关的 ±0.7°C 温度传感器 | PW | 8 | -50 to 150;
| 型号： | LM57TPW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电阻可编程温度开关的 ±0.7°C 温度传感器 | PW | 8 | -50 to 150 开关 温度传感 传感器 温度传感器 |
| 文件： | 总41页 (文件大小：1512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM57
ZHCSDV6E –MAY 2009–REVISED JULY 2015
LM57 电阻可编程温度开关和模拟温度传感器
1 特性
3 说明
1
•
关于 AEC-Q100 1 级/0 级/0 级扩展标准（符合
LM57 器件是一款具有模拟温度传感器输出的精密双路
AEC-Q100 标准并采用汽车级流程制造），请参见
LM57-Q1 数据表
输出温度开关，适用于宽温度范围的工业级应用。 跳
变温度 (TTRIP) 可从 –40°C 至 150°C 温度范围内的
256 种可能值中进行选择。VTEMP 是 AB 类模拟电压输
出，该电压输出与温度成正比，负温度系数 (NTC) 可
编程。 两个外部 1% 电阻设置 TTRIP 和 VTEMP 斜率。
数字和模拟输出具有保护功能，并且可监视系统过热事
件。
•
可通过外部电阻在 −40°C 至 +150°C 温度范围内设
置跳变温度，
精度为 ±1.7°C 或 ±2.3°C
•
•
•
•
电阻容差不会引入误差
推挽和开漏开关输出
宽工作温度范围：−50°C 至 150°C
内置的热滞后功能 (THYST) 可防止数字输出发生振荡。
超线性模拟 VTEMP 温度传感器输出，−50°C 至
+150°C 温度范围内的精度为
±0.8°C 或 ±1.3°C
TOVER 和 TOVER 数字输出将在芯片温度超过 TTRIP 时置
为有效，在芯片温度低于 TTRIP 与 THYST 的差值时置为
无效。
•
•
•
•
具有短路保护的模拟和数字输出
数字输出具有锁存功能
TOVER 为高电平有效，并且采用推挽结构。 TOVER 为
TRIP-TEST 引脚支持系统内测试
低功耗特性最大程度减少自发热，使其低于 0.02°C
低电平有效，并且采用开漏结构。 将 TOVER 与 TRIP-
TEST 相连，可在输出发生跳变后将其锁存。 将
TRIP-TEST 强制为低电平可将输出清零。 将 TRIP-
TEST 驱动为高电平会将数字输出置为有效。 处理器
可检查 TOVER 或 TOVER 的状态，从而确认它们是否已
切换至激活状态。 这样一来，便可以在系统装配后现
场验证比较器和输出电路的功能。 当 TRIP-TEST 为
高电平时，VTEMP 引脚为跳变基准电压。 系统随后可
使用该电压计算 LM57
2 应用范围
•
•
•
•
•
•
工厂自动化
工业用
汽车用
井下设备
航空电子设备
电信基础设施
器件信息 (1) (2)
器件型号
LM57BISD
LM57FPW
封装
WSON (8)
TSSOP (8)
封装尺寸（标称值）
2.50mm × 2.50mm
3.00mm × 6.40mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
(2) 关于器件比较，请参见 Device Comparison Table 。
LM57 过热报警
温度传递函数
V
DD
Supply
(+2.4V to +5.5V)
3,500
J2 (-5.166mV/°C)
J3 (-7.752mV/°C)
J4 (-10.339mV/°C)
J5 (-12.924mV/°C)
3,000
2,500
2,000
1,500
1,000
500
V
DD
Analog
V
TEMP
ADC Input
LM57
Microcontroller
SENSE1
T
OVER
SENSE2
Digital In
T
OVER
TRIP TEST
GND
Digital Out
0
-50
-25
0
25
50
75
100
125
150
TEMPERTURE (C)
C101
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNIS152
LM57
ZHCSDV6E –MAY 2009–REVISED JULY 2015
www.ti.com.cn
目录
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 23
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application .................................................. 26
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
9
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 29
11.3 Temperature Considerations................................. 30
12 器件和文档支持 ..................................................... 31
12.1 文档支持 ............................................................... 31
12.2 社区资源................................................................ 31
12.3 商标....................................................................... 31
12.4 静电放电警告......................................................... 31
12.5 Glossary................................................................ 31
13 机械、封装和可订购信息....................................... 31
7.5 Electrical Characteristics - Accuracy Characteristics –
Trip Point Accuracy.................................................... 7
7.6 Electrical Characteristics - Accuracy Characteristics –
VTEMP Analog Temperature Sensor Output
Accuracy .................................................................... 7
7.7 Electrical Characteristics........................................... 8
7.8 Switching Characteristics.......................................... 9
7.9 Typical Characteristics ........................................... 10
Detailed Description ............................................ 12
8
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2013) to Revision E
Page
•
•
已添加引脚配置和功能部分，ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，
布局部分，器件和文档支持部分以及机械、封装和可订购信息部分........................................................................................ 1
已在整篇数据表中添加 TSSOP 封装选项 ............................................................................................................................... 1
Changes from Revision C (February 2010) to Revision D
Page
•
已更改 国家数据表的布局以符合 TI 格式................................................................................................................................ 1
2
Copyright © 2009–2015, Texas Instruments Incorporated
LM57
www.ti.com.cn
ZHCSDV6E –MAY 2009–REVISED JULY 2015
5 Device Comparison Table
VTEMP
ACCURACY
TRIP POINT
HYSTERESIS
ACCURACY
ORDER NUMBER
PACKAGE
GRADE (TEMP RANGE)
WSON/SD/NGR Commercial (-50°C to
LM57BISD-5, LM57BISDX-5
LM57BISD-10, LM57BISDX-10
LM57CISD-5, LM57CISD-5
LM57CISD-10, LM57CISDX-10
LM57FPW, LM57FPWR
LM57TPW, LM57TPWR
±0.8°C
±0.8°C
±1.3°C
±1.3°C
±1.3°C
±1.3°C
±1.5°C
±1.5°C
±2.3°C
±2.3°C
±2.3°C
±2.3°C
5°C
/DFN (8)
WSON/SD/NGR Commercial (-50°C to
/DFN (8) 150°C)
WSON/SD/NGR Commercial (-50°C to
/DFN (8) 150°C)
WSON/SD/NGR Commercial (-50°C to
150°C)
10°C
5°C
10°C
5°C
/DFN (8)
150°C)
Commercial (-50°C to
150°C)
PW/TSSOP (8)
Commercial (-50°C to
150°C)
PW/TSSOP (8)
10°C
Automotive Grade 0
PW/TSSOP (8) Extended (-50°C to
160°C)
(1)
(1)
LM57FSPWQ1, LM57FSPWRQ1
LM57TSPWQ1, LM57TSPWRQ1
±1.3°C
±1.3°C
±2.3°C
±2.3°C
5°C
Automotive Grade 0
PW/TSSOP (8) Extended (-50°C to
160°C)
10°C
Automotive Grade 0
PW/TSSOP (8)
(1)
(1)
(1)
(1)
LM57FEPWQ1, LM57FEPWRQ1
LM57TEPWQ1, LM57TEPWRQ1
LM57FQPWQ1, LM57FQPWRQ1
LM57TQPWQ1, LM57TQPWRQ1
±1.3°C
±1.3°C
±1.3°C
±1.3°C
±2.3°C
±2.3°C
±2.3°C
±2.3°C
5°C
Standard (-50°C to 150°C)
Automotive Grade 0
PW/TSSOP (8)
10°C
5°C
Standard (-50°C to 150°C)
Automotive Grade 1
PW/TSSOP (8)
Standard (-50°C to 125°C)
Automotive Grade 1
PW/TSSOP (8)
10°C
Standard (-50°C to 125°C)
(1) For Automotive grade device complete datasheet see LM57-Q1.
Copyright © 2009–2015, Texas Instruments Incorporated
3
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ZHCSDV6E –MAY 2009–REVISED JULY 2015
www.ti.com.cn
6 Pin Configuration and Functions
TSSOP/PW and WSON/SD/NGR/DFN Packages
8-Pin
Top View
GND
1
2
3
4
8
7
6
5
V
TEMP
SENSE1
SENSE2
T
T
OVER
OVER
LM57
TRIP TEST
V
DD
Pin Functions
PIN
TYPE
EQUIVALENT CIRCUIT
DESCRIPTION
NAME
GND
NO.
1
Ground
—
Power supply ground
VDD
Trip-point resistor sense. One of two sense pins which selects the
temperature at which TOVER and TOVER will assert.
SENSE1
2
—
GND
GND
VDD
Trip-point resistor sense. One of two sense pins which selects the
temperature at which TOVER and TOVER will assert.
SENSE2
3
4
—
GND
GND
VDD
Power
Supply voltage
V
DD
TRIP TEST pin. Active High input.
If TRIP TEST = 0 (default), then the VTEMP output has the analog
temperature sensor output voltage.
If TRIP TEST = 1, then TOVER and TOVER outputs are asserted and VTEMP
VTRIP, the temperature trip voltage.
TRIP
TEST
Digital
Input
5
6
=
1 PA
Tie this pin to ground if not used.
GND
Overtemperature switch output
Active low, open-drain (see LM57 VTEMP Voltage-to-Temperature Equations
regarding required pullup resistor.)
Asserted when the measured temperature exceeds the Trip Point
Temperature or if TRIP TEST = 1
This pin may be left open if not used.
Digital
Output
TOVER
GND
V
DD
Overtemperature switch output
Active high, push-pull
Asserted when the measured temperature exceeds the trip point
temperature or if TRIP TEST = 1
Digital
Output
TOVER
7
This pin may be left open if not used.
GND
4
Copyright © 2009–2015, Texas Instruments Incorporated
LM57
www.ti.com.cn
ZHCSDV6E –MAY 2009–REVISED JULY 2015
Pin Functions (continued)
PIN
TYPE
EQUIVALENT CIRCUIT
DESCRIPTION
NAME
NO.
V
DD
V
SENSE
VTEMP analog voltage output
Analog
Output
If TRIP TEST = 0, then VTEMP = VTS, temperature sensor output voltage
If TRIP TEST = 1, then VTEMP = VTRIP, temperature trip voltage
This pin may be left open if not used.
VTEMP
8
GND
Thermal
Pad
(WSON
package
only)
—
—
—
Connected to GND
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
−0.3
−0.3
−0.3
MAX
UNIT
V
Supply voltage
6
Voltage at TOVER
6
V
Voltage at TOVER , VTEMP, TRIP-TEST, SENSE1, and SENSE2
Current at any pin
(VDD + 0.3 V)
V
5
mA
°C
Storage temperature
−65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.
7.2 ESD Ratings
VALUE
UNIT
LM57BISD and LM57CISD in WSON package
Human body model (HBM)
±5500
±1250
±450
Electrostatic discharge
V(ESD)
Charged-device model (CDM)
Machine Model (MM)
V
(1)
LM57FPW and LM57TPW in TSSOP package
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
±2000
±750
V(ESD)
Electrostatic discharge
V
(3)
(1) The Human Body Model (HBM) is a 100-pF capacitor charged to the specified voltage then discharged through a 1.5-kΩ resistor into
each pin. The Machine Model (MM) is a 200 pF capacitor charged to the specified voltage then discharged directly into each pin. The
Charged Device Model (CDM) is a specified circuit characterizing an ESD event that occurs when a device acquires charge through
some triboelectric (frictional) or electrostatic induction processes and then abruptly touches a grounded object or surface.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN NOM MAX UNIT
Supply voltage
2.4
5.5
V
Free air temperature range (TMIN ≤ TA ≤ TMAX
)
−50
150
°C
Copyright © 2009–2015, Texas Instruments Incorporated
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LM57
ZHCSDV6E –MAY 2009–REVISED JULY 2015
www.ti.com.cn
7.4 Thermal Information
LM57
NGR
(WSON/SD)
PW (TSSOP)
(1)
THERMAL METRIC
UNIT
8 PINS
71.3
82.8
43.4
2.2
8 PINS
183
66
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
111
8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
43.7
11.9
110
—
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
Copyright © 2009–2015, Texas Instruments Incorporated
LM57
www.ti.com.cn
ZHCSDV6E –MAY 2009–REVISED JULY 2015
7.5 Electrical Characteristics - Accuracy Characteristics – Trip Point Accuracy
LM57B
LM57C, LM57F or LM57T
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
J2 TA = −41°C to
52°C
VDD = 2.4 V to 5.5 V
VDD = 2.4 V to 5.5 V
VDD = 2.4 V to 5.5 V
±1.5
±2.3
°C
°C
°C
J3 TA
=
52°C to
±1.5
±1.5
±2.3
±2.3
Trip Point
Accuracy
(Includes 1% set-
97°C
TA = 97°C to
119°C
J4
J5
resistor tolerance)
(1)
TA = 119°C to
free air
temperature
max
VDD = 2.4 V to 5.5 V
±1.5
±2.3
°C
(1) Accuracy is defined as the error between the measured and reference output voltages, tabulated in the Conversion Table at the
specified conditions of supply gain setting, voltage, and temperature (expressed in °C). Accuracy limits include line regulation within the
specified conditions. Accuracy limits do not include load regulation; they assume no DC load.
7.6 Electrical Characteristics - Accuracy Characteristics – VTEMP Analog Temperature Sensor
Output Accuracy
These limits do not include DC load regulation. These stated accuracy limits are with reference to the values in Table 1.
LM57B
TYP
LM57C, LM57F or LM57T
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
TYP
MAX
TA = −50°C
to free air
temperature
max
J2
J3
VDD = 2.4 V to 5.5 V
±0.95
±1.3
°C
TA = −50°C
to free air
temperature
max
VDD = 2.4 V to 5.5 V
VDD = 2.4 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 3.1 V to 5.5 V
VDD = 2.4 V to 5.5 V
VDD = 2.9 V to 5.5 V
VDD = 3.2 V to 5.5 V
VDD = 4 V to 5.5 V
±0.8
±0.7
±0.7
±0.8
±0.7
±0.7
±0.7
±0.8
±1.3
±1.3
±1.3
±1.3
±1.3
±1.3
±1.3
±1.3
°C
°C
TA
= 20°C
to 50°C
VTEMP Accuracy
(These stated
accuracy limits are
with reference to
the values in
TA 0°C to
=
free air
temperature
max
J4
TA = −50°C
to 0°C
Table 1, LM57
VTEMP
TA
= 60°C
Temperature-to-
(1)
to free air
temperature
max
Voltage.)
TA
= 20°C
to 50°C
J5
°C
TA 0°C to
=
free air
temperature
max
TA = −50°C
to 0°C
(1) Accuracy is defined as the error between the measured and reference output voltages, tabulated in the Conversion Table at the
specified conditions of supply gain setting, voltage, and temperature (expressed in °C). Accuracy limits include line regulation within the
specified conditions. Accuracy limits do not include load regulation; they assume no DC load.
Copyright © 2009–2015, Texas Instruments Incorporated
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LM57
ZHCSDV6E –MAY 2009–REVISED JULY 2015
www.ti.com.cn
7.7 Electrical Characteristics
Unless otherwise noted, these specifications apply for VDD = 2.4 to 5.5 V. Limits apply over free air temperature range.
(1)
(2)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE SENSOR
J2: −50°C to 52°C
−5.166
−7.752
−10.339
−12.924
0.18
J3: 52°C to 97°C
J4: 97°C to 119°C
J5: 119°C to 150°C
VTEMP sensor gain
mV/°C
mV
μV/V
dB
Line regulation DC: supply-to- VDD = 2.4 V to 5.5 V
58
(3)
VTEMP
Temp = 90°C
−84
Source ≤ 240 µA, (VDD – VTEMP) ≥ 200 mV; TA
−50°C to 150°C
=
−1
mV
Load regulation: VTEMP output
Sink ≤ 300 µA, VTEMP ≥ 360 mV; TA = −50°C to
150°C
(4)
1
Source or sink = 100 µA; TA = −50°C to 150°C
1
Ω
Maximum Load capacitance:
VTEMP output
No output series resistor required; (See VTEMP
Capacitive Loads )
1100
28
pF
µA
(5)
IS
Supply current: quiescent
24
TRIP-TEST INPUT
VIH
VIL
IIH
Logic 1 threshold voltage
VDD – 0.5
V
V
Logic 0 threshold voltage
Logic 1 input current
0.5
3
1.4
µA
Logic 0 input leakage current
IIL
TA = −50°C to 150°C
0.001
1
µA
(6)
TOVER (PUSH-PULL, ACTIVE-HIGH) OUTPUT
Source ≤ 600 µA
VDD – 0.2
Logic 1 push-pull output
voltage
VOH
V
V
Source ≤ 1.2 mA
Sink ≤ 600 µA
Sink ≤ 1.2 mA
VDD – 0.45
0.2
VOL
Logic 0 output voltage
0.45
TOVER (OPEN-DRAIN, ACTIVE-LOW) OUTPUT
Sink ≤ 600 µA
Sink ≤1.2 mA
0.2
VOL
IOH
Logic 0 output voltage
V
0.45
Logic 1 output leakage current
Temperature = 30°C;
0.001
1
µA
(6)
(1) Limits are specified to TI's average outgoing quality level (AOQL).
(2) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(3) Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest
supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in VTEMP Voltage Shift .
(4) Source currents are flowing out of the LM57. Sink currents are flowing into the LM57. Load Regulation is calculated by measuring VTEMP
at 0 μA and subtracting the value with the conditions specified.
(5) Supply current refers to the quiescent current of the LM57 only and does not include any load current
(6) This current is leakage current only and is therefore highest at high temperatures. Prototype test indicate that the leakage is well below
1 μA over the full temperature range. This 1 μA specification reflects the limitations of measuring leakage at room temperature. For this
reason only, the leakage current is not specified at a lower value.
8
Copyright © 2009–2015, Texas Instruments Incorporated
LM57
www.ti.com.cn
ZHCSDV6E –MAY 2009–REVISED JULY 2015
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for VDD = 2.4 to 5.5 V. Limits apply over free air temperature range.
(1)
(2)
(1)
PARAMETER
HYSTERESIS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5°C hysteresis option (for all LM57F or LM57-5)
10°C hysteresis option (for all LM57T or LM57-10)
4.7
9.6
5
5.4
°C
°C
THYST Hysteresis temperature
10
10.6
7.8 Switching Characteristics
Unless otherwise noted, these specifications apply for VDD = 2.4 to 5.5 V over the free air temperature range.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Maximum time from power on
to digital output enabled
tEN
1.5
2.9
ms
Maximum time from power on
to analog temperature
(VTEMP) valid
tVTEMP
1.5
2.9
ms
V
DD
1.3V
t
EN
T
Enabled
Enabled
OVER
T
OVER
Figure 1. Definition of tEN
V
DD
t
VTEMP
Valid
V
TEMP
Figure 2. Definition of tVTEMP
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7.9 Typical Characteristics
30
29
28
27
26
25
24
23
22
21
20
30
29
28
27
26
T = 150°C
V
V
= 5.5V
= 2.4V
T = 30°C
V
= 3.5V
DD
DD
25
24
23
22
21
20
T = -40°C
DD
-50 -30 -10 10 30 50 70 90 110 130 150
2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6
TEMPERATURE (°C)
V
(V)
DD
Figure 4. Supply Current vs Temperature
Figure 3. Supply Current vs Supply Voltage
3.0
2.8
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
-2.2
-2.4
-2.6
-2.8
-3.0
V
= 2.4V
= 2.7V
DD
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
V
DD
Overhead =
400 mV
Overhead =
100 mV
V
= 3.3V
= 5.0V
DD
DD
V
Overhead =
200 mV
0.4
0.2
0.0
1000 12001400 1600
0
200 400 600 800
0
100 200 300 400 500 600 700
LOAD (PA)
LOAD (PA)
Figure 6. Load Regulation: Change In VTEMP vs Sink Current
Figure 5. Load Regulation: Change In VTEMP vs Source
Current Overhead Is Vdd-Vtemp
950
949
948
10.2
HYST J5
10.1
10.0
HYST J4
HYST J3
HYST J2
9.9
|
|
5.2
5.1
5.0
4.9
947
946
HYST J3
HYST J4
HYST J5
HYST J2
945
2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6
VDD
2.4 2.8 3.2 3.6
4
4.4 4.8 5.2 5.6
(V)
V
DD
Figure 7. Line Regulation: VTEMP vs Supply Voltage
Figure 8. Line Regulation: Hysteresis vs Supply Voltage
30°C
10
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ZHCSDV6E –MAY 2009–REVISED JULY 2015
Typical Characteristics (continued)
3
2
1
10.2
10.1
10.0
9.9
HYST J5
HYST J4
HYST J3
HYST J2
Tover
0
|
|
|
|
3
5.2
5.1
5.0
4.9
HYST J5
HYST J3
2
Vtemp
1
HYST J4
HYST J2
0
-1
0
1
2
3
4
5
6
7
8
9
-50 -30 -10 10 30 50 70 90 110 130 150
TEMPERATURE (oC)
TIME (ms)
Figure 9. Start-Up Response
Figure 10. Hysteresis vs Temperature
2.0
MAX LImit
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
MIN Limit
-2.0
0
25
50
75
100
125
150
±50
±25
DUT Temperature (C)
C102
Conditions: J2, VDD=5V
Figure 11. J2 Accuracy Specification Over Temperature
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8 Detailed Description
8.1 Overview
The LM57 is a precision, dual-output, temperature switch with analog temperature sensor output. The trip
temperature (TTRIP) is selected from 256 possible values by using two external 1% resistors. The VTEMP class AB
analog output provides a voltage that is proportional to temperature. The LM57 includes an internal reference
DAC, analog temperature sensor and analog comparator. The reference DAC is connected to one of the
comparator inputs. The reference DAC output voltage (VTRIP) is controlled by the value of resistance applied to
the SENSE pins. The resistance value sets one of 16 "logic" levels at the SENSE pins. These "logic" levels are
then decoded and applied to the DAC input, thus the actual resistance tolerance does not directly affect the
threshold level accuracy. The result of the reference DAC voltage and the temperature sensor output comparison
is provided on two output pins TOVER and TOVER
.
The VTEMP output has a programmable gain. The output gain has 4 possible settings as described in Figure 12.
The gain setting is dependent on the trip point selected by resistance applied to the SENSE pins.
Built-in temperature hysteresis (THYST) prevents the digital outputs from oscillating. The TOVER and TOVER will
activate when the die temperature exceeds TTRIP and will release when the temperature falls below a
temperature equal to TTRIP minus THYST. TOVER is active-high with a push-pull structure. TOVER , is active-low with
an open-drain structure. There are two different hysteresis options available that are factory preset. The preset
hysteresis can be selected by purchasing the proper order number as described in Device Comparison Table .
Driving the TRIP-TEST high will activate the digital outputs. A processor can check the logic level of the TOVER or
TOVER , confirming that they changed to their active state. This allows for system production testing verification
that the comparator and output circuitry are functional after system assembly. When the TRIP-TEST pin is high,
the trip-level reference voltage appears at the VTEMP pin. Tying TOVER to TRIP-TEST will latch the output after it
trips. It can be cleared by forcing TRIP-TEST low or powering off the LM57.
8.2 Functional Block Diagram
V
DD
= 2.4V to 5.5V
TRIP TEST
SENSE1
LM57
SENSE2
V
TRIP
T
OVER
DAC
GAIN
+
-
TEMP SENSOR
(negative temp
coefficient)
V
DD
TRIP
TEST = 1
TRIP
TEST = 0
T
OVER
V
TEMP
GND
12
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8.3 Feature Description
8.3.1 LM57 VTEMP Temperature-to-Voltage Transfer Function
The value of the RSENSE resistors select a trip point and a corresponding VTEMP gain (J2, J3, J4, or J5).The trip
point range associated with a given gain is shown in bold green in Table 1. The VTEMP gain is selected by the
RSENSE resistors. VTEMP is valid over the entire temperature range. The VTEMP gain is selected by the RSENSE
resistors. VTEMP is valid over the entire temperature range.
3,500
J2 (-5.166mV/°C)
J3 (-7.752mV/°C)
J4 (-10.339mV/°C)
J5 (-12.924mV/°C)
3,000
2,500
2,000
1,500
1,000
500
0
-50
-25
0
25
50
75
100
125
150
TEMPERTURE (C)
C101
Figure 12. Temperature Transfer Characteristics
(1)
Table 1. LM57 VTEMP Temperature to Voltage
VTEMP VOLTAGE (mV)
Temperature (°C)
J2 (-5.166 mV/°C)
1352.56
1347.60
1342.64
1337.67
1332.70
1327.73
1322.76
1317.78
1312.81
1307.82
1302.84
1297.86
1292.87
1287.88
1282.88
1277.89
1272.89
J3 (–7.752 mV/°C)
2028.80
2021.35
2013.90
2006.44
1998.98
1991.52
1984.05
1976.58
1969.11
1961.63
1954.15
1946.66
1939.17
1931.68
1924.18
1916.68
1909.17
J4 (–10.339 mV/°C)
2705.20
2695.26
2685.32
2675.38
2665.43
2655.47
2645.51
2635.54
2625.57
2615.60
2605.62
2595.63
2585.64
2575.64
2565.64
2555.63
2545.62
J5 (–12.924 mV/°C)
3381.40
3368.98
3356.55
3344.12
3331.68
3319.23
3306.78
3294.32
3281.85
3269.38
3256.90
3244.41
3231.92
3219.42
3206.92
3194.41
3181.89
–50
–49
–48
–47
–46
–45
–44
–43
–42
–41
–40
–39
–38
–37
–36
–35
–34
(1) The RSENSE resistors select a trip point and a corresponding VTEMP gain (J2, J3, J4, or J5). The trip point range associated with a given
gain is shown in bold green on this table. VTEMP is valid over the entire temperature range.
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Feature Description (continued)
(1)
Table 1. LM57 VTEMP Temperature to Voltage
(continued)
VTEMP VOLTAGE (mV)
J3 (–7.752 mV/°C)
Temperature (°C)
J2 (-5.166 mV/°C)
1267.88
J4 (–10.339 mV/°C)
2535.60
2525.58
2515.56
2505.52
2495.49
2485.44
2475.40
2465.34
2455.29
2445.23
2435.16
2425.09
2415.01
2404.93
2394.84
2384.74
2374.65
2364.54
2354.44
2344.32
2334.20
2324.08
2313.95
2303.82
2293.68
2283.54
2273.39
2263.24
2253.08
2242.91
2232.74
2222.57
2212.39
2202.21
2192.02
2181.82
2171.62
2161.42
2151.21
2141.00
2130.78
2120.55
2110.32
2100.09
2089.85
J5 (–12.924 mV/°C)
–33
–32
–31
–30
–29
–28
–27
–26
–25
–24
–23
–22
–21
–20
–19
–18
–17
–16
–15
–14
–13
–12
–11
–10
–9
1901.66
1894.15
1886.63
1879.11
1871.59
1864.06
1856.53
1848.99
1841.45
1833.91
1826.36
1818.81
1811.26
1803.70
1796.13
1788.57
1781.00
1773.42
1765.85
1758.26
1750.68
1743.09
1735.50
1727.90
1720.30
1712.69
1705.09
1697.47
1689.86
1682.24
1674.61
1666.99
1659.35
1651.72
1644.08
1636.44
1628.79
1621.14
1613.48
1605.83
1598.16
1590.50
1582.83
1575.15
1567.48
3169.37
3156.84
3144.30
3131.76
3119.21
3106.66
3094.10
3081.53
3068.96
3056.38
3043.79
3031.20
3018.60
3006.00
2993.38
2980.77
2968.14
2955.51
2942.87
2930.23
2917.58
2904.93
2892.26
2879.60
2866.92
2854.24
2841.55
2828.86
2816.16
2803.45
2790.74
2778.02
2765.30
2752.57
2739.83
2727.08
2714.33
2701.58
2688.82
2676.05
2663.27
2650.49
2637.70
2624.91
2612.10
1262.88
1257.87
1252.86
1247.85
1242.84
1237.82
1232.80
1227.78
1222.75
1217.73
1212.70
1207.67
1202.63
1197.59
1192.55
1187.51
1182.46
1177.42
1172.37
1167.31
1162.26
1157.20
1152.14
1147.07
1142.01
1136.94
1131.87
1126.79
1121.72
1116.64
1111.56
1106.47
1101.39
1096.30
1091.20
1086.11
1081.01
1075.91
1070.81
1065.71
1060.60
1055.49
1050.38
1045.26
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
14
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Feature Description (continued)
(1)
Table 1. LM57 VTEMP Temperature to Voltage
(continued)
VTEMP VOLTAGE (mV)
J3 (–7.752 mV/°C) J4 (–10.339 mV/°C)
Temperature (°C)
J2 (-5.166 mV/°C)
1040.14
J5 (–12.924 mV/°C)
2599.30
2586.48
2573.66
2560.84
2548.01
2535.17
2522.32
2509.47
2496.61
2483.75
2470.88
2458.00
2445.12
2432.23
2419.34
2406.43
2393.53
2380.61
2367.69
2354.76
2341.83
2328.89
2315.94
2302.99
2290.03
2277.07
2264.10
2251.12
2238.14
2225.15
2212.15
2199.15
2186.14
2173.12
2160.10
2147.07
2134.04
2121.00
2107.95
2094.90
2081.84
2068.77
2055.70
2042.62
2029.54
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1559.80
1552.11
1544.42
1536.73
1529.03
1521.33
1513.63
1505.92
1498.21
1490.49
1482.77
1475.05
1467.32
1459.59
1451.86
1444.12
1436.38
1428.63
1420.88
1413.13
1405.37
1397.61
1389.84
1382.07
1374.30
1366.52
1358.74
1350.96
1343.17
1335.38
1327.58
1319.78
1311.98
1304.17
1296.36
1288.54
1280.72
1272.90
1265.07
1257.24
1249.41
1241.57
1233.73
1225.88
1218.03
2079.60
2069.35
2059.10
2048.84
2038.57
2028.30
2018.03
2007.75
1997.46
1987.17
1976.88
1966.58
1956.27
1945.96
1935.64
1925.32
1915.00
1904.67
1894.33
1883.99
1873.64
1863.29
1852.94
1842.57
1832.21
1821.84
1811.46
1801.08
1790.69
1780.30
1769.90
1759.50
1749.09
1738.68
1728.26
1717.84
1707.41
1696.98
1686.54
1676.10
1665.65
1655.20
1644.74
1634.28
1623.81
1035.02
1029.90
1024.77
1019.65
1014.51
1009.38
1004.25
999.11
993.97
988.82
983.68
978.53
973.38
968.22
963.07
957.91
952.74
947.58
942.41
937.24
932.07
926.90
921.72
916.54
911.36
906.17
900.98
895.79
890.60
885.41
880.21
875.01
869.81
864.60
859.39
854.18
848.97
843.75
838.53
833.31
828.09
822.86
817.63
812.40
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Feature Description (continued)
(1)
Table 1. LM57 VTEMP Temperature to Voltage
(continued)
VTEMP VOLTAGE (mV)
J3 (–7.752 mV/°C)
Temperature (°C)
J2 (-5.166 mV/°C)
807.17
J4 (–10.339 mV/°C)
1613.34
1602.86
1592.38
1581.89
1571.40
1560.90
1550.40
1539.89
1529.37
1518.86
1508.33
1497.80
1487.27
1476.73
1466.19
1455.64
1445.08
1434.53
1423.96
1413.39
1402.82
1392.24
1381.65
1371.07
1360.47
1349.87
1339.27
1328.66
1318.04
1307.42
1296.80
1286.17
1275.53
1264.89
1254.25
1243.60
1232.94
1222.28
1211.61
1200.94
1190.27
1179.59
1168.90
1158.21
1147.52
J5 (–12.924 mV/°C)
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
1210.18
1202.32
1194.46
1186.60
1178.73
1170.86
1162.98
1155.10
1147.22
1139.33
1131.44
1123.54
1115.64
1107.74
1099.83
1091.92
1084.01
1076.09
1068.17
1060.24
1052.31
1044.38
1036.44
1028.50
1020.55
1012.60
1004.65
996.69
2016.44
2003.35
1990.24
1977.13
1964.02
1950.89
1937.76
1924.63
1911.49
1898.34
1885.19
1872.02
1858.86
1845.68
1832.50
1819.32
1806.13
1792.93
1779.72
1766.51
1753.30
1740.07
1726.84
1713.61
1700.36
1687.11
1673.86
1660.60
1647.33
1634.05
1620.77
1607.49
1594.19
1580.89
1567.59
1554.28
1540.96
1527.63
1514.30
1500.97
1487.62
1474.27
1460.92
1447.55
1434.18
801.93
796.69
791.45
786.20
780.96
775.71
770.46
765.20
759.94
754.68
749.42
744.16
738.89
733.62
728.35
723.07
717.79
712.51
707.23
701.94
696.65
691.36
686.07
680.77
675.48
670.17
664.87
659.56
654.25
648.94
643.63
638.31
632.99
627.67
622.35
617.02
611.69
606.36
601.02
595.69
590.34
585.00
579.66
574.31
988.73
980.77
972.80
964.83
956.85
948.87
940.89
932.90
924.91
916.92
908.92
900.91
892.91
884.90
876.88
868.87
860.84
16
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Feature Description (continued)
(1)
Table 1. LM57 VTEMP Temperature to Voltage
(continued)
VTEMP VOLTAGE (mV)
J3 (–7.752 mV/°C) J4 (–10.339 mV/°C)
Temperature (°C)
J2 (-5.166 mV/°C)
568.96
J5 (–12.924 mV/°C)
1420.81
1407.43
1394.04
1380.65
1367.24
1353.84
1340.42
1327.01
1313.58
1300.15
1286.71
1273.26
1259.81
1246.36
1232.89
1219.42
1205.95
1192.46
1178.98
1165.48
1151.98
1138.47
1124.96
1111.44
1097.91
1084.38
1070.84
1057.29
1043.74
1030.18
1016.62
1003.05
989.47
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
852.82
844.79
836.76
828.72
820.68
812.63
804.59
796.53
788.48
780.42
772.35
764.29
756.21
748.14
740.06
731.98
723.89
715.80
707.70
699.61
691.50
683.40
675.29
667.18
659.06
650.94
642.81
634.68
626.55
618.41
610.27
602.13
593.98
585.83
577.67
569.51
561.35
553.18
545.01
536.84
528.66
520.48
512.29
504.10
495.91
1136.81
1126.11
1115.40
1104.68
1093.96
1083.23
1072.50
1061.77
1051.02
1040.28
1029.53
1018.77
1008.01
997.24
986.47
975.69
964.91
954.12
943.33
932.53
921.73
910.92
900.11
889.29
878.47
867.64
856.81
845.97
835.13
824.28
813.43
802.57
791.71
780.84
769.97
759.09
748.20
737.32
726.42
715.52
704.62
693.71
682.80
671.88
660.95
563.61
558.25
552.89
547.53
542.17
536.80
531.43
526.06
520.69
515.31
509.93
504.55
499.17
493.78
488.39
483.00
477.61
472.21
466.81
461.41
456.00
450.60
445.19
439.78
434.36
428.94
423.52
418.10
412.67
407.25
401.82
396.38
390.95
385.51
380.07
374.63
369.18
363.73
358.28
352.83
347.37
341.91
336.45
330.99
975.89
962.30
948.70
935.10
921.49
907.87
894.25
880.62
866.99
853.35
839.70
826.05
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Feature Description (continued)
(1)
Table 1. LM57 VTEMP Temperature to Voltage
(continued)
VTEMP VOLTAGE (mV)
Temperature (°C)
J2 (-5.166 mV/°C)
325.52
J3 (–7.752 mV/°C)
J4 (–10.339 mV/°C)
650.03
J5 (–12.924 mV/°C)
147
148
149
150
487.71
479.51
471.30
463.09
812.39
798.73
785.05
771.38
320.05
314.58
309.10
639.09
628.15
617.21
18
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8.3.1.1 LM57 VTEMP Voltage-to-Temperature Equations
VTEMP= a (T-30)2+ b (T-30) + c
where
•
VTEMP is in mV and T is in °C
(1)
(2)
ꢁ b ꢁ b2 ꢁ 4a(c ꢁVTEMP
)
T
ꢀ 30qC
2a
where
•
T is in °C and VTEMP is in mV
Table 2. LM57 VTEMP Voltage-to-Temperature Equations Coefficients
Trip-Point
Region
LM57 Trip Point Range
a
b
c
J2
J3
J4
J5
−41°C to 52°C
52°C to 97°C
– 0.00129
– 0.00191
– 0.00253
– 0.00316
− 5.166
− 7.752
947.6
1420.9
1894.3
2367.7
97°C to 119°C
119°C to 150°C
− 10.339
− 12.924
8.3.2 RSENSE
The LM57 uses the voltage at the two SENSE pins to set the trip point for the temperature switch. It is possible
to drive the two SENSE pins with a voltage equal to the value generated by the resistor and the internal current-
source and have the same switch point. Thus one can use an external DAC to drive each SENSE pin, allowing
for the temperature trip point to be set dynamically by the system processor. Table 3 shows the RSENSE value
and its corresponding generated SENSE pin voltage (the center value).
Table 3. RSENSE Values (kΩ) vs SENSE Pin Voltage (mV)
SENSE Pin Voltage (mV)
RSENSE (kΩ)
Center Value
976
825
698
590
499
412
340
280
226
178
140
105
75
1875
1585
1341
1134
959
792
653
538
434
342
269
202
146
87
46.4
22.6
0.01
43
0
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8.3.3 Resistor Selection
Table 4. Trip Point (°C) vs Sense Resistor (RSENSE) Values (Ω)
RSENSE2
(1)
(1)
(1)
(1)
J2
825 kΩ
J3
J4
J5
976 kΩ
–40.68
–39.13
–37.57
–36.03
–34.49
–32.95
–31.41
–29.88
–28.34
–26.83
–25.32
–23.80
–22.29
–20.77
–19.26
–17.75
698 kΩ
7.33
590 kΩ
30.38
31.81
33.24
34.67
36.10
37.53
38.95
40.38
41.81
43.23
44.65
46.07
47.50
48.92
50.33
51.75
499 kΩ
52.73
53.68
54.62
55.56
56.50
57.44
58.39
59.33
60.27
61.21
62.15
63.08
64.02
64.96
65.90
66.84
412 kΩ
67.77
68.71
69.65
70.59
71.52
72.46
73.40
74.33
75.27
76.20
77.14
78.07
79.01
79.94
80.87
81.81
340 kΩ
82.74
83.67
84.60
85.53
86.46
87.40
88.33
89.26
90.19
91.12
92.05
92.99
93.92
94.84
95.77
96.70
280 kΩ
97.47
226 kΩ
108.61
109.30
110.00
110.70
111.39
112.09
112.79
113.48
114.18
114.87
115.57
116.26
116.95
117.65
118.34
119.04
178 kΩ
119.62
120.18
120.73
121.28
121.84
122.39
122.94
123.50
124.05
124.60
125.15
125.71
126.26
126.81
127.36
127.91
140 kΩ
128.46
129.01
129.56
130.12
130.67
131.22
131.77
132.32
132.87
133.43
133.98
134.53
135.08
135.63
136.18
136.73
105 kΩ
137.28
137.83
138.38
138.93
139.49
140.04
140.59
141.14
141.69
142.24
142.79
143.34
143.89
144.44
144.99
145.54
75 kΩ
146.08
146.62
147.16
147.71
148.25
148.80
149.34
149.88
150.43
976 kΩ
825 kΩ
698 kΩ
590 kΩ
499 kΩ
412 kΩ
340 kΩ
280 kΩ
226 kΩ
178 kΩ
140 kΩ
105 kΩ
75 kΩ
–16.26
–14.76
–13.27
–11.78
–10.29
–8.81
–7.32
–5.83
–4.35
–2.88
–1.42
0.04
8.79
98.17
10.24
11.70
13.15
14.60
16.05
17.49
18.93
20.36
21.79
23.22
24.65
26.08
27.51
28.94
98.86
99.56
100.25
100.95
101.64
102.34
103.03
103.73
104.42
105.11
105.81
106.50
107.19
107.89
RSENSE1
1.50
46.4 kΩ
22.6 kΩ
0.01 kΩ
2.96
4.42
5.88
(1) There are four gains corresponding to each of the four Temperature Trip Point Ranges:
J2 (-5.166 mV/°C) is the temperature sensor output gain used for Temperature Trip Points −40.68°C to 51.8°C.
J3 (-7.752 mV/°C) is for Trip Points 52°C to 97°C.
J4 (-10.339 mV/°C) for 97°C to 119°C.
J5 (-12.924 mV/°C) for 119°C to 150°C.
20
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Table 5. VTEMP (mV) at the Trip Point vs Sense Resistor (RSENSE) Value (Ω)
RSENSE2
(1)
(1)
(1)
(1)
J2
825 kΩ
J3
J4
280 kΩ
J5
976 kΩ
1306.23
1298.50
1290.72
1283.03
1275.33
1267.64
1259.94
1252.25
1244.55
1236.99
1229.38
1221.76
1214.15
1206.53
1198.92
1191.30
698 kΩ
590 kΩ
945.63
938.23
930.83
923.43
916.02
908.62
901.22
893.82
886.42
879.02
871.61
864.21
856.81
849.41
842.01
834.62
499 kΩ
1243.67
1236.27
1228.88
1221.48
1214.09
1206.69
1199.30
1191.90
1184.50
1177.11
1169.71
1162.32
1154.92
1147.53
1140.13
1132.74
412 kΩ
1125.34
1117.93
1110.52
1103.10
1095.69
1088.28
1080.87
1073.45
1066.04
1058.63
1051.22
1043.80
1036.39
1028.98
1021.57
1014.15
340 kΩ
1006.75
999.34
991.92
984.51
977.09
969.66
962.22
954.78
947.35
939.91
932.48
925.04
917.61
910.17
902.74
895.30
226 kΩ
178 kΩ
1184.05
1176.57
1169.10
1161.63
1154.16
1146.68
1139.21
1131.74
1124.27
1116.79
1109.32
1101.85
1094.38
1086.90
1079.43
1072.04
140 kΩ
1064.59
1057.10
1049.62
1042.13
1034.65
1027.16
1019.67
1012.19
1004.70
997.22
105 kΩ
944.83
937.33
929.83
922.33
914.83
907.33
899.83
892.33
884.83
877.33
869.82
862.32
854.82
847.32
839.82
832.32
75 kΩ
824.96
817.53
810.09
802.66
795.22
787.78
780.35
772.91
765.48
976 kΩ
825 kΩ
698 kΩ
590 kΩ
499 kΩ
412 kΩ
340 kΩ
280 kΩ
226 kΩ
178 kΩ
140 kΩ
105 kΩ
75 kΩ
1183.77
1176.23
1168.70
1161.16
1153.62
1146.09
1138.55
1131.02
1123.48
1116.05
1108.61
1101.18
1093.74
1086.30
1078.87
1071.43
1064.00
1056.56
1049.13
1041.69
1034.26
1026.82
1019.38
1011.99
1004.62
997.26
1185.27
1177.83
1170.40
1162.96
1155.52
1148.09
1140.65
1133.22
1125.78
1118.35
1110.91
1103.48
1096.04
1088.60
1081.17
1073.73
1066.00
1058.52
1051.03
1043.55
1036.07
1028.59
1021.10
1013.62
1006.14
998.66
RSENSE1
989.89
991.17
989.73
982.53
983.69
982.25
975.16
976.21
974.76
46.4 kΩ
22.6 kΩ
0.01 kΩ
967.80
968.73
967.28
960.43
961.24
959.79
953.07
953.76
952.31
(1) There are four gains corresponding to each of the four Temperature Trip Point Ranges:
J2 (-5.166 mV/°C) is the temperature sensor output gain used for Temperature Trip Points −40.68°C to 51.8°C.
J3 (-7.752 mV/°C) is for Trip Points 52°C to 97°C.
J4 (-10.339 mV/°C) for 97°C to 119°C.
J5 (-12.924 mV/°C) for 119°C to 150°C.
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8.3.4 TOVER and TOVER Digital Outputs
The TOVER active high, push-pull output and the TOVER Active Low, Open-Drain Output both assert at the same
time whenever the Die Temperature reaches the Trip Point. They also assert simultaneously whenever the TRIP
TEST pin is set high. Both outputs de-assert when the die temperature goes below the (Temperature Trip Point)
- (Hysteresis). These two types of digital outputs enable the user the flexibility to choose the type of output that is
most suitable for his design.
Either the TOVER or the TOVER Digital Output pins can be left open if not used.
The TOVER Active Low, Open-Drain Digital Output, if used, requires a pullup resistor between this pin and VDD
.
8.3.4.1 TOVER and TOVER Noise Immunity
The LM57 has some noise immunity to a premature trigger due to noise on the power supply. With the die
temperature at 1°C below the trip point, there are no premature triggers for a square wave injected into the
power supply with a magnitude of 100 mVPP over a frequency range of 100 Hz to 2 MHz. Above the frequency a
premature trigger may occur.
With the die temperature at 2°C below the trip point, and a magnitude of 200 mVPP, there are no premature
triggers from 100 Hz to 300 kHz. Above that frequency a premature trigger may occur.
Therefore if the supply line is noisy, it is recommended that a local supply decoupling capacitor be used to
reduce that noise.
8.3.5 Trip Test Digital Input
The TRIP TEST pin provides a means to test the digital outputs by causing them to assert, regardless of
temperature.
In addition, when the TRIP TEST pin is pulled high the VTEMP pin will be at the VTRIP voltage.
8.3.6 VTEMP Analog Temperature Sensor Output
The VTEMP push-pull output provides the ability to sink and source significant current. This is beneficial when, for
example, driving dynamic loads like an input stage on an analog-to-digital converter (ADC). In these applications
the source current is required to quickly charge the input capacitor of the ADC. See the Typical Application
section for more discussion of this topic. The LM57 is ideal for this and other applications which require strong
source or sink current.
8.3.6.1 VTEMP Noise Considerations
A load capacitor on VTEMP can help to filter noise.
For noisy environments, TI recommends a 100 nF supply decoupling capacitor placed closed across VDD and
GND pins of LM57.
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8.3.6.2 VTEMP Capacitive Loads
The VTEMP Output handles capacitive loading well. In an extremely noisy environment, or when driving a switched
sampling input on an ADC, it may be necessary to add some filtering to minimize noise coupling. Without any
precautions, the VTEMP can drive a capacitive load less than or equal to 1100 pF as shown in Figure 13. For
capacitive loads greater than 1100 pF, a series resistor is required on the output, as shown in Figure 14, to
maintain stable conditions.
V
DD
V
DD
R
S
V
TEMP
V
TEMP
LM57
LM57
GND
GND
C
LOAD
d 1100 pF
C
LOAD
> 1100 pF
Figure 13. LM57 With No Isolation Resistor
Required
Figure 14. LM57 With Series Resistor for
Capacitive Loading Greater than 1100 pF
Table 6. CLOAD and RS Values of Figure 14
CLOAD
1.1 to 99 nF
100 to 999 nF
1 μF
Minimum RS
3 kΩ
1.5 kΩ
750 Ω
8.3.6.3 VTEMP Voltage Shift
The LM57 is very linear over temperature and supply voltage range. Due to the intrinsic behavior of an
NMOS/PMOS rail-to-rail buffer, a slight shift in the output can occur when the supply voltage is ramped over the
operating range of the device. The location of the shift is determined by the relative levels of VDD and VTEMP. The
shift typically occurs when VDD − VTEMP = 1 V.
This slight shift (a few millivolts) takes place over a wide change (approximately 200 mV) in VDD or VTEMP. Since
the shift takes place over a wide temperature change of 5°C to 20°C, VTEMP is always monotonic. The accuracy
specifications in the table already includes this possible shift.
8.4 Device Functional Modes
The LM57 has several modes of operation as detailed in the following drawings.
V
DD
SENSE1
SENSE2
T
OVER
Asserts when T
DIE
> T
TRIP
See text
LM57
TRIP TEST
GND
Figure 15. Temperature Switch Using Push-Pull Output
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Device Functional Modes (continued)
V
DD
100k
SENSE1
SENSE2
T
OVER
Asserts when T
DIE
> T
TRIP
LM57
See text
TRIP TEST
GND
Figure 16. Temperature Switch Using Open-Drain Output
As shown in Figure 17 the LM57 has a TRIP Test input simplifying in situ board conductivity testing. Forcing
TRIP TEST pin "HIGH" will drive the TOVER pin "LOW" and the TOVER pin "HIGH".
V
DD
100k
T
OVER
TRIP TEST
LM57
T
OVER
GND
Figure 17. Trip Test Digital Output Test Circuit
In the circuit shown in Figure 18 when TOVER goes active high, it drives trip test high. Trip test high causes TOVER
to stay high. It is therefore latched. To release the latch, power down, then power up. The LM57 always comes
up in a released condition.
V
DD
T
OVER
TRIP TEST
LM57
T
OVER
GND
Figure 18. Simple Latch Circuit
24
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Device Functional Modes (continued)
The TRIP TEST pin, normally used to check the operation of the TOVER and TOVER pins, may be used to latch the
outputs whenever the temperature exceeds the programmed limit and causes the digital outputs to assert. As
shown in Figure 19, when TOVER goes high, the TRIP TEST input is also pulled high and causes TOVER output to
latch high and the TOVER output to latch low. Momentarily switching the TRIP TEST input low will reset the LM57
to normal operation. The resistor limits the current out of the TOVER output pin.
V
DD
100k
T
OVER
TRIP TEST
LM57
RESET
Momentary
T
OVER
GND
Figure 19. Latch Circuit Using TOVER Output
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM57 has several outputs allowing for varying system implementations.
9.1.1 ADC Input Considerations
The LM57 has an analog temperature sensor output (VTEMP) that can be directly connected to an ADC (Analog to
Digital Converter) input. Most CMOS ADCs found in microcontrollers and ASICs have a sampled data
comparator input structure. When the ADC charges the sampling cap, it requires instantaneous charge from the
output of the analog source such as the LM57 temperature sensor and many op amps. This requirement is easily
accommodated by the addition of a capacitor (CFILTER). The size of CFILTER depends on the size of the sampling
capacitor and the sampling frequency. Because not all ADCs have identical input stages, the charge
requirements will vary. The general ADC application shown in Figure 20 is an example only.
SAR Analog-to-Digital Converter
Reset
+2.4V to +5.5V
Input
Pin
LM57
Sample
R
IN
V
DD
V
TEMP
C
BP
C
C
PIN
SAMPLE
C
FILTER
GND
Figure 20. Suggested Connection to a Sampling Analog-to-Digital Converter Input Stage
9.2 Typical Application
V
DD
Supply
(+2.4V to +5.5V)
V
DD
Analog
V
TEMP
ADC Input
LM57
Microcontroller
SENSE1
T
OVER
SENSE2
Digital In
T
OVER
TRIP TEST
GND
Digital Out
Figure 21. Typical Application Schematic with Microcontroller TRIP TEST Control
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Typical Application (continued)
9.2.1 Design Requirements
By simply selecting the value of two resistors the trip point of the LM57 can easily be programmed as described
in the following section. If standard 1% values are used the actual trip point threshold is not degraded and stands
as described in the Electrical Characteristics section ( ).
9.2.2 Detailed Design Procedure
9.2.2.1 Selection of RSENSE Resistors
To set the trip point:
1. Locate the desired trip temperature in Table 4.
2. Identify the corresponding RSENSE2 value by following the column up to the resistor value.
3. Identify the corresponding RSENSE1 value by following the row leftwards to the resistor value.
4. Use only the EIA E96 standard resistor values from the list.
5. Use only a resistor with 1% tolerance and a temperature coefficient of 100 ppm (or better). These restrictions
are necessary to stay at the selected setting, and not to slip into an adjacent setting.
6. This is consistent with using resistors from the thick film chip resistors CRCW0402 family. These are
available with very small dimensions of L = 1 mm, W = 0.5 mm, H = 0.35 mm.
7. Note that the resistor tolerance does not diminish the accuracy of the trip point. As can be seen in the block
diagram these inputs drive the logic inputs of a DAC thus their tolerance does affect the trip point accuracy
unless the DAC setting slips into an adjacent level. See patent number 6924758.
9.2.3 Application Curves
The typical performance of the LM57 temperature sensor output can be seen in Figure 22. Figure 23 shows the
output behavior of the LM57 TOVER output.
2.0
MAX LImit
1.5
Trip Point
1.0
Trip Point - Hysteresis
0.5
VTEMP Output
(Temp. of Leads)
0.0
-0.5
-1.0
-1.5
-2.0
T
OVER
MIN Limit
50
0
25
75
100
125
150
±50
±25
DUT Temperature (C)
C102
Figure 23. Output Transfer Characteristic
Figure 22. J2 VTEMP Accuracy Characteristics
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Typical Application (continued)
9.2.4 Grounding of the TRIP TEST Pin
The circuit in Figure 24 shows the TRIP TEST pin grounded. This allows the LM57 to function autonomously
without microcontroller intervention. In all other respects this circuit functions similarly to the circuit shown in
Figure 21.
V
DD
Supply
(+2.4V to +5.5V)
V
DD
V
TEMP
LM57
Microcontroller
SENSE1
SENSE2
T
OVER
Digital In
T
OVER
TRIP TEST
GND
Figure 24. Typical Application Schematic without Microcontroller TRIP TEST Control
10 Power Supply Recommendations
Power supply bypass capacitors are optional and may be required if the supply line is noisy. TI recommends that
a local supply decoupling capacitor be used to reduce noise. For noisy environments, TI recommends a 100-nF
supply decoupling capacitor placed closed across VDD and GND pins of LM57.
11 Layout
11.1 Layout Guidelines
The LM57 can be applied easily in the same way as other integrated-circuit temperature sensors. It can be glued
or cemented to a surface. The temperatures of the lands and traces to the other leads of the LM57 will also
affect the temperature reading.
Alternatively, the LM57 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath or
screwed into a threaded hole in a tank. As with any IC, the LM57 and accompanying wiring and circuits must be
kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate at cold
temperatures where condensation can occur. If moisture creates a short circuit from the VTEMP output to ground
or VDD, the VTEMP output from the LM57 will not be correct. Printed-circuit coatings are often used to ensure that
moisture cannot corrode the leads or circuit traces.
28
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11.2 Layout Example
VIA to ground plane
VIA to power plane
GND
SENSE1
SENSE2
VDD
VTEMP
TOVER
RSENSE1
RSENSE2
TOVER
TRIP TEST
0.1 µ F
Figure 25. PW (TSSOP) Package Layout Example
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Layout Example (continued)
VIA to ground plane
VIA to power plane
GND
VTEMP
TOVER
RSENSE1
RSENSE2
SENSE1
DAP
SENSE2
VDD
TOVER
TRIP TEST
0.1 µ F
The best thermal conductivity to the junction of the LM57 is through the DAP. Make sure it is connected to the surface
whose temperature that is being measured.
Figure 26. SD (WSON) Package Layout Example
11.3 Temperature Considerations
The junction temperature of the LM57 is the actual temperature being measured. The thermal resistance
junction-to-ambient (RθJA) is the parameter (from Thermal Information ) used to calculate the rise of a device
junction temperature due to its power dissipation. Equation 3 is used to calculate the rise in the die temperature
of the LM57.
7J ꢀ ꢀ7A ꢀꢁꢀ5TJA ꢀ ꢂ9DD,Q ꢃꢀꢁꢀꢂ9DD ꢀ±ꢀ9TEMP ꢃꢀꢀ,L
ª
º
¼
¬
where
•
•
•
•
TA is the ambient temperature.
IQ is the quiescent current.
IL is the load current on VTEMP
.
RθJA can be found in Thermal Information
(3)
=
For example using an LM57 in the PW (TSSOP) package, in an application where TA = 30°C, VDD = 5.5 V, IDD
28 μA, J5 gain, VTEMP = 2368 mV, and IL = 0 μA, the total temperature rise would be [183°C/W × 5.5 V × 28 μA]
= 0.028°C. To minimize self-heating, the load current on VTEMP should be minimized.
30
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
相关文档如下：
•
•
•
LM57-Q1 汽车级数据表。
《回流温度曲线》规范，www.ti.com/packaging。
应用报告《IC 封装热指标》，SPRA953
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2009–2015, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM57BISD-10/NOPB
LM57BISD-5/NOPB
LM57BISDX-10/NOPB
LM57BISDX-5/NOPB
LM57CISD-10/NOPB
LM57CISD-5/NOPB
LM57CISDX-10/NOPB
LM57CISDX-5/NOPB
LM57FPW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
TSSOP
TSSOP
TSSOP
TSSOP
NGR
NGR
NGR
NGR
NGR
NGR
NGR
NGR
PW
8
8
8
8
8
8
8
8
8
8
8
8
1000 RoHS & Green
1000 RoHS & Green
4500 RoHS & Green
4500 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
4500 RoHS & Green
4500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-50 to 150
-50 to 150
-50 to 150
-50 to 150
-50 to 150
-50 to 150
-50 to 150
-50 to 150
-50 to 150
-50 to 150
-50 to 150
-50 to 150
57B9
57B5
57B9
57B5
57C9
57C5
57C9
57C5
SN
SN
SN
SN
SN
SN
SN
150
2000 RoHS & Green
150 RoHS & Green
2000 RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
LM57F
LM57F
LM57T
LM57T
LM57FPWR
PW
LM57TPW
PW
LM57TPWR
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM57BISD-10/NOPB
LM57BISD-5/NOPB
LM57BISDX-10/NOPB
LM57BISDX-5/NOPB
LM57CISD-10/NOPB
LM57CISD-5/NOPB
LM57CISDX-10/NOPB
LM57CISDX-5/NOPB
LM57FPWR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
TSSOP
TSSOP
NGR
NGR
NGR
NGR
NGR
NGR
NGR
NGR
PW
8
8
8
8
8
8
8
8
8
8
1000
1000
4500
4500
1000
1000
4500
4500
2000
2000
178.0
178.0
330.0
330.0
178.0
178.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
7.0
7.0
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
3.6
3.6
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.6
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LM57TPWR
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM57BISD-10/NOPB
LM57BISD-5/NOPB
LM57BISDX-10/NOPB
LM57BISDX-5/NOPB
LM57CISD-10/NOPB
LM57CISD-5/NOPB
LM57CISDX-10/NOPB
LM57CISDX-5/NOPB
LM57FPWR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
TSSOP
TSSOP
NGR
NGR
NGR
NGR
NGR
NGR
NGR
NGR
PW
8
8
8
8
8
8
8
8
8
8
1000
1000
4500
4500
1000
1000
4500
4500
2000
2000
208.0
208.0
356.0
356.0
208.0
208.0
356.0
356.0
356.0
356.0
191.0
191.0
356.0
356.0
191.0
191.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
LM57TPWR
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM57FPW
LM57TPW
PW
PW
TSSOP
TSSOP
8
8
150
150
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
NGR 8
2.5 x 2.5, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227146/A
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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Copyright © 2022，德州仪器 (TI) 公司
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