LM6125MD8 [TI]
BUFFER AMPLIFIER, UUC, DIE;
| 型号： | LM6125MD8 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BUFFER AMPLIFIER, UUC, DIE 放大器 |
| 文件： | 总12页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1994
LM6125/LM6225/LM6325
High Speed Buffer
±
n High output current:
300 mA
General Description
The LM6125 family of high speed unity gain buffers slew at
800 V/µs and have a small signal bandwidth of 50 MHz while
n Stable with large capacitive loads
n Current and thermal limiting
n Electronic shutdown
n 5V to 15V operation guaranteed
n Fully specified to drive 50Ω lines
±
driving a 50Ω load. These buffers drive 300 mA peak and
±
do not oscillate while driving large capacitive loads. The
LM6125 contains unique features not found in power buffers;
these include current limit, thermal shutdown, electronic
shutdown, and an error flag that warns of fault conditions.
Applications
n Line Driving
n Radar
™
These buffers are built with National’s VIP (Vertically Inte-
grated PNP) process which provides fast PNP transistors
that are true complements to the already fast NPN devices.
This advanced junction-isolated process delivers high speed
performance without the need for complex and expensive di-
electric isolation.
n Sonar
Features
n High slew rate: 800 V/µs
Simplified Schematic and Block Diagram
DS009222-1
DS009222-2
Numbers in () are for 14–pin N DIP.
™
VIP is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS009222
www.national.com
Pin Configurations
DS009222-4
Note: Pin 4 connected to case
DS009222-3
Top View
*Heat sinking pins.
Internally connected to V−.
Order Number LM6125H/883 (Note 1)
or LM6125H
Order Number LM6225N
See NS Package Number H08C
or LM6325N
See NS Package Number N14A
Note 1: Available per 5962-9081501
www.national.com
2
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
±
ESD Tolerance (Note 9)
θJA (Note 4)
1500V
H Package
150˚C/W
40˚C/W
N Package
±
36V ( 18V)
Supply Voltage
Maximum Junction
Temperature (TJ)
Operating Temperature Range
LM6125
±
Input to Output Voltage (Note 2)
Input Voltage
7V
150˚C
±
Vsupply
Output Short-Circuit to GND
(Note 3)
−55˚C to +125˚C
−40˚C to +85˚C
0˚C to +70˚C
Continuous
GND ≤ Vflag ≤ +Vsupply
−65˚C to +150˚C
LM6225
Flag Output Voltage
Storage Temperature Range
LM6325
±
4.75V to 16V
Operating Supply Voltage Range
Lead Temperature
(Soldering, 10 seconds)
260˚C
DC Electrical Characteristics
=
= =
15V, VCM 0, RL ≥ 100 kΩ and RS 50Ω unless otherwise noted.
±
The following specifications apply for Supply Voltage
=
=
=
=
Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
Parameter
Conditions
Typ
LM6125
Limit
(Notes 5, 10)
0.980
0.970
0.860
0.800
0.780
0.750
30
LM6225
Limit
(Note 5)
0.980
0.950
0.860
0.820
0.780
0.700
30
LM6325
Limit
(Note 5)
0.970
0.950
0.850
0.820
0.750
0.700
50
Units
=
=
=
±
±
AV1
AV2
AV3
VOS
IB
Voltage Gain 1
Voltage Gain 2
RL 1kΩ, VIN
10V
10V
0.990
0.900
0.840
15
=
RL 50Ω, VIN
V/V
Min
= =
RL 50Ω, V+ 5V
Voltage Gain 3
(Note 6)
=
VIN 2 VPP (1.5 VPP
)
=
Offset Voltage
RL 1 kΩ
mV
Max
µA
50
60
100
=
=
Input Bias Current
RL 1 kΩ, RS 10 kΩ
1
4
4
5
7
7
7
Max
MΩ
pF
=
RIN
CIN
RO
Input Resistance
Input Capacitance
Output Resistance
RL 50Ω
5
3.5
3
=
±
IOUT
10 mA
5
10
5
10
5
6
Ω
Max
= ∞
= ∞
= ∞
IS1
Supply Current 1
Supply Current 2
RL
RL
RL
15
14
18
18
20
22
18
20
1.5
2.0
13.2
13
11
10
10
9
20
20
=
IS2
, V+ 5V
16
16
mA
18
18
Max
=
±
±
15V
IS/D
VO1
VO2
VO3
VO4
PSRR
VOL
Supply Current
in Shutdown
, V
1.1
13.5
12.7
12
1.5
2.0
13.3
13
1.5
2.0
13.3
13
=
Output Swing 1
RL 1 kΩ
=
±
V
Output Swing 2
Output Swing 3
Output Swing 4
RL 100Ω
11.5
10
11.5
10
Min
=
RL 50Ω
11
11
9
9
=
RL 50Ω
1.8
70
1.6
1.3
60
1.6
1.4
60
1.6
1.5
60
50
340
400
VPP
Min
dB
=
V+ 5V (Note 6)
Power Supply
Rejection Ratio
Flag Pin Output
Low Voltage
55
50
Min
mV
Max
=
±
±
±
V
5V to 15V
300
400
300
400
=
VS/D 0V
3
www.national.com
DC Electrical Characteristics (Continued)
=
= =
15V, VCM 0, RL ≥ 100 kΩ and RS 50Ω unless otherwise noted.
±
The following specifications apply for Supply Voltage
=
=
=
=
Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
Parameter
Conditions
Typ
LM6125
Limit
LM6225
Limit
(Note 5)
10
LM6325
Limit
(Note 5)
10
Units
(Notes 5, 10)
10
=
IOH
Flag Pin Output
High Current
VOH Flag Pin 15V
0.01
1.4
µA
Max
V
(Note 6)
20
20
20
VTH
VIH
Shutdown Threshold
Shutdown Pin
2.0
2.0
2.0
2.0
0.8
0.8
−10
−20
−10
−20
50
2.0
2.0
V
Trip Point High
Shutdown Pin
Min
V
VIL
0.8
0.8
Trip Point Low
Shutdown Pin
0.8
0.8
Max
µA
=
IIL
VS/D 0V
−0.07
−0.05
1
−10
−20
−10
−20
50
−10
−20
−10
−20
100
200
Input Low Current
Shutdown Pin
Max
µA
=
VS/D 5V
IIH
Input High Current
Max
µA
=
Shutdown Pin 0V
IO
Bi-State Output
Current
=
VOUT +5V or −5V
2000
100
AC Electrical Characteristics
=
=
=
±
The following specifications apply for Supply Voltage
15V, VCM 0, RL ≥ 100 kΩ and RS 50Ω unless otherwise noted.
=
=
=
=
Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
Parameter
Conditions
Typ
LM6125
Limit
LM6225
Limit
LM6325
Limit
Units
(Note 5)
(Note 5)
(Note 5)
=
=
=
±
±
SR1
SR2
Slew Rate 1
VIN
VIN
11V, RL 1 kΩ
1200
800
V/µs
Min
=
Slew Rate 2
11V, RL 50Ω
550
30
550
30
550
30
(Note 8)
=
=
SR3
BW
tr, tf
tPD
Slew Rate 3
VIN 2 VPP, RL 50Ω
50
50
=
V+ 5V (Note 6)
=
−3 dB Bandwidth
VIN 100 mVPP
MHz
Min
ns
=
RL 50Ω, CL ≤ 10 pF
=
Rise Time
Fall Time
RL 50Ω, CL ≤ 10 pF
8.0
4.0
10
=
VO 100 mVPP
=
Propagation
Delay Time
Overshoot
RL 50Ω, CL ≤ 10 pF
ns
%
=
VO 100 mVPP
=
RL 50Ω, CL ≤ 10 pF
OS
=
VO 100 mVPP
=
Shutdown Pin 0V
VFT
VIN, VOUT Feedthrough
in Shutdown
=
VIN 4 VPP, 1 MHz
−50
30
dB
pF
ns
=
RL 50Ω
Shutdown Pin 0V
=
COUT
Output Capacitance
in Shutdown
tSD
Shutdown
700
Response Time
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its rated operating conditions.
Note 3: During current limit, thermal limit, or electronic shutdown the input current will increase if the input to output differential voltage exceeds 8V. See Overvoltage
Protection in Application Hints.
Note 4: The LM6125 series buffers contain current limit and thermal shutdown to protect against fault conditions.
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4
AC Electrical Characteristics (Continued)
=
Note 5: For operation at elevated temperature, these devices must be derated based on a thermal resistance of θ and T max, T
T
A
+ θ
P . θ for the
D JC
JA
J
J
JA
LM6125H and LM6225H is 17˚C/W. The thermal impedance θ of the device in the N package is 40˚C/W when soldered directly to a printed circuit board, and the
JA
heat-sinking pins (pins 3, 4, 5, 10, 11, and 12) are connected to 2 square inches of 2 oz. copper. When installed in a socket, the thermal impedance θ of the N pack-
JA
age is 60˚C/W.
Note 6: Limits are guaranteed by testing or correlation.
Note 7: The input is biased to +2.5V, and V swings V about this value. The input swing is 2 V at all temperatures except for the A 3 test at −55˚C where it
IN PP PP
V
is reduced to 1.5 V
.
PP
Note 8: The Error Flag is set (low) during current limit or thermal fault detection in addition to being set by the Shutdown pin. It is an open-collector output which re-
quires an external pullup resistor.
±
Note 9: Slew rate is measured with a 11V input pulse and 50Ω source impedance at 25˚C. Since voltage gain is typically 0.9 driving a 50Ω load, the output swing
±
±
will be approximately 10V. Slew rate is calculated for transitions between 5V levels on both rising and falling edges. A high speed measurement is done to minimize
±
device heating. For slew rate versus junction temperature see typical performance curves. The input pulse amplitude should be reduced to 10V for measurements
at temperature extremes. For accurate measurements, the input slew rate should be at least 1700 V/µs.
Note 10: The test circuit consists of the human body model of 120 pF in series with 1500Ω.
Note 11: A military RETS specification is available on request. At the time of printing, the LM6125H/883 RETS spec complied with the Boldface limits in this column.
The LM6125H/883 may also be procured as Standard Military Drawing specification #5962-9081501MXX.
±
Typical Performance Characteristics TA = 25˚C, VS= 15V unless otherwise specified
Frequency Response
Frequency Response
Slew Rate vs Temperature
DS009222-9
DS009222-10
DS009222-11
Overshoot vs Capacitive Load
Large Signal Response
Large Signal Response
=
(RL 1 kΩ)
=
(RL 50Ω)
DS009222-13
DS009222-14
DS009222-12
Supply Current
−3 dB Bandwidth
Slew Rate
DS009222-15
DS009222-16
DS009222-17
5
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±
Typical Performance Characteristics TA = 25˚C, VS= 15V unless otherwise specified (Continued)
Slew Rate
Power Bandwidth
Input Return Gain
(S11)
DS009222-19
DS009222-18
DS009222-20
Forward Transmission
Gain (S21)
Current Limit
DS009222-22
DS009222-21
Typical Connection Diagram
DS009222-6
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6
Application Hints
POWER SUPPLY DECOUPLING
down is activated, or the shutdown (S/D) pin is driven low by
external logic. Flag voltage returns to its HIGH state when
normal operation resumes.
If the S/D pin is not to be used, it should be connected to V+.
The method of supply bypassing is not critical for stability of
the LM6125 series buffers. However, their high current out-
put combined with high slew rate can result in significant
voltage transients on the power supply lines if much induc-
tance is present. For example, a slew rate of 900 V/µs into a
50Ω load produces a di/dt of 18 A/µs. Multiplying this by a
wiring inductance of 50 nH results in a 0.9V transient. To
minimize this problem use high quality decoupling very close
to the device. Suggested values are a 0.1 µF ceramic in par-
allel with one or two 2.2 µF tantalums. A ground plane is rec-
ommended.
OVERVOLTAGE PROTECTION
The LM6125 may be severely damaged or destroyed if the
Absolute Maximum Rating of 7V between input and output
pins is exceeded.
If the buffer’s input-to-output differential voltage is allowed to
exceed 7V,
a
base-emitter junction will be in
reverse-breakdown, and will be in series with
a
forward-biased base-emitter junction. Referring to the
LM6125 simplified schematic, the transistors involved are
Q1 and Q3 for positive inputs, and Q2 and Q4 for negative
inputs. If any current is allowed to flow through these junc-
tions, localized heating of the reverse-biased junction will oc-
cur, potentially causing damage. The effect of the damage is
typically increased offset voltage, increased bias current,
and/or degraded AC performance. The damage is cumula-
tive, and may eventually result in complete device failure.
LOAD IMPEDANCE
The LM6125 is stable into any load when driven by a 50Ω
source. As shown in the Overshoot vs Capacitive Load
graph, worst case is
1000 pF. Shunting the load capacitance with a resistor will
reduce overshoot.
a purely capacitive load of about
SOURCE INDUCTANCE
Like any high-frequency buffer, the LM6125 can oscillate at
high values of source inductance. The worst case condition
occurs at a purely capacitive load of 50 pF where up to
100 nH of source inductance can be tolerated. With a 50Ω
load, this goes up to 200 nH. This sensitivity may be reduced
at the expense of a slight reduction in bandwidth by adding a
resistor in series with the buffer input. A 100Ω resistor will en-
sure stability with source inductances up to 400 nH with any
load.
The device is best protected by the insertion of the parallel
combination of a 100 kΩ resistor (R1) and a small capacitor
(C1) in series with the buffer input, and a 100 kΩ resistor
(R2) from input to output of the buffer (see Figure 1). This
network normally has no effect on the buffer output. How-
ever, if the buffer’s current limit or shutdown is activated, and
the output has a ground-referred load of significantly less
than 100 kΩ, a large input-to-output voltage may be present.
R1 and R2 then form
a voltage divider, keeping the
input-output differential below the 7V Maximum Rating for in-
put voltages up to 14V. This protection network should be
sufficient to protect the LM6125 from the output of nearly any
ERROR FLAG LOGIC
The Error Flag pin is an open-collector output which requires
an external pull-up resistor. Flag voltage is HIGH during op-
eration, and is LOW during a fault condition. A fault condition
occurs if either the internal current limit or the thermal shut-
±
op amp which is operated on supply voltages of 15V or
lower.
DS009222-8
FIGURE 1. LM6125 with Overvoltage Protection
7
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Physical Dimensions inches (millimeters) unless otherwise noted
Metal Can Package (H)
Order Number LM6125H/883 or LM6125H
NS Package Number H08C
Molded Dual-In-Line Package (N)
Order Number LM6225N or LM6325N
NS Package Number N14A
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8
Notes
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National P/N LM6125 - High Speed Buffer
file:////roarer/root/data13/imaging/BIT...0804/08032000/NATL/08012000/LM6125.html
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Product Folder
LM6125
High Speed Buffer
Generic P/N 6125
Contents
Parametric Table
Number of Channels
1
General Description
Features
Applications
(Channels)
Type
Fixed
50
BW at AV+1, typ (MHz)
Datasheet
Package Availability, Models, Samples
& Pricing
Design Tools
Slew Rate, typ (Volts/usec) 800
Gain, typ
.999
300
Output Current, typ (mA)
Min Supply Voltage (Volt) 10
Max Supply Voltage (Volt) 36
Supply Current per Channel,
14
typ (mA)
Vos, typ (mV)
30
Input Bias Current, Max
(nA)
7000
Special Features
Shutdown,Error Flag
General Description
The LM6125 family of high speed unity gain buffers slew at 800 V/µs and have a small
signal bandwidth of 50 MHz while driving a 50 Ohm load. These buffers drive ±300 mA
peak and do not oscillate while driving large capacitive loads. The LM6125 contains unique
features not found in power buffers; these include current limit, thermal shutdown,
electronic shutdown, and an error flag that warns of fault conditions.
These buffers are built with National's VIP™ (Vertically Integrated PNP) process which
provides fast PNP transistors that are true complements to the already fast NPN devices.
This advanced junction-isolated process delivers high speed performance without the need
for complex and expensive dielectric isolation.
1 of 3
05-Aug-2000 9:45 AM
National P/N LM6125 - High Speed Buffer
file:////roarer/root/data13/imaging/BIT...0804/08032000/NATL/08012000/LM6125.html
Features
High slew rate: 800 V/µs
High output current: ±300 mA
Stable with large capacitive loads
Current and thermal limiting
Electronic shutdown
5V to ±15V operation guaranteed
Fully specified to drive 50 Ohm lines
Applications
Line Driving
Radar
Sonar
Datasheet
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LM6125/LM6225/LM6325 High Speed
Buffer
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LM6125 Mil-Aero Datasheet
MNLM6125-X
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Samples
&
Electronic
Orders
Package
Models
Budgetary Pricing
Std
Pack
Size
Pack
Mar
Part Number
Status
#
$US
Quantity
Type
SPICE IBIS
pins
each
[logo] ¢Z
LM6125H
5962-9081
$E
tray
20
Full
production
LM6125H/883 TO-5
8
N/A N/A
N/A N/A
.
.
50+
$15.0000 of
Full
production
LM6125 MD8
die
N/A
-
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Amplifiers Selection Guide
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