LM6171BIM/NOPB [TI]
高速、低功耗、低失真电压反馈放大器 | D | 8 | -40 to 85;
| 型号： | LM6171BIM/NOPB |
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TEXAS INSTRUMENTS |
| 描述： | 高速、低功耗、低失真电压反馈放大器 | D | 8 | -40 to 85 放大器 光电二极管 |
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LM6171
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SNOS745C –MAY 1998–REVISED MARCH 2013
LM6171 High Speed Low Power Low Distortion Voltage Feedback Amplifier
Check for Samples: LM6171
1
FEATURES
DESCRIPTION
The LM6171 is a high speed unity-gain stable voltage
feedback amplifier. It offers a high slew rate of
3600V/μs and a unity-gain bandwidth of 100 MHz
while consuming only 2.5 mA of supply current. The
LM6171 has very impressive AC and DC
performance which is a great benefit for high speed
signal processing and video applications.
23
•
(Typical Unless Otherwise Noted)
Easy-To-Use Voltage Feedback Topology
Very High Slew Rate: 3600V/μs
Wide Unity-Gain-Bandwidth Product: 100 MHz
−3dB Frequency @ AV = +2: 62 MHz
Low Supply Current: 2.5 mA
•
•
•
•
•
•
•
•
The ±15V power supplies allow for large signal
swings and give greater dynamic range and signal-to-
noise ratio. The LM6171 has high output current
drive, low SFDR and THD, ideal for ADC/DAC
systems. The LM6171 is specified for ±5V operation
for portable applications.
High CMRR: 110 dB
High Open Loop Gain: 90 dB
Specified for ±15V and ±5V Operation
APPLICATIONS
The LM6171 is built on TI's advanced VIP III
(Vertically Integrated PNP) complementary bipolar
process.
•
•
•
•
•
•
•
•
•
Multimedia Broadcast Systems
Line Drivers, Switchers
Video Amplifiers
NTSC, PAL® and SECAM Systems
ADC/DAC Buffers
HDTV Amplifiers
Pulse Amplifiers and Peak Detectors
Instrumentation Amplifier
Active Filters
CONNECTION DIAGRAM
Figure 1. Top View
8-Pin SOIC/PDIP
See Package Number D (SOIC) or
See Package Number P (PDIP)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PAL is a registered trademark of and used under lisence from Advanced Micro Devices, Inc..
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
LM6171
SNOS745C –MAY 1998–REVISED MARCH 2013
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Absolute Maximum Ratings(1)(2)
ESD Tolerance(3)
Supply Voltage (V+–V−)
2.5 kV
36V
Differential Input Voltage
±10V
Common-Mode Voltage Range
Input Current
V++0.3V to V− −0.3V
±10mA
Output Short Circuit to Ground(4)
Storage Temperature Range
Maximum Junction Temperature(5)
Soldering Information
Continuous
−65°C to +150°C
150°C
Infrared or Convection Reflow
(20 sec.)
235°C
Wave Soldering Lead Temp
(10 sec.)
260°C
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(3) Human body model, 1.5 kΩ in series with 100 pF.
(4) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
of 150°C.
(5) The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) − TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Operating Ratings(1)
Supply Voltage
5.5V ≤ VS ≤ 34V
−40°C to +85°C
108°C/W
Operating Temperature Range
LM6171AI, LM6171BI
P Package, 8-Pin PDIP
D Package, 8-Pin SOIC
Thermal Resistance (θJA
)
172°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
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±15V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, and RL = 1 kΩ. Boldface
limits apply at the temperature extremes
Symbol
Parameter
Conditions
Typ
LM6171AI
LM6171BI
Units
(1)
Limit
Limit
(2)
(2)
VOS
Input Offset Voltage
1.5
3
6
mV
max
μV/°C
μA
5
8
TC VOS
IB
Input Offset Voltage Average Drift
Input Bias Current
6
1
3
4
2
3
3
4
2
3
max
μA
IOS
Input Offset Current
Input Resistance
0.03
max
RIN
Common Mode
40
4.9
14
MΩ
Differential Mode
RO
Open Loop Output Resistance
Common Mode Rejection Ratio
Ω
dB
CMRR
VCM = ±10V
110
80
75
85
80
75
70
80
75
min
dB
PSRR
Power Supply Rejection Ratio
VS = ±15V to ±5V
95
min
V
VCM
AV
Input Common-Mode Voltage Range
Large Signal Voltage Gain(3)
CMRR ≥ 60 dB
RL = 1 kΩ
±13.5
90
80
70
80
70
dB
min
dB
RL = 100Ω
RL = 1 kΩ
83
70
70
60
60
min
V
VO
Output Swing
13.3
−13.3
11.6
−10.5
116
12.5
12
12.5
12
min
V
−12.5
−12
9
−12.5
−12
9
max
V
RL = 100Ω
8.5
−9
8.5
−9
min
V
−8.5
90
−8.5
90
max
mA
min
mA
max
mA
mA
mA
mA
mA
max
Continuous Output Current (Open Loop)(4) Sourcing, RL = 100Ω
Sinking, RL = 100Ω
85
85
105
90
90
85
85
Continuous Output Current (in Linear
Region)
Sourcing, RL = 10Ω
Sinking, RL = 10Ω
Sourcing
100
80
ISC
Output Short Circuit Current
135
135
2.5
Sinking
IS
Supply Current
4
4
4.5
4.5
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT
±5V. For VS = +5V, VOUT = ±1V.
=
(4) The open loop output current is the output swing with the 100Ω load resistor divided by that resistor.
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±15V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, and RL = 1 kΩ. Boldface
limits apply at the temperature extremes
Symbol
Parameter
Conditions
Typ
LM6171AI
LM6171BI
Units
(1)
Limit
Limit
(2)
(2)
SR
Slew Rate(3)
AV = +2, VIN = 13 VPP
AV = +2, VIN = 10 VPP
3600
3000
100
160
62
V/μs
GBW
Unity Gain-Bandwidth Product
MHz
MHz
MHz
deg
−3 dB Frequency
AV = +1
AV = +2
φm
Phase Margin
40
ts
Settling Time (0.1%)
AV = −1, VOUT = ±5V RL
500Ω
=
48
6
ns
ns
Propagation Delay
VIN = ±5V, RL = 500Ω, AV
−2
=
AD
φD
en
in
Differential Gain(4)
Differential Phase(4)
0.03
0.5
12
%
deg
Input-Referred Voltage Noise
Input-Referred Current Noise
f = 1 kHz
f = 1 kHz
nV/√Hz
pA/√Hz
1
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Differential gain and phase are measured with AV = +2, VIN = 1 VPP at 3.58 MHz and both input and output 75Ω terminated.
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SNOS745C –MAY 1998–REVISED MARCH 2013
±5V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V, and RL = 1 kΩ. Boldface limits
apply at the temperature extremes
Symbol
Parameter
Conditions
Typ
LM6171AI
LM6171BI
Units
(1)
Limit
Limit
(2)
(2)
VOS
Input Offset Voltage
1.2
3
6
mV
max
μV/°C
μA
5
8
TC VOS
IB
Input Offset Voltage Average Drift
Input Bias Current
4
1
2.5
3.5
1.5
2.2
2.5
3.5
1.5
2.2
max
μA
IOS
Input Offset Current
Input Resistance
0.03
max
MΩ
RIN
Common Mode
40
4.9
14
Differential Mode
RO
Open Loop Output Resistance
Common Mode Rejection Ratio
Ω
CMRR
VCM = ±2.5V
105
80
75
85
80
75
70
80
75
dB
min
dB
PSRR
Power Supply Rejection Ratio
VS = ±15V to ±5V
95
min
VCM
AV
Input Common-Mode Voltage
Range
Large Signal Voltage Gain(3)
CMRR ≥ 60 dB
RL = 1 kΩ
±3.7
84
V
75
65
75
65
dB
min
dB
RL = 100Ω
RL = 1 kΩ
80
3.5
−3.4
3.2
−3.0
32
70
70
60
60
min
V
VO
Output Swing
3.2
3
3.2
3
min
V
−3.2
−3
−3.2
−3
max
V
RL = 100Ω
2.8
2.5
−2.8
−2.5
28
2.8
2.5
−2.8
−2.5
28
min
V
max
mA
min
mA
max
mA
mA
mA
max
Continuous Output Current (Open Sourcing, RL = 100Ω
Loop)(4)
25
25
Sinking, RL = 100Ω
30
28
28
25
25
ISC
Output Short Circuit Current
Supply Current
Sourcing
Sinking
130
100
2.3
IS
3
3
3.5
3.5
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT
±5V. For VS = +5V, VOUT = ±1V.
=
(4) The open loop output current is the output swing with the 100Ω load resistor divided by that resistor.
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±5V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V, and RL = 1 kΩ. Boldface limits
apply at the temperature extremes
Symbol
Parameter
Conditions
Typ
LM6171AI
LM6171BI
Units
(1)
Limit
Limit
(2)
(2)
SR
Slew Rate(3)
AV = +2, VIN = 3.5 VPP
750
70
V/μs
MHz
MHz
GBW
Unity Gain-Bandwidth Product
−3 dB Frequency
AV = +1
AV = +2
130
45
φm
Phase Margin
57
deg
ns
ts
Settling Time (0.1%)
AV = −1, VOUT = +1V, RL
500Ω
=
60
8
Propagation Delay
VIN = ±1V, RL = 500Ω, AV
−2
=
ns
AD
φD
en
in
Differential Gain(4)
Differential Phase(4)
0.04
0.7
11
%
deg
Input-Referred Voltage Noise
Input-Referred Current Noise
f = 1 kHz
f = 1 kHz
nV/√Hz
pA/√Hz
1
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Differential gain and phase are measured with AV = +2, VIN = 1 VPP at 3.58 MHz and both input and output 75Ω terminated.
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SNOS745C –MAY 1998–REVISED MARCH 2013
Typical Performance Characteristics
Unless otherwise noted, TA = 25°C
Supply Current
Supply Current
vs.
Temperature
vs.
Supply Voltage
Figure 2.
Figure 3.
Input Offset Voltage
vs.
Input Bias Current
vs.
Temperature
Temperature
Figure 4.
Figure 5.
Input Offset Voltage
vs.
Common Mode Voltage
Short Circuit Current
vs.
Temperature (Sourcing)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise noted, TA = 25°C
Short Circuit Current
Output Voltage
vs.
Output Current
vs.
Temperature (Sinking)
Figure 8.
Figure 9.
Output Voltage
vs.
Output Current
CMRR
vs.
Frequency
Figure 10.
Figure 11.
PSRR
vs.
Frequency
PSRR
vs.
Frequency
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise noted, TA = 25°C
Open Loop Frequency Response
Open Loop Frequency Response
Figure 14.
Figure 15.
Gain Bandwidth Product
vs.
Gain Bandwidth Product
vs.
Supply Voltage
Load Capacitance
Figure 16.
Figure 17.
Large Signal Voltage Gain
Large Signal Voltage Gain
vs.
vs.
Load
Load
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Unless otherwise noted, TA = 25°C
Input Voltage Noise
Input Voltage Noise
vs.
vs.
Frequency
Frequency
Figure 20.
Figure 21.
Input Current Noise
vs.
Input Current Noise
vs.
Frequency
Frequency
Figure 22.
Figure 23.
Slew Rate
vs.
Supply Voltage
Slew Rate
vs.
Input Voltage
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
Unless otherwise noted, TA = 25°C
Slew Rate
Open Loop Output Impedance
vs.
vs.
Load Capacitance
Frequency
Figure 26.
Figure 27.
Open Loop Output Impedance
vs.
Large Signal Pulse Response
Frequency
AV = −1, VS = ±15V
Figure 28.
Figure 29.
Large Signal Pulse Response
Large Signal Pulse Response
AV = +1, VS = ±15V
AV = −1, VS = ±5V
Figure 30.
Figure 31.
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Typical Performance Characteristics (continued)
Unless otherwise noted, TA = 25°C
Large Signal Pulse Response
Large Signal Pulse Response
AV = +2, VS = ±15V
AV = +1, VS = ±5V
Figure 32.
Figure 33.
Large Signal Pulse Response
AV = +2, VS = ±5V
Small Signal Pulse Response
AV = −1, VS = ±15V
Figure 34.
Figure 35.
Small Signal Pulse Response
Small Signal Pulse Response
AV = +1, VS = ±15V
AV = −1, VS = ±5V
Figure 36.
Figure 37.
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Typical Performance Characteristics (continued)
Unless otherwise noted, TA = 25°C
Small Signal Pulse Response
Small Signal Pulse Response
AV = +2, VS = ±15V
AV = +1, VS = ±5V
Figure 38.
Figure 39.
Closed Loop Frequency Response
vs.
Small Signal Pulse Response
AV = +2, VS = ±5V
SupplyVoltage
(AV = +1)
Figure 40.
Figure 41.
Closed Loop Frequency Response
Closed Loop Frequency Response
vs.
vs.
Supply Voltage
(AV = +2)
Capacitive Load
(AV = +1)
Figure 42.
Figure 43.
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Typical Performance Characteristics (continued)
Unless otherwise noted, TA = 25°C
Closed Loop Frequency Response
Closed Loop Frequency Response
vs.
vs.
Capacitive Load
(AV = +1)
Capacitive Load
(AV = +2)
Figure 44.
Figure 45.
Closed Loop Frequency Response
vs.
Total Harmonic Distortion
Capacitive Load
(AV = +2)
vs.
Frequency
Figure 46.
Figure 47.
Total Harmonic Distortion
Total Harmonic Distortion
vs.
vs.
Frequency
Frequency
Figure 48.
Figure 49.
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Typical Performance Characteristics (continued)
Unless otherwise noted, TA = 25°C
Total Harmonic Distortion
Undistorted Output Swing
vs.
vs.
Frequency
Frequency
Figure 50.
Figure 51.
Undistorted Output Swing
Undistorted Output Swing
vs.
vs.
Frequency
Frequency
Figure 52.
Figure 53.
Undistorted Output Swing
Total Power Dissipation
vs.
Ambient Temperature
vs.
Frequency
Figure 54.
Figure 55.
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LM6171 SIMPLIFIED SCHEMATIC
Figure 56.
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APPLICATION INFORMATION
LM6171 PERFORMANCE DISCUSSION
The LM6171 is a high speed, unity-gain stable voltage feedback amplifier. It consumes only 2.5 mA supply
current while providing a gain-bandwidth product of 100 MHz and a slew rate of 3600V/μs. It also has other great
features such as low differential gain and phase and high output current. The LM6171 is a good choice in high
speed circuits.
The LM6171 is a true voltage feedback amplifier. Unlike current feedback amplifiers (CFAs) with a low inverting
input impedance and a high non-inverting input impedance, both inputs of voltage feedback amplifiers (VFAs)
have high impedance nodes. The low impedance inverting input in CFAs will couple with feedback capacitor and
cause oscillation. As a result, CFAs cannot be used in traditional op amp circuits such as photodiode amplifiers,
I-to-V converters and integrators.
LM6171 CIRCUIT OPERATION
The class AB input stage in LM6171 is fully symmetrical and has a similar slewing characteristic to the current
feedback amplifiers. In LM6171 Figure 56, Q1 through Q4 form the equivalent of the current feedback input
buffer, RE the equivalent of the feedback resistor, and stage A buffers the inverting input. The triple-buffered
output stage isolates the gain stage from the load to provide low output impedance.
LM6171 SLEW RATE CHARACTERISTIC
The slew rate of LM6171 is determined by the current available to charge and discharge an internal high
impedance node capacitor. The current is the differential input voltage divided by the total degeneration resistor
RE. Therefore, the slew rate is proportional to the input voltage level, and the higher slew rates are achievable in
the lower gain configurations.
When a very fast large signal pulse is applied to the input of an amplifier, some overshoot or undershoot occurs.
By placing an external series resistor such as 1 kΩ to the input of LM6171, the bandwidth is reduced to help
lower the overshoot.
LAYOUT CONSIDERATION
Printed Circuit Boards and High Speed Op Amps
There are many things to consider when designing PC boards for high speed op amps. Without proper caution, it
is very easy and frustrating to have excessive ringing, oscillation and other degraded AC performance in high
speed circuits. As a rule, the signal traces should be short and wide to provide low inductance and low
impedance paths. Any unused board space needs to be grounded to reduce stray signal pickup. Critical
components should also be grounded at a common point to eliminate voltage drop. Sockets add capacitance to
the board and can affect frequency performance. It is better to solder the amplifier directly into the PC board
without using any socket.
Using Probes
Active (FET) probes are ideal for taking high frequency measurements because they have wide bandwidth, high
input impedance and low input capacitance. However, the probe ground leads provide a long ground loop that
will produce errors in measurement. Instead, the probes can be grounded directly by removing the ground leads
and probe jackets and using scope probe jacks.
Components Selection And Feedback Resistor
It is important in high speed applications to keep all component leads short because wires are inductive at high
frequency. For discrete components, choose carbon composition-type resistors and mica-type capacitors.
Surface mount components are preferred over discrete components for minimum inductive effect.
Large values of feedback resistors can couple with parasitic capacitance and cause undesirable effects such as
ringing or oscillation in high speed amplifiers. For LM6171, a feedback resistor of 510Ω gives optimal
performance.
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COMPENSATION FOR INPUT CAPACITANCE
The combination of an amplifier's input capacitance with the gain setting resistors adds a pole that can cause
peaking or oscillation. To solve this problem, a feedback capacitor with a value
CF > (RG × CIN)/RF
(1)
can be used to cancel that pole. For LM6171, a feedback capacitor of 2 pF is recommended. Figure 57 illustrates
the compensation circuit.
Figure 57. Compensating for Input Capacitance
POWER SUPPLY BYPASSING
Bypassing the power supply is necessary to maintain low power supply impedance across frequency. Both
positive and negative power supplies should be bypassed individually by placing 0.01 μF ceramic capacitors
directly to power supply pins and 2.2 μF tantalum capacitors close to the power supply pins.
Figure 58. Power Supply Bypassing
TERMINATION
In high frequency applications, reflections occur if signals are not properly terminated. Figure 59 shows a
properly terminated signal while Figure 60 shows an improperly terminated signal.
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Figure 59. Properly Terminated Signal
Figure 60. Improperly Terminated Signal
To minimize reflection, coaxial cable with matching characteristic impedance to the signal source should be
used. The other end of the cable should be terminated with the same value terminator or resistor. For the
commonly used cables, RG59 has 75Ω characteristic impedance, and RG58 has 50Ω characteristic impedance.
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DRIVING CAPACITIVE LOADS
Amplifiers driving capacitive loads can oscillate or have ringing at the output. To eliminate oscillation or reduce
ringing, an isolation resistor can be placed as shown below in Figure 61. The combination of the isolation resistor
and the load capacitor forms a pole to increase stablility by adding more phase margin to the overall system. The
desired performance depends on the value of the isolation resistor; the bigger the isolation resistor, the more
damped the pulse response becomes. For LM6171, a 50Ω isolation resistor is recommended for initial
evaluation. Figure 62 shows the LM6171 driving a 200 pF load with the 50Ω isolation resistor.
Figure 61. Isolation Resistor Used to Drive Capacitive Load
Figure 62. The LM6171 Driving a 200 pF Load with a 50Ω Isolation Resistor
POWER DISSIPATION
The maximum power allowed to dissipate in a device is defined as:
PD = (TJ(max) − TA)/θJA
where
•
•
•
•
PD is the power dissipation in a device
TJ(max) is the maximum junction temperature
TA is the ambient temperature
θJA is the thermal resistance of a particular package
(2)
For example, for the LM6171 in a SOIC-8 package, the maximum power dissipation at 25°C ambient
temperature is 730 mW.
20
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Product Folder Links: LM6171
LM6171
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SNOS745C –MAY 1998–REVISED MARCH 2013
Thermal resistance, θJA, depends on parameters such as die size, package size and package material. The
smaller the die size and package, the higher θJA becomes. The 8-pin PDIP package has a lower thermal
resistance (108°C/W) than that of 8-pin SOIC-8 (172°C/W). Therefore, for higher dissipation capability, use an 8-
pin PDIP package.
The total power dissipated in a device can be calculated as:
PD = PQ + PL
(3)
PQ is the quiescent power dissipated in a device with no load connected at the output. PL is the power dissipated
in the device with a load connected at the output; it is not the power dissipated by the load.
Furthermore,
PQ = supply current × total supply voltage with no load
PL = output current × (voltage difference between supply voltage and output voltage of the same supply)
For example, the total power dissipated by the LM6171 with VS = ±15V and output voltage of 10V into 1 kΩ load
resistor (one end tied to ground) is
PD = PQ + PL
= (2.5 mA) × (30V) + (10 mA) × (15V − 10V)
= 75 mW + 50 mW
= 125 mW
APPLICATION CIRCUITS
Figure 63. Fast Instrumentation Amplifier
Copyright © 1998–2013, Texas Instruments Incorporated
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LM6171
SNOS745C –MAY 1998–REVISED MARCH 2013
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Figure 64. Multivibrator
Figure 65. Pulse Width Modulator
22
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Product Folder Links: LM6171
LM6171
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SNOS745C –MAY 1998–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
Copyright © 1998–2013, Texas Instruments Incorporated
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23
Product Folder Links: LM6171
PACKAGE OPTION ADDENDUM
www.ti.com
23-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM6171AIM
NRND
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
D
D
P
8
8
8
8
8
8
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-NA-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LM61
71AIM
LM6171AIM/NOPB
LM6171AIMX/NOPB
LM6171BIM
ACTIVE
ACTIVE
NRND
95
RoHS & Green
SN
SN
LM61
71AIM
Samples
Samples
2500 RoHS & Green
LM61
71AIM
95
95
Non-RoHS
& Green
Call TI
SN
LM61
71BIM
LM6171BIM/NOPB
LM6171BIMX/NOPB
LM6171BIN/NOPB
ACTIVE
ACTIVE
ACTIVE
RoHS & Green
LM61
71BIM
Samples
Samples
Samples
2500 RoHS & Green
40 RoHS & Green
SN
LM61
71BIM
NIPDAU
LM6171
BIN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Feb-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM6171AIMX/NOPB
LM6171BIMX/NOPB
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.5
6.5
5.4
5.4
2.0
2.0
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM6171AIMX/NOPB
LM6171BIMX/NOPB
SOIC
SOIC
D
D
8
8
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM6171AIM
LM6171AIM
D
D
D
D
D
D
P
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
8
8
8
8
8
8
8
95
95
95
95
95
95
40
495
495
495
495
495
495
502
8
8
4064
4064
4064
4064
4064
4064
11938
3.05
3.05
3.05
3.05
3.05
3.05
4.32
LM6171AIM/NOPB
LM6171BIM
8
8
LM6171BIM
8
LM6171BIM/NOPB
LM6171BIN/NOPB
8
14
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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