LM6172 [TI]
双路高速、低功耗、低失真电压反馈放大器;
| 型号： | LM6172 |
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LM6172
www.ti.com
SNOS792D –MAY 1999–REVISED MARCH 2013
LM6172 Dual High Speed, Low Power, Low Distortion, Voltage Feedback Amplifiers
Check for Samples: LM6172
1
FEATURES
DESCRIPTION
The LM6172 is a dual high speed voltage feedback
amplifier. It is unity-gain stable and provides excellent
DC and AC performance. With 100MHz unity-gain
bandwidth, 3000V/μs slew rate and 50mA of output
current per channel, the LM6172 offers high
performance in dual amplifiers; yet it only consumes
2.3mA of supply current each channel.
2
•
(Typical Unless Otherwise Noted)
Easy to Use Voltage Feedback Topology
High Slew Rate 3000V/μs
•
•
•
•
•
•
Wide Unity-Gain Bandwidth 100MHz
Low Supply Current 2.3mA/Channel
High Output Current 50mA/channel
Specified for ±15V and ±5V Operation
The LM6172 operates on ±15V power supply for
systems requiring large voltage swings, such as
ADSL, scanners and ultrasound equipment. It is also
specified at ±5V power supply for low voltage
applications such as portable video systems.
APPLICATIONS
•
•
•
•
•
•
•
Scanner I-to-V Converters
ADSL/HDSL Drivers
The LM6172 is built with TI's advanced VIP III
(Vertically Integrated PNP) complementary bipolar
process. See the LM6171 datasheet for a single
amplifier with these same features.
Multimedia Broadcast Systems
Video Amplifiers
NTSC, PAL and SECAM Systems
ADC/DAC Buffers
Pulse Amplifiers and Peak Detectors
LM6172 Driving Capacitive Load
Connection Diagram
Figure 1. Top View 8-Pin
See Package Numbers P (PDIP) and D (SOIC)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
LM6172
SNOS792D –MAY 1999–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
ESD Tolerance(3)
Human Body Model
Machine Model
3kV
300V
Supply Voltage (V+ − V−)
Differential Input Voltage
Common Mode Voltage Range
Input Current
36V
±10V
V+ +0.3V to V− −0.3V
±10mA
Output Short Circuit to Ground(4)
Continuous
−65°C to +150°C
150°C
Storage Temp. Range
Maximum Junction Temperature(5)
Soldering Information
Infrared or Convection Reflow
(20 sec.)
235°C
Wave Soldering Lead Temp
(10 sec.)
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human body model, 1.5kΩ in series with 100pF. Machine Model, 200Ω in series with 100pF.
(4) Continuous short circuit operation can result in exceeding the maximum allowed junction temperature of 150°C.
(5) The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) − TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Operating Ratings(1)
Supply Voltage
5.5V ≤ VS ≤ 36V
−40°C to +85°C
95°C/W
Operating Temperature Range
LM6172I
Thermal Resistance (θJA
)
P Package, 8-Pin PDIP
D Package, 8-Pin SOIC
160°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
±15V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C,V+ = +15V, V− = −15V, VCM = 0V, and RL = 1kΩ. Boldface
limits apply at the temperature extremes
Symbol
Parameter
Conditions
Typ
LM6172I
Units
(1)
Limit
(2)
VOS
Input Offset Voltage
0.4
3
mV
max
μV/°C
μA
4
TC VOS
IB
Input Offset Voltage Average Drift
Input Bias Current
6
1.2
3
4
2
3
max
μA
IOS
RIN
RO
Input Offset Current
0.02
max
Input Resistance
Common Mode
Differential Mode
40
4.9
14
MΩ
Open Loop Output Resistance
Ω
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
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±15V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ = 25°C,V+ = +15V, V− = −15V, VCM = 0V, and RL = 1kΩ. Boldface
limits apply at the temperature extremes
Symbol
Parameter
Conditions
Typ
LM6172I
Units
(1)
Limit
(2)
CMRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
VCM = ±10V
110
95
70
65
75
70
dB
min
dB
PSRR
VS = ±15V to ±5V
min
V
VCM
AV
Input Common Mode Voltage Range
Large Signal Voltage Gain(3)
CMRR ≥ 60dB
RL = 1kΩ
±13.5
86
80
75
dB
min
dB
RL = 100Ω
RL = 1kΩ
78
13.2
−13.1
9
65
60
min
V
VO
Output Swing
12.5
12
min
V
−12.5
−12
6
max
V
RL = 100Ω
5
min
V
−8.5
90
−6
−5
max
mA
min
mA
max
mA
mA
mA
max
Continuous Output Current
(Open Loop)(4)
Sourcing, RL = 100Ω
Sinking, RL = 100Ω
60
50
−85
−60
−50
ISC
Sourcing
107
−105
4.6
Current Output Short Circuit
Supply Current
Sinking
IS
Both Amplifiers
8
9
(3) Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT
±5V. For VS = ±5V, VOUT = ±1V.
=
(4) The open loop output current is the output swing with the 100Ω load resistor divided by that resistor.
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±15V AC Electrical Characteristics
Unless otherwise specified, TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, and RL = 1kΩ
Symbol
Parameter
Conditions
LM6172I
Units
Typ
(1)
SR
Slew Rate
AV = +2, VIN = 13 VPP
AV = +2, VIN = 10 VPP
3000
2500
100
160
62
V/μs
V/μs
MHz
MHz
MHz
MHz
Deg
Unity-Gain Bandwidth
−3 dB Frequency
AV = +1
AV = +2
Bandwidth Matching between Channels
Phase Margin
2
φm
40
ts
Settling Time (0.1%)
AV = −1, VOUT = ±5V,
RL = 500Ω
65
ns
AD
φD
en
in
Differential Gain(2)
Differential Phase(2)
Input-Referred Voltage Noise
Input-Referred Current Noise
Second Harmonic
Distortion(3)
0.28
0.6
%
Deg
nV/√Hz
pA/√Hz
dB
f = 1kHz
f = 1kHz
f = 10kHz
f = 5MHz
f = 10kHz
f = 5MHz
12
1
−110
−50
−105
−50
dB
Third Harmonic
Distortion(3)
dB
dB
(1) Typical Values represent the most likely parametric normal.
(2) Differential gain and phase are measured with AV = +2, VIN = 1 VPP at 3.58MHz and both input and output 75Ω terminated.
(3) Harmonics are measured with AV = +2, VIN = 1 VPP and RL = 100Ω.
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±5V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V, and RL = 1 kΩ. Boldface limits
apply at the temperature extremes
Symbol
Parameter
Conditions
Typ
LM6172I
Units
(1)
Limit
(2)
VOS
Input Offset Voltage
0.1
3
mV
4
max
μV/°C
μA
TC VOS
IB
Input Offset Voltage Average Drift
Input Bias Current
4
1.4
2.5
3.5
1.5
2.2
max
μA
IOS
Input Offset Current
Input Resistance
0.02
max
RIN
Common Mode
40
4.9
14
MΩ
Differential Mode
RO
Output Resistance
Ω
dB
CMRR
Common Mode Rejection Ratio
VCM = ±2.5V
105
70
65
75
70
min
dB
PSRR
Power Supply Rejection Ratio
VS = ±15V to ±5V
95
min
V
VCM
AV
Input Common Mode Voltage Range
Large Signal Voltage Gain(3)
CMRR ≥ 60dB
RL = 1kΩ
±3.7
82
70
65
dB
min
dB
RL = 100Ω
RL = 1kΩ
78
3.4
65
60
min
V
VO
Output Swing
3.1
3
min
V
−3.3
2.9
−3.1
−3
max
V
RL = 100Ω
2.5
2.4
−2.4
−2.3
25
min
V
−2.7
29
max
mA
min
mA
max
mA
mA
mA
max
Continuous Output Current (Open
Loop)(4)
Sourcing, RL = 100Ω
Sinking, RL = 100Ω
24
−27
−24
−23
ISC
Output Short Circuit Current
Supply Current
Sourcing
93
−72
4.4
Sinking
IS
Both Amplifiers
6
7
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
(3) Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT
±5V. For VS = ±5V, VOUT = ±1V.
=
(4) The open loop output current is the output swing with the 100Ω load resistor divided by that resistor.
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±5V AC Electrical Characteristics
Unless otherwise specified, TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V, and RL = 1 kΩ.
Symbol
Parameter
Conditions
LM61722
Units
Typ
(1)
SR
Slew Rate
AV = +2, VIN = 3.5 VPP
750
70
V/μs
MHz
MHz
MHz
Deg
ns
Unity-Gain Bandwidth
−3 dB Frequency
AV = +1
AV = +2
130
45
φm
ts
Phase Margin
57
Settling Time (0.1%)
AV = −1, VOUT = ±1V, RL = 500Ω
72
AD
φD
en
in
Differential Gain(2)
Differential Phase(2)
0.4
0.7
11
%
Deg
nV/√Hz
pA/√Hz
dB
Input-Referred Voltage Noise
Input-Referred Current Noise
Second Harmonic Distortion(3)
f = 1kHz
f = 1kHz
f = 10kHz
f = 5MHz
f = 10kHz
f = 5MHz
1
−110
−48
−105
−50
dB
Third Harmonic Distortion(3)
dB
dB
(1) Typical Values represent the most likely parametric normal.
(2) Differential gain and phase are measured with AV = +2, VIN = 1 VPP at 3.58MHz and both input and output 75Ω terminated.
(3) Harmonics are measured with AV = +2, VIN = 1 VPP and RL = 100Ω.
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Typical Performance Characteristics
unless otherwise noted, TA = 25°C
Supply Voltage
Supply Current
vs.
Temperature
vs.
Supply Current
Figure 2.
Figure 3.
Input Offset Voltage
vs.
Input Bias Current
vs.
Temperature
Temperature
Figure 4.
Figure 5.
Short Circuit Current
vs.
Temperature (Sourcing)
Short Circuit Current
vs.
Temperature (Sinking)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA = 25°C
Output Voltage
Output Voltage
vs.
Output Current
(VS = ±5V)
vs.
Output Current
(VS = ±15V)
Figure 8.
Figure 9.
CMRR
vs.
Frequency
PSRR
vs.
Frequency
Figure 10.
Figure 11.
PSRR
vs.
Frequency
Open-Loop Frequency Response
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA = 25°C
Gain-Bandwidth Product
vs.
Supply Voltage at Different Temperature
Open-Loop Frequency Response
Figure 14.
Figure 15.
Large Signal Voltage Gain
Large Signal Voltage Gain
vs.
vs.
Load
Load
Figure 16.
Figure 17.
Input Voltage Noise
vs.
Input Voltage Noise
vs.
Frequency
Frequency
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA = 25°C
Input Current Noise
Input Current Noise
vs.
vs.
Frequency
Frequency
Figure 20.
Figure 21.
Slew Rate
vs.
Supply Voltage
Slew Rate
vs.
Input Voltage
Figure 22.
Figure 23.
Large Signal Pulse Response
AV = +1, VS = ±15V
Small Signal Pulse Response
AV = +1, VS = ±15V
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA = 25°C
Large Signal Pulse Response
Small Signal Pulse Response
AV = +1, VS = ±5V
AV = +1, VS = ±5V
Figure 26.
Figure 27.
Large Signal Pulse Response
AV = +2, VS = ±15V
Small Signal Pulse Response
AV = +2, VS = ±15V
Figure 28.
Figure 29.
Large Signal Pulse Response
AV = +2, VS = ±5V
Small Signal Pulse Response
AV = +2, VS = ±5V
Figure 30.
Figure 31.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA = 25°C
Large Signal Pulse Response
Small Signal Pulse Response
AV = −1, VS = ±15V
AV = −1, VS = ±15V
Figure 32.
Figure 33.
Large Signal Pulse Response
Small Signal Pulse Response
AV = −1, VS = ±5V
AV = −1, VS = ±5V
Figure 34.
Figure 35.
Closed Loop Frequency Response
Closed Loop Frequency Response
vs.
vs.
Supply Voltage
(AV = +1)
Supply Voltage
(AV = +2)
Figure 36.
Figure 37.
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Typical Performance Characteristics (continued)
unless otherwise noted, TA = 25°C
Harmonic Distortion
Harmonic Distortion
vs.
vs.
Frequency
(VS = ±15V)
Frequency
(VS = ±5V)
Figure 38.
Figure 39.
Crosstalk Rejection
vs.
Maximum Power Dissipation
vs.
Frequency
Ambient Temperature
Figure 40.
Figure 41.
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LM6172 Simplified Schematic (Each Amplifier)
Figure 42.
APPLICATION NOTES
LM6172 PERFORMANCE DISCUSSION
The LM6172 is a dual high-speed, low power, voltage feedback amplifier. It is unity-gain stable and offers
outstanding performance with only 2.3mA of supply current per channel. The combination of 100MHz unity-gain
bandwidth, 3000V/μs slew rate, 50mA per channel output current and other attractive features makes it easy to
implement the LM6172 in various applications. Quiescent power of the LM6172 is 138mW operating at ±15V
supply and 46mW at ±5V supply.
LM6172 CIRCUIT OPERATION
The class AB input stage in LM6172 is fully symmetrical and has a similar slewing characteristic to the current
feedback amplifiers. In Figure 42, Q1 through Q4 form the equivalent of the current feedback input buffer, RE the
equivalent of the feedback resistor, and stage A buffers the inverting input. The triple-buffered output stage
isolates the gain stage from the load to provide low output impedance.
LM6172 SLEW RATE CHARACTERISTIC
The slew rate of LM6172 is determined by the current available to charge and discharge an internal high
impedance node capacitor. This current is the differential input voltage divided by the total degeneration resistor
RE. Therefore, the slew rate is proportional to the input voltage level, and the higher slew rates are achievable in
the lower gain configurations.
When a very fast large signal pulse is applied to the input of an amplifier, some overshoot or undershoot occurs.
By placing an external series resistor such as 1kΩ to the input of LM6172, the slew rate is reduced to help lower
the overshoot, which reduces settling time.
REDUCING SETTLING TIME
The LM6172 has a very fast slew rate that causes overshoot and undershoot. To reduce settling time on
LM6172, a 1kΩ resistor can be placed in series with the input signal to decrease slew rate. A feedback capacitor
can also be used to reduce overshoot and undershoot. This feedback capacitor serves as a zero to increase the
stability of the amplifier circuit. A 2pF feedback capacitor is recommended for initial evaluation. When the
LM6172 is configured as a buffer, a feedback resistor of 1kΩ must be added in parallel to the feedback capacitor.
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Another possible source of overshoot and undershoot comes from capacitive load at the output. Please see
DRIVING CAPACITIVE LOADS for more detail.
DRIVING CAPACITIVE LOADS
Amplifiers driving capacitive loads can oscillate or have ringing at the output. To eliminate oscillation or reduce
ringing, an isolation resistor can be placed as shown in Figure 43. The combination of the isolation resistor and
the load capacitor forms a pole to increase stability by adding more phase margin to the overall system. The
desired performance depends on the value of the isolation resistor; the bigger the isolation resistor, the more
damped (slow) the pulse response becomes. For LM6172, a 50Ω isolation resistor is recommended for initial
evaluation.
Figure 43. Isolation Resistor Used to Drive Capacitive Load
Figure 44. The LM6172 Driving a 510pF Load with a 30Ω Isolation Resistor
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Figure 45. The LM6172 Driving a 220 pF Load with a 50Ω Isolation Resistor
LAYOUT CONSIDERATION
PRINTED CIRCUIT BOARDS AND HIGH SPEED OP AMPS
There are many things to consider when designing PC boards for high speed op amps. Without proper caution, it
is very easy to have excessive ringing, oscillation and other degraded AC performance in high speed circuits. As
a rule, the signal traces should be short and wide to provide low inductance and low impedance paths. Any
unused board space needs to be grounded to reduce stray signal pickup. Critical components should also be
grounded at a common point to eliminate voltage drop. Sockets add capacitance to the board and can affect
frequency performance. It is better to solder the amplifier directly into the PC board without using any socket.
USING PROBES
Active (FET) probes are ideal for taking high frequency measurements because they have wide bandwidth, high
input impedance and low input capacitance. However, the probe ground leads provide a long ground loop that
will produce errors in measurement. Instead, the probes can be grounded directly by removing the ground leads
and probe jackets and using scope probe jacks.
COMPONENTS SELECTION AND FEEDBACK RESISTOR
It is important in high speed applications to keep all component leads short because wires are inductive at high
frequency. For discrete components, choose carbon composition-type resistors and mica-type capacitors.
Surface mount components are preferred over discrete components for minimum inductive effect.
Large values of feedback resistors can couple with parasitic capacitance and cause undesirable effects such as
ringing or oscillation in high speed amplifiers. For LM6172, a feedback resistor less than 1kΩ gives optimal
performance.
COMPENSATION FOR INPUT CAPACITANCE
The combination of an amplifier's input capacitance with the gain setting resistors adds a pole that can cause
peaking or oscillation. To solve this problem, a feedback capacitor with a value
CF > (RG × CIN)/RF
(1)
can be used to cancel that pole. For LM6172, a feedback capacitor of 2pF is recommended. Figure 46 illustrates
the compensation circuit.
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Figure 46. Compensating for Input Capacitance
POWER SUPPLY BYPASSING
Bypassing the power supply is necessary to maintain low power supply impedance across frequency. Both
positive and negative power supplies should be bypassed individually by placing 0.01μF ceramic capacitors
directly to power supply pins and 2.2μF tantalum capacitors close to the power supply pins.
Figure 47. Power Supply Bypassing
TERMINATION
In high frequency applications, reflections occur if signals are not properly terminated. Figure 48 shows a
properly terminated signal while Figure 49 shows an improperly terminated signal.
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Figure 48. Properly Terminated Signal
Figure 49. Improperly Terminated Signal
To minimize reflection, coaxial cable with matching characteristic impedance to the signal source should be
used. The other end of the cable should be terminated with the same value terminator or resistor. For the
commonly used cables, RG59 has 75Ω characteristic impedance, and RG58 has 50Ω characteristic impedance.
POWER DISSIPATION
The maximum power allowed to dissipate in a device is defined as:
PD = (TJ(max) − TA)/θJA
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Where
•
•
•
•
PD is the power dissipation in a device
TJ(max) is the maximum junction temperature
TA is the ambient temperature
θJA is the thermal resistance of a particular package
For example, for the LM6172 in a SOIC-8 package, the maximum power dissipation at 25°C ambient
temperature is 780mW.
Thermal resistance, θJA, depends on parameters such as die size, package size and package material. The
smaller the die size and package, the higher θJA becomes. The 8-pin DIP package has a lower thermal
resistance (95°C/W) than that of 8-pin SO (160°C/W). Therefore, for higher dissipation capability, use an 8-
pin DIP package.
The total power dissipated in a device can be calculated as: PD = PQ + PL
(2)
PQ is the quiescent power dissipated in a device with no load connected at the output. PL is the power dissipated
in the device with a load connected at the output; it is not the power dissipated by the load.
Furthermore,
PQ = supply current x total supply voltage with no load
PL = output current x (voltage difference between supply voltage and output voltage of the same supply)
For example, the total power dissipated by the LM6172 with VS = ±15V and both channels swinging output
voltage of 10V into 1kΩ is
PD = PQ + PL
=
=
=
2[(2.3mA)(30V)] + 2[(10mA)(15V − 10V)]
138mW + 100mW
238mW
Application Circuits
Figure 50. I-to-V Converters
Figure 51. Differential Line Driver
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 19
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM6172IM
LM6172IM/NOPB
LM6172IMX
NRND
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
P
8
8
8
8
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-NA-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LM61
72IM
ACTIVE
NRND
95
RoHS & Green
SN
Call TI
SN
LM61
72IM
Samples
2500
Non-RoHS
& Green
LM61
72IM
LM6172IMX/NOPB
LM6172IN/NOPB
ACTIVE
ACTIVE
2500 RoHS & Green
LM61
72IM
Samples
Samples
40 RoHS & Green
NIPDAU
LM6172IN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Feb-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM6172IMX
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.5
6.5
5.4
5.4
2.0
2.0
8.0
8.0
12.0
12.0
Q1
Q1
LM6172IMX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Feb-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM6172IMX
SOIC
SOIC
D
D
8
8
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
LM6172IMX/NOPB
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Feb-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM6172IM
LM6172IM
D
D
D
P
SOIC
SOIC
SOIC
PDIP
8
8
8
8
95
95
95
40
495
495
495
502
8
8
4064
4064
4064
11938
3.05
3.05
3.05
4.32
LM6172IM/NOPB
LM6172IN/NOPB
8
14
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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